Electronic chip having a plurality of functions

Abstract

Disclosed is an electronic chip (100) comprising a first circuit (101) associated with an electronic function and a second circuit (102) associated with an electronic function different from the electronic function of the first circuit (101). The electronic chip (100) comprises external connection terminals (103), the first circuit (101) comprises first connection terminals (104) and the second circuit (102) comprises second connection terminals (105). The electronic chip comprises switches (106) which are each electrically connected to one of the external connection terminals (103), to one of the first connection terminals (104) and to one of the second connection terminals (105).

Description

Multi-function electronic chip Technical field of the invention

[0001] The technical field of the invention relates to an electronic chip integrating several functions and more particularly, in a particular embodiment, an electronic chip for a display. State of the prior art

[0002] It is known, for example, for a liquid crystal display (LCD) or an organic light-emitting diode (OLED) display, to use different electronic chips, each associated with a predetermined function. For example, to control the display via pixels of the display arranged in columns and rows, it is known to use a controller chip connected to a pixel row control chip and a pixel column control chip. The pixel row control chip makes it possible to control the operation of pixel rows connected to this pixel row control chip and the pixel column control chip makes it possible to control, i.e.send the data to be displayed by the pixels in the pixel columns connected to this pixel column driver chip. This solution requires managing different versions of electronic chips, which can cause supply problems, as well as space problems at the periphery of the display. In addition, this solution also requires that the controller chip, the pixel row driver chip, and the chosen pixel column driver chip be compatible with each other in terms of communication protocols, which makes this solution more complex.

[0003] To address the supply issue, it is known, for example, to use electronic chips integrating several functions. For an electronic chip with several functions, each function is capable of being implemented by a dedicated circuit integrated into the corresponding electronic chip. Typically, an electronic chip intended to be integrated into a display may comprise a pixel row control circuit to perform the function of the pixel row control chip mentioned above, a pixel column control circuit to perform the function of the pixel column control chip mentioned above and a control circuit (performing the function of the control chip) making it possible to control any of the pixel row control circuit and the pixel column control circuit within the corresponding electronic chip.This also overcomes the compatibility problem since the electronic chip includes all the means necessary to carry out communications between the circuits it integrates. Although such integration is potentially satisfactory because it limits the number of separate component references to be used to manufacture a display, it induces the presence, within each electronic chip, of numerous connection terminals. external, in this case mainly output terminals, to be connected for example each to a corresponding pin of an electronic chip package to be mounted for example on the display or on a logic board of the display.Each external connection terminal occupies a certain surface area of ​​the electronic chip and, depending on the electronic chip, the sum of the surfaces required to produce the external connection terminals associated with a particular function of the electronic chip may be greater than the logical implementation surface area of ​​said function within the electronic chip: as a result, the surface area of ​​the electronic chip may be mainly defined by its external connection terminals (in English this phenomenon is called "pad limited"); this is all the more problematic when the electronic chip integrates several functions, its size may then be disproportionate given the functions, which may cause problems when integrating the housing containing this electronic chip into a display.When such an electronic chip housed in its housing is mounted within the display, only the pins useful for the desired function will be effectively connected within the display, for example on the logic board. A disadvantage of such an electronic chip with several integrated functions lies in its flexibility of use, particularly in the sense that:. • the surface area of ​​the electronic chip is large and therefore the overall size of the box integrating the corresponding electronic chip is also large: it is therefore more difficult to connect this electronic chip to a logic board due to its size; • when connecting the electronic chip to a logic board, the pins on its housing may involve making the tracks printed on the logic board more complex to connect said electronic chip to other components assembled on the logic board. Furthermore, the significant increase in the surface area of ​​the electronic chip integrating several functions increases its cost for functions which may only be partially used. Subject of the invention

[0004] The aim of the invention is to provide an electronic chip which offers satisfactory flexibility of use.

[0005] For this purpose, the invention relates to an electronic chip comprising a first circuit associated with an electronic function and a second circuit associated with an electronic function different from the electronic function of the first circuit, the electronic chip comprising external connection terminals, the first circuit comprising first connection terminals and the second circuit comprising second connection terminals. This electronic chip comprises switches each electrically connected to one of the external connection terminals, to one of the first connection terminals and to one of the second connection terminals, each switch being configured to selectively adopt: • a first state from which it results that an electrical link is formed between the terminal of external connection to which said switch is electrically connected and the first connection terminal to which said switch is electrically connected; • a second state from which it results that an electrical link is formed between the external connection terminal to which said switch is electrically connected and the second connection terminal to which said switch is electrically connected. This allows great flexibility in using the electronic chip, for example by choosing which of the first and second circuits is to be used or by choosing to which external connection terminals to route the first and second connection terminals in order to facilitate the integration of the electronic chip in a particular environment such as a logic board.

[0006] The electronic chip may further include one or more of the following features.

[0007] According to a characteristic of the electronic chip, it is configured to present: • a first configuration in which the first circuit is active while the second circuit is inactive; • a second configuration in which the second circuit is active while the first circuit is inactive. The choice of configuration advantageously makes it possible to limit the component references in the context of the manufacture of devices using one or more electronic chips and therefore to improve the management of the component supply chain.

[0008] According to a characteristic of the electronic chip, the number of external connection terminals is strictly less than the sum of the number of first connection terminals and the number of second connection terminals. This makes it possible to limit the number of external terminals when they are intended to be used to be connected either to the first circuit or to the second circuit.

[0009] According to a feature of the electronic chip, it comprises a control circuit electrically connected to the first circuit and to the second circuit, the control circuit being configured to control any of the first and second circuits. This has the advantage, when the first and second circuits must be associated with a control circuit, that the function of the control circuit is directly integrated within the electronic chip, thus facilitating its use without having to worry about adding a compatible control chip, integrating the control circuit.

[0010] According to a characteristic of the electronic chip, it is such that: at least a portion of the external connection terminals are intended to be electrically connected each to a circuit for controlling a pixel of a display; the first circuit is a circuit for controlling rows of pixels of the display; the second circuit is a circuit for controlling columns of pixels of the display. Thus, the electronic chip has the advantage of presenting two functions to allow the control of pixels respectively either in rows or in columns while limiting the number of external connection terminals.

[0011] According to a feature of the electronic chip, the electronic chip includes means for enabling the configuration of the switches. This has the advantage of allowing easy selection of the state of each of the switches, which can then be frozen or redefined each time a device using the electronic chip is started.

[0012] According to a feature of the electronic chip, the means for enabling the configuration of the switches comprise a configuration input electrically connected to each of the switches so as to enable the propagation, from the configuration input, of a switch configuration signal. This allows a single configuration signal to simultaneously configure all the switches of the electronic chip.

[0013] According to a characteristic of the electronic chip, as an alternative to the configuration signal, the means for enabling the configuration of the switches comprise memory cells each associated with one of the switches to enable the operation of said switch to be configured, each memory cell being configurable, preferably definitively, by a configuration function implemented in the control circuit.

[0014] According to a feature of the electronic chip, the first and second circuits are digital circuits, the first connection terminals and the second connection terminals all supporting the same low level voltage and the same high level voltage. This has the advantage that the external connection terminals, the first and second connection terminals can be sized similarly and as precisely as possible so as not to have to support different voltage amplitudes dependent on the function chosen to be implemented among the electronic function of the first circuit and the electronic function of the second circuit.

[0015] According to a feature of the electronic chip, the electronic chip comprises a daisy chain output intended to be electrically connected to another electronic chip. The daisy chain output makes it possible to electrically connect several electronic chips in series in order, for example, to adapt to the number of lines of pixels or the number of columns of pixels of a display.

[0016] According to a characteristic of the electronic chip, the chain output is constituted by one of the external connection terminals and: • when active, the first circuit is configured to emit a chaining signal through one of its first connection terminals only after having sent a signal to each of the external connection terminals electrically connected to a corresponding line of pixels of the display; • when active, the second circuit is configured to emit the chaining signal through one of its second connection terminals only after having sent a signal to each of the connected external connection terminals electrically to a corresponding column of pixels of the display; • in the first state of the switch electrically connected to the chaining output, the first connection terminal intended to emit the chaining signal is electrically connected to said switch; • in the second state of the switch electrically connected to the chaining output, the second connection terminal intended to emit the chaining signal is electrically connected to said switch. This makes it possible to operate first or second circuits of separate electronic chips one after the other without needing to synchronize them by an external signal, for example in a screen scanning mode of the display.

[0017] According to a feature of the electronic chip, the control circuit can be configured to send vertical control signals to the first circuit and to send horizontal control signals and data to be displayed to the second circuit. This is suitable for displaying images.

[0018] The invention also relates to a display comprising a pixel matrix and at least one electronic chip as described for controlling the display of the pixels of the pixel matrix Px. In particular, the display may comprise several electronic chips as described

[0019] Such a display has the advantage that it can be manufactured with a limited number of component references and that the space occupied by such components, particularly on the periphery of the pixel matrix, can be limited.

[0020] Other advantages and features may emerge from the detailed description that follows. Brief description of the drawings

[0021] The invention will be better understood upon reading the following detailed description, given solely by way of non-limiting example and made with reference to the appended drawings listed below.

[0022] Figure 1 schematically illustrates an electronic chip according to a particular embodiment of the present invention.

[0023] Figure 2 schematically illustrates the electronic chip according to a particular embodiment of the present invention.

[0024] Figure 3 schematically illustrates the electronic chip according to a particular embodiment of the present invention.

[0025] Figure 4 schematically illustrates the electronic chip according to a particular embodiment of the present invention.

[0026] Figure 5 schematically illustrates the electronic chip integrated in a package.

[0027] Figure 6 schematically illustrates a display comprising electronic chips according to the present invention for controlling pixels arranged in the form of a row and column matrix.

[0028] Figure 7 schematically illustrates a set of electronic chips chained.

[0029] In these figures, the same references are used to designate the same elements. The elements represented in the different figures are not necessarily drawn to scale in order to facilitate understanding of the figures. Detailed description

[0030] In this description, when two electrically connected elements are mentioned, it is understood that there is a physical link, such as for example an electrically conductive track, which allows the propagation of an electrical signal between these two elements. An element can for example be a connection terminal, a circuit, an input, an output or a switch as will be seen later.

[0031] By "circuit associated with an electronic function", it is understood that this electronic function is the one to which the corresponding circuit is dedicated, this electronic function being implemented using the electronic components integrated into said circuit.

[0032] Below is an operating environment for an electronic chip; this environment may in particular be a logic board on which the electronic chip is plugged / connected.

[0033] The invention relates to an electronic chip 100, embodiments of which are illustrated schematically in FIGS. 1 to 4. The electronic chip 100 comprises a first circuit 101 associated with an electronic function and a second circuit 102 associated with an electronic function different from the electronic function of the first circuit 101. The electronic chip 100 comprises external connection terminals 103. The first circuit 101 comprises first connection terminals 104 and the second circuit 102 comprises second connection terminals 105. The electronic chip 100 comprises switches 106 each electrically connected to one of the external connection terminals 103, to one of the first connection terminals 104 and to one of the second connection terminals 105, each switch 106 being configured to selectively adopt: • a first state from which it results that an electrical link is formed between the external connection terminal 103 to which said switch 106 is electrically connected and the first connection terminal 104 to which said switch 106 is electrically connected; • a second state from which it results that an electrical link is formed between the external connection terminal 103 to which said switch 106 is electrically connected and the second connection terminal 105 to which said switch 106 is electrically connected.

[0034] Thus, it is understood that for each switch 106: • in the first state of said switch 106, the external connection terminal 103, to which said switch 106 is electrically connected, is electrically isolated from the second connection terminal 105 to which said switch 106 is electrically connected; • in the second state of said switch 106, the external connection terminal 103, to which said switch 106 is electrically connected, is electrically isolated from the first connection terminal 104 to which said switch 106 is electrically connected.

[0035] Generally speaking, the advantage of such an electronic chip 100 lies in its flexibility of use in the sense that its operation can be parameterized by the choice of the operating state of the switches 106, this operating state being notably selected, for each of the switches 106, from among the first state and the second state.

[0036] A particular advantage of such an electronic chip 100 is that it makes it possible, if desired, to limit the number of external connection terminals 103 depending on the intended use of the electronic chip 100 which can then be used to implement the electronic function of the first circuit 101 or the electronic function of the second circuit 102. Limiting the number of external connection terminals 103 of the electronic chip 100 makes it possible to limit the surface area required, for example on a support substrate such as a silicon substrate, to form the electronic chip 100 and its external connection terminals 103 regardless of the electronic function (for example chosen between the electronic function of the first circuit 101 and the electronic function of the second circuit 102) of the electronic chip 100 to be activated.Furthermore, the electronic chip 100 as described may, if necessary, make it possible to limit the number of unused external connection terminals 103 when the electronic chip 100 is functionally connected in its operating environment.

[0037] In the examples illustrated in figures 1 to 4, taking as an example the fact that: the number of first connection terminals 104 is equal to the number of second connection terminals 105; • in the event of operation of the first circuit 101 all of its first connection terminals 104 are used; • in the event of operation of the second circuit 102, all of its second connection terminals 105 are used; this ultimately allows, whether the first circuit 101 is activated or the second circuit 102 is activated, to divide by two the number of external connection terminals 103 in comparison with a known solution where the number of external connection terminals would be equal to the sum of the number of first connection terminals 104 and the number of second connection terminals 105.

[0038] In the case where both the first and second circuits 101, 102 are functional when using the electronic chip 100, another particular advantage of the electronic chip 100 as described is that it allows, for example, to flexibly choose, via the switches 106, which external connection terminals 103 are to be electrically connected to the first circuit 101 and which external connection terminals 103 are to be electrically connected to the second circuit 102 for adapt the electronic chip 100 to the operating environment in which it will be used. It can then be understood here that all the first connection terminals 104 and all the second connection terminals 105 are not necessary for the operation of the first circuit 101 and the second circuit 102 respectively. This makes it possible to present a modularity allowing, for example, to adapt the electronic chip 100 in the operating environment where it will be connected, for example by distributing all the external connection terminals 103 over the entire periphery of one face of the electronic chip 100 (not shown). Thus, the external connection terminals 103 can be configured on demand.

[0039] By “switch 106” is meant in the present description any system allowing, for example, to implement as desired: an electrical link between the corresponding external connection terminal 103 and the first corresponding connection terminal 104; and an electrical link between the corresponding external connection terminal 103 and the second corresponding connection terminal 105. Therefore, the switch 106 can be a switch, for example formed by a set of field effect transistors behaving like a switch controlled by a logic signal varying for example from 0 to 1 and conversely from 1 to 0.

[0040] Preferably: • each switch 106 is electrically connected to only one of the external connection terminals 103, to only one of the first connection terminals 104, and to only one of the second connection terminals 105; • each first connection terminal 104 is electrically connected to only one of the switches 106; • each second connection terminal 105 is electrically connected to only one of the switches 106; • each external connection terminal 103 is electrically connected to only one of the switches 106. This effectively ensures flexibility in managing internal connections to the electronic chip.

[0041] Preferably, each of the external connection terminals 103 is intended to be electrically connected to an external connection member 201, also called a “pin” or “lug”, of a housing 200 for the electronic chip 100 (this housing not being shown in figures 1 to 4 but visible in figure 5 in a schematic manner with the electronic chip 100 shown in dotted lines). The housing 200 makes it possible in particular to connect the electronic chip 100 in its operating environment.

[0042] In the case where the external connection terminals 103 are intended to be electrically connected to the connection members 201 of the housing 200 of the electronic chip 100 for which not all the electronic functions are to be activated, this also makes it possible to reduce the number of connection members 201 and therefore the size of the housing 200 while allowing various uses of the housing 200 in the sense that it may be used in different ways depending on the electronic function chosen within the electronic chip 100 (i.e. the first circuit 101 or the second circuit 102) to be connected to the external connection terminals 103.

[0043] According to a particular application, in particular in the field of display which will be described in more detail below, the external connection terminals 103 are output terminals of the electronic chip 100.

[0044] In particular, the first circuit 101 and the second circuit 102 are each staged, that is to say that they integrate for example each of the shift registers. Therefore, each stage of the first circuit 101 can be connected to only one of the first connection terminals 104 of this first circuit 101 and each stage of the second circuit 102 can be connected to only one of the second connection terminals 105 of this second circuit 102. This has the advantage of scheduling the processing within the first and second circuits 101, 102 in the sense that: • within the first circuit 101, all or part of the first connection terminals 104 will sequentially receive a signal to be transmitted depending on the processing order in the first circuit 101; • within the second circuit 102 all or part of the second connection terminals 105 will sequentially receive a signal to be transmitted depending on the processing order in the second circuit 102.

[0045] In particular, the invention also relates to a display 1000 comprising a matrix of pixels Px and at least one electronic chip 100a, 100b as described for controlling the display of the pixels Px of the matrix of pixels Px. In particular, the display 1000 may comprise several electronic chips 100a, 100b for controlling the display of the pixels Px of the matrix of pixels Px. Such a display 1000, an exemplary embodiment of which is illustrated in FIG. 6, has the advantage that it can be manufactured with a limited number of references of electronic chips 100a, 100b and that the space occupied by such electronic chips 100a, 100b, in particular at the periphery of the matrix of pixels framed in dotted lines in FIG. 6, can be limited. In the event of the presence of a single electronic chip 100 as described in the display 1000, it is understood that its first and second circuits 101, 102 are functional.

[0046] In a particular case, the electronic chip 100 can be configured to present: • a first configuration in which the first circuit 101 is active while the second circuit 102 is inactive (figure 1); • a second configuration in which the second circuit 102 is active while the first circuit 101 is inactive (figure 2). The choice of configuration here makes it possible to limit the references of 100 electronic chips in the context of the manufacture of devices using one or more 100 electronic chips, such as for example the 1000 display described above, and therefore to improve the management of the supply chain for 100 electronic chips. Of course, it follows from what has been described previously that this choice also makes it possible to greatly limit the number of external connection terminals 103, for example by dividing it by two compared to a conventional electronic chip which would have a number of external connection terminals equal to the sum of the number of first connection terminals and the number of second connection terminals. Therefore, the electronic chip 100 makes it possible to have a reduced size and a satisfactory cost, in particular when it is of the “pad limited” type. In the first configuration, the switches 106 are in particular all in their first state. In the second configuration, the switches 106 are in particular all in their second state.

[0047] The first circuit 101 can be considered active when at least one (or more or all) of its first connection terminals 104 is electrically connected to one of the external connection terminals 103 using one of the corresponding switches 106 in its first state. The first circuit 101 can be considered inactive when none of its first connection terminals 104 is electrically connected to any of the external connection terminals 103 of the electronic chip 100.

[0048] The second circuit 102 can be considered active when at least one (or more or all) of its second connection terminals 105 is electrically connected to one of the external connection terminals 103 using one of the corresponding switches 106 in its second state. The second circuit 102 can be considered inactive when none of its second connection terminals 105 is electrically connected to any of the external connection terminals 103 of the electronic chip 100.

[0049] When the first circuit 101, or the second circuit 102, is inactive and the electronic chip 100 is operating in the display 1000, the first circuit 101 or the second inactive circuit 102 can be switched off, i.e. not powered to limit the overall energy consumption of the electronic chip 100.

[0050] Of course, when the first circuit 101, or the second circuit 102, is active and the electronic chip 100 is operating in the display 1000, this first or second active circuit 101, 102 can be supplied with energy to ensure its electronic function.

[0051] In particular, the number of external connection terminals 103 may be such that: • in the first configuration, each first connection terminal 104 is electrically connected to only one of the external connection terminals 103 and none of the second connection terminals 105 is electrically connected to any of the external connection terminals 103; • in the second configuration, each second connection terminal 105 is electrically connected to only one of the external connection terminals 103 and none of the first connection terminals 104 is electrically connected to any of the external connection terminals 103. This is of course ensured by the states of the switches 106. Thus, the number of external connection terminals 103 can be adapted to the design of the electronic chip 100 according to the circuits (at least the first and second circuits 101, 102) that it integrates in order to ensure the chosen electronic function; either by choosing to use the electronic chip 100 to implement the electronic function of the first circuit 101, or by choosing to use the electronic chip 100 to implement the electronic function of the second circuit 102.

[0052] It is possible for all the switches 106 to be in the same state, for example in the case of a display 1000 with one hundred lines of pixels and a chip 100 as described comprising one hundred switches 106, implying that the one hundred switches 106 are in their first state making it possible to connect one by one, via the external connection terminals 103, the one hundred lines of the display 1000 to the first one hundred connection terminals 104 of the first circuit 101, which is then a “line driver” circuit, i.e. a circuit making it possible to control the lines of pixels of the display 1000.In another example, if the display 1000 comprises more than one hundred lines of pixels, then an electronic chip 100 as described with one hundred switches 106 may be such that ninety-nine of its switches 106 make it possible (via their first state) to connect ninety-nine lines of pixels of the display 1000, via ninety-nine external connection terminals 103 of the chip 100, to ninety-nine first connection terminals 104 of the first circuit 101 which is then a “line driver” circuit, and the remaining switch 106 (i.e. the hundredth) makes it possible to ensure chaining to another electronic chip which connects other lines of pixels to be controlled of the display 1000. What is described in this paragraph may also apply to connecting columns of pixels of the display 1000, and in this case the switches 106 are in their second state so that the second circuit 102 is active and serves as a “column driver” circuit, iea circuit for controlling the pixel columns of the display 1000.

[0053] In particular, the number of external connection terminals 103 may be strictly less than the sum of the number of first connection terminals 104 and the number of second connection terminals 105. This makes it possible to limit the number of external connection terminals 103 when they are intended to be used to be connected either to the first circuit 101 or to the second circuit 102. Thus, the surface area of ​​the electronic chip 100 may be limited, which is particularly advantageous when it is of the “Pad Limited” type. Preferably, the number of external connection terminals 103 may be equal to the largest of the numbers chosen from the number of first connection terminals 104 and the number of second connection terminals 105 in order to ensure that the necessary connections can be made by the switches 106 according to their state chosen from the first state and the second state.Of course, those skilled in the art will understand that this can also apply to N circuits (including at least the first circuit 101 and the second circuit 102) formed on the electronic chip 100 and each being able to be activated while the other N1 circuits remain in the inactive state; in this case, the number of external connection terminals 103 can be:. • strictly less than the sum of the number of connection terminals, of the N circuits, connectable via switches 106 to external connection terminals 103; and • for example equal to the number of connection terminals of the circuit, chosen from the group of N circuits, having the greatest number of connection terminals connectable to the external connection terminals 103 via the switches 106. Here N is a positive integer greater than or equal to 3 and the switches 106 can comprise N states in order to ensure, as desired, the establishment of the desired electrical links.

[0054] The electronic chip 100 may comprise a control circuit 107, also called a controller, electrically connected to the first circuit 101 and to the second circuit 102 as shown by way of example in FIGS. 1 to 4. In this case, the control circuit 107 is configured to control any of the first and second circuits 101, 102. By "control", it is here understood in particular to control the operation for example by transmitting to it suitable data to be processed and, where appropriate, signals intended for the timing of its operation (e.g. signals conventionally used in the field of display such as a synchronization signal, a clock signal, an output activation signal, a scanning direction signal).The output activation signal may, for example in the case of a shift register of the corresponding circuit (where appropriate the first circuit 101 or the second circuit 102), validate when data is authorized at the output of the shift register for edge synchronization reasons. Thus, the electronic chip 100 may further integrate a control function making it possible to control any of the first and second circuits 101, 102 for example depending on which one is ultimately active. The integration of a control function (i.e. the control circuit 107), when this control function is necessary, of the first and second circuits 101, 102 allows the electronic chip 100 not to require an external chip to control it.For example, in the field of application of displays 1000 intended to display a video, the electronic chip 100 may comprise a vertical signal input, a horizontal signal input and a clock signal input connected to the control circuit 107 which then determines, as a function of the clock signal and one or other of the vertical and horizontal signals, within the electronic chip 100 the signals necessary for the operation, where appropriate, of the first circuit 101 or the second circuit 102. Furthermore, this integration also makes it possible to simplify the electronic interfaces in the sense that the communication between the control circuit 107 and the first and second circuits 101, 102 will be directly provided within the electronic chip 100.Although it is preferred to integrate the control circuit 107 into the electronic chip 100 for the reasons mentioned above, it is of course possible not to do so and therefore to relocate the control circuit 107 within an electronic control chip, external to the electronic chip 100, which will be electrically connected to said electronic chip 100.

[0055] Generally, the control circuit 107 is configured to organize the operation, if applicable, of the first circuit 101 or of the second circuit 102 by providing it with electrical control and configuration signals.

[0056] In particular, the first circuit 101 is configured to process first data in order to perform its function and the second circuit 102 is configured to process second data in order to perform its function, the first data and the second data being different. These first or second data can be sent to the first circuit 101 or to the corresponding second circuit 102 via the control circuit 107.

[0057] The display 1000, also called a display panel, has been mentioned previously and can advantageously integrate several electronic chips 100. The pixels Px of the pixel matrix Px of the display 1000 are in particular capable of being controlled to produce a display, for example of images and in particular in the form of a video stream. Each pixel Px may comprise light-emitting diodes (not shown), such as LEDs (acronym for "Light-Emitting Diodes" in English) or OLEDs, to allow the pixel to emit at a desired wavelength. Conventionally, the pixels Px of the pixel matrix Px are ordered in columns and rows so as to form a display panel 1001 (figure 6). These pixels Px can be controlled using one or more pixel row control circuits and one or more pixel column control circuits which are, taken independently, standard circuits well known to those skilled in the art.In the present case, it is advantageously proposed to use electronic chips 100 as described to control the pixel lines (e.g. electronic function of the first circuit 101) and the pixel columns Px (e.g. electronic function of the second circuit 102). For this purpose, the display 1000 may comprise at least one first electronic chip 100a, and in particular first electronic chips 100a, the or each first electronic chip 100a corresponding to the electronic chip 100 as described for which the first circuit 101 is active and forms a circuit for controlling pixel lines of the display 1000, and at least one second electronic chip 100b, and in particular second electronic chips 100b, the or each second electronic chip 100b corresponding to the electronic chip 100 for which the second circuit 102 is active and forms a circuit for controlling pixel columns of the display 1000.In Figure 6, the number of first electronic chips 100a is equal to two and the number of second electronic chips 100b is equal to two; this is only illustrative in the sense that the number of electronic chips 100a, 100b within the display 1000 depends in particular on the resolution of the display 1000 in terms of number of pixels Px and the capacities of the electronic chips 100a, 100b used in terms of number of lines of pixels or number of columns of pixels that they are each able to control. For example, the use of several electronic chips 100 to control the lines of pixels and / or the columns of pixels may be imposed by the fact that:. • the pixel matrix Px comprises n columns of pixels Px and p rows, with n>q where q is the number of second connection terminals 105 in the electronic chips 100 and / or with p>r where r is the number of first connection terminals 104 in the electronic chips; • several electronic chips 100a with the first active circuit 101 are used if p>r; • several electronic chips 100b with the second active circuit 102 are used if n>q; • in case of several 100a electronic chips with the first active 101 circuit used they can be chained; • if several 100b electronic chips with the second active 102 circuit are used, they can be chained.

[0058] Thus, to satisfy the need to be used in the context of the display 1000 for example such as that described in the preceding paragraph, the electronic chip 100 may be such that: at least a portion of the external connection terminals 103 (i.e. all or part of the external connection terminals 103) are intended to be electrically connected each to a circuit for controlling a pixel of the display 1000; the first circuit 101 is a circuit for controlling rows of pixels of the display 1000; the second circuit 102 is a circuit for controlling columns of pixels of the display 1000.

[0059] By "control circuit of a pixel of the display" it is understood that the control circuit of the pixel (in particular integrated in Px in figure 6 which also includes the pixel to be controlled) controls the emission of photons by the pixel according to the information received via an electronic chip whose first circuit 101 is active and an electronic chip whose second circuit 102 is active connected to said control circuit of the pixel within the display 1000 by one of the lines of pixels and one of the columns of pixels respectively to address the control circuit of the pixel according to the line of pixels which includes it and the column of pixels which includes it.

[0060] For example, each row of pixels of the display 1000 is connected to one of the stages of a first circuit 101 of a corresponding electronic chip 100 and each column of pixels of the display 1000 is connected to one of the stages of the second circuit 102 of a corresponding electronic chip 100.

[0061] In the context of the display 1000 and in the case where the electronic chip 100 integrated into this display 1000 has the first active circuit 101 and the second inactive circuit 102, the first circuit 101 is connected, via all or part of the external connection terminals 103 of said electronic chip 100, to lines of pixels, with an external connection terminal 103 electrically connected to only one of said lines of pixels, which results in the connection of the pixel control circuits of each of said lines of pixels, for example to a stage of said first circuit 101.In the context of the display 1000 and in the case where the electronic chip 100 integrated in this display 1000 has the first inactive circuit 101 and the second active circuit 102, the second circuit 102 is connected, via all or part of the external connection terminals 103 of said electronic chip 100, to columns of pixels, with an external connection terminal 103 electrically connected to only one of said columns of pixels, which results in the connection of the pixel control circuits of each of said columns of pixels for example to a stage of said. second circuit 102. Therefore, by using at least two electronic chips 100, each pixel Px connected to these two electronic chips 100 can be addressed according to its position in the pixel matrix given by the row of pixels to which it is connected (i.e. to the row of pixels which includes it) and the column of pixels to which it is connected (i.e. to the column of pixels which includes it). In particular, the first and second circuits 101, 102 make it possible, by being used in synergy using two electronic chips 100, one of which has its first circuit 101 active and the other has its second circuit 102 active, to store digital information in pixels of the display 1000 and to control the light emission, for example, of light-emitting diodes of the pixels according to the values ​​of the digital information stored in the pixels.Thus, such an electronic chip 100 has the advantage of having two electronic functions respectively to allow the control / command of pixels Px either in rows or in columns while benefiting from a reduced number of external connection terminals 103 by limiting or avoiding for example having unused external connection terminals 103 of the electronic chip 100 when one of the two electronic functions (i.e. of the first circuit 101 or of the second circuit 102) will be active while the other of the two electronic functions will be inactive. Electronic chips 100 can thus be manufactured so as to offer the two electronic functions of pixel row control and pixel column control, the activation of one of the electronic functions then being able to be done subsequently within the display 1000.

[0062] In other words, it is for example possible to choose the way in which the electronic chip 100 is used in the display 1000: either the first circuit 101 is active (as for the electronic chips 100a shown in FIG. 6) and the switches 106 are then in their first state, or the second circuit 102 is active (as for the electronic chips 100b shown in FIG. 6) and the switches 106 are in their second state. If the first circuit 101 is active then its first connection terminals 104 are electrically connected to all or part of the external connection terminals 103 which are themselves each electrically connected to a row of pixels Px of the display 1000. In particular, all the pixels of the same row of pixels of the display 1000 have at least one common electrode (i.e. these pixels are electrically connected to each other) for the application of a potential VCC.If the second circuit 102 is active then its second connection terminals 105 are electrically connected to all or part of the external connection terminals 103 which are themselves each electrically connected to a column of pixels Px of the display 1000.

[0063] According to a particular embodiment, the electronic chip 100 may comprise a write mode and a read mode. The pixel row control circuit, i.e. the first circuit 101, makes it possible, in the write mode, to control the selection of a complete pixel row of the display 1000. Thus, if necessary, the first data may be used by the first circuit 101 to determine the pixel row Px to be selected. The pixel column control circuit, i.e. the second circuit 102, allows, in the write mode, to load digital data, if applicable from the second data, into the pixels to which the second circuit 102 is connected and belonging to a line of pixels selected by the first circuit 101 of another electronic chip 100. The pixel line control circuit allows, in the read mode and for each line of pixels Px electrically connected to said pixel line control circuit, to control the emission of each pixel Px of said line of pixels and the light emission of said pixel controlled by pulse width modulation in a synchronized manner on the line of pixels by the pixel line control circuit; the information necessary for controlling the emission of the pixels is contained in the first data.

[0064] Switches 106 have been described above, the state of which, in particular chosen from the first state and the second state, makes it possible to define to what the external connection terminals 103 within the electronic chip 100 are electrically connected, via the electrical links. This being the case, there is a need to make it possible to implement an easy choice of the state of each of the switches 106. To meet this need, the electronic chip 100 may comprise means 108 for enabling the configuration of the switches 106; i.e. enabling the configuration of the state in which they are each found, chosen from the first state and the second state. Different embodiments of these means are illustrated in FIGS. 1 to 4.

[0065] According to one embodiment, these means 108 for enabling the configuration of the switches 106 comprise a configuration input 109 electrically connected to each of the switches 106 so as to enable the propagation, from the configuration input 109, of a configuration signal for the switches 106. This embodiment is notably that illustrated in figures 1 and 2 and can be implemented using switches 106 formed by NMOS transistors (N-type “Metal Oxide Semiconductor” transistors for N-type insulated gate transistors) each connected to the configuration input 109 to determine the state of the corresponding switch 106.For example, a switch 106 may be formed by a first NMOS transistor electrically connected to the corresponding first connection terminal 104 and to the external connection terminal 103 and a second NMOS transistor electrically connected to the corresponding second connection terminal 105 and to said external connection terminal 103. The first and second NMOS transistors are controlled by a signal S (corresponding to the logic signal mentioned above), the signal S propagating according to one example directly to a gate electrode of the first NMOS transistor and, according to this example, via an inverter to a gate electrode of the second NMOS transistor so that when the first NMOS transistor is on the second NMOS transistor is off (i.e.the first connection terminal 104 is electrically connected to the external connection terminal 103 while the second connection terminal 105 is electrically isolated from the external connection terminal 103) and conversely when the second NMOS transistor is on the first NMOS transistor is off (i.e. the second connection terminal 105 is electrically connected to the external connection terminal 103. while the first connection terminal 104 is electrically isolated from the external connection terminal 103). Thus, the same configuration signal (e.g., the signal S) makes it possible to simultaneously configure all the switches 106 of the electronic chip 100. Furthermore, the use of the same configuration signal has the advantage that the electronic chip 100 concerned can be configured in an application external to the electronic chip 100, from which it follows that the electronic chip 100 does not need to be programmable: the propagation of the configuration signal generated by the external application and applied to the configuration input 109 within the chip 100 (in particular via wiring directly carried out within a printed circuit of the electronic chip 100) is sufficient.Of course, the means 108 for enabling the configuration of the switches 106 may also comprise a track 110 connecting the configuration input 109 to the switches 106 to enable the propagation of the configuration signal.

[0066] Alternatively to the solution described in the previous paragraph to meet the need to choose the state of each of the switches 106, the means 108 for enabling the configuration of the switches 106 may comprise, as for example illustrated in FIGS. 3 and 4, memory cells 111, for example of 1 bit each, each associated with one of the switches 106 to enable the operation of said switch 106 to be configured and therefore to enable the state of the latter to be chosen at least from the first state and the second state. In particular, here a static or fixed programmable memory cell is required for each pair of stages of the first circuit 101 and of the second circuit 102, the stages of which are each capable of being electrically connected selectively to the same corresponding switch 106.Each memory cell can be configurable by a configuration function implemented in the control circuit 107, for example in configuration registers (which can be simple shift registers) of the control circuit 107 of said electronic chip 100. Furthermore, this is advantageous when the number of rows of pixels or the number of columns of pixels is not an integer multiple of the number of stages of the first circuit 101 or of the second circuit 102: it can then be envisaged to share the operation of the electronic chip 100 so that the two electronic functions are active (i.e. that the first and second circuits 101, 102 are active), this allows an optimization of the number of circuits and therefore of the cost of the display 1000.

[0067] For example, it is possible to configure each memory cell by the configuration function implemented in the control circuit 107 in the following manner. When the display 1000 or any device comprising the electronic chip(s) 100 is started, the control circuit 107 of each electronic chip 100 will read the state that each of its switches 106 must have in an installation memory and through a control bus 117 of the memory cells 111 making it possible to control the memory cells 111 (the control bus 117 making it possible to configure the switches 106 is visible in figures 3 and 4), the control circuit 107 writes the state of each of the switches 106 in each memory cell 111.

[0068] Preferably, each memory cell 111 is configurable in a definitive (in this case each memory cell 111 can be of the ROM type, acronym for "read only memory"). In this case, when an electronic chip 100 has been activated by choosing the operation of its first circuit 101 or its second circuit 102, it is no longer possible to change this operation. Therefore, a corresponding circuit (i.e. the first circuit 101 or the second circuit 102) within the display 1000 is connected either to a row of pixels or to a column of pixels of the display 1000 definitively: any change in electronic function means that the display 1000 no longer functions correctly because this would amount to placing a signal for a row of pixels on a column of pixels and conversely a signal for a column of pixels on a row of pixels.

[0069] According to one embodiment, the first and second circuits 101, 102 are preferably digital circuits, therefore the first connection terminals 104 and the second connection terminals 105 all support the same low level voltage and the same high level voltage, in particular these voltages are also supported by the external connection terminals 103. This has the advantage that the first and second connection terminals 104, 105, and in particular the external connection terminals 103, can be dimensioned in a similar and as precisely as possible manner so as not to have to support different voltage amplitudes dependent on the electronic function chosen to be implemented from among the electronic function of the first circuit 101 and the electronic function of the second circuit 102.In particular, by "the first and second circuits 101, 102 are digital circuits", it is understood that the latter are entirely digital, that is to say that they do not implement an analog function. Of course, the first and second circuits 101, 102 could also be hybrid, i.e. have digital and analog functions.

[0070] An advantage of using digital circuits is that it allows the use of 100 electronic chips within the 1000 display to be rationalized. Indeed, in LCD or OLED type displays, the control circuits for rows of pixels and columns of analog pixels are generally different and difficult to combine within the same electronic chip, except by over-sizing its internal electrical connections, because the voltages required at the external connection terminals are very different depending on the electronic function. For example, for an LCD display, the voltage on the rows of pixels can go up to 45 V and the voltage on the columns of pixels can go up to 13 V with an accuracy of 5 mV in the digital to analog conversion.For example, for an OLED display, the voltage on the pixel rows can be up to 25 V and the voltage on the pixel columns can be up to 10 V with an accuracy of 5 mV in the digital to analog conversion. Offering pixel row and pixel column driver circuits provides an opportunity to integrate the corresponding electronic functions by using compatible external connection terminals 103 for both electronic functions since the voltage levels will then be identical for both electronic functions. Of course, it is then appropriate that the pixels Px of the display. 1000 are digital and, in particular, are in digital control in line and in column.

[0071] In the context of the display 1000, it has been mentioned above the possibility that several electronic chips 100 are necessary for the proper functioning of the display of the pixels Px of the display panel 1001; these electronic chips then being distributed according to one or more first electronic chips 100a and one or more second electronic chips 100b. Therefore, the display 1000 can in particular be such that it will comprise a set of first electronic chips 100a connected to the same first data bus 1006 and chained in series to control the pixels Px according to their row and a set of second electronic chips 100b connected to the same second data bus 1007 and chained in series to control the pixels Px according to their column. Therefore, there is a need to allow the chaining of electronic chips 100, also called cascade connection, within the display 1000. For this purpose, the electronic chip 100 may comprise achaining output 112 (as illustrated for example in figures 1 and 4) intended to be electrically connected to another electronic chip 100; this chaining output 112 makes it possible in particular to synchronize the processing of data received by the electronic chips 100 chained together (for example, these data correspond to the first data received by the electronic chips 100 connected to the first data bus 1006 or to the second data received by the electronic chips 100 connected to the second data bus 1007) in the sense that the chaining output 112 makes it possible to send a chaining signal to another electronic chip 100 to indicate to it the end of the processing sequence by the electronic chip 100 which precedes it and which sent it said chaining signal in order to authorize said other electronic chip 100 to begin its own processing sequence of the data which it has received, where appropriate, by the first data bus 1006 or by the second data bus1007 of data. Therefore, the chaining output 112 participates in forming, where appropriate, the set of first electronic chips 100a or the set of second electronic chips 100b within the framework of the display 1000 and in sequencing in an appropriate manner the data processing to be carried out by each of the electronic chips 100 (where appropriate, the first electronic chips 100a or the second electronic chips 100b).

[0072] Of course, the electronic chip 100 may comprise a data reception input 113 (visible in particular in figures 1 to 4). It is to this data reception input 113 that, if necessary, the first data bus 1006 or the second data bus 1007 is connected within the framework of the display 1000. The data appearing on the data reception input 113 during operation of the electronic chip 100 are intended to be processed by the electronic chip 100, for example in whole or in part by the first circuit 101 or by the second circuit 102 and, if necessary, by the control circuit 107 of the electronic chip 100. For example, the control circuit 107 is electrically connected to the data reception input 113 as shown in figures 1 to 4, which then allows it, in operation, to control / command in an appropriate manner the first circuit 101 or the second circuit 102 by exploiting the data received via the data reception input 113. In particular, when the electronic chip 100 concerned has its first circuit 101 active within the display 1000, its data reception input 113 is such that the data received are preferably synchronization signals, in particular for synchronizing the operation of the pixels. In particular, when the electronic chip 100 concerned has its second circuit 101 active within the display 1000, its data reception input 113 is such that the data received are preferably display data to be displayed by the display 1000.As mentioned above, the data reception inputs 113 of several electronic chips 100 can be connected to the same data bus (first data bus 1006 or second data bus 1007) so that the electronic chips 100 receive data that they can process in whole or in part in a sequential manner, for example using the propagation of the chaining signal in a sequential manner to the electronic chips 100 intended to control lines of pixels or columns of pixels of the display 1000.

[0073] The electronic chip 100 may further comprise a chaining input 115 as for example visible in figures 1, 4 and 7. This chaining input 115 may be connected to the first circuit 101 and to the second circuit 102. This chaining input 115, of the so-called current electronic chip 100, is intended to be connected, if necessary, to the chaining output 112 of a previous electronic chip 100. In this case, as long as the previous electronic chip 100 does not emit the chaining signal, the operation of the first active circuit 101 or of the second active circuit 102 of the current electronic chip 100 is inhibited to satisfy the synchronization needs.Of course, when the electronic chip 100 concerned does not have a previous electronic chip 100, the operation of the first circuit 101 or of the second circuit 102 is not inhibited and in this case the chaining signal can come directly from an external controller which makes it possible to ensure vertical or horizontal synchronization of a corresponding video. In fact, the external controller belongs to the display 1000 and is notably configured to clock the writing of video information (images) in the pixels of the display 1000; the images are then presented sequentially for their writing in said pixels, and the horizontal and vertical synchronization signals trigger or clock the writing of each image in said pixels, thus defining when and how the image must be written in said pixels.

[0074] Therefore, the data reception inputs 113, the chaining output(s) 112 and the chaining input(s) 115 of several electronic chips 100 make it possible to form the set of first electronic chips 100a or the set of second electronic chips 100b within the framework of the display 1000, the operation of which can then be sequenced in an appropriate manner.

[0075] In the context of the display 1000, the chaining of the electronic chips 100 makes it possible to guarantee the writing of the new image at each frame of a video to be displayed on the display 1000

[0076] According to a particular example, the chaining output 112 is constituted by one of the external connection terminals 103, as for example visible in figures 1 and 4. In this particular example: • when it is active, the first circuit 101 is configured to emit the chaining signal via one of its first connection terminals 104 only after having sent a signal to each of the external connection terminals 103 electrically connected to a corresponding pixel line of the display 1000, this can advantageously be ensured when the first circuit 101 has a succession of stages, some of which stages are electrically connected to the pixel lines, the last stage of the succession of stages of the first circuit 101 is then electrically connected to said one of its first connection terminals 104 and is configured to ensure the propagation of the chaining signal; • when it is active, the second circuit 102 is configured to emit the chaining signal via one of its second connection terminals 105 only after having sent a signal to each of the external connection terminals 103 electrically connected to a corresponding column of pixels of the display 1000, this can advantageously be ensured when the second circuit 102 has a succession of stages, some of which stages are electrically connected to the columns of pixels, the last stage of the succession of stages of the second circuit 102 is then electrically connected to said one of its second connection terminals 105 and is configured to ensure the propagation of the chaining signal; • in the first state of the switch 106 electrically connected to the chaining output 112, the first connection terminal 104 intended to emit the chaining signal is electrically connected to said switch 106; • in the second state of the switch 106 electrically connected to the chaining output 112, the second connection terminal 105 intended to emit the chaining signal is electrically connected to said switch 106. This makes it possible to ensure, for two consecutive electronic chips 100, that the following electronic chip 100 only begins its processing via its first or second circuit 101, 102 when the electronic chip 100 preceding it has completed its processing via its first or second circuit 101, 102. Thus, it follows that one of the first connection terminals 104 of the first circuit 101 and one of the second connection terminals 105 of the second circuit 102 are reserved, where appropriate, to ensure the chaining of chips 100 electronics. Preferably, this is the first terminal 104 of the first circuit 101 and the second terminal 105 of the second circuit 102 which are generally used last in the context of the processing carried out by the corresponding circuit for example on a given image of a video stream to be displayed by the display 1000. It results from this paragraph that, within the display 1000 and this being in particular valid for each electronic chip 100 of the display 100 having its chaining output 112 electrically connected to the chaining input 115 of another of the electronic chips of the display 1000, the external connection terminal 103 of said electronic chip 100 dedicated to chaining is neither electrically connected to a row of pixels of the display 1000 nor electrically connected to a column of pixels of the display 1000.

[0077] The presence of stages within the first circuit 101 and the second circuit 102 makes it possible to induce a temporality of data processing and to ensure that the last active stage (i.e. in the temporal sense) of the corresponding succession of stages is, as the case may be, connected to a row of pixels, a column of pixels or to the chaining output 112 to be connected to a circuit, where appropriate the first circuit 101 or the second circuit 102, of another electronic chip 100.

[0078] In other words, the chaining function that the first circuit 101 and / or the second circuit 102 comprise can be provided by a shift register internal to the first circuit 101 whose last stage is connected to the chaining output 112 via the first corresponding connection terminal 104 when the associated switch 106 is in its first state and / or by a shift register internal to the second circuit 102 whose last stage is connected to the chaining output 112 via the second corresponding connection terminal 105 when the associated switch 106 is in its second state. This allows the chaining signal to be automatically transmitted to the chaining output 112 when the processing to be carried out by the first circuit 101, or the second circuit 102, is finished.

[0079] The chaining signal sent to the chaining output 112 can also come from a last stage of a shift register, integrated into the electronic chip 100, which would control the loading of data into memory registers associated, where appropriate, with the lines of pixels of the display 1000 or with the columns of pixels of the display 1000.

[0080] In the following, reference is made to a set of chained electronic chips 100. What is described in connection with this set of electronic chips 100 can in particular apply indifferently to the set of first electronic chips 100a and to the set of second electronic chips 100b.

[0081] In particular, the set of chained electronic chips comprises (see figure 7 as an example) a primary 100e electronic chip and a final 100g electronic chip between which one or more intermediate 100f electronic chips is / are arranged (an intermediate 107f electronic chip in the example).The primary 100e electronic chip, the intermediate 100f electronic chip(s) and the last 100g electronic chip are in particular all physically identical, which makes it possible to limit the references of 100 electronic chips to be used in said set of 100 electronic chips; in particular, the 100 electronic chips of the set of first 100a electronic chips and the 100 electronic chips of the set of second 100b electronic chips are also physically identical in the sense that they can be interchanged so that, for example, only the wiring external to the 100 electronic chips, in particular via the external terminals 103 of the 100 electronic chips, has an influence on their operation, i.e. the electronic chips are in particular all produced by the same manufacturing process.

[0082] Preferably, within the display 1000, the primary electronic chip 100e, the intermediate electronic chip(s) 100f and the last electronic chip 100g each receive data (the first data or the second data as the case may be) on their data reception input 113 due to the connection of these chips 100e, 100f, 100g, via their reception input 113, to a data bus 116 (either the first data bus 1006 mentioned above or the second data bus 1007 mentioned above) making it possible to process the pixels Px of the display 1000 either according to their row or according to their column.The chaining output 112 of the primary electronic chip 100th is electrically connected to the chaining input 115 of the or one of the intermediate electronic chip(s) 100f of the set of electronic chips and so on until the chaining output 112 of one of the electronic chips (the intermediate electronic chip 100f in the example illustrated in FIG. 7) is electrically connected to the chaining input 115 of the last electronic chip 100g of the electronic chips of the set of electronic chips.In other words, for any intermediate 100th electronic chip of the set of electronic chips and located between the primary 100th electronic chip of this set of 100 electronic chips and the last 100g electronic chip of this set of 100 electronic chips, its chaining output 112 is electrically connected to the chaining input 115 of one of the electronic chips of the set of electronic chips and its chaining input 115 is electrically connected to the chaining output 112 of another of the electronic chips of the set of electronic chips. This allows the primary 100th electronic chip, the intermediate 100th electronic chip(s) and the last 100g electronic chip to process the data sequentially; iean electronic chip having a chaining output 112 of a previous electronic chip connected to its chaining input 115 waits to receive on its chaining input 115 the chaining signal from the previous electronic chip to process the data received at its data reception input 113. In particular, in FIG. 6, connecting elements 114a, 114b show the chaining of the first electronic chips 100a and the second electronic chips 100b.

[0083] According to an embodiment not shown, the control circuits 107 may have a role to play in the chaining of the electronic chips 100e, 100f, 100g of the set of electronic chips. For example, as mentioned above, each control circuit 107 may decide when to send a chaining signal to the chaining output 112 of the electronic chip 100e, 100f, 100g that comprises it. Although this embodiment is possible, it is generally the first active circuit 101 or the second active circuit 102 that activates the propagation of the chaining signal at the desired time to ensure the synchronization of a series of electronic chips 100 chained together and connected to the same data bus 116 via their data reception input 113.

[0084] According to one embodiment, the control circuit 107 of the primary electronic chip 100th of the set of electronic chips can be a master circuit and it makes it possible to synchronize the operations of all the control circuits 107, then called slave control circuits, of the other electronic chips of the set of electronic chips. (i.e. the intermediate electronic chip(s) and the last electronic chip of the corresponding series) in the sense that the control circuits 107 of the other electronic chips can be electrically connected in series from the control circuit 107 of the 100th primary electronic chip. According to this embodiment, for each electronic chip 100, its chaining input 115 is connected to its control circuit 107 and its chaining output 112 is connected to its control circuit which then ensures the desired synchronization. In fact, the control circuit 107 of the 100th primary electronic chip of the set of electronic chips is considered to be the master circuit because it is the only one to receive the global synchronization information for the corresponding set of electronic chips and it initiates the scanning, i.e.that triggering the operation of the 100th primary electronic chip will induce the sequential propagation of the processing of the data received by the other electronic chips of said set of electronic chips chained in series from the 100th primary electronic chip. In this case, it is possible to transmit, within the same set of electronic chips and in a manner resulting from the operation of the control circuit 107 of the 100th primary electronic chip of this set of electronic chips, a chaining signal whose function is to synchronize the electronic chips of the set of electronic chips. In particular, as soon as a 100th, 100f, 100g electronic chip of the set of electronic chips has finished its work and when a following electronic chip in the series is present, it sends, preferably automatically, the chaining signal.

[0085] It is noted that if the electronic chips 100 are each such that the chaining input 115 is directly connected to the first and second circuits 101, 102 and the chaining output 112 is directly connected to the first and second circuits 101, 102, the control circuits 107 are then, apart from the control circuit 107 of the primary electronic chip 100th, are almost inactive, that is to say that they each have reduced functionality compared to the control circuit 107 of the primary electronic chip 100th.

[0086] Depending on requirements, the chaining input 115 can be electrically connected to the control circuit 107 and to the first and second circuits 101, 102 (not shown).

[0087] Alternatively, the master circuit can directly send the chaining signal that controls / commands the tasks of the slave circuits. In this case, the master circuit indicates by a change in the state of the chaining signal that the relevant electronic chip must start working. Therefore, for a given set of electronic chips, the electronic chip that comprises the master circuit is connected to all the other electronic chips of said set of electronic chips in order to appropriately control the synchronization of said other electronic chips by sending a specific synchronization signal for each of said other electronic chips. In order to change the state of the signal appropriately, the master circuit can count the number of clock ticks corresponding to the number of stages activated in each electronic chip of the set of electronic chips.

[0088] Regarding the display 1000, it may include an image processing chip 1002 configured to: • sending first control signals 1003, via the first data bus 1006 of the display 1000, to the electronic chips 100a whose first circuits 101 are active, these first control signals 1003 including at least vertical synchronization data generated by the image processing chip 1002; • sending second control signals 1004, via the second data bus 1007 of the display 1000, to the electronic chips 100b whose second circuits 102 are active, these second control signals including at least horizontal synchronization data generated by the image processing chip 1002; • send display data 1005, via the second data bus 1007 of the display 1000, to the electronic chips 100b whose second circuits 102 are active. In fact, vertical synchronization triggers the successive activation of the lines of pixels (or vertical scanning) clocked by a line clock and horizontal synchronization triggers the transfer of data on the columns of pixels (horizontal scanning). In particular, the first data mentioned above include, or are constituted by, the first control signals, and the second data mentioned above include, or are constituted by, the display data and the second control signals. This makes it possible to write in the display 1000 the information of a video to be displayed according to a line-by-line scanning of pixels. Therefore, in general, the control circuit 107 can be configured to: • send vertical control signals (ie the first signals 1003) to the first circuit 101; • send horizontal control signals and data to be displayed (i.e. the second signals 1004 and the display data 1005) to the second circuit 102. This is suitable for displaying images.

[0089] The electronic chip 100 as described finds industrial application in the field of electronic chips 100 with several integrated functions that can be partially or fully activated. For example, such an electronic chip 100 can be used, as discussed above, as an integrated display chip comprising at least one pixel row driver circuit and one pixel column driver circuit in which any of the pixel row driver circuit and the pixel column driver circuit can be activated either in software or in hardware.

[0090] In summary and according to its characteristics, the 100 electronic chip as described has the following advantages: • it has a reduced size; • it has a reduced manufacturing cost in terms of substrate surface area required to form the external connection terminals, thus making it possible, for example, to limit the silicon used for an electronic chip in question (a multifunction electronic chip with configurable internal connection of circuits - i.e. the first and second circuits 101, 102 - to the external connection terminals 103 makes it possible to reduce the silicon surface area used in comparison with an electronic chip in which each of the circuits would be permanently connected to external connection terminals); • it can be easily integrated into a 1000 display; • it makes it possible to reduce the number of connection components in the box that must integrate said electronic chip 100.

Claims

Tl Claims 1. Electronic chip (100) comprising a first circuit (101) associated with an electronic function and a second circuit (102) associated with an electronic function different from the electronic function of the first circuit (101), the electronic chip (100) comprising external connection terminals (103), the first circuit (101) comprising first connection terminals (104) and the second circuit (102) comprising second connection terminals (105), characterized in that the electronic chip comprises switches (106) each electrically connected to one of the external connection terminals (103), to one of the first connection terminals (104) and to one of the second connection terminals (105), each switch (106) being configured to selectively adopt: • a first state from which it results that an electrical link is formed between the external connection terminal (103) to which said switch (106) is electrically connected and the first connection terminal (104) to which said switch (106) is electrically connected; • a second state from which it results that an electrical link is formed between the external connection terminal (103) to which said switch (106) is electrically connected and the second connection terminal (105) to which said switch (106) is electrically connected.

2. Electronic chip (100) according to claim 1, characterized in that it is configured to have: • a first configuration in which the first circuit (104) is active while the second circuit (105) is inactive; • a second configuration in which the second circuit (105) is active while the first circuit (104) is inactive.

3. Electronic chip (100) according to claim 2, characterized in that the number of external connection terminals (103) is strictly less than the sum of the number of first connection terminals (104) and the number of second connection terminals (105).

4. Electronic chip (100) according to any one of claims 1 to 3, characterized in that it comprises a control circuit (107) electrically connected to the first circuit (101) and to the second circuit (102), the control circuit (107) being configured to control any of the first and second circuits (101, 102).

5. Electronic chip (100) according to any one of claims 1 to 4, characterized in that: • at least part of the external connection terminals (103) are intended to be electrically connected each to a control circuit of a pixel of a display; • the first circuit (101) is a circuit for driving lines of pixels of the display (1000); • the second circuit (102) is a circuit for controlling columns of pixels of the display (1000).

6. Electronic chip (100) according to claim 5, characterized in that it comprises a chaining output (112) intended to be electrically connected to another electronic chip (100).

7. Electronic chip (100) according to claim 6, characterized in that the chaining output (112) is constituted by one of the external connection terminals (103) and in that: • when it is active, the first circuit (101) is configured to emit via one of its first connection terminals (104) a chaining signal only after having sent a signal to each of the external connection terminals (103) connected to a corresponding line of pixels of the display (1000); • when it is active, the second circuit (102) is configured to emit the chaining signal via one of its second connection terminals (105) only after having sent a signal to each of the external connection terminals (103) connected to a corresponding column of pixels of the display (1000); • in the first state of the switch (106) electrically connected to the chaining output (112), the first connection terminal (104) intended to emit the chaining signal is electrically connected to said switch (106); • in the second state of the switch (106) electrically connected to the chaining output (112), the second connection terminal (105) intended to emit the chaining signal is electrically connected to said switch (106).

8. Electronic chip (100) according to claim 4 and any one of claims 5 to 7, characterized in that the control circuit (107) is configured to: sending vertical control signals to the first circuit (101); • send horizontal control signals and data to be displayed to the second circuit (102).

9. Electronic chip (100) according to any one of claims 1 to 8, characterized in that it comprises means (108) for allowing the configuration of the switches (106).

10. Electronic chip (100) according to claim 9, characterized in that the means (108) to allow configuration of the switches (106) include an input (109) configuration electrically connected to each of the switches (106) so as to allow propagation, from the configuration input (109), of a configuration signal of the switches (106).

11. Electronic chip (100) according to claim 4 and claim 9, characterized in that the means (108) for enabling the configuration of the switches (106) comprise memory cells (111) each associated with one of the switches (106) to enable the operation of said switch (106) to be configured, each memory cell (111) being configurable, preferably definitively, by a configuration function implemented in the control circuit (107).

12. Electronic chip (100) according to any one of the preceding claims, characterized in that the first and second circuits (101, 102) are digital circuits, the first connection terminals (104) and the second connection terminals (105) all supporting the same low level voltage and the same high level voltage.

13. Display (1000) comprising a matrix of pixels (Px) and at least one electronic chip (100a, 100b) according to any one of claims 1 to 12 for controlling the display of the pixels (Px).

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