Interface module for a subscriber station of a serial bus system and method for transmitting a message in a serial bus system

Abstract

The invention relates to an interface module (16) for a subscriber station (10; 30) of a serial bus system (1), and to a method for transmitting differential signals (CAN_H, CAN_L) in a serial bus system (1). In the case of the bus system (1), a transmitting module (121) is designed for transmitting a digital transmission signal (TxD_TC) as an analog differential signal (CAN_H, CAN_L) onto a bus (40) of the bus system (1) in order to transmit a message (45) to at least one other subscriber station (10; 20; 30) of the bus system (1), wherein bits in the digital transmission signal (TxD_TC) have a longer bit duration (t_bt1) in a first communication phase (451) than in a second communication phase (451) of the transmission signal (TxD_TC). The interface module (16) has at least one time measuring block (161; 1621, 1622; 1631, 1632) for measuring, with a predetermined timing clock (TK), a predetermined time (t_SL; t_1; t_bt2) in the digital transmission signal (TxD), wherein the at least one time measuring block (161; 1621, 1622; 1631, 1632) is designed to stop its measurement if the measured value of the at least one time measuring block (161; 1621, 1622; 1631, 1632) has reached a predetermined limit value (GW), and an evaluation block (165) for evaluating the measured value of the at least one time measuring block (161; 1621, 1622; 1631, 1632) at the end of the predetermined time (t_SL; t_1; t_bt2) in order to set the transmitting module (121) for operation in the first communication phase (451) or for operation in the second communication phase (452) on the basis of the evaluation result.

Description

[0001] Description

[0002] Interface module for a subscriber station of a serial and

[0003] Method for sending a message in a serial

[0004] The present invention relates to an interface module for a subscriber station of a serial bus system and a method for sending a message in a serial bus system, which is in particular a CAN XL bus system.

[0005] State of the art

[0006] Serial bus systems, especially CAN bus systems, are used for message or data transmission in technical systems. For example, a serial bus system can enable communication between sensors and control units in a vehicle or a technical production facility, etc.

[0007] In a CAN bus system, messages are transmitted using the CAN and / or CAN FD protocol, as described in the ISO 11898-1:2015 standard as a CAN protocol specification with CAN FD. With CAN FD, transmission on the bus switches between a slow operating mode in a first communication phase (arbitration phase) and a fast operating mode in a second communication phase (data phase). For example, most manufacturers use CAN FD in vehicles with a 500 kbit / s arbitration bit rate and a 2 Mbps data bit rate.

[0008] Successor bus systems to CAN FD, such as CAN-SIC and CAN XL, are compatible with CAN FD and designed for even higher data rates in the second communication phase. With CAN-SIC, according to the CiA601-4 standard of the CAN in Automation (CiA) organization, a data rate of approximately 5 to 8 Mbit / s can be achieved in the second communication phase. CAN XL, according to the CiA601-3 standard, requires a data rate of > 10 Mbit / s in the second communication phase. In addition to pure data transport via the CAN bus, CAN XL is also intended to support other functions, such as functional safety, data security, and quality of service (QoS). These are fundamental properties required in an autonomously driving vehicle.

[0009] Thus, in the CAN XL, CAN FD, and CAN SIC bus systems, data is sent to the bus at a higher data rate in the second communication phase than in the first communication phase. With CAN XL, a bit of a transmitted signal not only has a shorter bit duration or bit time or temporal length in the second communication phase than in the first communication phase, but is usually also sent to the bus using a different physical layer and received with a different reception threshold than in the first communication phase. As a result, with CAN XL, the bus levels of the CAN_H and CAN_L bus signals for the first communication phase can differ from the bus levels in the second communication phase. In CAN XL, the type of communication in the second communication phase is also called FAST MODE. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model).

[0010] Therefore, interference-free communication on the bus can only occur if CAN XL subscriber stations in the bus system use a transmit / receive device that detects and performs the switching between the two communication phases in a message being sent to or received from the bus as accurately as possible, and correctly converts the levels of a transmitted signal for the bus. The transmit / receive device can also be referred to as a CAN transceiver or CAN FD transceiver, etc.

[0011] Therefore, a transmitting / receiving device (transceiver) for CAN XL is required that ensures the most error-free communication possible for all operational phases of communication on the bus. Disclosure of the invention

[0012] Therefore, it is an object of the present invention to provide an interface module for a subscriber station of a serial bus system and a method for sending a message in a serial bus system that solve the aforementioned problems. In particular, an interface module for a subscriber station of a serial bus system and a method for sending a message in a serial bus system should enable reliable and cost-effective creation / generation of bus signals, even when the physical layer is switched between two communication phases during communication on the bus.

[0013] The object is achieved by an interface module for a subscriber station of a serial bus system having the features of claim 1. In the bus system, a transmission module is designed to transmit a digital transmission signal as an analog differential signal to a bus of the bus system in order to send a message to at least one other subscriber station of the bus system, wherein bits in the digital transmission signal have a longer bit duration in a first communication phase than in a second communication phase of the transmission signal. The interface module has at least one time measurement block for measuring, with a predetermined clock pulse, a predetermined time in the digital transmission signal, wherein the at least one time measurement block is designed to stop its measurement when the measured value of the at least one time measurement block has reached a predetermined limit value,and an evaluation block for evaluating the measured value of the at least one time measurement block at the end of the predetermined time in order to set the transmitting module for operation in the first communication phase or for operation in the second communication phase based on the evaluation result.

[0014] The described interface module is designed to reliably, accurately, and yet inexpensively generate a transmit signal for bus signals during operation of the bus system. The transmit signal can indicate to the subscriber station how to preselect or set the operating mode for the transmit module in order to correctly switch between two communication phases for communication on the bus within a message.

[0015] Furthermore, the described interface module is designed to ensure reliable and uncomplicated detection of bus signals during operation of the bus system. This applies in particular to communication in which the physical layer is switched between two communication phases for communication on the bus.

[0016] The described interface module ensures very low-error and therefore largely interference-free communication between subscriber stations of the bus system, particularly in accordance with the CAN XL CiA610-3 standard. Additional advantages are explained in more detail in the figure description.

[0017] Furthermore, the described interface module also enables the use of different receive thresholds for the arbitration and data phases. This not only enables communication between other subscriber stations in the bus system at higher bit rates, but also prevents the transmittable bit rate from being reduced due to communication errors.

[0018] Advantageous further embodiments of the interface module are described in the dependent claims.

[0019] The evaluation block may be configured to switch the transmitting module into a first operating mode for the first communication phase for transmitting on the basis of the evaluation result, or to switch the transmitting module into a second operating mode or third operating mode for the second communication phase for transmitting.

[0020] In one embodiment, the at least one time measurement block can have at least four time measurement blocks, wherein the evaluation block is designed to evaluate the measured value of the at least four time measurement blocks at the end of the predetermined time in order to decode a pulse-width-modulated symbol of the transmission signal by evaluating the measured values ​​of the at least four time measurement blocks in order to output a pulse-width-demodulated transmission signal to the transmission module.

[0021] The interface module described above may also comprise a switching block for outputting an oscillating signal for specifying the predetermined timing cycle with which all timing blocks intermittently carry out their measurement.

[0022] In one embodiment, a first time measurement block is configured to restart the measurement with each edge of the transmission signal and to stop the measurement when the measured value of the first time measurement block has reached a predetermined limit value, wherein the evaluation block is configured to preselect the second operating mode for the transmission module for the second communication phase when the measured value of the first time measurement block corresponds to a first predetermined time.

[0023] In this case, a second time measurement block can be designed to start the measurement with each rising edge of the transmission signal and to measure until the next rising edge of the transmission signal until the predetermined limit is exceeded, wherein a third time measurement block is designed to start the measurement with each falling edge of the transmission signal and to measure until the next falling edge of the transmission signal until the predetermined limit is exceeded, and wherein the evaluation block is designed to switch the transmission module to the second operating mode for the second communication phase if the evaluation of the measurement result of the second and third time measurement blocks shows that in the transmission signal the distance between a rising edge and a falling edge or the distance between a falling edge and a rising edge is equal to a second predetermined time,which is the bit duration of bits of the second communication phase, and which is shorter than the first predetermined time.,

[0024] In addition, a fourth time measuring block can be designed to start the measurement with each rising edge of the transmission signal and to measure until the next falling edge of the transmission signal until the predetermined limit value is exceeded, wherein a fifth time measuring block is designed to start the measurement with each falling edge of the transmission signal and to measure until the next rising edge of the transmission signal until the predetermined limit value is exceeded, and wherein the evaluation block is designed to compare the measurement of the second and fourth time measuring blocks with each other and to compare the measurement of the third and fifth time measuring blocks with each other, and to output a pulse-width demodulated transmission signal to the transmission module on the basis of the comparison results.

[0025] According to one embodiment, the at least one timing block is a counter. At least two timing blocks of the at least one timing block can be configured to stop counting at a count value corresponding to the symbol duration for a PWM symbol of a pulse-width-modulated signal. The evaluation block is configured to evaluate the value of the PWM symbol of the pulse-width-modulated signal at the end of a PWM symbol using the at least one timing block and to output a level for the pulse-width-demodulated transmission signal to the transmission module using the evaluation result.

[0026] According to one embodiment, the at least one time-measuring block is configured as a capacitor with a voltmeter for measuring the voltage across the capacitor. At least one switchable constant current source is provided as a switching block, which is configured to switch the at least one constant current source to charge the capacitor over time. The at least one time-measuring block is configured to stop charging the at least one capacitor at a predetermined threshold voltage value corresponding to the predetermined time. The evaluation block can be configured to evaluate the voltage value of the at least one time-measuring block.

[0027] The interface module described above can be part of a transmitting / receiving device which also has a transmitting module for transmitting a digital transmit signal as an analog differential signal to a bus of the bus system in order to send a message to at least one other subscriber station of the bus system, and also has a receiving module for receiving signals from the bus and for generating a digital receive signal from the analog differential signal.

[0028] The transmitting module can be designed to generate the analog differential signals in the first communication phase of the message with a different physical layer than in the second communication phase.

[0029] The previously described transmitting / receiving device can be part of a subscriber station for a serial bus system. The subscriber station can also be a communication control device for controlling communication within the bus system and for generating a digital transmission signal as the basis for the digital pulse-width-modulated transmission signal for the interface module.

[0030] Optionally, the subscriber station is designed for communication in a bus system in which exclusive, collision-free access of a subscriber station to the bus of the bus system is guaranteed, at least temporarily.

[0031] The aforementioned object is also achieved by a method for transmitting a message in a serial bus system having the features of claim 16. The method is carried out with an interface module for a subscriber station of a serial bus system, wherein the subscriber station has a transmission module and wherein the interface module has at least one time measurement block and an evaluation block, and wherein the method comprises the steps of measuring with the at least one time measurement block and with a predetermined time pulse, a predetermined time in the digital transmission signal, wherein the at least one time measurement block stops its measurement when the at least one time measurement block has reached a predetermined limit value, evaluating, with the evaluation block, the measurement result of the at least one time measurement block at the end of the predetermined time,Setting the transmitting module on the basis of the evaluation result for operation in the first communication phase or for operation in the second communication phase, and transmitting, with the transmitting module, a digital, pulse-width-demodulated transmit signal as an analog differential signal to the bus of the bus system in order to send a message to at least one other subscriber station of the bus system, wherein bits in the digital, pulse-width-demodulated transmit signal have a longer bit duration in a first communication phase than in a second communication phase of the transmit signal.

[0032] The method offers the same advantages as previously mentioned with regard to the interface module.

[0033] Further possible implementations of the invention also include combinations of features or embodiments described above or below with respect to the exemplary embodiments that are not explicitly mentioned. In this case, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the invention.

[0034] Drawings

[0035] The invention is described in more detail below with reference to the accompanying drawings and exemplary embodiments. They show:

[0036] Fig. 1 is a simplified block diagram of a bus system according to a first embodiment;

[0037] Fig. 2 is a diagram illustrating the structure of a message that can be sent by subscriber stations of the bus system according to the first embodiment;

[0038] Fig. 3 shows an example of the ideal time course of bus signals CAN_H, CAN_L, which are sent by subscriber stations of the bus system for the message of Fig.

[0039] 2 are sent to a bus of the bus system;

[0040] Fig. 4 shows the time course of a differential voltage VDIFF which develops on the bus of the bus system as a result of the bus signals of Fig. 3;

[0041] Fig. 5 shows a block diagram of a transmitting / receiving device for a subscriber station of the bus system according to the first embodiment; Fig. 6 shows an example of a time profile of a digital transmit signal, which indicates to the transmitting / receiving device for a transmitting node the switching to an operating mode for transmitting in the data phase of a message;

[0042] Fig. 7 shows the time course of a digital transmission signal which the transceiver generates from the signal of Fig. 6 in order to send the message to the bus;

[0043] Fig. 8 shows an example of a time course of a digital transmission signal which indicates to the transmitting / receiving device for a receiving node the switching to an operating mode for receiving in the data phase of a message;

[0044] Fig. 9 shows the time course of a digital transmission signal which the transmitting / receiving device generates from the signal of Fig. 8;

[0045] Fig. 10 to Fig. 15 signal waveforms to explain the function of an interface module of the transmitting / receiving device in the case that the associated subscriber station is the sender of the message on the bus (transmitting node) in the data phase and therefore the transmitting / receiving device is switched to an operating mode for transmitting the transmission signal on the bus in the data phase; and

[0046] Fig. 16 to Fig. 21 Signal waveforms to explain the function of the interface module of the transmitting / receiving device in the case that the associated subscriber station in the data phase is only a receiver, but not a transmitter, of the message on the bus (receiving node) and therefore the transmitting / receiving device in the data phase is switched into an operating mode for receiving the message from the bus.

[0047] In the figures, identical or functionally equivalent elements are provided with the same reference numerals unless otherwise indicated. Description of the embodiments

[0048] Fig. 1 shows a bus system 1, which can, for example, at least in sections, be a CAN bus system, a CAN-FD bus system, etc. The bus system 1 can be used in a vehicle, in particular a motor vehicle, an aircraft, etc., or in a hospital, etc.

[0049] In Fig. 1, the bus system 1 has a plurality of subscriber stations 10, 20, 30, each connected to a bus 40 or bus line with a first bus wire 41 and a second bus wire 42. The bus wires 41, 42 can also be called CAN_H and CAN_L for the signals on the bus 40. Messages 45, 46, 47 can be transmitted in the form of signals between the individual subscriber stations 10, 20, 30 via the bus 40. The subscriber stations 10, 20, 30 are, for example, control units or display devices of a motor vehicle.

[0050] As shown in Fig. 1, the subscriber stations 10, 30 each have a communication control device 11 and a transmitting / receiving device 12. The transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122.

[0051] The subscriber station 20 has a communication control device 21 and a transmitting / receiving device 22. The transmitting / receiving device 22 has a transmitting module 221 and a receiving module 222.

[0052] The transmitting / receiving devices 12 of the subscriber stations 10, 30 and the transmitting / receiving device 22 of the subscriber station 20 are each directly connected to the bus 40, even if this is not shown in Fig. 1.

[0053] The communication control devices 11, 21 each serve to control communication between the respective subscriber station 10, 20, 30 via the bus 40 and at least one other subscriber station of the subscriber stations 10, 20, 30 connected to the bus 40. The communication control device 11 creates and reads first messages 45, 47, which are, for example, modified CAN messages 45, 47. The modified CAN messages 45, 47 are structured, for example, on the basis of the CAN XL format. The transceiver device 12 serves to transmit and receive the messages 45, 47 from the bus 40. The transmit module 121 receives a digital transmit signal TxD created by the communication control device 11 for one of the messages 45, 47 and converts this into signals on the bus 40. The digital transmit signal TxD can be a pulse-width modulated signal, at least in sections.The receiving module 122 receives signals transmitted on the bus 40 according to the messages 45 to 47 and generates a digital received signal RxD therefrom. The receiving module 122 sends the received signal RxD to the communication control device 11.

[0054] In addition, the communication control device 11 can be configured to create and read second messages 46, which are, for example, CAN SIC messages 46. The transmitting / receiving device 12 can be configured accordingly.

[0055] The communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, i.e. like a CAN FD-tolerant Classical CAN controller or a CAN FD controller or a CAN SIC controller. The communication control device 21 creates and reads second messages 46, for example CAN SIC messages. The transmit / receive device 22 is used to transmit and receive the messages 46 from the bus 40. The transmit module 221 receives a digital transmit signal TxD created by the communication control device 21 and converts it into signals for a message 46 on the bus 40. The receive module 222 receives signals transmitted on the bus 40 corresponding to the messages 45 to 47 and generates a digital receive signal RxD therefrom. The transmit / receive device 22 may be designed like a conventional CAN SIC transceiver.

[0056] To send messages 45, 46, and 47 with CAN SIC or CAN XL, proven features are adopted that are responsible for the robustness and user-friendliness of CAN and CAN FD, in particular the frame structure with identifier and arbitration according to the well-known CSMA / CR method. The CSMA / CR method requires so-called recessive states on bus 40, which can be overwritten by other subscriber stations 10, 20, and 30 with dominant levels or dominant states on bus 40.

[0057] The two subscriber stations 10, 30 can generate and then transmit messages 45, 47 using various CAN formats, in particular the CAN FD format, the CAN SIC format, or the CAN XL format, as well as receive such messages 45, 47. This is described in more detail below for one message 45.

[0058] Fig. 2 shows a frame 450 for message 45, which is in particular a CAN XL frame, as provided by the communication control device 11 for the transceiver 12 to transmit on the bus 40. In this embodiment, the communication control device 11 creates the frame 450 as compatible with CAN FD. Alternatively, the frame 450 is compatible with any successor standard to CAN FD.

[0059] According to Fig. 2, the frame 450 for CAN communication on the bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has, after a start bit SOF, an arbitration field 453, a control field 454, a data field 455, a

[0060] Checksum field 456 and a frame termination field 457. The checksum field 456 and the frame termination field 457 form a frame termination phase 456, 457 of the frame 450.

[0061] In the arbitration phase 451, using an identifier (ID) in the arbitration field 453, the subscriber stations 10, 20, 30 negotiate bit by bit to determine which subscriber station 10, 20, 30 wishes to send the message 45, 46 with the highest priority and will therefore receive exclusive access to the bus 40 of the bus system 1 for the next transmission time in the subsequent data phase 452. In the arbitration phase 451, a physical layer is used, similar to CAN and CAN-FD. The physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection Model).

[0062] An important point during phase 451 is the use of the well-known CSMA / CR method, which allows simultaneous access of the subscriber stations 10, 20, 30 to the bus 40 without destroying the higher-priority message 45, 46. This allows additional bus subscriber stations 10, 20, 30 to be added to the bus system 1 relatively easily, which is very advantageous.

[0063] The CSMA / CR method requires so-called recessive states on bus 40, which can be overwritten by other subscriber stations 10, 20, or 30 with dominant levels or dominant states on bus 40. In the recessive state, high-impedance conditions prevail at the individual subscriber stations 10, 20, or 30, which, in combination with the parasitics of the bus circuitry, results in longer time constants. This limits the maximum bit rate of today's CAN FD physical layer to approximately 2 megabits per second in real-world vehicle use.

[0064] In the data phase 452, in addition to a portion of the control field 454, the payload of the CAN-XL frame 450 or the message 45 from the data field 455, as well as the checksum field 456, are transmitted. The checksum field 456 can contain a checksum of the data of the data phase 452, including the stuff bits, which are inserted by the sender of the message 45 as an inverse bit after a predetermined number of identical bits, in particular 10 identical bits. At the end of the data phase 452, the system switches back to the arbitration phase 451.

[0065] An end field in the frame termination field 457 can contain at least one acknowledge bit. Furthermore, a sequence of 11 identical bits can be present, indicating the end of the CAN XL frame 450. The at least one acknowledge bit can be used to indicate whether or not a receiver has detected an error in the received CAN XL frame 450 or message 45. A sender of message 45 begins sending bits of the data phase 452 to the bus 40 only when the subscriber station 10, as the sender, has won the arbitration and the subscriber station 10, as the sender, thus has exclusive access to the bus 40 of the bus system 1 for sending.

[0066] Thus, in the arbitration phase 451 as the first communication phase, the subscriber stations 10, 30 partially use, particularly up to the FDF bit (inclusive), a format known from CAN / CAN-FD according to ISO 11898-1:2015. However, compared to CAN or CAN FD, in the data phase 452 as the second communication phase, an increase in the net data transmission rate is possible, particularly to over 10 megabits per second. Furthermore, an increase in the size of the payload data per frame is possible, particularly to approximately 2 kbytes or any other value.

[0067] As shown in Fig. 3, in the arbitration phase 451, the transceivers 12 use a physical layer 451_P to transmit a transmit signal TxD (Fig. 1) over time t as signals CAN_H, CAN_L onto the bus 40. The same applies to the transceiver 22. In contrast, in the data phase 452, the transceiver 12 can use a physical layer 452_P that differs from the physical layer 451_P to transmit the transmit signal TxD (Fig. 1) as signals CAN_H, CAN_L onto the bus 40, as previously described. There are two operating modes for the physical layer 452_P, namely FAST_TX and FAST_RX, as described in more detail below. The course of the corresponding transmission signals is explained in more detail below using Fig. 6 to Fig. 21.

[0068] Fig. 3 shows on the left that in the arbitration phase 451, the subscriber stations 10, 20, and 30 each transmit signals CAN_H and CAN_L over time t to the bus 40. These signals have a first bit duration t_btl. The signals CAN_H and CAN_L are serial signals and alternately have at least one dominant state 401 or at least one recessive state 402. After the arbitration in the arbitration phase 451, one of the subscriber stations 10, 20, and 30 is determined to be the winner. Assume that the first subscriber station 10 has won the arbitration. Then, at the end of the arbitration phase 451, the transmitting / receiving device 12 of the subscriber station 10 switches its physical layer 451_P from a first operating mode (SLOW), which can also be implemented as SIC operating mode, to a second operating mode (FAST_TX), since the subscriber station 10 is the sender of the message 45 in the data phase 452. As shown in Fig. 3, the transmitting module 121 then generates in the data phase 452 orIn the second operating mode (FAST_TX), depending on a transmit signal TxD, the states L0 or LI are successively and thus serially transmitted to the physical layer 452_P for the signals CAN_H, CAN_L on the bus 40. The frequency of the signals CAN_H, CAN_L can be increased in the data phase 452. In the example of Fig. 3, the bit time or bit duration t_bt2 in the data phase 452 is shorter or less than the bit time or bit duration t_btl in the arbitration phase 451. Thus, the net data transmission rate in the data phase 452 in the example of Fig. 3 is increased compared to the arbitration phase 451. In contrast, the transmitting / receiving device 12 of the subscriber station 30 switches its physical layer 451_P from the first operating mode (SLOW or SIC) to a third operating mode (FAST_RX) at the end of the arbitration phase 451, since the subscriber station 30 is only a receiver, i.e. not a transmitter, of the frame 450 in the data phase 452.

[0069] If the transmitting / receiving device 12 detects that a switchover from the data phase 452 back to the arbitration phase 451 is required, the transmitting / receiving device 12 switches from transmitting (FAST_TX mode) and / or receiving (FAST RX mode) signals with the physical layer 452_P to transmitting and / or receiving in the physical layer 451_P. Accordingly, all transmitting / receiving devices 12 of the subscriber stations 10, 30 switch their operating mode to the first operating mode (SLOW or SIC) after the end of the arbitration phase 451. Thus, all transmitting / receiving devices 12 can not only switch between the bit durations t_btl, t_bt2, but also switch their physical layer, as previously described.

[0070] According to Fig. 4, in the arbitration phase 451, in the ideal case, a differential signal VDIFF = CAN_H - CAN_L with values ​​of VDIFF = 2V for dominant states 401 and VDIFF = 0V for recessive states 402 is formed on the bus 40 over time t. This is shown on the left side of Fig. 4. In contrast, in the data phase 452, a differential signal VDIFF = CAN_H - CAN_L corresponding to the states L0, LI of Fig. 4 is formed on the bus 40 over time t, as shown on the right side of Fig. 4. The state LO has a value VDIFF = IV. The state LI has a value VDIFF = -IV.

[0071] The receiving module 122 can distinguish the states 401, 402 using two of the receiving thresholds TI, T2, T3, respectively, which lie in the ranges TH_T1, TH_T2, TH_T3. For this purpose, the receiving module 122 samples the signals from Fig. 3 or Fig. 4 at times t_A, as shown in Fig. 4. To evaluate the sampling result, the receiving module 122 uses the receiving threshold TI of, for example, 0.7 V and the receiving threshold T2 of, for example, -0.35 V in the arbitration phase 451. In contrast, the receiving module 122 only uses signals evaluated with the receiving threshold T3 in the data phase 452. When switching between the first to third operating modes (SLOW or SIC, FAST_TX, FAST_RX) previously described with reference to Fig. 3, the receiving module 122 switches the receiving thresholds T2, T3, respectively.

[0072] The reception threshold T2 is used to detect whether the bus 40 is free when the subscriber station 12 is newly connected to the communication on the bus 40 and attempts to integrate itself into the communication on the bus 40. Each subscriber station 10, 30 switches the operating mode of the transmitting / receiving device 12 to the arbitration phase 451 operating mode when the subscriber station 12 is (newly) connected to the communication on the bus 40 or attempts to reintegrate itself into the communication on the bus 40 after an error in the bus communication. Only when it is detected that the bus 40 is free may the subscriber station 10 itself send data, in particular messages 45, 47, to the bus 40 in the aforementioned cases.

[0073] Upon receiving the corresponding signals from the bus 40, each transceiver 12 generates the associated receive signal RxD, as illustrated in Fig. 1 and Fig. 5. The receive signal RxD ideally has no time offset from the transmit signal TxD.

[0074] Fig. 5 shows the basic structure of the subscriber station 10 with its communication control device 11 and its transmit / receive device 12, which includes the transmit module 121 and the receive module 122. The subscriber station 10 also has a microcontroller 13, a system ASIC (ASIC = Application-Specific Integrated Circuit) 14, a first interface module 15, and a second interface module 16. The second interface module 16 has timing blocks 161, 1621, 1622, 1631, 1632, a switching block 164, and an evaluation block 165.

[0075] The first interface module 15 is assigned to the microcontroller 13 and the device 11. The first interface module 15 is arranged between the device 11 and a TXD port of the microcontroller 13. The first interface module 15 is connected to the TXD port of the microcontroller 13. The first interface module 15 outputs a TxD signal to the second interface module 16.

[0076] The second interface module 16 is assigned to the device 12 and the system ASIC 14. The second interface module 16 is arranged between a TXD port of the system ASIC 14 and the transmitter module 121. The second interface module 16 is connected to the TXD port of the system ASIC 14 and / or a corresponding TXD port of the device 12.

[0077] The communication control device 11 can be configured as a protocol controller for transmitting and / or receiving CAN XL messages 45, 47. Optionally, the device 11 is configured for transmitting and / or receiving CAN FD or CAN SIC messages 46.

[0078] The microcontroller 13 generates or processes data that the device 11 must convert into the appropriate frame format for transmitting messages 45, 47 via the bus 40. To transmit the data to the bus 40, the communication control device 11 generates a transmit signal TxD_PC according to the appropriate standard for CAN FD, CAN SIC, or CAN XL messages 45, 47 and outputs the transmit signal TxD_PC to the first interface module 15.

[0079] The first interface module 15 is configured for pulse-width modulation (PWM) of the transmission signal TxD_PC. Accordingly, the transmission signal TxD at the TXD terminal of the microcontroller 13 is a transmission signal that is at least partially pulse-width modulated. The second interface module 16 is configured for processing the transmission signal TxD. In particular, the second interface module 16 is configured for pulse-width demodulation of the transmission signal TxD. Accordingly, the transmission signal TxD_TC output by the module 16 is a decoded or pulse-width demodulated transmission signal. These functions are explained in more detail with reference to Fig. 6 to Fig. 9.

[0080] The system ASIC 14 of the subscriber station 10 shown in Fig. 5 can alternatively be a system base chip (SBC) on which several functions required for an electronic module of the subscriber station 10 are combined. In addition to the transmitting / receiving device 12, a power supply device (not shown) can be integrated into the system ASIC 14, which supplies the transmitting / receiving device 12 with electrical energy. The power supply device typically supplies a CAN_Supply voltage of 5 V. However, depending on requirements, the power supply device 19 can supply a different voltage with a different value. Additionally or alternatively, the power supply device is designed as a current source.

[0081] In Fig. 5, the transmitter module 121 is shown only in a simplified form. The transmitter module 121 is connected directly to the bus 40 via the CANH and CANL connections in order to be able to transmit a transmission signal TxD_TC from the second interface module 16 to the bus 40.

[0082] According to Fig. 5, the receiving module 122 is also directly connected to the bus 40 via the CANH and CANL terminals. The receiving module 122 is designed to generate the digital received signal RxD. The receiving module 122 transmits or outputs the received signal RxD via the RXD terminal of the system ASIC 14 or the transceiver device 12 to the RXD terminal of the microcontroller 13 or the communication control device 11.

[0083] In the present embodiment, the timing blocks 161, 1621, 1622, 1631, 1632 are each designed as counters. The switching block 164 operates or clocks the measurement, in particular the counting, of the timing blocks 161, 1621, 1622, 1631, 1632. The timing blocks 161, 1621, 1622, 1631, 1632 therefore do not perform their measurements continuously, but rather at predetermined time intervals or intermittently.

[0084] The switching block 164 can be designed as an oscillator block that outputs an oscillating signal FO (Fig. 12) with a clock pulse TK or a frequency f that corresponds to the period of the signal in Fig. 12. The clock pulse TK, and thus also the frequency f, is tuned to a time t_d in Fig. 6 or t-decode. During the time period or time t_d, when sampling a bit of the transmission signal TxD, the level or bit value, namely high (H = High) or low (L = Low), of the bit is to be determined. The time t_d of Fig. 6 begins or ends with a bit of the transmission signal TxD. In addition, the value of the bit in the middle of a bit can be sampled at the time t_d (Fig. 6), which begins or ends with the middle of the bit time period t_per. Since the time t_d is specified to be no less than or shorter than 5 ns, the frequency f of the switching block 164 is selected to be f > 200 MHz, specifically approximately 300 MHz. This allows the specification for the time t_d to be met.In the example above, the bit time t_per of bits of data phase 452 can have a value of < 205 ns. As described in more detail below, the time period t_per is divided into the time periods t_l, t_2. Each of the time periods t_l, t_2 must not be shorter or less than 5 ns.

[0085] Timing block 161 is provided for preselecting the operating mode of data phase 452. Timing blocks 1621, 1622 are provided for detecting bits of the transmit signal TxD that have the bit time t_bt2. Timing blocks 1621, 1631 are used to detect whether the data or bits in the transmit signal TxD are being transmitted pulse-modulated in the FAST_TX operating mode. Timing blocks 1622, 1632 are used to detect whether the data or bits in the transmit signal TxD are being transmitted pulse-modulated in the FAST_RX operating mode.

[0086] Fig. 6 shows an example of a transmit signal TxD for a transmitting node, which the second interface module 16 receives from the first interface module 15 over time t, and thus serially. Fig. 7 shows the transmit signal TxD_TC, which the interface module 16 generates from the signal in Fig. 6 over time t for the transmitting module 121. Figs. 8 and 9 show other examples of the transmit signal TxD and the transmit signal TxD TC generated therefrom for a receiving node.

[0087] Fig. 6 and Fig. 8 each show the part of the transmission signal TxD of a message 45 at the end of the arbitration phase 451. In this phase, the transmission module 121 is switched to the SLOW or SIC operating mode, as shown in Fig. 6 and Fig. 8 by the state S_TX.

[0088] If an edge occurs in the TxD signal, as shown in Fig. 6 and Fig. 8, the time period t_SL begins to run, and the timing block 161 starts a time measurement. The time period t_SL corresponds to the time period t_select, where, according to CiA610-3, t_select = 500...980 ns. The measurement with the timing block 161 restarts with each edge on the transmit signal TxD. After the time period t_SL has elapsed, the timing block 161 stops its measurement, and the evaluation block 165 detects the level of the transmit signal TxD. If this level is L (low), the evaluation block 165 specifies the FAST_TX operating mode, as indicated in Fig. 6 with the state F_TX_SL. Thus, the FAST_TX operating mode is preselected for the transmitting / receiving device 12 toward the end of the arbitration phase 451. However, if the H (High) level is evaluated at the end of the time period t_SL, the evaluation block 165 specifies the FAST_RX operating mode, as indicated in Fig. 8 by the state F_RX_SL.Thus, the FAST_RX operating mode is preselected for the transmitting / receiving device 12 towards the end of the arbitration phase 451.

[0089] In addition, if the FAST_TX operating mode is preselected, as indicated in Fig. 6 with the F_TX_SL state, the timing block 1621 begins to measure whether two rising edges of the transmit signal TxD are transmitted in a time window having a time length equal to the time duration or symbol duration t_per. In particular, the time duration t_per is equal to the time duration t_bt2. The time duration t_bt2 corresponds to the time duration tfast, where, according to CiA610-3, tfast = 205 ns...245 ns. Starting with a rising edge of the transmit signal TxD, the timing block 1621 measures whether two consecutive rising edges occur within the symbol duration t_per of the transmit signal TxD. The timing block 1621 stops the measurement when the time duration t_bt2 is reached. If two consecutive rising edges occur in the symbol duration t_per of the transmission signal TxD, the evaluation block 165 detects that the transmitting / receiving device 12 is to be switched to the FAST_TX operating mode, as shown in Fig.6 with the state F_TX for the levels F_TX_L1 and F_TX_LO. The FAST_TX operating mode is deactivated again when the evaluation block 165 detects that a longer or shorter period of time than the time period t_bt2 elapses in the transmit signal TxD between two consecutive rising edges. Furthermore, the FAST_TX operating mode is exited or deactivated again when the evaluation block 165 detects that the transmit signal TxD has the level H or L for a predetermined long period of time, in particular permanently.

[0090] At the end and after the arbitration phase 451, the transmit signal TxD of Fig. 6 is a partially pulse-width-modulated (PWM) signal. In the pulse-width-modulated signal, PWM symbols have the symbol duration t_per, which in turn is divided into the time periods t_l, t_2. After the time period t_l, the transmit signal TxD changes from a first level, for example, L (low), to a second level, for example, H (high), as shown in Fig. 6. Based on the L and H levels of the transmission signal TxD and the time periods t_l, t_2, the evaluation block 165 evaluates which PWM symbol is encoded in the transmission signal TxD, and thus which level is to be created for bits in the transmission signal TxD_TC of Fig. 7 in order to generate the corresponding state (LI, LO of Fig. 4) on the bus 40 with the transmission module 121. For this purpose, the evaluation block 165 evaluates the measurements of at least two of the time measurement blocks 1621, 1622, 1631, 1632, as described in more detail below.

[0091] In addition, if the FAST_RX operating mode is preselected, as indicated in Fig. 8 with the F_RX_SL state, the timing block 1622 begins to measure whether two falling edges of the transmit signal TxD are transmitted in a time window having a time length equal to the duration of a PWM symbol or symbol duration t_per. In particular, the duration t_per is equal to the duration t_bt2, as mentioned above. Starting with a falling edge of the transmit signal TxD, the timing block 1622 measures whether two consecutive falling edges occur within the symbol duration t_per of the transmit signal TxD. The timing block 1622 stops the measurement when the duration t_bt2 is reached. If two consecutive falling edges occur in the symbol duration t_per of PWM symbols of the transmission signal TxD, the evaluation block 165 detects that the transmitting / receiving device 12 is to be switched to the FAST_RX operating mode, as indicated in Fig. 8 with the state F_RX.The FAST_RX operating mode is deactivated again when the evaluation block 165 detects that a longer or shorter time than the time period t_bt2 elapses in the transmit signal TxD between two consecutive falling edges. Furthermore, the FAST_RX operating mode is exited or deactivated again when the evaluation block 165 detects that the transmit signal TxD has the level H or L for a predetermined long time, in particular permanently.

[0092] The following procedure can be used to decode the pulse-width-modulated signal TxD in Fig. 6 into the signal TxD_TC in Fig. 7. The same applies to decoding the pulse-width-modulated signal TxD in Fig. 8 into the signal TxD_TC in Fig. 9.

[0093] Fig. 10 shows, for the data phase 452, an example of a transmission signal TxD_PC, which the device 11 of Fig. 3 generates over time t with the values ​​H, L for bits with the symbol duration t_per or bit time or bit duration t_bt2 and outputs serially to the first interface module 15 of Fig. 3. Fig. 11 shows the transmission signal TxD, which the first interface module 15 generates from the signal of Fig. 10 by means of pulse modulation and outputs serially to the terminal TXD of the device 12 of Fig. 3. The transmission signal TxD encodes the states L0, LI for the bus signal of Fig. 4 with PWM symbols, as previously mentioned. The time t_2 in the signal TxD of Fig. 11 corresponds to the on time of the transmission signal TxD. The on time is the time during which the transmit signal TxD is at level H or switched on. For the remaining time at the beginning or from the beginning of the symbol time t_per, the transmit signal TxD is at level L or switched off.If communication takes place on bus 40 at 10 Mbit / s, the symbol duration t_per has a length of 100 ns, for example. In this case, a length of 25 ns can be selected as the time t_l for a PWM symbol that encodes the state L0. Furthermore, a length of 75 ns can be selected as the time t_l for a PWM symbol that encodes the state L1. The time t_l is therefore either, for example, 25% of the symbol duration t_per or, for example, 75% of the symbol duration t_per to encode the states L0, L1. Of course, other lengths for the time t_l are possible, in particular those approved by the CiA610-3 standard for CAN XL. The transmission signal TxD is demodulated or decoded in the second interface module 16. Here, the oscillator signal FO from Fig. 12 is used to trigger the timing blocks 161, 1621, 1622, 1631, 1632. Using the corresponding signals from Fig. 13 and Fig.14, the second interface module 16 generates the transmit signal TxD_TC, as previously mentioned. The second interface module 16 generates the transmit signal TxD_TC with a predetermined time offset from the transmit signal TxD, as shown by the arrows between Fig. 11 and Fig. 15. According to Fig. 11 and Fig. 15, the time offset is slightly more than one bit time or bit duration t_bt2.

[0094] If the FAST_TX operating mode is preselected, as indicated in Fig. 6 with the state F_TX_SL, the timing block 1621 begins measuring from a rising edge to the next rising edge of the transmit signal TxD, as shown in Fig. 13. The count value C2_FT of the timing block 1621 increases to a maximum limit value GW, which corresponds to the time period t_per or t_bt2. The timing block 1621 stops when the limit value GW (maximum count value) or the time period t_per is reached. Furthermore, as shown in Fig. 14, the timing block 1631 begins measuring from a rising edge to the next falling edge of the transmit signal TxD. The timing block 1631 stops when the time period t_per is reached. At the end of the PWM symbol, i.e., the second rising edge of the transmit signal TxD, the PWM symbol is decoded. The digital circuit design allows for a simple halving of the count value C2_FT of the timing block 1631 by one digit using a digital shift operation.The comparison then occurs. Evaluation block 165 evaluates state LI as the value for the measured PWM symbol of the transmit signal TxD if the count value C3_FT < count value C2_FT / 2, so that the value L is to be generated in the transmit signal TxD_TC of Fig. 15. Evaluation block 165 evaluates LO as the value for the measured PWM symbol of the transmit signal TxD if the count value C3_FT > count value C2_FT / 2, so that the value L is to be generated in the transmit signal TxD_TC of Fig. 15. It is not defined which value or level is to be generated in the transmit signal TxD_TC if the count value C3_FT = count value C2_FT / 2. The respective evaluation result by evaluation block 165 is forwarded to transmission module 121 as the decoded transmission signal TxD_TC from Fig. 15. Transmission module 121 converts an L level of the transmission signal TxD_TC into an LO signal or an LO state on the bus (VDIFF = IV, Fig. 4). Transmission module 121 converts an H level of the transmission signal TxD_TC into an LL signal oran Ll state on bus 40 (VDIFF = -IV, Fig. 4).

[0095] Fig. 16 to Fig. 21 show the corresponding signals for a receiving node for which the FAST_RX operating mode is preselected for the data phase 452, as indicated in Fig. 8 with the state F_RX_SL. The transmit signal TxD_PC is in this case transmitted in the data phase 452 at level H, as shown in Fig. 16. The interface module 15 accordingly generates the transmit signal TxD with PWM symbols LI, as shown in Fig. 17. In this case, triggered by the signal according to Fig. 18 from the switching block 164, the timing block 1622 begins measuring from a falling edge of the transmit signal TxD to the next falling edge of the transmit signal TxD. Thus, the timing block 1622 measures the duration of the time period t_per. The count value C2_FR of the time measurement block 1622 in Fig. 19 increases to a maximum of a limit value GW, which corresponds to the time period t_per. The time measurement block 1622 stops when the limit value GW or the time period t_per is reached. Furthermore, according to Fig.20, the timing block 1632 measures the time from a falling edge of the transmit signal TxD to the next rising edge of the transmit signal TxD. Thus, the timing block 1632 measures the duration of the off-time of the PWM symbol. The timing block 1632 stops when the time period t_per or t_bt2 is reached. At the end of the PWM symbol, i.e., the second falling edge of the transmit signal TxD in Fig. 17, the PWM symbol is validated. The PWM symbol is accepted by the evaluation block 165 if C3_FR > 1 and C3_FR < GW - 1. If the PWM symbol is accepted, an Fl level is evaluated as the value for the measured PWM symbol of the transmit signal TxD. The H level corresponds to a recessive state 402 (Fig. 4) on bus 40.

[0096] The previously described design of the second interface module 16 forms a digital circuit concept. This concept enables high accuracy in the execution of the three functions (operating mode preselection, detection of the bit time t_bt2 of the data phase 452 for switching between the operating modes for the transmit module 121, decoding of the PWM symbols of the transmit signal TxD) of the second interface module 16. This is made possible by using a calibrated circuit block 164, in particular a ring oscillator block that outputs an oscillating signal FO, as shown in Fig. 12. The achievable accuracy is approximately +1-7%.

[0097] A particular advantage of the second interface module 16 is the high accuracy for evaluating the pulse-modulated signal TxD, since the timing blocks 161, 1621, 1622, 1631, 1632 are operated with the same clock pulse TK or the same frequency f of the switching block 164. This also applies in particular to the timing blocks 1621, 1622 for period t_bt2 and the timing blocks 1631, 1632 for the on-time t_1 or off-time t_2, since the timing blocks 161, 1621, 1622, 1631, 1632 also cooperate very well.

[0098] In addition, the previously described design of the second interface module 16 in the hardware enables very low silicon footprint. This allows the interface module 16 to be implemented very cost-effectively and in a space-saving manner. This also contributes to the very cost-effective and space-saving manufacture of a higher-level transceiver 12.

[0099] Another advantage of the second interface module 16 is its high test coverage and the associated component quality.

[0100] In addition, there is a high degree of flexibility for adjustments in additional development steps of the second interface module 16.

[0101] Furthermore, there is the option of using the second interface module 16 as a digital component in a CAN-XL transceiver device 12. This allows functional extensions, such as security functions, particularly against manipulation, in the device 12. According to a second embodiment, the evaluation block 165 is configured to additionally evaluate the measurement of the timing block 1632 in the FAST_RX operating mode. The FAST_RX operating mode remains active as long as the value of the timing block 1632 is greater than or equal to l*t_d, AND the value of the timing block 1632 is less than the value of the timing block 1622 minus l*t_d.

[0102] This provides redundancy that prevents the FAST_RX mode from being deactivated too quickly or remaining active for too long.

[0103] According to a third embodiment, at least one of the time measuring blocks 161, 1621, 1622, 1631, 1632 is realized according to an analog circuit concept.

[0104] In contrast to the transmitting / receiving device 12 of the preceding embodiment, at least one of the timing blocks 161, 1621, 1622, 1631, 1632 is configured to perform the previously described time measurement using at least one switched constant current. At least one of the timing blocks 161, 1621, 1622, 1631, 1632 includes a capacitor. Additionally, the at least one timing block 161, 1621, 1622, 1631, 1632 includes at least one voltmeter for measuring the voltage across the capacitor.

[0105] The constant currents are switched such that the capacitor is charged or discharged as needed. Evaluation block 165 can be configured to evaluate the voltage measurement. In particular, evaluation block 165 can perform a voltage comparison of the measured capacitor voltages.

[0106] Accordingly, switching block 164 can include at least one switchable constant current source. Switching block 164 is configured to switch the at least one constant current source to charge the capacitor over time. The at least one time-measuring block 161, 1621, 1622, 1631, 1632 is configured to stop the switching of the at least one constant current source and thus the charging of the at least one capacitor at a predetermined threshold voltage value (GW), which corresponds to the predetermined time t_per or t_l or t_bt2 or t_SL.

[0107] In this way, the functions previously described for the second interface module 16 of the preceding embodiments can also be advantageously implemented.

[0108] However, such an implementation requires a significantly higher silicon area consumption for the second interface module 16 than in the previous embodiments.

[0109] All previously described configurations of the interface module 16 of the transmitting / receiving device 12, the subscriber stations 10, 20, 30, the bus system 1, and the method implemented therein according to the exemplary embodiments and their modifications can be used individually or in all possible combinations. In addition, the following modifications are particularly conceivable.

[0110] The previously described bus system 1 according to at least one of the exemplary embodiments is described with reference to a bus system based on the CAN protocol. However, the bus system 1 according to at least one of the exemplary embodiments can alternatively be a different type of communications network in which the signals are transmitted as differential signals. It is advantageous, but not a mandatory requirement, that in the bus system 1, exclusive, collision-free access of a subscriber station 10, 20, 30 to the bus 40 is guaranteed, at least for certain time periods.

[0111] The bus system 1 according to at least one of the embodiments and their modifications is in particular a bus system in which communication can take place between at least two of the subscriber stations 10, 20, 30 according to two different CAN standards, such as CAN-HS or CAN FD or CAN SIC or CAN XL. However, the bus system 1 can be a different communication network in which the signals are transmitted as differential signals and serially via the bus 40. Thus, the functionality of the previously described embodiments can be used, for example, in transmitting / receiving devices 12, 22 that are to be operated in such a bus system. The number and arrangement of the subscriber stations 10, 20, 30 in the

[0112] Bus system 1 according to at least one of the embodiments and their modifications can be selected as desired.

Claims

Claims 1) Interface module (16) for a subscriber station (10; 30) of a serial bus system (1), in which a transmission module (121) is designed to transmit a digital transmission signal (TxD_TC) as an analog differential signal (CAN_H, CAN_L) to a bus (40) of the bus system (1) in order to send a message (45) to at least one other subscriber station (10; 20; 30) of the bus system (1), wherein bits in the digital transmission signal (TxD_TC) have a longer bit duration (t_btl) in a first communication phase (451) than in a second communication phase (451) of the transmission signal (TxD_TC), wherein the interface module (16) has at least one time measuring block (161; 1621, 1622; 1631, 1632) for measuring, with a predetermined time cycle (TK), a predetermined Time (t_SL; t_bt2; t_per; t_btl) in the digital transmission signal (TxD), wherein the at least one time measuring block (161; 1621, 1622;1631, 1632) is designed to stop its measurement when the measured value of the at least one time measuring block (161; 1621, 1622; 1631, 1632) has reached a predetermined limit value (GW), and an evaluation block (165) for evaluating the measured value of the at least one time measuring block (161; 1621, 1622; 1631, 1632) at the end of the predetermined time (t_SL; t_per; t_btl) in order to set the transmission module (121) for operation in the first communication phase (451) or for operation in the second communication phase (452) on the basis of the evaluation result. 2) Interface module (16) according to claim 1, wherein the evaluation block (165) is designed to switch the transmission module (121) on the basis of the evaluation result for transmission into a first operating mode (SIC) for the first communication phase (451) or for the second Communication phase (452) to switch to a second operating mode (FAST_TX) or third operating mode (FAST_RX) for sending. ) Interface module (16) according to claim 1 or 2, wherein the at least one time measurement block (161; 1621, 1622; 1631, 1632) has at least four time measurement blocks (161; 1621, 1622; 1631, 1632), and wherein the evaluation block (165) is designed to evaluate the measured value of the at least four time measurement blocks (161; 1621, 1622; 1631, 1632) at the end of the predetermined time (t_per; t_l; t_bt2) in order to decode a pulse-width modulated symbol of the transmission signal (TxD) by evaluating the measured values ​​of the at least four time measurement blocks (161; 1621, 1622; 1631, 1632) in order to send the measured value to the transmission module (121) to output a pulse width demodulated transmission signal (TxD_TC).) Interface module (16) according to one of the preceding claims, further comprising a switching block (164) for outputting an oscillating signal (FO) for specifying the predetermined timing cycle (TK) with which all time measuring blocks (161; 1621, 1622; 1631, 1632) carry out their measurement intermittently. ) Interface module (16) according to one of the preceding claims, wherein a first time measuring block (161) is designed to restart the measurement with each edge of the transmission signal (TxD) and to stop the measurement when the measured value of the first time measuring block (161; 1621, 1622; 1631, 1632) has reached a predetermined limit value (GW), and wherein the evaluation block (165) is designed to preselect the second operating mode (FAST_TX) for the transmission module (121) for the second communication phase (452) when the measured value of the first time measuring block (161) corresponds to a first predetermined time (t_SL).) Interface module (16) according to claim 5, wherein a second time measuring block (1621) is designed to start the measurement with each rising edge of the transmission signal (TxD) and until the next rising edge of the transmission signal. (TxD) until the predetermined limit value (GW) is exceeded, wherein a third time measuring block (1622) is designed to start the measurement with each falling edge of the transmission signal (TxD) and to measure until the next falling edge of the transmission signal (TxD) until the predetermined limit value (GW) is exceeded, and wherein the evaluation block (165) is designed to switch the transmission module (121) for the second communication phase (452) to the second operating mode (FAST_TX) if the evaluation of the measurement result of the second and third time measuring blocks (1621, 1622) shows that in the transmission signal (TxD) the distance between a rising edge and a falling edge or the distance between a falling edge and a rising edge is equal to a second predetermined time (t_bt2), which is the bit duration of bits of the second communication phase (452) and which is shorter than the first predetermined time (t_SL).) Interface module (16) according to claim 6, wherein a fourth time measuring block (1631) is designed to start the measurement with each rising edge of the transmission signal (TxD) and to measure until the next falling edge of the transmission signal (TxD) until the predetermined limit value (GW) is exceeded, wherein a fifth time measuring block (1632) is designed to start the measurement with each falling edge of the transmission signal (TxD) and to measure until the next rising edge of the transmission signal (TxD) until the predetermined limit value (GW) is exceeded, and wherein the evaluation block (165) is designed to compare the measurement of the second and fourth time measuring blocks (1621, 1631) with each other and to compare the measurement of the third and fifth time measuring blocks (1622, 1632) with each other, and on the basis of the comparison results, a pulse width demodulated transmission signal (TxD_TC) to the transmission module (121). ) Interface module (16) according to one of the preceding claims, wherein at least one time measuring block (161; 1621; 1622; 1631; 1632) is a counter. ) Interface module (16) according to claim 8, wherein at least two time measuring blocks (161) of the at least one time measuring block (161; 1621; 1622; 1631; 1632) are designed to stop the counting at a count value which corresponds to the symbol time period (t_per) for a PWM symbol of a pulse-width modulated signal (TxD), and wherein the evaluation block (165) is designed to evaluate the value (LO; LI) of the PWM symbol of the pulse-width modulated signal (TxD) at the end of a PWM symbol using the at least one time measuring block (161; 1621; 1622; 1631; 1632) and to send a level (L; H) for the pulse-width demodulated transmission signal (TxD_TC) to the Transmitter module (121).0) Interface module (16) according to one of claims 1 to 7, wherein the at least one time measuring block (161; 1621; 1622; 1631; 1632) is designed as a capacitor with a voltage measuring device for measuring the voltage across the capacitor, wherein at least one switchable constant current source is provided as a switching block (164) which is designed to switch the at least one constant current source in order to charge the capacitor over time, wherein the at least one time measuring block (161) is designed to stop the charging of the at least one capacitor at a predetermined limit voltage value (GW) which corresponds to the predetermined time (t_SL; t_bt2; t_per; t_btl). 1) Interface module (16) according to claim 10, wherein the evaluation block (165) is designed to evaluate the voltage value of the at least one time measuring block (161; 1621; 1622; 1631; 1632). 2) Transmitting / receiving device (12), with a transmitting module (121) for transmitting a digital transmit signal (TxD_TC) as an analog differential signal (CAN_H, CAN_L) to a bus (40) of the bus system (1) in order to send a message (45) to at least one other subscriber station (10; 20; 30) of the bus system (1), a receiving module (122) for receiving signals (CAN_H, CAN_L) from the bus (40) and for generating a digital receive signal (RxD) from the analog differential signal (CAN_H, CAN_L), and an interface module (16) according to one of the preceding claims. 3) Transmitting / receiving device (12) according to claim 12, wherein the transmitting module (121) is designed to generate the analog differential signals (CAN_H, CAN_L) in the first communication phase (451) of the message (45) with a different physical layer (451_P) than in the second communication phase (452).4) Subscriber station (20) for a serial bus system (1), with a transmitting / receiving device (12) according to claim 12 or 13, and a communication control device (11) for controlling communication in the bus system (1) and for generating a digital transmit signal (TxD_TC) as the basis for the digital pulse-width modulated transmit signal (TxD) for the interface module (16). 5) Subscriber station (20) according to claim 14, wherein the subscriber station (20) is designed for communication in a bus system (1) in which at least temporarily exclusive, collision-free access of a subscriber station (10, 20, 30) to the bus (40) of the bus system (1) is guaranteed. ) Method for transmitting differential signals (CAN_H, CAN_L) in a serial bus system (1), wherein the method comprises a. Interface module (16) for a subscriber station (10; 30) of a serial bus system (1), wherein the subscriber station (10; 30) has a transmitting module (121) and wherein the interface module (16) has at least one time measuring block (161; 1621, 1622; 1631, 1632) and an evaluation block (165), and wherein the method comprises the steps Measuring with the at least one time measuring block (161; 1621, 1622; 1631, 1632) and with a predetermined time cycle (TK), a predetermined time (t_SL; t_l; t_bt2) in the digital transmission signal (TxD), wherein the at least one time measuring block (161; 1621, 1622; 1631, 1632) stops its measurement when the at least one time measuring block (161; 1621, 1622; 1631, 1632) has reached a predetermined limit value (GW), Evaluating, with the evaluation block (165), the measurement result of the at least one time measuring block (161; 1621, 1622; 1631, 1632) at the end of the predetermined time (t_SL; t_l; t_bt2), Setting the transmitting module (121) on the basis of the evaluation result for operation in the first communication phase (451) or for operation in the second communication phase (452), and Sending, with the transmission module (121), a digital, pulse-width-demodulated transmission signal (TxD_TC) as an analog differential signal (CAN_H, CAN_L) to the bus (40) of the bus system (1) in order to send a message (45) to at least one other subscriber station (10; 20; 30) of the bus system (1), wherein bits in the digital, pulse-width-demodulated transmission signal (TxD_TC) have a longer bit duration (t_btl) in a first communication phase (451) than in a second communication phase (451) of the transmission signal (TxD_TC).

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