Reading apparatus and method for the delayed reading of a plurality of quantum devices, in particular quantum dots or quantum bits, and quantum apparatus

Abstract

The present invention relates to a reading apparatus (4) for the delayed reading of a plurality of quantum devices (2), comprising - a plurality of sample and hold modules (5), wherein each of the sample and hold modules (5) is or can be connected to at least one quantum device (2), and wherein each of the sample and hold modules (5) comprises at least two sample and hold elements (6, 7), - at least two global trigger lines, - at least one global comparator (8), - at least two global transmission lines (9, 10) which can be used to transmit quantum state values held in the sample and hold elements (6, 7) of the associated sample and hold modules (5) to the global comparator (8), and - activation means which are assigned to the sample and hold elements (6, 7) of the sample and hold modules (5) and are designed and / or configured such that quantum state values held by the sample and hold elements (6, 7) of the sample and hold modules (5) can be sequentially transmitted to the global comparator (8) in a module-by-module manner.

Description

[0001] DESCRIPTION

[0002] Readout device and method for the time-shifted readout of several quantum devices, in particular quantum dots or quantum bits, and quantum device

[0003] The invention relates to a readout device for the time-shifted readout of multiple quantum devices, in particular quantum dots or quantum bits. Furthermore, the invention relates to a quantum device, in particular a quantum computer, and a method for the time-shifted readout of multiple quantum devices, in particular quantum dots or quantum bits.

[0004] Quantum devices are known from the state of the art, which can be, for example, quantum bits or quantum dots.

[0005] Quantum bits, also referred to as qubits, are two-state quantum systems, i.e., quantum mechanical systems that have two states that can be reliably distinguished by measurement and are used in quantum computers. Quantum bits play a role for quantum computers analogous to that of classical bits for conventional computers.

[0006] Quantum dots (QDs) are nanoscopic material structures that are usually semiconductor-based. Quantum dots can also be used independently of quantum computers. Various methods are known for implementing quantum bits for quantum computers. Examples include ions in ion traps, SQUIDs (superconducting quantum interference devices), nuclear spins in molecules and solids, and electrons in quantum dots.

[0007] The applicant is aware of various multiplexing methods for reading quantum devices such as quantum dots or quantum bits. These methods can essentially be divided into frequency and time multiplexing.

[0008] For frequency division multiplexing, the quantum devices themselves, or the associated charge sensors used for quantum state detection, are each connected to a high-quality resonant circuit. The resonant circuits assigned to the individual quantum devices or charge sensors have different resonant frequencies. When excited at the appropriate frequency, the reflected wave is altered by the complex conductance change. Since both the exciting and reflected waves are particularly narrowband signals, they can be transmitted over a single line.

[0009] For time-division multiplexing, the drain-source terminals of all charge sensors are connected in parallel, and the total current is measured. This can be illustrated using the example of a single-electron transistor (SET). In addition to the drain and source terminals, such a transistor has at least one gate electrode. The gate electrode can be used in such a way that only one of the parallel-connected charge sensors reacts to a charge change, thus allowing a signal change to be assigned to a specific charge sensor. Another option is amplitude-division multiplexing. For this, the charge sensors are set to different operating points so that they react to the same charge change with different signal changes.If, for example, values ​​from the binary system are assigned to the significance of the signal change, the signal changes can also be assigned to a specific charge sensor if only the sum of the signals is measured.

[0010] There are various disadvantages associated with the aforementioned multiplexing methods.

[0011] Frequency division multiplexing has the disadvantage that the components required for the oscillator circuit require a comparatively high amount of space and energy. This reduces the maximum density of the quantum bits through the readout electronics.

[0012] The disadvantage of time-division multiplexing is that the coherence time of a quantum bit limits the maximum number of possible operations. Reading the quantum bit state also has to be done within the coherence time, so time-division multiplexing limits the maximum number of feasible operations.

[0013] For amplitude modulation, the sensitivity of the charge sensor is limited for a given resolution of the signal measuring device, since the optimal operating point cannot be selected. This results from the additional requirement of distinguishing the different signals. Furthermore, with a typically subsequent analog-to-digital conversion, the requirements for the converter's resolution are significantly increased, or, with lower requirements, the number of readable quantum bits is limited. Based on this, it is an object of the present invention to provide a device for reading quantum devices that avoids or at least reduces the aforementioned disadvantages. Furthermore, it is an object of the invention to provide a corresponding method for reading quantum devices.

[0014] The first-mentioned object is achieved by a readout device for the time-shifted readout of several quantum devices, in particular quantum dots or quantum bits, comprising

[0015] - a plurality of sample and hold modules, wherein each of the sample and hold modules is connected or connectable to at least one quantum device or to a state sensor, in particular a charge sensor, used to detect the state of at least one quantum device, and wherein each of the sample and hold modules comprises at least two sample and hold elements, with which quantum state values ​​from the at least one connected or connectable quantum device or the connected or connectable state sensor can be sampled and held,

[0016] - at least two global trigger lines by means of which the sample and hold elements of the sample and hold module can be triggered,

[0017] - at least one global comparator assigned to several sample and hold modules,

[0018] - at least two global transmission lines, via which quantum state values ​​held in the sample and hold elements of the associated sample and hold modules can be transmitted to the respective global comparator(s), and

[0019] - activation means associated with the sample and hold elements of the sample and hold modules, which are designed and / or configured such that quantum state values ​​held by the sample and hold elements of the sample and hold modules can be transmitted sequentially, module by module, to the respective global comparator(s).

[0020] The second object is achieved by a method for the time-shifted readout of several quantum devices, in particular quantum dots or quantum bits, using a readout device according to the invention, in which

[0021] 51) in an initialization phase, several quantum devices, in particular all quantum devices, are preferably initialized simultaneously,

[0022] 52) in a reference sampling phase, state values ​​of the quantum devices are recorded after initialization, in particular simultaneously, by means of the connected sample and hold modules, wherein a sample and hold element of each sample and hold module samples and holds a state value, and these state values ​​are considered as reference values,

[0023] 53) in an operation phase the quantum devices perform operations,

[0024] 54) in a measurement sampling phase, state values ​​of the quantum devices are recorded, in particular simultaneously, by means of the connected sample and hold modules, wherein a different sample and hold element of each sample and hold module samples and holds the state value, and these state values ​​are regarded as measured values,

[0025] 55) in particular after the end of the coherence time of the quantum devices in a multiplex phase, the held reference and measured values ​​are transmitted sequentially in modules to the respective global comparator or comparators in order to compare them, in particular, wherein the respective global comparator or comparators each output a signal, in particular a binary signal, which is dependent on the signal change between the reference and measured values.

[0026] In other words, the invention is based on the idea of ​​storing the states of quantum devices, such as quantum dots or quantum bits, particularly simultaneously in classical electronics, namely the associated sample-and-hold elements of the sample-and-hold modules, so that the actual (time) multiplexing does not have to take place within the coherence time of the quantum devices, as was previously the case, but can be performed outside of it. This offers the great advantage that new operations can then be performed by the quantum devices during the multiplexing process.

[0027] For this purpose, according to the invention, at least two sample-and-hold elements are assigned to each quantum device or each quantum state sensor, in particular one for the reference value and one for the measured value. The sample-and-hold elements are each part of a sample-and-hold module or jointly form one and are expediently triggered at different times within the quantum bit coherence time so that sampling processes can take place. It should be noted that two sample-and-hold elements are generally sufficient. Then, each module can sample a reference value at a first time with its one sample-and-hold element and a measured value from the assigned state sensor at a second, later time with its other sample-and-hold element. Simultaneous triggering of one sample-and-hold element each of all sample-and-hold modules is preferably possible.Then, reference or measured values ​​are recorded simultaneously using all sample and hold modules. In particular, to avoid error propagation, it can be advantageous to use a third sample and hold element with an additional reference value for each sample and hold module. In a further development, it can be provided that each sample and hold module comprises three sample and hold elements, preferably exactly three sample and hold elements. This makes it possible, in particular, to sample a new reference value for each iteration without restricting multiplexability outside the coherence time. More than three sample and hold elements per sample and hold module will generally not be necessary. However, it is also not excluded that a higher number of these is or will be provided for each module.

[0028] "Time-delayed" preferably means time-delayed from the coherence time. The reading of state values ​​held in the sample-and-hold elements particularly preferably takes place after the coherence time within which the states were sampled by the sample-and-hold elements.

[0029] The initialization of a quantum device is understood in particular to mean bringing it into a defined or known state. This is possible, for example, through relaxation. Following the initialization in step S1, the states or state values ​​of the quantum devices are thus known, and in step S2, in other words, known state values ​​are acquired using the sample and hold elements. This makes it possible, in particular, to consider these state values ​​as reference values.

[0030] It should be emphasized that the aforementioned steps of the method according to the invention do not necessarily have to be carried out in the above order; rather, a different order is also possible. Steps can also be repeated. For example, as an alternative to the order S1, S2, S3, S4, it can be provided that the initialization in step S1 is followed by an operation phase and a subsequent measurement phase, then initialization takes place again, and then, in a reference sampling phase, state values ​​are acquired and these reference values ​​are considered. In other words, the order would then be S1, S3, S4, (again) S1, and S2.

[0031] Purely as an example of quantum bit devices or components thereof, the aforementioned quantum dots are mentioned. Quantum dots, which are usually semiconductor-based, can be used to "capture" individual charges and their associated spin, which can then be used as quantum bits. They are also referred to as spin-based quantum bits or spin quantum bits. The present invention has proven particularly suitable for spin quantum bits.

[0032] Quantum devices such as quantum dots or quantum bits are typically operated at temperatures in the range of a few Kelvin, for example, 5 Kelvin. The readout device according to the invention is therefore expediently designed such that it can also be operated in this temperature range or at the higher temperature level in a mixture cryostat, which can be, for example, 55 Kelvin. Particularly preferably, the readout device is designed such that it can be operated in a temperature range from 100 millikelvin (mK) to 55 Kelvin.

[0033] In a particularly preferred embodiment, the readout device is located directly above the quantum device and is directly connected to it via VIAs (Vertical Interconnect Access). Due to the small space requirement, a design using an integrated circuit is expedient. The quantum bits of quantum computers are generally assigned state sensors. It is possible for each quantum bit to be assigned its own state sensor, or for several, such as two or more, quantum bits to share a state sensor. It is also possible for a pair comprising a data and an auxiliary quantum bit (ancilla qubit) to share a state sensor. Quantum bits can also be provided by two quantum dots, in other words, a quantum dot pair. Sensors for state detection can be provided by charge sensors, which is usually the case especially with spin quantum bits.

[0034] A charge sensor is, in particular, a single-electron transistor capacitively coupled to a quantum bit, or a quantum dot junction. When correctly adjusted, both change the conductance with high sensitivity to the capacitively coupled charge change of the quantum bit.

[0035] The quantum bit state values ​​can, for example, be the localization or spin properties of a particle representing quantum states, which can be converted into classical charge, current, or voltage values ​​using a corresponding sensor. In this process, the superposition of the quantum states is lost.

[0036] Preferably, exactly one read-and-hold module is present for each state sensor and is connected or connectable to it. It is also possible for exactly one read-and-hold module to be provided for each quantum bit. Preferably, the number of read-and-hold modules of the readout device according to the invention corresponds to the number of state sensors or the number of quantum bits of a quantum computer. To trigger sampling processes, at least two global trigger lines are provided. Preferably, a number of global trigger lines is provided that corresponds to the number of sample-and-hold elements per sample-and-hold module. The sample-and-hold modules are expediently all characterized by the same number of sample-and-hold elements.Preferably, one of the global trigger lines is connected to exactly one sample-and-hold element of each sample-and-hold module, allowing simultaneous triggering of one sample-and-hold element of each sample-and-hold module. The global trigger lines can, for example, each comprise a root section and several branch sections extending from it, each of which runs to a sample-and-hold element of each sample-and-hold module.

[0037] A module-by-module sequential transmission of quantum bit state values ​​to the respective global comparator or comparators is understood in particular to mean that the state values ​​held therein are transmitted or passed to the comparator module by module. The transmission of quantum bit state values ​​held in at least two sample-and-hold elements of a sample-and-hold module is expediently carried out simultaneously, so that a comparison of these values, in particular of the reference and measured values, can be performed in the comparator.

[0038] In an advantageous embodiment, the activation means provided according to the invention comprise a plurality of switches, transfer switches, wherein each sample and hold element is assigned one of the transfer switches. Preferably, a number of transfer switches corresponding to the number of sample and hold elements is present, and each sample and hold element is assigned exactly one transfer switch. Preferably, the respective transfer switch is arranged at the output of the associated sample and hold element and / or in one of the transmission lines. In particular, if a transfer switch is active or "switched on," a state value held in the associated sample and hold element is output and, in particular, transmitted or routed to the or a global comparator.

[0039] The global transmission lines can, for example, each comprise a root section and a plurality of branch sections extending therefrom, one of which in each case runs to a sample and hold element or to a transmission switch provided on the output side of at least one or more sample and hold modules.

[0040] Address lines can be provided by means of which the transfer switches can be addressed module by module. Preferably, each transfer switch is connected to two address lines and is activated when it receives a signal on both address lines—in other words, is addressed via both address lines. "Modularly addressable" means, in particular, that the sample-and-hold elements of individual modules can be addressed independently of those of other modules. Then, state values ​​of the sample-and-hold elements of only one module can be transferred to the global comparator or to a global comparator. The module-by-module transfer is more conveniently carried out sequentially, module by module.

[0041] The sample and hold modules can be arranged in an array of multiple rows and columns, which has proven to be particularly efficient in terms of space.

[0042] The present invention has proven particularly suitable for an arrangement of quantum bits referred to as a "spider-web array." Such a quantum bit array is described in the article "The spider-web array - a sparse spin quantum bit array" by Jelmer M. Boter et al., ar-Xiv:2110.00189v1 [quant-ph], October 1, 2021. The quantum bits and associated charge sensors are also arranged in rows and columns here. The readout device according to the invention is preferably used together with such a "spider-web array," in which case it is particularly preferred that the sample and hold modules of the readout device according to the invention or the sample and hold elements thereof are each arranged above, for example directly on, or next to the charge sensors of the "spider-web array."

[0043] The readout device according to the invention can, for example, be bonded or otherwise connected to a chip comprising or implementing quantum bits.

[0044] If the sample and hold modules or sample and hold elements are arranged in an array of rows and columns, an advantageous development of the readout device according to the invention can further provide for the address lines to extend either parallel to the rows formed by the sample and hold modules (row address lines) or parallel to the columns formed by the sample and hold modules (column address lines). This ensures a particularly small space requirement due to the address lines.

[0045] Each of the transfer switches is then connected, in particular, to a row address line and a column address line and is activated, in other words "switched on," when it receives a signal via both the row and column address lines. A further embodiment of the invention is further characterized in that the output of each sample-and-hold element is connected, in particular via one of the transfer lines, to an input of the global comparator or, in the case of several global comparators, preferably, wherein for each sample-and-hold module, the outputs of its sample-and-hold elements are connected to different inputs of the global comparator or of a global comparator.

[0046] The respective global comparator, or in the case of multiple comparators, the respective global comparator, is advantageously designed and / or configured to output a signal, in particular a binary signal, that depends on the signal change between two input values. In other words, the (respective) comparator preferably outputs a signal, in particular a binary signal, when there is a signal change between two input signals to be compared, in other words, between state values, i.e., when they differ from one another.

[0047] As regards the design of the sample and hold elements, it should be mentioned purely by way of example that these each comprise or are formed by a capacitor and an associated reset switch for resetting the capacitor.

[0048] Digital logic can also be used for time-shifted multiplexing. Accordingly, in a further development of the readout device according to the invention, digital logic is provided, which is designed such that the sequential transmission of quantum bit state values ​​held in the sample and hold elements takes place outside the coherence time of the quantum bit devices within which the held quantum bit state values ​​were sampled by the sample and hold elements. If digital logic is present, it can also be designed to implement the method according to the invention.

[0049] Particularly in the case where a comparatively high number of quantum bits is present, these, or the associated state sensors, can be divided into several sectors, and a separate global comparator can be used for each sector. A further embodiment is characterized in that the readout device is divided into several sectors, each sector comprising its own global comparator and connected to other sample-and-hold modules or connectable or connected to other quantum devices or state sensors, in particular charge sensors. This would be an embodiment of a readout device according to the invention with several global comparators. Separate trigger lines and separate transmission lines can then also be provided for each sector.

[0050] The readout device according to the invention can further comprise one or more preamplifiers and / or one or more switchable or non-switchable low-pass filters. The at least one optional preamplifier and / or at least one optional low-pass filter can be part of the respective sample and hold module. It is further preferred that the at least one optional preamplifier and / or the at least one optional low-pass filter is connected upstream of the sample and hold elements of the respective sample and hold module, in other words, the state values ​​are amplified and / or filtered.

[0051] In an advantageous development, the method according to the invention is characterized in that one or more iterations of method steps are carried out, wherein the respective iteration comprises steps S3 to S5 or steps S2 to S5 or steps S1 to S5 or steps S1 and S3 to S5. In other words, steps S3 to S5 or steps S2 to S5 or steps S1 and S3 to S5 or even all steps can be repeated several times in succession. Regarding the order, as noted, it can also vary here.

[0052] In particular, in the event that the respective iteration comprises steps S3 to S5, it is further preferred that the measured values ​​of the previous iteration can be regarded as reference values ​​and in step S4, state values ​​are sampled, held and regarded as measured values ​​using one or the other sample and hold elements.

[0053] It may also be provided that during a multiplexing phase following a coherence period, the quantum devices perform new operations. This may also apply to all iterations.

[0054] Particularly in the case where a readout device is used whose sample and hold modules each comprise three, preferably exactly three, sample and hold elements, it can further be provided that the three sample and hold elements are used in turn, in particular for recording reference and measured values. In other words, for example, a reference value can then be recorded first with a first sample and hold element of the respective module, then a measured value can be recorded with a second sample and hold element of the respective module, and finally a reference value can be recorded again with the third sample and hold element of the respective module. After that, the first can be used again for measured value recording, the second for reference value recording, the third for measured value recording, and so on.

[0055] In order to be able to detect and resolve dependencies between the results of a previous and subsequent operation, measures similar to those for the pipeline of a conventional processor are also provided in an advantageous further development. For example, operations that have no dependency on previous measured values ​​can be prioritized, or measured values ​​can be assumed speculatively. In the latter case, the result is conveniently discarded if the actual measured value deviates from the assumed measured value, and the operation is executed again. Furthermore, it is possible to pause the operation for the duration of the conflict.

[0056] The invention also relates to a quantum device, in particular a quantum computer, comprising a plurality of quantum devices, in particular quantum dots or quantum bits, and a readout device according to the invention, wherein in each case a quantum device or in each case a state sensor, in particular a charge sensor, serving to detect the state of at least one quantum device is connected to one of the sample and hold modules, preferably wherein in each case a sample and hold module is arranged above or next to a quantum device and / or above or next to a state sensor.

[0057] In particular, in the event that the quantum device according to the invention is designed as a quantum computer, it comprises, in an advantageous further development, an arrangement of quantum bits referred to as a “spider-web array”, as described in the above-mentioned article “The spider-web array - a sparse spin quantum bit array” by Jelmer M. Boter et al., arXiv:2110.00189v1 [quant-ph], 1 October 2021 .

[0058] In an advantageous development of the quantum device according to the invention, it is further provided that the quantum devices implement spin quantum bits, and / or that the quantum devices are provided by, in particular, semiconductor-based quantum dots, and / or that the state sensors, in particular charge sensors, comprise or are provided by, in particular, semiconductor-based quantum dots.

[0059] With regard to the embodiments of the invention, reference is also made to the subclaims and to the following description of embodiments with reference to the accompanying drawings.

[0060] The drawing shows:

[0061] Figure 1 is a purely schematic partial representation of a quantum computer with an embodiment of a readout device according to the invention in plan view;

[0062] Figure 2 is a circuit diagram of a sample and hold element, a transfer switch and address lines of the readout device of Figure 1;

[0063] Figure 3 shows a more detailed circuit diagram of the transfer switch from Figure 2;

[0064] Figure 4 is a purely schematic representation of four quantum bits arranged in an array with two rows and two columns; and

[0065] Figure 5 is a purely schematic representation of a time-delayed readout process.

[0066] Figure 1 shows, in a highly simplified, purely schematic partial representation, an embodiment of a quantum computer 1 according to the invention. This comprises, among other things, a plurality of quantum devices defined by quantum bits 2 and associated state sensors, which in the example shown here are designed as charge sensors 3 and serve to detect the state of the quantum bits 2. In the partial representation in Figure 1, nine quantum bits 2 and associated charge sensors 3 can be seen by way of example, only a few of which are provided with reference numerals by way of example. The quantum bits 2 and charge sensors 3 are arranged, for example, on a chip of the quantum computer 1. In the present case, the quantum bits are defined by spin quantum bits 2. These and the associated charge sensors 3, which are arranged in rows and columns, are part of a “spider-web array”, as described in the article “The spider-web array - a sparse spin quantum bit array” by Jelmer M.Boter et al., arXiv:2110.00189v1 [quant-ph], October 1, 2021 . However, this is to be understood purely as an example. The charge sensors 3 comprise or are formed by single-electron transistors. For the sake of completeness, it should be noted that, even though the quantum bits 2 are indicated in the purely schematic Figure 1 by block elements next to the corresponding charge sensors 3, their position may be poorly defined, especially in a spider web array, since the electrons are transferred between modules.

[0067] The charge sensors 3 can also be designed as described in Eugen Kammerloher's doctoral thesis "Improving the output signal of charge readout for quantum computing in electrostatically defined quantum dots with a new sensing dot concept" (doi: 10.18154 / RWTH-2022-01567) using the example of an asymmetric single-electron transistor, although this is to be understood purely as an example. Accordingly, the charge sensors 3 can generate a state-dependent signal of approximately 1 mV, for example, at a quiescent current of 500 pA.

[0068] The quantum computer 1 further comprises an embodiment of a readout device 4 according to the invention for the time-shifted readout of a plurality of quantum bits 2. It should be noted that further components of the quantum computer 1 are not shown in the highly simplified Figure 1 for reasons of clarity.

[0069] The readout device 4 comprises a plurality of sample-and-hold modules 5, each of which is connected to one of the charge sensors 3. Each sample-and-hold module 5 has two sample-and-hold elements 6, 7, with which quantum state values, specifically reference and signal values, can be sampled and held. The sample-and-hold elements 6, 7 are each connected to the associated charge sensor 3. Optionally, additional elements are interposed. In the present case, each sample-and-hold module 5 optionally comprises a preamplifier and / or optionally a switchable or non-switchable low-pass filter, which are connected between the respective charge sensor 3 and the respective sample-and-hold elements 6, 7, which can be connected in parallel to one another.

[0070] As can be seen in Figure 1, the two sample and hold elements 6, 7 of each module 5 are arranged on or above the associated charge sensor 3. Since Figure 1 shows nine charge sensors 3 by way of example, and each charge sensor 3 is assigned a sample and hold module 5 and thus two sample and hold elements 6, 7, a total of 18 sample and hold elements 6, 7 can be seen in Figure 1.

[0071] In addition to the sample-and-hold elements 6, 7, the readout device 4 comprises two global trigger lines (not shown in the figure) by means of which the sample-and-hold elements 6, 7 can be triggered. In this case, one sample-and-hold element 6 of each sample-and-hold module 5 is connected to one global trigger line, and the other sample-and-hold element 7 of each sample-and-hold module 5 is connected to the other global trigger line. Thus, one sample-and-hold element 6 of each module 5 can be triggered simultaneously via one trigger line, and the other sample-and-hold elements 7 of each module 5 can be triggered simultaneously via the other (independently of the two, or vice versa).

[0072] It should be noted that, as an alternative to the illustration in Figure 1, the sample-and-hold modules 5 can each comprise a further, in other words, third sample-and-hold element 6, 7. This is particularly useful to prevent error propagation. If each module 5 contains not just two, but three sample-and-hold elements 6, 7, a third trigger line is also expediently provided for the third sample-and-hold elements, which then enables simultaneous triggering of the third sample-and-hold elements.

[0073] The readout device 4 further comprises a global comparator 8 assigned to the plurality of sample-and-hold modules 5 and the plurality of state sensors 3, and two global transmission lines 9, 10, via which quantum state values ​​read and held by the sample-and-hold elements 6, 7 of the modules 5 can be transmitted to the global comparator 8. As can be seen in the figure, one sample-and-hold element 6 is connected to the comparator 8 via a transmission line 9, and the other sample-and-hold elements 7 are connected via the other transmission line 10. Each of the two transmission lines 9, 10 comprises a root section 9a, 10a and a plurality of branch sections 9b, 10b, each of which extends to the sample-and-hold elements 6, 7.

[0074] The sample and hold elements 6, 7 of the sample and hold modules 5 are further assigned activation means which are designed and / or configured such that quantum state values ​​held by the sample and hold elements 6, 7 can be transmitted sequentially, module by module, to the global comparator 8.

[0075] In the embodiment shown, the activation means comprise a plurality of transmission switches 11, which can only be seen in Figure 2, each of which is assigned to a sample and hold element 6, 7 and is located at the output of the respective sample and hold element 6, 7 and in one of the transmission lines 9, 10.

[0076] As can also be seen in Figure 2, the sample-and-hold elements each have, for example, a capacitor 12 and a reset switch 13 associated with the capacitor 12 for resetting the capacitor 12. The reset switch 13 for the capacitor 12 is optional. A further switch 14 is also provided on the input side of the respective sample-and-hold elements 6, 7. This switch 14 is closed when the corresponding global trigger line is activated, so that the capacitor 12 is charged to the current measured value of the charge sensor 3.

[0077] It is advisable that the sum of all leakage currents of a sample-and-hold circuit 6, 7 does not result in an excessive reduction in the signal. Assuming that a signal decrease of DeltaV = 300 mV is permissible, the maximum time between two sampling points is t=500 ps, ​​and the capacitor 12 of the sample-and-hold circuit has a capacitance of C=1 pF, the maximum total leakage current (assuming a constant leakage current) is C * DeltaV / C = 600 pA.

[0078] It should be noted that the requirement for the maximum leakage current during the phase in which both the reference and signal values ​​are held by the sample and hold elements 6, 7 is less strict, assuming that the difference in the leakage currents between the signal and reference sample and hold elements 6, 7 is significantly smaller than the total leakage current of one element 6, 7.

[0079] Furthermore, the signal-to-noise ratio should be at least large enough that the probability of a false electronic measurement is significantly lower than the error frequency of the quantum bit 2 to be read out.

[0080] When implementing the sample-and-hold elements 6, 7 and the global comparator 8, it is useful to note that the signal voltage of 1 mV is added to the quiescent voltage caused by the applied quiescent current to adjust the operating point of the single-electron transistor. This voltage represents the common-mode input voltage of the global comparator 8.

[0081] Depending on the level of the common-mode input voltage, it may be necessary to shift the reference potential of the readout device 4 relative to the reference potential of the quantum bit 2 with charge sensor 3, so that a more optimal common-mode input voltage of the comparator 8 is present.

[0082] The offset voltage of the comparator 8 should be at least so small that the probability of a false electronic measurement together with the influence of noise is significantly lower than the error frequency of the quantum bits 2 to be read out. A calibration option is expediently provided.

[0083] Ideally, the threshold voltage of comparator 8 lies exactly between the values ​​corresponding to quantum bit state 1 and quantum bit state 0. In addition to the transfer switches 11, the activation means comprise address lines 15, 16, by means of which the transfer switches 11 can be addressed module by module. In the illustrated embodiment, each of the address lines 15, 16 extends either parallel to the rows formed by the sample and hold modules 5 (row address lines 15), or parallel to the columns formed by the sample and hold modules 5 (column address lines 16). A row address line 15 is provided for each row of sample and hold modules 5, and a column address line 16 is provided for each column of sample and hold modules 5.

[0084] Each transfer switch 11 is connected to two address lines 15, 16 and is or will be activated, in other words "switched on," when it receives a signal on both address lines 15, 16. Each transfer switch 11 is connected to a row address line 15 and a column address line 16. It should be noted that in Figure 2, a block element 17 belonging to the transfer switch 11 and marked with an "&" visualizes that a signal is required on the row 15 and column address lines 16. Even though this is shown as a separate element in the schematic of Figure 2, it can of course also be integrated into the transfer switch 11 or form a structural unit with it.

[0085] As can be seen in Figure 1, each row address line 15 and each column address line 16 comprises two branch sections 15a, 15b, 16a, 16b, each of which extends to a transfer switch 11 of the sample and hold elements 6, 7 of a sample and hold module 5. The branch sections 15a, 15b, 16a, 16b ensure that the transfer switches 11 of both sample and hold elements 6, 7 of a module 5 are addressed simultaneously when the corresponding row and column are selected. The reference and measured values ​​held in a module 5 can thus each be fed simultaneously to the global comparator 8 and compared. However, due to the row- and column-wise addressing, only the values ​​of one sample and hold module 5 are ever fed to the comparator 8.

[0086] Figure 3 shows an enlarged view of an exemplary structure of a transfer switch 11 comprising NMOS transistors 18 and PMOS transistors 19. This is a conventional implementation of an analog switch. The PMOS transistor 19, marked INVP, and the NMOS transistor 18, marked INVN, form an inverter that inverts the digital control signal D_EN. The two control signals then simultaneously switch the transistors 18, 19, marked SWN and SWP, on and off, respectively. In contrast to a single transistor, this implementation has the advantages of a larger voltage range and lower charge injection, for example. However, any other switch implementation can also be used to optimize individual circuit parameters.

[0087] It should be noted that, as an alternative to the exemplary embodiment shown here, it is also possible for a readout device 4 according to the invention to comprise more than one global comparator 8, for example two, three, or more global comparators 8. This is particularly true if the number of quantum devices to be read out, such as qubits 2, is comparatively large. The quantum devices, in particular qubits 2 and any associated state sensors 3, can then be divided into several sectors, and a separate global comparator can be used for each sector. Accordingly, a readout device 4 according to the invention can also be divided into several sectors, each sector comprising its own global comparator 8, and each comparator 8 being connected to other sample and hold modules 5 or being or being connectable to other state sensors, in particular charge sensors 3, of a quantum computer 1.Then, separate trigger lines and separate transmission lines 9, 10 can be provided for each sector.

[0088] Using the readout device 4, an embodiment of a readout method according to the invention can be carried out, which is described below with reference to Figures 4 and 5.

[0089] In an initialization phase In (see Figure 5), all quantum bits 2 of the quantum computer 1 are initialized simultaneously (step S1). Figure 4 shows, in a purely schematic representation, four charge sensors 3 of the quantum computer 1, each associated with a quantum bit 2, arranged in an array of two rows and two columns. The charge sensors 3 are numbered CS0 to CS3. These could, for example, be the four charge sensors 3 in the top left corner of Figure 1. The quantum bits are not shown again in Figure 4.

[0090] Initialization is understood in particular to mean that the quantum bits are brought into a defined or known state, which is possible, for example, through relaxation. Following the initialization in step S1, the states or state values ​​of the quantum bits 2 are thus known.

[0091] In a step S2, in a reference sampling phase RO, the (defined, known) state values ​​of the quantum bits 2 are acquired after initialization, in particular simultaneously, by means of the sample and hold modules 5, with one of the two sample and hold elements 6 of each sample and hold module 5 sampling and holding a state value, and these state values ​​are considered reference values. To initiate the acquisition of the reference values, a trigger TR1 (cf. Figure 5) is output to the sample and hold elements 6 of all sample and hold modules 5 via the one global trigger line, and these sample. In other words, the reference values ​​are transferred to a conventional electronics, namely the associated sample and hold elements 6, within the coherence time Ko of the quantum bits 2, which is also shown in Figure 5 (unitless).

[0092] In a subsequent operation phase, the quantum bits perform 2 operations (step S3, also abbreviated as “Ma” for “Manipulation” in Figure 5).

[0093] Then, in step S4, in a measurement sampling phase RO, state values ​​of the quantum bits 2 are simultaneously acquired by the connected sample and hold modules 5, with the other, second sample and hold element 7 of each sample and hold module 5 sampling and holding the state value, and these state values ​​are considered measured values. This is again achieved by simultaneously triggering the other, second sample and hold elements 7 of each sample and hold module. The corresponding trigger is denoted by TR2 in Figure 5. In other words, the measured values ​​are also transferred to classical electronics, namely the associated sample and hold elements 7, within the coherence time Ko of the quantum bits 2.

[0094] Outside of the respective coherence time Ko, specifically after this time, the held reference and measured values ​​are transferred sequentially, module by module, to the global comparator 8 in a multiplex phase for comparison (step S5 and abbreviation "Comp" in Figure 5). In this case, the sample and hold elements 6, 7 are addressed one after the other - module 5 by module 5 - via the address lines 15, 16, specifically their transfer switch 11. In the example shown in Figure 5, the state values ​​are transferred in the order CSO, CS1, CS2, CS3, which is indicated by the abbreviations R.0, R.1, R.2 and R.3 bottom right. In order to transfer the held states of the sample and hold module 5 from the first charge sensor CSO to the global comparator 8, a signal is passed via the row address line RO and column address line CO. For the second charge sensor CS1 on the row address line R1 and the column address line CO and so on (cf.the signals shown in Figure 5 for CO, C1, RO and R1).

[0095] The global comparator 8 outputs a particular binary signal whenever there is a signal change between the compared reference value and the measured value.

[0096] Steps S3 to S5, for example, can then be repeated any number of times, with the measured values ​​from the previous iteration being considered as reference values ​​in each case, and in step S4, state values ​​are sampled, held, and considered as measured values ​​using one or the other of the sample and hold elements 6, 7. In other words, in the next iteration, the measured values ​​from the distance and hold elements 7 would serve as reference values, and the measured values ​​would now be acquired using the sample and hold elements 6, which were previously used for the reference.

[0097] It should be noted that it is of course also possible for the initialization, i.e., step S1, and / or the reference sampling phase, i.e., step S2, to be part of the iteration, in other words, to also occur in the respective iteration. Furthermore, it should be emphasized that the order of the steps (in the respective iteration) can also be different.

[0098] During the time-multiplexing phase, new operations can then be performed by the quantum bits 2. Digital logic can be present that is configured to implement the method described above. The digital logic can be a component of the readout device 4 or be assigned to it.

[0099] List of reference symbols

[0100] 1 quantum computer

[0101] 2 quantum bits

[0102] 3 Charge sensor

[0103] 4 Reading device

[0104] 5 Sample and hold module

[0105] 6 Sample and hold element

[0106] 7 Sample and hold element

[0107] 8 global comparator

[0108] 9 Transmission line

[0109] 9a Root section

[0110] 9b branch section

[0111] 10 transmission line

[0112] 10a Root section

[0113] 10b branch section

[0114] 11 Transfer switch

[0115] 12 Capacitor

[0116] 13 Reset switch

[0117] 14 additional switches

[0118] 15 Address line

[0119] 15a branch section

[0120] 15b branch section

[0121] 16 Address line

[0122] 16a branch section

[0123] 16b branch section

[0124] 17 Block element

[0125] 18 NMOS transistors

[0126] 19 PMOS transistor

[0127] C0 first column address line C1 second column address line

[0128] R0 first row address line

[0129] R1 second row address line

[0130] CSO first charge sensor

[0131] CS1 second charge sensor

[0132] CS2 third charge sensor

[0133] CS3 fourth charge sensor

[0134] In initialization phase

[0135] Ma Operation phase

[0136] RO sampling phase

Claims

CLAIMS 1. Readout device (4) for the time-shifted readout of several quantum devices (2), in particular quantum dots or quantum bits, comprising - a plurality of sample and hold modules (5), wherein each of the sample and hold modules (5) is connected or connectable to at least one quantum device (2) or to a state sensor, in particular a charge sensor (3), used to detect the state of at least one quantum device (2), and wherein each of the sample and hold modules (5) comprises at least two sample and hold elements (6, 7), with which quantum state values ​​from the at least one connected or connectable quantum device (2) or the connected or connectable state sensor (3) can be sampled and held, - at least two global trigger lines by means of which the sample and hold elements (6, 7) of the sample and hold modules (5) can be triggered, - at least one global comparator (8) associated with several sample and hold modules (5), - at least two global transmission lines (9, 10) via which quantum state values ​​held in the sample and hold elements (6, 7) of the associated sample and hold modules (5) can be transmitted to the respective global comparator (8), and - activation means associated with the sample and hold elements (6, 7) of the sample and hold modules (5), which activation means are designed and / or arranged such that quantum state values ​​held by the sample and hold elements (6, 7) of the sample and hold modules (5) are can be transmitted sequentially to the respective global comparator (8).

2. Read-out device (4) according to claim 1, characterized in that the activation means comprise a plurality of switches (11), transfer switches, wherein each sample and hold element (6, 7) is assigned one of the transfer switches (11), wherein the respective transfer switch (11) is arranged in particular at the output of the associated sample and hold element (6, 7) and / or in one of the transmission lines (9, 10), and wherein address lines (15, 16) are provided, by means of which the transfer switches (11) can be addressed module by module, preferably wherein each transfer switch (11) is connected to two address lines (15, 16) and is activated when it receives a signal on both address lines (15, 16).

3. Read-out device (4) according to claim 1 or 2, characterized in that the sample and hold modules (5) are arranged in an array of several rows and columns.

4. Read-out device (4) according to claim 2 and 3, characterized in that the address lines (15, 16) each extend either parallel to the rows formed by the sample and hold modules (5), row address lines, or each extend parallel to the columns formed by the sample and hold modules (5), column address lines, preferably, wherein each of the transfer switches (11) is connected to a row address line and a column address line and is activated when it receives a signal via both the row and the column address line.

5. Read-out device (4) according to one of the preceding claims, characterized in that the output of each sample and hold element (6, 7) is connected, in particular via one of the transmission lines (9, 10), to an input of the or the respective global comparator (8), preferably, wherein for each sample and hold module (5) the outputs of its sample and hold elements (6, 7) are connected to different inputs of the or the respective global comparator (8).

6. Read-out device (4) according to one of the preceding claims, characterized in that the or the respective global comparator (8) is designed and / or arranged such that it outputs a signal, in particular a binary signal, which is dependent on the signal change between two input values.

7. Read-out device (4) according to one of the preceding claims, characterized in that the sample and hold elements (6, 7) each comprise or are formed by a capacitor (12) and preferably an associated reset switch (13) for resetting the capacitor (12).

8. Readout device (4) according to one of the preceding claims, characterized in that a digital logic is provided which is designed such that the sequential transmission of quantum state values ​​held in the sample and hold elements (6, 7) takes place outside the coherence time of the quantum bit devices (2) within which the held quantum state values ​​were sampled with the sample and hold elements (6, 7).

9. Reading device (4) according to one of the preceding claims, characterized in that the reading device (4) is divided into several sectors ren, each sector comprising its own global comparator (8) and connected to other quantum devices (2) or state sensors (3) connectable or connected.

10. Read-out device (4) according to one of the preceding claims, characterized in that each sample and hold module (5) comprises three sample and hold elements (6, 7), preferably exactly three sample and hold elements (6, 7).

11. Reading device (4) according to one of the preceding claims, characterized in that a digital logic is provided which is designed to carry out the method according to one of claims 14 to 18.

12. Quantum device, in particular quantum computer (1), comprising a plurality of quantum devices (2), in particular quantum dots or quantum bits, and a readout device (4) according to one of claims 1 to 11, wherein in each case a quantum device (2) or in each case a state sensor, in particular a charge sensor (3) serving to detect the state of at least one quantum device (2) is connected to one of the sample and hold modules (5), preferably wherein in each case a sample and hold module (5) is arranged above or next to a quantum device (2) and / or above or next to a state sensor (3).

13. Quantum device (1) according to claim 12, characterized in that the quantum devices (2) implement spin quantum bits, and / or that the quantum devices (2) are provided by, in particular, semiconductor-based quantum dots, and / or that the state, in particular charge sensors (3) comprise, in particular, semiconductor-based quantum dots or are provided by such.

14. Method for the time-shifted readout of a plurality of quantum devices (2), in particular quantum dots or quantum bits, using a readout device (4) according to one of claims 1 to 11, in which 51) in an initialization phase, several quantum devices (2), in particular all quantum devices (2), are initialized, preferably simultaneously, 52) in a reference sampling phase, state values ​​of the quantum devices (2) are detected after initialization, in particular simultaneously by means of the connected sample and hold modules (5), wherein a sample and hold element (6, 7) of each sample and hold module (5) samples and holds a state value, and these state values ​​are regarded as reference values, 53) in an operation phase the quantum devices (2) perform operations, 54) in a measurement sampling phase, state values ​​of the quantum devices (2) are recorded, in particular simultaneously, by means of the connected sample and hold modules (5), wherein a different sample and hold element (6, 7) of each sample and hold module (5) samples and holds the state value, and these state values ​​are regarded as measured values, 55) in particular after the end of the coherence time of the quantum devices (2) in a multiplex phase, the held reference and measured values ​​are transmitted sequentially in modules to the respective global comparator (8) in order to compare them, in particular, wherein the respective global comparator (8) each outputs a signal, in particular a binary signal, which is dependent on the signal change between the reference value and the measured value.

15. The method according to claim 14, characterized in that one or more iterations of method steps are carried out, wherein the or the respective iteration comprises steps S3 to S5 or steps S2 to S5 or steps S1 to S5 or steps S1 and S3 to S5.

16. The method according to claim 15, characterized in that the or the respective iteration comprises steps S3 to S5, wherein the measured values ​​of the previous iteration are regarded as reference values ​​and in step S4, state values ​​are sampled, held and regarded as measured values ​​using one or the other sample and hold elements (6, 7).

17. Method according to one of claims 14 to 16, characterized in that the quantum devices (2) carry out new operations during a multiplex phase following a coherence time.

18. Method according to one of claims 14 to 17, characterized in that a readout device (4) according to claim 10 is used and the three, in particular exactly three, sample and hold elements (6, 7) of the sample and hold modules (5) are used in turn, in particular for detecting reference and measured values.

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