Electronic device for controlling command provided to display

Abstract

An electronic device includes a display including a display driving integrated circuit and display panel , a memory including storing instructions, and a processor , wherein the instructions, when executed by the processor , cause the electronic device to obtain a second image to be displayed after the first image while the first image is displayed on the display panel , store the second image in the memory based on an event, wherein the event includes transmitting data of an image to the display driving integrated circuit at a reference refresh rate higher than a refresh rate for the second image, and, while the second image is displayed on the display panel , transmit the data for the second image obtained from the memory again to the display driving integrated circuit to display the second image on the display panel based on the reference refresh rate.

Description

[Technical Field]

[0001] The present disclosure relates to an electronic device controlling a command provided to a display.[Background Art]

[0002] For various visual effects, an electronic device may provide an image combining a plurality of layers or images. The electronic device may obtain each layer, combine the obtained layers, and provide the image. The electronic device may display the image on a display based on a refresh rate for the combined image.

[0003] The above-described information may be provided as a related art for the purpose of helping to understand the present disclosure. No claim or determination is raised as to whether any of the above-described information may be applied as a prior art related to the present disclosure.[Disclosure] [Technical Solution]

[0004] An electronic device is disclosed. The electronic device may comprise a display including a display driving integrated circuit and display panel. The electronic device may further comprise memory including one or more storage mediums storing instructions. The electronic device may further comprise at least one processor including one or more processing circuits. The instructions, when executed individually or collectively by the at least one processor, cause the electronic device to obtain, while a first image is displayed on the display panel, a second image obtained by using multiple images as an image to be changed from the first image on the display panel. The at least one processor may be configured to at least temporarily store the second image in the memory, based on an event of transmitting data of an image to the display driving integrated circuit at a reference refresh rate higher than a refresh rate for the second image. The at least one processor may be configured to transmit the data of the second image to the display driving integrated circuit to display the second image on the display panel. The at least one processor may be configured to transmit the data of the second image obtained from the memory again to the display driving integrated circuit to display the second image again on the display panel, based on the reference refresh rate, while the second image is displayed on the display panel through the display driving integrated circuit.

[0005] A method is disclosed. The method may be executed in an electronic device comprising a display including a display driving integrated circuit and a display panel. The method may comprise obtaining a second image generated by using multiple images as an image to be changed from a first image on the display panel while the first image is displayed on the display panel. The method may comprise at least temporarily storing the second image in the memory, based on an event of transmitting data of an image to the display driving integrated circuit at a reference refresh rate higher than a refresh rate for the second image. The method may comprise transmitting the data for the second image to the display driving integrated circuit to display the second image on the display panel. The method may comprise transmitting the data for the second image obtained from the memory again to the display driving integrated circuit to display the second image again on the display panel, based on the reference refresh rate, while the second image is displayed on the display panel through the display driving integrated circuit.

[0006] An electronic device is disclosed. The electronic device may comprise a display including a display driving integrated circuit including a first memory configured to store image and display panel. The electronic device may comprise second memory including one or more storage mediums storing instructions. The electronic device may comprise a plurality of processors, including at least one first processor and at least one second processor, including one or more processing circuits. The instructions, when executed by the second processor, cause the electronic device to obtain a second image generated by using multiple images obtained from the first processor as an image to be changed from the first image on the display panel, while the first image is displayed on the display panel, based on an event that the first memory is deactivated. The instructions may cause the electronic device to at least temporarily store the second image in the second memory, based on an event of transmitting data of the second image to the display driving integrated circuit at a reference refresh rate higher than a refresh rate for the second image. The instructions may cause the electronic device to transmit the data of the second image to the display driving integrated circuit to display the second image on the display panel. The instructions may cause the electronic device to transmit the data of the second image obtained from the second memory again to the display driving integrated circuit to display the second image again on the display panel, based on the reference refresh rate, while the second image is displayed on the display panel through the display driving integrated circuit.

[0007] A method is disclosed. The method may be executed in an electronic device comprising a display including a display driving integrated circuit including a first memory configured to store an image and display panel, and a plurality of processors, including at least one first processor and at least one second processor, including one or more processing circuits. The method may comprise obtaining a second image, in which multiple images obtained from the first processor are overlaid, as a next image of the first image, while the first image is displayed on the display panel, based on an event that the first memory is deactivated. The method may comprise at least temporarily storing the second image in the second memory based on an event of transmitting data for the second image to the display driving integrated circuit at a reference refresh rate higher than a refresh rate for the second image. The method may comprise transmitting the data for the second image to the display driving integrated circuit to display the second image on the display panel. The method may comprise transmitting the data for the second image obtained from the second memory again to the display driving integrated circuit to display the second image again on the display panel, based on the reference refresh rate, while the second image is displayed on the display panel through the display driving integrated circuit.[Description of the Drawings]

[0008] FIG. 1 is a simplified block diagram illustrating an exemplary electronic device. FIG. 2A is a diagram illustrating an operation of generating an image obtained through a plurality of layers. FIG. 2B is a diagram illustrating an operation of generating an image obtained by replacing some layers of an image obtained through a plurality of layers. FIG. 3 is a diagram illustrating storing an image in memory and transferring the image stored in the memory to a display driving integrated circuit. FIG. 4 is a diagram illustrating storing an image in memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a first event. FIG. 5 is a diagram illustrating storing an image in memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a second event. FIG. 6A is a diagram illustrating storing an image in memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a third event. FIG. 6B is a diagram illustrating storing an image in memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a fourth event. FIG. 7 is a diagram illustrating storing an image in memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a fifth event. FIG. 8 is a block diagram of an electronic device 801 in a network environment according to various embodiments. FIG. 9 is a block diagram of a display module according to various embodiments. [Mode for Invention]

[0009] FIG. 1 is a simplified block diagram illustrating an exemplary electronic device.

[0010] Referring to FIG. 1, an electronic device 100 may include at least one processor 110, at least one first memory 120, and a display 130. In the electronic device 100, components other than those shown in Fig. 1 may be added or some components may be omitted.

[0011] The at least one processor 110 may include at least a portion of a processor 820 of FIG. 8. The at least one processor 110 may be operably coupled to the display 130 (or a display driving integrated circuit 131) and the at least one first memory 120. The at least one processor 110 being operably coupled to the display 130 and / or the at least one first memory 120 may represent that they are directly or indirectly connected. For example, the at least one processor 110 being operably coupled to the display driving integrated circuit 131 of the display 130 may represent that the at least one processor 110 is connected to the display driving integrated circuit 131 through an interface 135. For example, the interface 135 may be configured to transmit an image from the at least one processor 110 to the display driving integrated circuit 131. For example, the interface 135 may be a Display Serial Interface (DSI) of the Mobile Industry Processor Interface (MIPI) Alliance. However, it is not limited thereto. For example, the at least one processor 110 being operably coupled to the display driving integrated circuit 131 may mean that the display driving integrated circuit 131 operates based on instructions executed by the at least one processor 110. For example, the at least one processor 110 being operably coupled to the display driving integrated circuit 131 may mean that the display driving integrated circuit 131 is controlled by the at least one processor 110. For example, when the at least one processor 110 is operated, the instructions may cause the electronic device 100 to provide visual information through a display panel 133 by controlling the display driving integrated circuit 131. The at least one processor 110 may display an image on the display panel 133 by using the display driving integrated circuit 131 based on a video hybrid mode of the DSI.

[0012] The at least one processor 110 may include a first processor 111, a second processor 112, and an internal memory 113. The first processor 111 may include a central processing unit (CPU) or a graphics processing unit (GPU). The second processor 112 may include a display controller (or a display processing unit (DPU)). The first processor 111, the second processor 112, and the at least one first memory 120 may be operably coupled to each other. For example, that the first processor 111, the second processor 112, and the at least one first memory 120 are operably coupled to each other may represent that the first processor 111, the second processor 112, and the memory 120 are directly or indirectly connected to each other.

[0013] The first processor 111 may generate visual information through graphic processing. For example, the first processor 111 may generate an image, video, or user interface (UI) through graphic processing. The generated visual information may be displayed on the display 130 and thus provided to a user. The generated visual information may be generated from an image obtained from the at least one first memory 120. For example, the first processor 111 may obtain at least two images from the at least one first memory 120 and obtain the generated visual information by combining the obtained at least two images. The first processor 111 may store the generated visual information in the internal memory 113 or transfer the generated visual information to the second processor 112. For example, the first processor 111 may transfer a command, control, information, and / or control signal related to the generated visual information to the second processor 112. The generated visual information may be visual information in which a plurality of layers included in the obtained at least two image are combined.

[0014] The second processor 112 may be operably coupled to the display driving integrated circuit 131. The second processor 112 being operably coupled to the display driving integrated circuit 131 may represent that the second processor 112 is connected to the display driving integrated circuit 131 through the interface 135. For example, the interface 135 may be configured to transmit an image from the second processor 112 to the display driving integrated circuit 131. For example, the second processor 112 may be configured to transfer a signal related to an image to the display driving integrated circuit 131 through the interface 135. The signal related to the image may include image display characteristics such as resolution, refresh rate, or screen brightness. The first processor 111 and the second processor 112 are shown as separate processors, but this disclosure is not limited thereto. For example, the first processor 111 and the second processor 112 may be implemented as one processor.

[0015] The at least one processor 110 may comprise the internal memory 113. The internal memory 113 may store an image or visual information generated by the at least one processor 110. The internal memory 113 may store various data used by the at least one processor 110. The data may be visual information generated by the first processor 111 or the second processor 112 or image display characteristics such as resolution, refresh rate, or screen brightness.

[0016] The at least one first memory 120 may include at least a portion of memory 830 of FIG. 8. The at least one first memory 120 may store various data used by the at least one processor 110. The data may be visual information generated by the first processor 111 or the second processor 112 or image display characteristics such as resolution, refresh rate, or screen brightness. The at least one first memory 120 may be a plurality of memories. The first processor 111 and / or the second processor 112 may be operably connected to the at least one first memory 120. For example, the first processor 111 may be connected to one of the plurality of memories, and the second processor 112 may be connected to another one of the plurality of memories. The first processor 111 or the second processor 112 may be connected to one of the plurality of memories. The first processor 111 and / or the second processor 112 may comprise the at least one first memory 120. The at least one first memory 120 may include a volatile memory.

[0017] The display driving integrated circuit 131 may include at least a portion of a display driver integrated circuit (DDI) 930 of FIG. 9. The display driving integrated circuit 131 may be operably coupled to the display panel 133. For example, the display driving integrated circuit 131 being operably coupled to the display panel 133 may represent that the display driving integrated circuit 131 is connected to the display panel 133. For example, the display driving integrated circuit 131 being operatively coupled to the display panel 133 may represent that the display panel 133 is controlled by the display driving integrated circuit 131. However, it is not limited thereto. The display driving integrated circuit 131 may include a second memory 132. The second memory 132 may include at least a portion of memory 933 of FIG. 9. The second memory 132 may be configured to be selectively activated or deactivated. For example, the second memory 132 may be configured to be selectively connected to the first display driving integrated circuit 131. The display driving integrated circuit 131 may further include a switch (not illustrated) configured to be selectively connected to the second memory 132. The switch may be connected to the at least one processor 110.

[0018] The second memory 132 may be a memory in the display driving integrated circuit 131. The second memory 132 may include a graphic random-access memory (GRAM) or a video random-access memory (VRAM). The second memory 132 may store image information to be displayed on the display panel 133. The image to be displayed on the display panel 133 may be transferred to the display panel 133 through the first processor 111, the second processor 112, and the display driving integrated circuit 131. The second memory 132 in the display driving integrated circuit 131 may store the image transferred to the display panel 133. After displaying the image on the display panel 133, the display driving integrated circuit 131 may be configured to display the image stored in the second memory 132 again on the display panel 133.

[0019] An electronic device operating in a DSI command mode may store the image displayed on the display panel 133 in the second memory 132 inside the display driving integrated circuit 131. The display driving integrated circuit 131 may transfer the stored image to the display panel 133 by reading or loading the stored image as needed. The operation of storing the image in the second memory 132 and reading or loading again as needed may be referred to as a self-scan. In effect, in the command mode, the display driving integrated circuit 131 can read or load the image stored in the second memory 132 without the need for further input from the at least one processor 110.

[0020] When an electronic device is operating in a DSI video hybrid mode, the display driving integrated circuit 131 may display an image on a display panel based on a first state or a second state. The first state is a state in which the second memory 132 is deactivated. For example, the first state may correspond to a video mode of the DSI. The second state may be a state for displaying an image using the second memory 132 in the display driving integrated circuit 131, i.e., the second state is a state in which the second memory 132 is activated. The second state correspond to a command mode of the DSI. In effect, in the second state, the display driving integrated circuit 131 may store data for displaying the image obtained from the at least one processor 110 in the second memory 132. In the second state, the display driving integrated circuit 131 may display an image on the display panel 133 by scanning data stored in the second memory 132, i.e., by conducting a self-scan operation. In the video hybrid mode, the display driving integrated circuit 131 may display an image obtained from the at least one processor 110. In the video hybrid mode, the first state and the second state may be selectively provided. The display driving integrated circuit 131 may display the image obtained from the at least one processor 110 based on activation or deactivation of the second memory 132 in the display driving integrated circuit 131.

[0021] According to an embodiment, in the video hybrid mode of the DSI, the electronic device 100 may require a self-scan. According to an embodiment, in the video hybrid mode of the DSI, since the display driving integrated circuit 131 activates selectively the second memory 132, the self-scan operation by the at least one processor 110 instead of the self-scan operation of the display driving integrated circuit 131 may be supported. The self-scan operation by the at least one processor 110 may be the same as the operation in the second state in which the second memory 132 below is activated.

[0022] The current consumption of the second memory 132 may be reduced as the video hybrid mode of the DSI provides the first state for deactivating the second memory 132 in a state that the update of the image displayed on the display panel 133 is frequent. The display driving integrated circuit 131 may obtain image data stored in the second memory 132 instead of receiving image data from the at least one processor 110 as the video hybrid mode of the DSI provides the second state for activating the second memory 132 in a state of occasionally updates of the image displayed on the display panel 133. For example, in the second state, the display driving integrated circuit 131 may read an image stored in the second memory 132.

[0023] According to an embodiment, the display panel 133 may include at least a portion of a display 910 of FIG. 9. During the first state in which the second memory 132 is deactivated, at least one first processor 110 may store image data in the internal memory 113 and / or the at least one first memory 120. In a case that both the internal memory 113 and the first memory 120 in the electronic device 100 are used, the at least one processor 110 may obtain a rendered image or blended images from the first memory 120. The at least one processor 110 may store the image or image data for the images in the internal memory 113 for self-scanning by the processor. In a case that only the first memory 120 of the internal memory 113 and the first memory 120 in the electronic device 100 is used, the at least one processor 110 may obtain the rendered image or the blended images from the first memory 120. The at least one processor 110 may store the image or image data for the images in the first memory 120 for self-scanning by the processor. According to an embodiment, at least one processor 110 may store the image displayed on the display panel 133 in the first memory 120 or the internal memory 113 in an initial frame for the image, when a self-scan operation for displaying the same image again on the display panel 133 is required because the image displayed on the display panel 133 is not changed.

[0024] According to an embodiment, in the command mode of the DSI, the at least one processor 110 may store image data in the at least one first memory 120. According to an embodiment, the at least one processor 110 may obtain image data stored in the at least one first memory 120. For example, the at least one processor 110 may read image data stored in the at least one first memory 120.

[0025] The operation of the electronic device 100 in the first state in the command mode of the DSI or the video hybrid mode of the DSI will be described below FIG. 2A.

[0026] FIG. 2A is a diagram illustrating an operation of generating an image using a plurality of layers. FIG. 2B is a diagram illustrating an operation of generating an image obtained by replacing some layers of an image comprising the plurality of layers. An image layer may include a transparent portion to allow overlap and combination with other image layers, or may be smaller than the combined image, e.g., image 210.

[0027] Referring to FIGS. 2A and 2B, at least one processor 110 may generate an image 210 by mixing a plurality of layers 201, 202 and 203. The plurality of layers 201, 202 and 203 may be configured to overlap each other. The at least one processor 110 may obtain the image 210 by on overlapping and mixing the layers 201, 202 and 203. For example, the at least one processor 110 may generate the image 210 based on overlapping and mixing the layers 201, 202 and 203. For example, a second processor 112 may obtain the layers 201, 202 and 203 generated by a first processor 111. For example, the second processor 112 may obtain the layers 201, 202 and 203 stored in at least one memory 120. The second processor 112 may blend the obtained layers 201, 202 and 203. The second processor 112 may combine the layers 201, 202 and 203 using software, but is not limited thereto. For example, the second processor 112 may obtain the combined image 210 from the layers 201, 202 and 203 using another circuit or another component configured to combine the plurality of layers.

[0028] The second processor 112 is described as obtaining the combined image 210 based on the layers 201, 202 and 203, but is not limited thereto. For example, the first processor 111 may generate the plurality of layers 201, 202 and 203 and combine the plurality of generated layers 201, 202 and 203. For example, the first processor 111 may generate the plurality of layers 201, 202 and 203 and obtain the image 210 combined with the generated layers, using the other circuit or the other component.

[0029] The at least one processor 110 may write back the obtained image 210 to the at least one first memory 120. The write back may represent recording data related to the image 210 in the at least one first memory 120 or storing data related to the image 210 in an allocated space 220 in an internal memory 113 or the at least one first memory 120. For example, an instruction for at least temporarily storing the image in the internal memory 113 or the at least one first memory 120, when executed individually or collectively by the one or more processors, may cause the electronic device 100 to store the image in the space 220 when there is an empty space for the image in the internal memory 113 or the at least one first memory 120. When the at least one processor 110 includes an internal memory 113, to facilitate reading the image again by the at least one processor 110, the image may be stored in a space 220 in the internal memory 113. When the at least one processor 110 does not include an internal memory 113, the image may be stored in a space 220 of the first memory 120. When the at least one processor 110 executes instructions stored in the at least one first memory 120, the electronic device may obtain a second image to be displayed after a first image displayed on a display panel 133 and may remove or delete data for the second image from the space 220 in the at least one first memory 120 or the internal memory 113. The at least one processor 110 may obtain the image 210 recorded in the internal memory 113 or the at least one first memory 120. For example, the at least one processor 110 may read the image 210 recorded in the internal memory 113 or the at least one first memory 120.

[0030] The at least one processor 110 may store the combined image 210 in the internal memory 113 or the at least one first memory 120, and obtain the stored image 210, and therefore omit the operation of blending the plurality of layers 201, 202, and 203. Reducing the number of blending operations carried out by the electronic device 100 reduces the total current consumed by blending operations. By reducing the total current consumed by blending operations, the overall current and power usage of the electronic device 100 may be reduced.

[0031] The at least one processor 110 may be configured to transfer the combined image 210 to a display driving integrated circuit 131. For example, the at least one processor 110 may transfer the combined image 210 to the display driving integrated circuit 131 through an interface 135. Based on obtaining the image 210 by mixing the plurality of layers 201, 202 and 203, the at least one processor 110 may be configured to write the obtained image 210 to the at least one first memory 120, and simultaneously transmit the obtained image 210 to the display driving integrated circuit 131. The at least one processor 110 may transmit the obtained image 210 to the display driving integrated circuit 131 and then transmit the stored image 210 again to the display driving integrated circuit 131. For example, the at least one processor 110 may be configured to transmit the obtained image 210 to the display driving integrated circuit 131 and simultaneously store the obtained image 210 in the internal memory 113 or the at least one first memory 120, and then transmit the image 210 obtained from the internal memory 113 or the at least one first memory 120 again to the display driving integrated circuit 131.

[0032] The display driving integrated circuit 131 may be configured to display the received image 210 through the display panel 133.

[0033] Referring to FIG. 2B, the at least one processor 110 may write (or store) the image 210 obtained by blending (or mixing) the plurality of layers 201, 202 and 203 in the space 220 in the internal memory 113 or the at least one memory 120 and may transmit the image 210 to the display driving integrated circuit 131 through the interface 135. In a state in which the image 210 is recorded in the internal memory 113 or the at least one memory 120, the at least one processor 110 may combine an additional layer 201' into the image 210. For example, the at least one processor 110 may obtain a combined image 210' based on the image 210 and the additional layer 201'. The additional layer 201' may be a layer similar to a first layer 201 among the plurality of layers 201, 202 and 203 used to combine the image 210. For example, the first layer 201 may be a layer representing a status bar, a second layer 202 may be a layer representing a background image, and a third layer 203 may be a layer representing an icon. For example, the first layer 201 has a relatively small image area, but may have more frequent image changing, switching or conversion, as compared to the other layers 202 and 203.

[0034] The at least one processor 110 may obtain the image 210 stored in the space 220. The image 210 may be a layer in which the first layer 201, the second layer 202, and the third layer 203 are combined. The at least one processor 110 may obtain the image 210' by mixing the image 210 and the additional layer 201'. For example, the at least one processor 110 may generate the image 210' based on the image 210 and the additional layer 201'. For example, the second processor 112 may obtain the image 210 stored in the internal memory 113 or the at least one memory 120 and the additional layer 201'. For example, the second processor 112 may obtain the additional layer 201' generated from the first processor 111 and the image 210 stored in the internal memory 113 or the at least one memory 120. The second processor 112 may blend the obtained additional layer 201' and the stored image 210. The second processor 112 may combine the additional layer 201' and the stored image 210 using software, but is not limited thereto. For example, the second processor 112 may obtain the combined image 210' from the additional layer 201' and the stored image 210 using another circuit or another component configured to combine the additional layer 201' and the stored image 210.

[0035] According to an embodiment, the second processor 112 is described as obtaining the combined image 210' based on the additional layer 201' and the image 210, but is not limited thereto. For example, the first processor 111 may generate the additional layer 201', and obtain an image from the generated additional layer 201' and the image 210 obtained from the internal memory 113 or the at least one memory 120. For example, the first processor 111 may generate the additional layer 201', and obtain the image 210' combined with the generated additional layer 201' and the image 210 obtained from the internal memory 113 or the at least one memory 120 using the other circuit or the other component.

[0036] According to an embodiment, when combining the additional layer 201' and the image 210, the at least one processor 110 may be configured to remove a portion corresponding to the layer 201 displayed on the image 210 and combine the additional layer 201'. The at least one processor 110 may record another image obtained by combining the second layer 202 and the third layer 203 in the internal memory 113 or the at least one memory 120 when combining the image 210 of after combining the image 210. For example, in order to generate the image 210, the at least one processor 110 may first generate an intermediate image by combining the second layer 202 and the third layer 203, and then obtain the image 210 by combining the intermediate image with the first layer 201. The at least one processor 110 may store (or record) the obtained image 210 and the intermediate image obtained by combining the second layer 202 and the third layer 203 in the internal memory 113 or the at least one memory 120. The at least one processor 110 may store the image 210 in the space 220 in the internal memory 113 or the memory 120, and store (or record) the intermediate image obtained by combining the second layer 202 and the third layer 203 in another space different from the space 220.

[0037] The at least one processor 110 may obtain the intermediate image obtained by combining the second layer 202 and the third layer 203 different from the image 210 stored in the space 220 in the internal memory 113 or the at least one memory 120. The at least one processor 110 may obtain the image 210' by mixing the intermediate image obtained by combining the second layer 202 and the third layer 203 and the additional layer 201'. For example, the at least one processor 110 may generate the image 210' based on the intermediate image obtained by combining the second layer 202 and the third layer 203 and the additional layer 201'. For example, the second processor 112 may obtain the image obtained by combining the second layer 202 and the third layer 203 stored in the internal memory 113 or the at least one memory 120 and the additional layer 201'. For example, the second processor 112 may obtain the intermediate image obtained by combining the second layer 202 and the third layer 203 stored in the internal memory 113 or the at least one memory 120 and the additional layer 201' generated by the first processor 111. The second processor 112 may blend the intermediate image obtained by combining the second layer 202 and the third layer 203 and the obtained additional layer 201'. The first processor 111 may generate the additional layer 201', and obtain the image 210' by combining the intermediate image obtained by combining the second layer 202 and the third layer 203 obtained from the internal memory 113 or the at least one memory 120 and the generated additional layer 201' using another circuit or another component. The at least one processor 110 may write back the image 210' to the internal memory 113 or the at least one first memory 120.

[0038] Although the second processor 112 is described as obtaining the combined image 210' based on the additional layer 201' and the image 210, it is not limited thereto.

[0039] According to an embodiment, when an image 210 is displayed on the display panel 133, and when a self-scan operation for displaying the same image, i.e., the image 210, again on the display panel 133 is required, i.e., to maintain the image 210 on the display panel 133, the electronic device 100 may store the image 210 in the internal memory 113 or the at least one first memory 120 while the image 210 is initially displayed on the display panel 133. A self-scan operation is required, for example, to remove an afterimage or ghosting effect; in adjusting the display brightness; in changing the screen mode, e.g., to a night mode in which the screen has a warmer color tone; in compensating for the screen image quality or optical characteristics of the display panel.

[0040] According to an embodiment, the at least one processor 110 may be configured to transmit an image stored in the internal memory 113 or the at least one first memory 120 to the display driving integrated circuit 131 at a previous frame timing in the self-scan operation. Since the combined image 210' is stored in the internal memory 113 or the at least one memory 120, the current consumption used for overlay combining may be improved by omitting the combining process. The at least one processor 110 may obtain the image 210' recorded in the internal memory 113 or the at least one first memory 120. For example, in case that the write back operation supports the internal memory 113 of the at least one processor 110, the at least one processor 110 may read the image 210' recorded in the internal memory 113. In case that the write back operation does not support the internal memory 113 of the at least one processor 110, the at least one processor 110 may read the image 210' recorded in the at least one first memory 120. The at least one processor 110 may omit the repetition of the operation of blending a plurality of layers 201', 202 and 203 by storing the image 210' in the internal memory 113 or the at least one first memory 120 and obtaining the stored image 210'. By reducing the current consumed in the blending operation, the power usage of the electronic device 100 may be reduced. The at least one processor 110 may be configured to transfer the combined image 210' to the display driving integrated circuit 131. The at least one processor 110 may transfer the combined image 210' to the display driving integrated circuit 131 through the interface 135. Based on obtaining the image 210' in which the plurality of layers 201', 202 and 203 are mixed, the at least one processor 110 may be configured to record the obtained image 210' to the internal memory 113 or the at least one first memory 120, and simultaneously transmit the obtained image 210' to the display driving integrated circuit 131. The at least one processor 110 may transmit the image 210' again to the display driving integrated circuit 131, after transmitting the obtained image 210' to the display driving integrated circuit 131. The display driving integrated circuit 131 may be configured to display the received image 210' through the display panel 133.

[0041] The image 210 and 210' of FIG. 2A or FIG. 2B may be an image obtained by combining each of a plurality of images. The meaning of the combination may represent combining multiple images, combining a plurality of images obtained by combining multiple images, or combining at least one image obtained by combining multiple images and another image. For example, the image 210 of FIG. 2A may be an image obtained by combining images composed of the plurality of layers 201, 202 and 203. The image 210' of FIG. 2B may be an image obtained by combining the multiple image 210 obtained by combining images composed of the plurality of layers 201, 202 and 203 and another image 201'. Combining a plurality of images obtained by combining multiple images may be an image obtained by combining the multiple image 210 obtained by combining images composed of the plurality of layers 201, 202 and 203 and multiple images obtained by combining images composed of another plurality of layers. The combination may represent overlaying a plurality of layers and obtaining one image using a plurality of layers.

[0042] The at least one processor 110 may include at least one first processor 111 and at least one second processor 112, wherein the instructions, when executed by the second processor 112, may cause the electronic device 100 to obtain a first partial image of the first layer 201 from the at least one first processor 111, obtain the image 210' by combining the first partial image with the image 210 obtained from the internal memory 113 or the memory 120, and transmit the image 210' to the display driving integrated circuit 131. The instructions, when executed by the second processor 112, may cause the electronic device to obtain a partial image displayed on the additional layer 201' different from the partial image displayed on the first layer 201 from the at least one first processor 111 while the image 210 is displayed on the display panel 133. The instructions, when executed by the second processor 112, may cause the electronic device to obtain the image 210' by combining the partial image displayed on the additional layer 201' with the image 210 obtained from the internal memory 113 or the memory 120. The instructions, when executed by the second processor 112, may cause the electronic device 100 to transmit the image 210' to the display driving integrated circuit 131. A partial image may be a part or an area of an image or layer, i.e., a subregion of the image or layer.

[0043] FIG. 3 is a diagram illustrating storing an image in a memory and transferring the image stored in the memory to a display driving integrated circuit.

[0044] A blended first image 301, a blended second image 302, a blended third image 303, and a blended fourth image 304 may be obtained through a combining operation of FIG. 2A or FIG. 2B, i.e., the images 210 and 210'. One or more of the first image 301, the second image 302, the third image 303, and the fourth image 304 may not have been formed using the combining operation.

[0045] Referring to FIG. 3, at least one processor 110 may transmit the blended first image 301 to a display driving integrated circuit 131 through an interface 135. For example, the at least one processor 110 may obtain a first image 331 during a first time period 311 corresponding to a vertical synchronization signal period. For example, the display driving integrated circuit 131 may display the first image 301 obtained through the interface 135 from the at least one processor 110 on a display panel 133 based on the vertical synchronization signal.

[0046] The at least one processor 110 may identify that a specified event occurs. The at least one processor 110 may obtain the blended second image 302 during a second time period 312 corresponding to the vertical synchronization signal period after the specified event occurs. The specified event is an event in which self-scan is required. To maintain the optical characteristics of the display panel 133, the specified event may include an operation performed for preventing a momentary afterimage, changing the screen brightness, or changing the screen mode. The at least one processor 110 may transmit the blended second image 302 to the display driving integrated circuit 131 through the interface 135. For example, the display driving integrated circuit 131 may obtain the second image 302 from the at least one processor 110 through the interface 135. Then, the display driving integrated circuit 131 may display the second image 302 obtained through the interface 135 from the at least one processor 110 on the display panel 133. The at least one processor 110 is described as obtaining the blended second image 302 after a specified event occurs, but it is not limited thereto. The at least one processor 110 may obtain the blended second image 302 and then identify that a specified event occurs. For example, the at least one processor 110 may obtain the second image 302 as an image to be displayed after the blended first image 301. For example, the at least one processor 110 may obtain the second image 302, that is an image to be changed from the first image 301 on the display panel, while the first image 301 is displayed. The at least one processor 110 may be configured to at least temporarily store the second image 332 in at least one memory 120 based on a specified event. The specified event may be an event that causes the display driving integrated circuit to transmit data for the second image 302 and / or 332 at a reference refresh rate f2 (e.g., 60 Hz or 120 Hz) higher than a refresh rate f1 (e.g., 30 Hz) for the second image 302. The refresh rate f1 for the second image 302 may represent a frequency targeted for displaying the image when the second image is obtained or blended. For example, the second time period 312 may be a time period identified for the second image when the second image 302 is obtained or blended. The reference refresh rate may represent a frequency targeted to transmit an image recorded in the at least one memory 120 to the display driving integrated circuit 131 through the interface 135. The instructions stored in the at least one memory 120, when executed by the second processor 112, may cause the electronic device 100 to display the second image 302 on the display panel 133 through the display driving integrated circuit 131 until the display driving integrated circuit 131 receives a third image 303 different from the second image 302 through the at least one first processor 111.

[0047] The at least one processor 110 may at least temporarily record or store the blended second image 302 in the at least one memory 120. For example, the at least one processor 110 may at least temporarily store a blended image obtained by overlaying multiple images in the at least one memory 120 and transmit the blended image to the display driving integrated circuit 131. The at least one processor 110 may refrain from recording or storing a blended image obtained from a single image in the at least one memory 120, and transmit the blended image to the display driving integrated circuit 131.

[0048] For example, based on identifying that the first image 301 is to be changed to the second image 302 in the second time period 312 after the specified event occurs, the at least one processor 110 may transmit the blended second image 302 to the display driving integrated circuit 131 through the interface 135 and simultaneously record the blended second image 302 to at least one memory 120. For example, the data for the second image 302 may be transmitted to the display driving integrated circuit 131 to display the second image 302 on the display panel 133. The at least one processor 110 may transmit the second image 332 stored in the at least one memory 120 to the display driving integrated circuit 131 through the interface 135 when it is identified that the second image 302 is to be maintained during the vertical synchronization signal after obtaining the second image 302. While the second image 302 is displayed on the display panel 133 through the display driving integrated circuit 131, the at least one processor 110 may transmit the data for the second image 332 obtained from the at least one memory 120 to the display driving integrated circuit 131 to display the second image 302 or 332 again on the display panel 133 based on the reference refresh rate f2. The display driving integrated circuit 131 may obtain the second image 332 stored in the at least one memory 120 from the at least one processor 110 through the interface 135. For example, the display driving integrated circuit 131 may display the second image 332 stored in the at least one memory 120 obtained through the interface 135 from the at least one processor 110 on the display panel 133. A blended image and the blended image stored in the at least one memory 120 may be the same image. For example, the blended second image 302 and the second image 332 stored in the at least one memory 120 may be substantially the same image.

[0049] If self-scan is not used and the second image 302 is not stored in the at least one memory 120, then the at least one processor 110 must repeatedly blend each frame and must repeatedly transmit the blended images to the display driving integrated circuit 131 through the interface 135 to repeatedly display the images 302-1, 302-2, and 302-3 which are identical to the second image 302. By using the image 332 stored in the at least one memory 120, the number of times that blending is required may be reduced, and the total current and power consumption required for blending may be reduced.

[0050] The at least one processor 110 may obtain the blended third image 303 during a third time period 313 corresponding to the vertical synchronization signal period during which a specified event is maintained or continues to be detected. The at least one processor 110 may transmit the blended third image 303 to the display driving integrated circuit 131 through the interface 135. For example, the display driving integrated circuit 131 may obtain the third image 303 from the at least one processor 110 through the interface 135. For example, the display driving integrated circuit 131 may display the third image 303 obtained through the interface 135 from the at least one processor 110 on the display panel 133.

[0051] The at least one processor 110 may record the blended third image 303 in the at least one memory 120. For example, based on identifying that the second image 302 is to be changed to the third image 303 in the third time period 313 after the specified event occurs, the at least one processor 110 may transmit the blended third image 303 to the display driving integrated circuit 131 through the interface 135 and simultaneously record the blended third image 303 in the at least one memory 120. The at least one processor 110 may transmit the third image 333 stored in the at least one memory 120 to the display driving integrated circuit 131 through the interface 135 when it is identified that the third image 303 is to be maintained during the vertical synchronization signal after obtaining the third image 303. The display driving integrated circuit 131 may obtain the third image 333 stored in the at least one memory 120 from the at least one processor 110 through the interface 135. For example, the display driving integrated circuit 131 may display the third image 333 stored in the at least one memory 120 obtained through the interface 135 from the at least one processor 110 on the display panel 133.

[0052] The at least one processor 110 may obtain the fourth image 304 blended in a fourth time period 314 corresponding to the vertical synchronization signal period based on identifying that a specified event ends. The at least one processor 110 may transmit the blended fourth image 304 to the display driving integrated circuit 131 through the interface 135. For example, the display driving integrated circuit 131 may obtain the fourth image 304 from the at least one processor 110 through the interface 135. For example, the display driving integrated circuit 131 may display the fourth image 304 obtained through the interface 135 from the at least one processor 110 on the display panel 133. For example, the at least one processor 110 may bypass or refrain from storing or recording the fourth image 304 obtained by the at least one processor 110 in the at least one memory 120 based on identifying that the specified event ends.

[0053] The above-described specified event may include a mode change of the display panel 133. For example, the mode change of the display panel 133 may include changing the brightness of the display panel 133. For example, the above-described specified event may include changing a brightness level of the display panel 133 from a first brightness level to a second brightness level different from the first brightness level within a predetermined number of frames.

[0054] The above-described specified event may include blocking a particular color of light emitted from a display. For example, the above-described specified event may include changing the display to a blue light blocking mode. For example, the above-described specified event may include changing an amount of light emitted from subpixels configured to emit a specified color from a first light amount level to a second light amount level different from the first light amount level within a predetermined number of frames. For example, the above-described specified event may include changing the brightness level of a specified color from the first brightness level to the second brightness level through software processing within a predetermined number of frames.

[0055] The above-described specified event may include preventing an afterimage of the display panel. For example, the probability that an afterimage will be caused by hysteresis in a driving transistor for driving an organic light emitting diode in a display panel may increase as a time length from the end timing of displaying an image to the start timing of a next image increases. The above-described specified event may include that a time period during which one or more images is displayed is longer than a reference time length. For example, the above-described specified event may include that a time for which an image displayed on the display is displayed on the display panel is longer than a reference time. For example, the above-described specified event may include that a refresh rate for the image displayed on the display panel is lower than a refresh rate for a previously displayed image.

[0056] Examples of the above-described specified event are described in detail with reference to FIGS. 4 to 7.

[0057] FIG. 4 is a diagram illustrating storing an image in a memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a first event.

[0058] Referring to FIG. 4, at least one processor 110 may sequentially display a first image 401 and a second image 402. The at least one processor 110 may display the second image 402 on a display panel 133 after displaying the first image 401 on the display panel 133. For example, the at least one processor 110 may switch the image displayed on the display panel 133 from the first image 401 to the second image 402. The at least one processor 110 may be configured to obtain the second image 402 overlaid with multiple images while the first image 401 is displayed on the display panel 133. The at least one processor 110 may transmit the first image 401 to a display driving integrated circuit 131 through an interface 135 to display the first image 401 on the display panel 133.

[0059] The at least one processor 110 may obtain the blended second image 402 within a time period 411 corresponding to a vertical synchronization signal period. The at least one processor 110 may be configured to transmit the data for the second image 402 to the display driving integrated circuit 131 to display the second image 402 on the display panel 133. For example, the at least one processor 110 may transmit the blended second image 402 to the display driving integrated circuit 131 through the interface 135 to display the second image 402 on the display panel 133.

[0060] The at least one processor 110 may at least temporarily store or record the second image 402 in at least one memory 120 based on a first event, i.e., when a first event occurs. The first event may be an event that causes the data for the second image 402 to be transmitted to the display driving integrated circuit 131 at a reference refresh rate f2 higher than a refresh rate f1 for displaying the second image 402.

[0061] The first event may include an operation during which an afterimage is to be prevented, i.e., an operation during which there is likely to be an afterimage effect. The first event may include that a time length from the start timing of displaying the first image 401 to the end timing of displaying the first image 401 is longer than a reference time length. For example, the first event may include that the length of the time (1 / 30s * 4 frames) at which the first image 401 is displayed on the display panel 133 is longer than the length of the reference time (e.g., 1 / 10s). In case that the displayed time is greater than the reference time length, when the second image 402 is displayed on the display panel 133, a portion of the first image 401 that is a previous image of the second image 402 may continue to be displayed, causing the afterimage effect. The reference time length depends on the display panel 133, and may be a maximum time length for which an image may be displayed by the display panel 133 without causing an afterimage effect.

[0062] The at least one processor 110 may be configured to display an image corresponding to the second image 402 again on the display panel 133 to remove the afterimage. For example, the at least one processor 110 may be configured to transmit data for a second image 432 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the second image 402 again on the display panel 133 based on the reference refresh rate f2 while the second image 402 is displayed on the display panel 133 through the display driving integrated circuit 131. The at least one processor 110 may at least temporarily record or store the blended second image 302 in the at least one memory 120. For example, based on identifying that the first image 401 changes to the second image 402 in the time period 411 after the first event occurs, or identifying that the first image 401 changes to the second image and the first event occurs in the time period 411, the at least one processor 110 may transmit the blended second image 402 to the display driving integrated circuit 131 through the interface 135 and simultaneously record the blended second image 402 in the at least one memory 120. For example, the data for the second image 402 may be transmitted to the display driving integrated circuit 131 to display the second image 402 on the display panel 133.

[0063] When it is identified that the second image 402 is maintained in the vertical synchronization signal after obtaining the second image 402, the at least one processor 110 may transmit the second image 432 stored in the at least one memory 120 to the display driving integrated circuit 131 through the interface 135. The at least one processor 110 may be configured to transmit data for the second image 432 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the second image 402 or 432 again on the display panel 133 based on the reference refresh rate f2 while the second image 402 is displayed on the display panel 133 through the display driving integrated circuit 131. The display driving integrated circuit 131 may obtain the second image 432 stored in the at least one memory 120 from the at least one processor 110 through the interface 135. For example, the display driving integrated circuit 131 may display the second image 432 stored in the at least one memory 120 on the display panel 133. The at least one processor 110 may display the second image 402 obtained from the at least one processor 110 on the display panel 133 through the display driving integrated circuit 131, and then display the second image 432 stored in the at least one memory 120 on the display panel 133 as the following frame. The display panel 133 may reduce or remove the afterimage caused by the first image 401 by displaying the second image 432 obtained from the at least one memory 120 corresponding to the second image 402 again.

[0064] FIG. 5 is a diagram illustrating storing an image in memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a second event.

[0065] Referring to FIG. 5, at least one processor 110 may sequentially display a first image 501 and a second image 502. The at least one processor 110 may control the display to display the second image 502 on the display panel 133 after displaying the first image 501 on the display panel 133. For example, the at least one processor 110 may switch the image displayed on the display panel 133 from the first image 501 to the second image 502. The at least one processor 110 may be configured to obtain the second image 502 as a next image of the first image 501 while the first image 501 is displayed on the display panel 133. For example, the at least one processor 110 may be configured to obtain the second image 502 generated using the multiple images or layers as an image to be changed from the first image 501, i.e., the next image to be displayed after the first image 501, while the first image 501 is displayed on the display panel 133. The at least one processor 110 may transmit the first image 501 to a display driving integrated circuit 131 through an interface 135 to display the first image 501 on the display panel 133.

[0066] The at least one processor 110 may obtain or generate the blended second image 502 in a time period 511 corresponding to a vertical synchronization signal period. The at least one processor 110 may be configured to transmit the data for the second image 502 to the display driving integrated circuit 131 to display the second image 502 on the display panel 133. For example, the at least one processor 110 may transmit the blended second image 502 to the display driving integrated circuit 131 through the interface 135 to display the second image 502 on the display panel 133.

[0067] The at least one processor 110 may at least temporarily store or record the second image 502 in at least one memory 120 based on a second event.

[0068] The second event may include a mode change of the display panel 133, as described hereinbefore. For example, the mode change of the display panel 133 may include a change in brightness of the display panel 133. For example, the second event may include changing a brightness level of the display panel 133 from a first brightness level to a second brightness level different from the first brightness level within a predetermined number of frames. For example, the second event may include changing a brightness level of a specified color from the first brightness level to the second brightness level through software processing within a predetermined number of frames. When the brightness level of the image displayed on the display panel 133 changes from the first brightness level to the second brightness level in the next frame, a user of an electronic device 100 may perceive an unnatural screen switch, i.e., may notice a sudden jump in the brightness of the screen. Therefore, the at least one processor 110 may cause the brightness level of the image displayed through the display panel 133 to be more gradually changed.

[0069] In order to change the first brightness level to the second brightness level during a specified frame , i.e., within a predetermined number of frames (e.g., within 5 frames), the at least one processor 110 may transfer an image stored in at least one memory to the display driving integrated circuit 131 during at least a portion of the specified frame. For example, the at least one processor 110 may be configured to gradually lower the brightness level during the specified frame to adjust the brightness level of the display panel.

[0070] For example, the at least one processor 110 may receive a second event while the second image 502 is displayed on the display panel 133, or receive the second event while the first image 501, which is an image displayed before the second image 502, is displayed on the display panel 133. When the second event is identified, the at least one processor 110 may be configured to record an image to be displayed in the next frame in the at least one memory 120. For example, when the second event is identified while the second image 502 is displayed on the display panel 133, the at least one processor 110 may record or store the second image 502 in the at least one memory 120. For example, when identifying the second event while the first image 501 is displayed on the display panel 133, the at least one processor 110 may record or store the second image 502, which is an image to be displayed in a frame after receiving the second event, in the at least one memory 120. For example, when the second event is identified in a time interval or time period l0 during which the first image 501 is displayed, the at least one processor 110 may record or store the second image 502 to be displayed in the next time interval 11 after the time interval l0 in the at least one memory 120.

[0071] The at least one processor 110 may adjust the gray scale of the second image 502 to be displayed on the display panel 133 in the next frame based on identifying the second event of changing the brightness level of a specified color from the first brightness level to the second brightness level through software processing within a predetermined number of frames. The interval between the first brightness level and the second brightness level may be divided into a step corresponding to a specified number of frames. For example, the first image 501 may be displayed on the display panel 133 as the first brightness level, and the second image 502 may be converted into a first divided brightness level obtained by dividing the first brightness level and the second brightness level into five sub-levels.

[0072] The at least one processor 110 may transfer the gray-scale-adjusted second image 502 to the display driving integrated circuit 131 to display the gray-scale-adjusted second image 502 on the display panel 133 at the first divided brightness level based on the second event. The at least one processor 110 may store or record the gray-scale-unadjusted second image 502 in the at least one memory 120 while transferring the gray-scale-adjusted second image 502 to the display driving integrated circuit 131, based on the second event. For example, the at least one processor 110 may transfer the gray-scale-adjusted second image 502 to the display driving integrated circuit 131 to display the second image during the first time interval l1 on the display panel 133 based on the second event, and store images to be displayed in a second time interval l2 or after the second time interval l2 in the at least one memory 120.

[0073] The at least one processor 110 may read or obtain an image to be displayed in the second time interval l2 from the at least one memory 120 to adjust the brightness level to the second brightness level. The at least one processor 110 may obtain a second image 532 stored in the at least one memory 120 to change the brightness of the display panel 133 to a second divided brightness level between the first brightness and the second brightness while the second image 502 is displayed on the display panel 133 through the display driving integrated circuit 131. The at least one processor 110 may adjust the gray scale of the second image 532 obtained from the at least one memory 120 to have the second brightness level.

[0074] The at least one processor 110 may be configured to transmit data for the second image 532 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the second image 502 again on the display panel 133. The at least one processor 110 may transfer the gray-scale-adjusted second image 502 to the display driving integrated circuit 131 to display the gray-scale-adjusted second image 532 obtained from the at least one memory 120 on the display panel 133 at the second divided brightness level during the second time interval l2, based on the second event. When there is no change in an image displayed from the second time interval l2 to a fifth time interval l5, the at least one processor 110 may transfer the gray scale of data for an image obtained from the at least one memory 120 to the display driving integrated circuit 131 in each time interval by adjusting the gray scale of data obtained from the at least one memory 120 as a brightness corresponding to each time interval.

[0075] The at least one processor 110 may be configured to record or store a third image 503 to be displayed in the next frame following the second image 532 in the at least one memory 120 when the image displayed on the display panel 133 changes from the second image 502 or 532 to the third image 503 or 533 during the specified frame. For example, when the image displayed on the display panel 133 changes from the second image 532 displayed in the second time interval l2 to the third image 503, the at least one processor 110 may record or store the third image 503 in the at least one memory 120. For example, the at least one processor 110 may record or store the third image 503 to be displayed in the third time interval l3 in the at least one memory 120.

[0076] The at least one processor 110 may transfer the gray-scale-adjusted second image 502 to the display driving integrated circuit 131 to display the gray-scale-adjusted second image 502 on the display panel 133 at the first divided brightness level, based on the second event. The at least one processor 110 may store or record the gray-scale-unadjusted second image 502 in the at least one memory 120 while transferring the gray-scale-adjusted second image 502 to the display driving integrated circuit 131, based on the second event. For example, the at least one processor 110 may transfer the gray-scale-adjusted second image 502 to the display driving integrated circuit 131 to display the second image during the first time interval l1 on the display panel 133 based on the second event, and store images to be displayed in the second time interval l2 or after the second time interval l2 in the at least one memory 120.

[0077] The at least one processor 110 may obtain the third image 503 to be displayed in the third time interval l3 to adjust the brightness level to the second brightness level. The at least one processor 110 may transmit the third image 503 to the display driving integrated circuit 131 through the interface 135 to display the third image 503 on the display panel 133, and at least temporarily store or record the third image 503 in the at least one memory 120.

[0078] The at least one processor 110 may adjust the gray scale of the blended third image 503 to change the brightness of the display panel 133 to a third divided brightness level between the first brightness and the second brightness so that the brightness-adjusted third image 503 is displayed on the display panel 133 through the display driving integrated circuit 131. The at least one processor 110 may store the blended third image 503 in the at least one memory 120 to be used again in the next frame.

[0079] The at least one processor 110 may obtain the third image 533 stored in the at least one memory 120. The at least one processor 110 may adjust the gray scale of the third image 533 obtained from the at least one memory 120 to have the second brightness level.

[0080] The at least one processor 110 may be configured to transmit data for the third image 533 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the third image 503 again on the display panel 133 in the third time interval 13. The at least one processor 110 may transfer a gray-scale-adjusted third image 533 to the display driving integrated circuit 131 to display the gray-scale-adjusted third image 533 obtained from the at least one memory 120 at the fourth divided brightness level on the display panel 133 during a fourth time interval l4, based on the second event. When there is no change in an image displayed in the fifth time interval l5, the at least one processor 110 may transfer the gray scale of data for the third image 533 obtained from the at least one memory 120 to the display driving integrated circuit 131 in the fifth time interval l5 by adjusting the gray scale of data for the third image 533 obtained from the at least one memory 120 as a fifth divided brightness.

[0081] The above-described brightness change is illustrated as adjusting a color of an image, such as the gray scale, by the at least one processor 110, but is not limited thereto. The at least one processor 110 may be configured to adjust a source voltage and a gate voltage applied to the display panel 133 through the display driving integrated circuit 131 to adjust the brightness of the display panel 133. For example, the at least one processor 110 may transmit image data to the display driving integrated circuit 131. The image data may include information related to the magnitude of the source voltage and the gate voltage to adjust the brightness of the display panel 133.

[0082] FIG. 6A is a diagram illustrating storing an image in a memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a third event.

[0083] Referring to FIG. 6A, at least one processor 110 may sequentially display a first image 601 and a second image 602. The at least one processor 110 may display the second image 602 on a display panel 133 after displaying the first image 601 on the display panel 133. For example, the at least one processor 110 may switch the image displayed on the display panel 133 from the first image 601 to the second image 602. The at least one processor 110 may be configured to obtain a third image 603 overlaid with multiple images as a next image of the second image 602, i.e., an image to display after the second image 602, while the second image 602 is displayed on the display panel 133. For example, the at least one processor 110 may be configured to obtain the second image 602 using the multiple images while the first image 601 is displayed on the display panel 133. The at least one processor 110 may transmit the second image 602 to a display driving integrated circuit 131 through an interface 135 to display the second image 602 on the display panel 133.

[0084] The at least one processor 110 may obtain the blended third image 603 in a time period t1 corresponding to a vertical synchronization signal period. The time period t1 may be a time period using a time at which the second image 602 starts to be displayed on the display panel 133 as a start time point, and a time at which the second image 602 stops displaying on the display panel 133 as an end time point. For example, the time period t1 may use the time at which the first image 601 stops being displayed as a start time point, and use the time at which the third image 603 starts being displayed as an end time point.

[0085] The at least one processor 110 may be configured to transmit the data for the third image 603 to the display driving integrated circuit 131 to display the third image 603 on the display panel 133. For example, the at least one processor 110 may transmit the blended third image 603 to the display driving integrated circuit 131 through the interface 135 to display the third image 603 on the display panel 133.

[0086] The at least one processor 110 may at least temporarily store or record the third image 603 in the at least one memory 120 based on a third event. The third event may include preventing an afterimage of the display panel 133. The third event may include that a length of time from the time at which the second image 602 starts being displayed to the time at which the second image 602 stops being displayed is longer than a reference time length. For example, the third event may include that the length of time during which the second image 602 is displayed on the display panel 133 is longer than the length of the reference time. In case that the displayed time is greater than the length of the reference time, when the third image 603 is displayed on the display panel 133, a portion of the second image 602, which is a previous image of the third image 603, may be displayed.

[0087] The third event may include preventing an afterimage of the display panel 133. The first event may include that a time length from the start timing of displaying the first image 601 to the end timing of displaying the first image 601 is longer than the reference time length. For example, the first event may include that the length of the time (1 / 30s * 4 frames) at which the first image 601 is displayed on the display panel 133 is longer than the length of the reference time (e.g., 1 / 10s). In case that the displayed time is greater than the reference time length, when the third image 603 is displayed on the display panel 133, a portion of the second image 602, which is a previous image of the third image 603, may be displayed.

[0088] The at least one processor 110 may be configured to display an image corresponding to the third image 603 again on the display panel 133 to remove the afterimage. For example, the at least one processor 110 may be configured to transmit data for a third image 633 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the third image 603 again on the display panel 133, based on a reference refresh rate related to reading an image stored in the at least one memory 120, while the third image 603 is displayed on the display panel 133 through the display driving integrated circuit 131. The at least one processor 110 may at least temporarily record or store the blended third image 603 in the at least one memory 120. For example, based on identifying that the time period t1, which is a display time of the second image 602, is longer than a reference time length ts, the at least one processor 110 may transmit the blended third image 603 to the display driving integrated circuit 131 through the interface 135 and simultaneously record the blended third image 603 in the at least one memory 120. For example, the data for the third image 603 may be transmitted to the display driving integrated circuit 131 to display the third image 603 on the display panel 133.

[0089] The at least one processor 110 may transmit the third image 633 stored in the at least one memory 120 to the display driving integrated circuit 131 through the interface 135 based on identifying that the third image 603 is maintained in the vertical synchronization signal time period after obtaining the third image 603. The at least one processor 110 may be configured to transmit data for the third image 633 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the third image 603 or 633 again on the display panel 133, based on the reference refresh rate related to reading the image stored in the at least one memory 120, while the third image 603 is displayed on the display panel 133 through the display driving integrated circuit 131. The display driving integrated circuit 131 may obtain the third image 633 stored in the at least one memory 120 from the at least one processor 110 through the interface 135. For example, the display driving integrated circuit 131 may display the third image 633 stored in the at least one memory 120 on the display panel 133. The at least one processor 110 may display the third image 603 obtained from the at least one processor 110 on the display panel 133 through the display driving integrated circuit 131, and then display the third image 633 stored in the at least one memory 120 on the display panel 133 in a subsequent frame. The display panel 133 may remove the afterimage caused by the second image 602 by displaying the third image 633 obtained from the at least one memory 120 corresponding to the third image 603 again.

[0090] FIG. 6B is a diagram illustrating storing an image in a memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a fourth event.

[0091] Referring to FIG. 6B, at least one processor 110 may sequentially display a second image 612 and a third image 613. The at least one processor 110 may display the third image 613 on a display panel 133 after displaying the second image 612 on the display panel 133. For example, the at least one processor 110 may switch the image displayed on the display panel 133 from the second image 612 to the third image 613. The at least one processor 110 may be configured to obtain the third image 613 overlaid with multiple images as a next image of the second image 612 while the second image 612 is displayed on the display panel 133. For example, the at least one processor 110 may be configured to obtain the third image 613 using the multiple images as an image to be changed from the second image 612 while the second image 612 is displayed on the display panel 133. The at least one processor 110 may transmit the second image 612 to a display driving integrated circuit 131 through an interface 135 to display the second image 612 on the display panel 133.

[0092] The at least one processor 110 may obtain the blended third image 613. The at least one processor 110 may be configured to display the third image 613 through the display panel 133 for a time period t2. The time period t3 may be a length of time using a time at which the third image 613 starts to be displayed on the display panel 133 as a start time point, and a time at which the third image 613 stops displaying on the display panel 133 as an end time point. For example, the time period t2 may use the time at which the second image 612 stops being displayed on the display panel 133 as a start time point, and use the time at which the next image following the third image 613 starts being displayed on the display panel 133 as an end time point. If the time period t2 is longer than a time period for the first image 611 and a time period for the second image 612, or if the time period t2 is longer than the reference time length, the at least one processor 110 may store or record the third image 613 in the at least one memory 120 to prevent an afterimage effect.

[0093] The at least one processor 110 may be configured to transmit the data for the third image 613 to the display driving integrated circuit 131 to display the third image 613 on the display panel 133. For example, the at least one processor 110 may transmit the blended third image 613 to the display driving integrated circuit 131 through the interface 135 to display the third image 613 on the display panel 133.

[0094] The at least one processor 110 may at least temporarily store or record the third image 613 in the at least one memory 120 based on a fourth event. The fourth event may include an event during which an afterimage of the display panel 133 is to be prevented. The fourth event may include that the time period t2 is longer than the reference time length ts. If the displayed time period t2 is greater than the reference time length ts, when the next image displayed on the display panel 133, a portion of the third image 613 may continue to be displayed.

[0095] The at least one processor 110 may be configured to display an image corresponding to the third image 613 again on the display panel 133 to remove or reduce the afterimage effect. For example, the at least one processor 110 may be configured to transmit data for the third image 633 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the third image 613 again on the display panel 133, based on the reference time length ts, while the third image 613 is displayed on the display panel 133 through the display driving integrated circuit 131. For example, the at least one processor 110 may identify that a display time period of the third image 613 exceeds the reference time length ts, while the third image 613 is displayed on the display panel 133. The at least one processor 110 may therefore transmit data for the third image 643 obtained from the at least one memory 120 to the display driving integrated circuit 131 through the interface 135 based on the identification. The at least one processor 110 may at least temporarily record or store the blended third image 613 in the at least one memory 120. For example, based on identifying that the time period t2, which is the display time of the third image 613, is longer than the reference time length ts, the at least one processor 110 may transmit the blended third image 613 to the display driving integrated circuit 131 through the interface 135 and simultaneously record the blended third image 613 in the at least one memory 120. For example, the data for the third image 613 may be transmitted to the display driving integrated circuit 131 to display the third image 613 on the display panel 133.

[0096] The at least one processor 110 may transmit the third image 643 stored in the at least one memory 120 to the display driving integrated circuit 131 through the interface 135 based on the display time period of the third image 613 exceeding the reference time length ts. The at least one processor 110 may be configured to transmit data for the third image 643 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the third image 613 or 643 again on the display panel 133, based on the display time period of the third image 613 exceeding the reference time length ts, while the third image 613 is displayed on the display panel 133 through the display driving integrated circuit 131. The display driving integrated circuit 131 may obtain the third image 643 stored in the at least one memory 120 from the at least one processor 110 through the interface 135. For example, the display driving integrated circuit 131 may display the third image 643 stored in the at least one memory 120 on the display panel 133. The at least one processor 110 may display the third image 613 obtained from the at least one processor 110 on the display panel 133 through the display driving integrated circuit 131, and then display the third image 643 stored in the at least one memory 120 on the display panel 133 in a subsequent frame. The display panel 133 may reduce or remove an afterimage phenomenon in which a portion of the third image 643 remains in an image to be displayed after the third image again, i.e., by displaying the third image 643 obtained from the at least one memory 120.

[0097] FIG. 7 is a diagram illustrating storing an image in a memory and transferring the image stored in the memory to a display driving integrated circuit, in response to a fifth event.

[0098] Referring to FIG. 7, at least one processor 110 may sequentially display a first image 701 and a second image 702. The at least one processor 110 may display the second image 702 on a display panel 133 after displaying the first image 701 on the display panel 133. For example, the at least one processor 110 may switch the image displayed on the display panel 133 from the first image 701 to the second image 702. The at least one processor 110 may be configured to obtain or generate the second image 702 overlaid with multiple images as a next image of the first image 701 while the first image 701 is displayed on the display panel 133. For example, the at least one processor 110 may be configured to obtain the blended second image 702 using the multiple images or layers while the first image 701 is displayed on the display panel 133. The at least one processor 110 may transmit the first image 701 to a display driving integrated circuit 131 through an interface 135 to display the first image 701 on the display panel 133.

[0099] The at least one processor 110 may obtain the blended second image 702. The at least one processor 110 may be configured to display the second image 702 through the display panel 133. The first image 701 and the second image 702 may be the same image or substantially the same image. The first image 701 and the second image 702 may be displayed on the display panel 133 for a time period t3. The time period t3 may be a length of time using a time at which the first image 701 starts to be displayed on the display panel 133 as a start time point, and a time at which the second image 702 stops displaying on the display panel 133 as an end time point. For example, the time period t3 may use the time at which the previous image to the first image 701 stops being displayed on the display panel 133 as a start time point, and use the time at which the next image to the second image 702 starts being displayed on the display panel 133 as an end time point. If the time period t3 is longer than a reference time length ts, the at least one processor 110 may store or record the second image 702 in at least one memory 120 to prevent, i.e., reduce or remove, an afterimage effect.

[0100] The at least one processor 110 may be configured to transmit the image data for the second image 702 to the display driving integrated circuit 131 to display the second image 702 on the display panel 133. For example, the at least one processor 110 may transmit the blended second image 702 to the display driving integrated circuit 131 through the interface 135 to display the second image 702 on the display panel 133.

[0101] The at least one processor 110 may at least temporarily store or record the second image 702 in the at least one memory 120 based on a fifth event. The fifth event may include an event during which an afterimage of the display panel 133 is to be prevented. The fifth event may include that the time period t3 from the start time of displaying the first image 701 to the end time of displaying the second image 702 is longer than the reference time length ts. For example, the fifth event may include that a time period t3 during which the substantially identical first image 701 and second image 702 are displayed on the display panel 133 is longer than the reference time length ts. Substantially identical includes images that are completely identical and images that have some minor differences but are mostly the same in configuration or visual appearance. In case that the time period t3 during which the first image 701 and the second image 702 are displayed is greater than the reference time length ts, when the next image following the second image 702 is displayed on the display panel 133, a portion of the second image 702 may continue to be displayed.

[0102] The at least one processor 110 may be configured to display an image corresponding to the second image 702 again on the display panel 133 to remove or reduce the afterimage effect. For example, the at least one processor 110 may be configured to transmit data for the second image 732 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the second image 702 again on the display panel 133, based on the reference time length ts, while the second image 702 is displayed on the display panel 133 through the display driving integrated circuit 131. For example, the at least one processor 110 may identify that a display time period t3, which is a sum of the display time of the first image 701 and the second image 702, exceeds the reference time length ts, while the second image 702 is displayed on the display panel 133. The at least one processor 110 may transmit data for the second image 732 obtained from the at least one memory 120 to the display driving integrated circuit 131 through the interface 135 based on the identification. The at least one processor 110 may at least temporarily record or store the blended second image 732 in the at least one memory 120. For example, based on identifying that the display time period t3 which is the sum of the display time of the first image 701 and the second image 702, is longer than the reference time length ts, the at least one processor 110 may transmit the blended second image 702 to the display driving integrated circuit 131 through the interface 135 and simultaneously record the blended second image 702 in the at least one memory 120. For example, the data for the second image 702 may be transmitted to the display driving integrated circuit 131 to display the second image 702 on the display panel 133.

[0103] The at least one processor 110 may transmit the second image 732 stored in the at least one memory 120 to the display driving integrated circuit 131 through the interface 135 based on the display time period t3, which is the sum of the display time of the first image 701 and the second image 702, exceeding the reference time length ts. The at least one processor 110 may be configured to transmit data for the second image 732 obtained from the at least one memory 120 again to the display driving integrated circuit 131 to display the second image 702 or 732 again on the display panel 133, based on the display time period t3, which is the sum of the display time of the first image 701 and the second image 702, exceeding the reference time length ts, while the second image 702 is displayed on the display panel 133 through the display driving integrated circuit 131. The display driving integrated circuit 131 may obtain the second image 732 stored in the at least one memory 120 from the at least one processor 110 through the interface 135. For example, the display driving integrated circuit 131 may display the second image 732 stored in the at least one memory 120 on the display panel 133. The at least one processor 110 may display the second image 702 obtained from the at least one processor 110 on the display panel 133 through the display driving integrated circuit 131, and then display the second image 732 stored in the at least one memory 120 on the display panel 133 in a subsequent frame. The display panel 133 may reduce an afterimage phenomenon in which a portion of the second image 732 remains in the next image to be displayed after the second image 732 can be reduced or removed, by displaying the second image 732 obtained from the at least one memory 120 corresponding to the second image 702 again.

[0104] According to an embodiment, an electronic device expresses an image using multiple image or layers to apply an effect of images displayed on a display. In the electronic device, a lot of power is consumed in the combination operation of an image in which multiple images are overlaid. A method to reduce the power consumption is needed.

[0105] Technical tasks to be achieved in the present disclosure are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those having ordinary knowledge in the art to which the present disclosure belongs.

[0106] An electronic device (e.g., the electronic device 100 of FIG. 1) according to the above-described embodiment may comprise a display 130 including a display driving integrated circuit 131 and a display panel 133. The electronic device may further comprise memory 120 including one or more storage mediums storing instructions. The electronic device may further comprise at least one processor 110 including one or more processing circuits.

[0107] The instructions, when executed individually or collectively by the at least one processor 110, may cause the electronic device to obtain, while a first image is displayed on the display panel 133, a second image, in which multiple images are overlaid, as a next image of the first image. The instructions may cause the electronic device to at least temporarily store the second image in the memory 120, based on an event of transmitting data for the second image to the display driving integrated circuit 131 at a reference refresh rate higher than a refresh rate for the second image. The instructions may cause the electronic device to transmit the data for the second image to the display driving integrated circuit 131 to display the second image on the display panel 133. The instructions may cause the electronic device 100 to transmit data for the second image obtained from the memory 120 again to the display driving integrated circuit 131 to display the second image again on the display panel 133, based on the reference refresh rate, while the second image is displayed on the display panel 133 through the display driving integrated circuit 131.

[0108] According to an embodiment, the event may include changing a brightness level from a first brightness level to a second brightness level that is different from the first brightness level, within a predetermined number of frames.

[0109] According to an embodiment, the event may include that a time during which the first image is displayed on the display panel 133 is longer than a reference time.

[0110] According to an embodiment, the event may include that the refresh rate for the second image is lower than a refresh rate for the first image.

[0111] According to an embodiment, the event may include changing an amount of light emitted from subpixels configured to emit a specified color from a first light amount level to a second light amount level that is different from the first light amount level, within a predetermined number of frames.

[0112] According to an embodiment, the at least one processor 110 may include at least one first processor (e.g., the first processor 111 of FIG. 1) and at least one second processor (e.g., the second processor 112 of FIG. 1), wherein the instructions, when executed by the second processor 112, may cause the electronic device to obtain a first partial image from the at least one first processor 111. The instructions may cause the electronic device to obtain a third image by combining the first partial image with the second image obtained from the memory 120. The instructions may cause the electronic device 100 to transmit the third image to the display driving integrated circuit 131.

[0113] According to an embodiment, the instructions, when executed by the second processor 112, may cause the electronic device to obtain a second partial image different from the first partial image from the at least one first processor 111 while the third image is displayed on the display panel 133. The instructions may cause the electronic device to obtain a fourth image by combining the second partial image with the second image obtained from the memory 120. The instructions may cause the electronic device 100 to transmit the fourth image to the display driving integrated circuit 131.

[0114] According to an embodiment, the at least one processor 110 may include at least one first processor 111 and at least one second processor 112. The instructions, when executed by the second processor 112, may cause the electronic device to obtain a third image different from the second image from the at least one first processor 111. The instructions may cause the electronic device 100 to delete, in response to obtaining the third image, the second image stored in the memory 120 and transmit data for the third image to the display driving integrated circuit 131.

[0115] According to an embodiment, the at least one processor 110 may include a circuit including the storage medium of the memory 120 in which the second image is at least temporarily stored.

[0116] According to an embodiment, the instructions for at least temporarily storing the second image in the memory 120, when executed individually or collectively by the one or more processors, may cause the electronic device 100 to change the first image stored in the memory 120 into the second image.

[0117] According to an embodiment, when there is an empty space for the second image in the memory 120, the instructions for at least temporarily storing the second image in the memory 120, when executed individually or collectively by the one or more processors, may cause the electronic device 100 to store the second image in the empty space.

[0118] The at least one processor 110 may include at least one first processor 111 and at least one second processor 112, wherein the instructions, when executed by the second processor 112, may cause the electronic device 100 to display the second image on the display panel 133 through the display driving integrated circuit 131, until reception of a third image different from the second image through the at least one first processor 111.

[0119] According to an embodiment, the instructions, when executed by the second processor 112, may cause the electronic device 100 to display the second image stored in the memory 120 on the display panel 133 based on the reference refresh rate, while displaying the second image on the display panel 133.

[0120] According to an embodiment, the at least one processor 110 may include at least one first processor 111 and at least one second processor 112, wherein the instructions, when executed by the second processor 112, may cause the electronic device to obtain a third image different from the second image, as a next image of the second image. The instructions may cause the electronic device 100 to remove data for the second image stored in the memory 120 in a space for data for an image displayed on the display panel 133.

[0121] According to an embodiment, the instructions, when executed by the second processor 112, may cause the electronic device to at least temporarily store the third image in the memory 120 and transmit the data for the third image to the display driving integrated circuit 131, in case that the third image is obtained by overlaying multiple images. The instructions may cause the electronic device 100 to refrain from storing the third image in the memory 120 and transmit the data for the third image to the display driving integrated circuit 131, in case that the third image is obtained from a single image.

[0122] According to an embodiment, the event may include transferring an image obtained from the at least one processor 110 to the display driving integrated circuit 131 by bypassing the memory 132, while the memory 132 in the display driving integrated circuit 131 is deactivated within a video hybrid mode of display serial interface (DSI).

[0123] According to an embodiment, the electronic device (e.g., the electronic device 100 of FIG. 1) may comprise a display (e.g., the display 130 of FIG. 1) including a display driving integrated circuit (e.g., the display driving integrated circuit 131 of FIG. 1) including a first memory (e.g., the at least one first memory 120 of FIG. 1) configured to store an image and a display panel (e.g., the display panel 133 of FIG. 1). The electronic device may comprise a second memory (e.g., the memory 113 of FIG. 1) including one or more storage mediums storing instructions. The electronic device may comprise a plurality of processors (e.g., the at least one processor 110 of FIG. 1) including at least one first processor (e.g., the first processor 111 of FIG. 1) and at least one second processor (e.g., the second processor 112 of FIG. 1), including one or more processing circuits. The instructions, when executed by the second processor 112, may cause the electronic device to obtain a second image, in which multiple images obtained from the first processor 111 are overlaid, as a next image to be displayed after the first image, while the first image is displayed on the display panel 133, based on an event that the first memory 120 is deactivated. The instructions may cause the electronic device to at least temporarily store the second image in the second memory 132, based on an event of transmitting data for the second image to the display driving integrated circuit 131 at a reference refresh rate higher than a refresh rate for the second image. The instructions may cause the electronic device to transmit the data for the second image to the display driving integrated circuit 131 to display the second image on the display panel 133. The instructions may cause the electronic device 100 to transmit data for the second image obtained from the second memory 132 again to the display driving integrated circuit 131 to display the second image again on the display panel 133, based on the reference refresh rate, while the second image is displayed on the display panel 133 through the display driving integrated circuit 131.

[0124] According to an embodiment, the event may include one of changing a brightness level from a first brightness level to a second brightness level that is different from the first brightness level, a time for which the first image is displayed on the display panel 133 being longer than a reference time, the refresh rate for the second image is lower than a refresh rate for the first image, within a predetermined number of frames, or changing an amount of light emitted from subpixels configured to emit a specified color from a first light amount level to a second light amount level that is different from the first light amount level within a predetermined number of frames.

[0125] According to an embodiment, the instructions, when executed by the second processor 112, may cause the electronic device to obtain a first partial image from the at least one first processor 111. The instructions may cause the electronic device to obtain a third image by combining the first partial image with the second image obtained from the memory 132. The instructions may cause the electronic device 100 to transmit the third image to the display driving integrated circuit 131.

[0126] According to an embodiment, the instruction for at least temporarily storing the second image in the memory 132, when individually or collectively executed by the one or more processors, may cause the electronic device 100 to change the first image stored in the memory 132 into the second image.

[0127] According to an embodiment, an event in which the first memory 120 is deactivated may include that a playback frame of the first image is more than or equal to a reference frame.

[0128] According to an embodiment, the event may include transferring an image obtained from the at least one of the plurality of processors to the display driving integrated circuit 131 by bypassing the memory 120, while the memory 120 in the display driving integrated circuit 131 is deactivated within a video hybrid mode of DSI.

[0129] FIG. 8 is a block diagram illustrating an electronic device 801 in a network environment 800 according to various embodiments.

[0130] Referring to FIG. 8, the electronic device 801 in the network environment 800 may communicate with an electronic device 802 via a first network 898 (e.g., a short-range wireless communication network), or at least one of an electronic device 804 or a server 808 via a second network 899 (e.g., a long-range wireless communication network). According to an embodiment, the electronic device 801 may communicate with the electronic device 804 via the server 808. According to an embodiment, the electronic device 801 may include a processor 820, memory 830, an input module 850, a sound output module 855, a display module 860, an audio module 870, a sensor module 876, an interface 877, a connecting terminal 878, a haptic module 879, a camera module 880, a power management module 888, a battery 889, a communication module 890, a subscriber identification module (SIM) 896, or an antenna module 897. In some embodiments, at least one of the components (e.g., the connecting terminal 878) may be omitted from the electronic device 801, or one or more other components may be added in the electronic device 801. In some embodiments, some of the components (e.g., the sensor module 876, the camera module 880, or the antenna module 897) may be implemented as a single component (e.g., the display module 860).

[0131] The processor 820 may execute, for example, software (e.g., a program 840) to control at least one other component (e.g., a hardware or software component) of the electronic device 801 coupled with the processor 820, and may perform various data processing or computation. According to an embodiment, as at least part of the data processing or computation, the processor 820 may store a command or data received from another component (e.g., the sensor module 876 or the communication module 890) in volatile memory 832, process the command or the data stored in the volatile memory 832, and store resulting data in non-volatile memory 834. According to an embodiment, the processor 820 may include a main processor 821 (e.g., a central processing unit (CPU) or an application processor (AP)), or an auxiliary processor 823 (e.g., a graphics processing unit (GPU), a neural processing unit (NPU), an image signal processor (ISP), a sensor hub processor, or a communication processor (CP)) that is operable independently from, or in conjunction with, the main processor 821. For example, when the electronic device 801 includes the main processor 821 and the auxiliary processor 823, the auxiliary processor 823 may be adapted to consume less power than the main processor 821, or to be specific to a specified function. The auxiliary processor 823 may be implemented as separate from, or as part of the main processor 821.

[0132] The auxiliary processor 823 may control at least some of functions or states related to at least one component (e.g., the display module 860, the sensor module 876, or the communication module 890) among the components of the electronic device 801, instead of the main processor 821 while the main processor 821 is in an inactive (e.g., sleep) state, or together with the main processor 821 while the main processor 821 is in an active state (e.g., executing an application). According to an embodiment, the auxiliary processor 823 (e.g., an image signal processor or a communication processor) may be implemented as part of another component (e.g., the camera module 880 or the communication module 890) functionally related to the auxiliary processor 823. According to an embodiment, the auxiliary processor 823 (e.g., the neural processing unit) may include a hardware structure specified for artificial intelligence model processing. An artificial intelligence model may be generated by machine learning. Such learning may be performed, e.g., by the electronic device 801 where the artificial intelligence is performed or via a separate server (e.g., the server 808). Learning algorithms may include, but are not limited to, e.g., supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning. The artificial intelligence model may include a plurality of artificial neural network layers. The artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), deep Q-network or a combination of two or more thereof but is not limited thereto. The artificial intelligence model may, additionally or alternatively, include a software structure other than the hardware structure.

[0133] The memory 830 may store various data used by at least one component (e.g., the processor 820 or the sensor module 876) of the electronic device 801. The various data may include, for example, software (e.g., the program 840) and input data or output data for a command related thereto. The memory 830 may include the volatile memory 832 or the non-volatile memory 834.

[0134] The program 840 may be stored in the memory 830 as software, and may include, for example, an operating system (OS) 842, middleware 844, or an application 846.

[0135] The input module 850 may receive a command or data to be used by another component (e.g., the processor 820) of the electronic device 801, from the outside (e.g., a user) of the electronic device 801. The input module 850 may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0136] The sound output module 855 may output sound signals to the outside of the electronic device 801. The sound output module 855 may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as playing multimedia or playing record. The receiver may be used for receiving incoming calls. According to an embodiment, the receiver may be implemented as separate from, or as part of the speaker.

[0137] The display module 860 may visually provide information to the outside (e.g., a user) of the electronic device 801. The display module 860 may include, for example, a display, a hologram device, or a projector and control circuitry to control a corresponding one of the display, hologram device, and projector. According to an embodiment, the display module 860 may include a touch sensor adapted to detect a touch, or a pressure sensor adapted to measure the intensity of force incurred by the touch.

[0138] The audio module 870 may convert a sound into an electrical signal and vice versa. According to an embodiment, the audio module 870 may obtain the sound via the input module 850, or output the sound via the sound output module 855 or a headphone of an external electronic device (e.g., an electronic device 802) directly (e.g., wiredly) or wirelessly coupled with the electronic device 801.

[0139] The sensor module 876 may detect an operational state (e.g., power or temperature) of the electronic device 801 or an environmental state (e.g., a state of a user) external to the electronic device 801, and then generate an electrical signal or data value corresponding to the detected state. According to an embodiment, the sensor module 876 may include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0140] The interface 877 may support one or more specified protocols to be used for the electronic device 801 to be coupled with the external electronic device (e.g., the electronic device 802) directly (e.g., wiredly) or wirelessly. According to an embodiment, the interface 877 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, or an audio interface.

[0141] A connecting terminal 878 may include a connector via which the electronic device 801 may be physically connected with the external electronic device (e.g., the electronic device 802). According to an embodiment, the connecting terminal 878 may include, for example, an HDMI connector, a USB connector, a SD card connector, or an audio connector (e.g., a headphone connector).

[0142] The haptic module 879 may convert an electrical signal into a mechanical stimulus (e.g., a vibration or a movement) or electrical stimulus which may be recognized by a user via his tactile sensation or kinesthetic sensation. According to an embodiment, the haptic module 879 may include, for example, a motor, a piezoelectric element, or an electric stimulator.

[0143] The camera module 880 may capture a still image or moving images. According to an embodiment, the camera module 880 may include one or more lenses, image sensors, image signal processors, or flashes.

[0144] The power management module 888 may manage power supplied to the electronic device 801. According to an embodiment, the power management module 888 may be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0145] The battery 889 may supply power to at least one component of the electronic device 801. According to an embodiment, the battery 889 may include, for example, a primary cell which is not rechargeable, a secondary cell which is rechargeable, or a fuel cell.

[0146] The communication module 890 may support establishing a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device 801 and the external electronic device (e.g., the electronic device 802, the electronic device 804, or the server 808) and performing communication via the established communication channel. The communication module 890 may include one or more communication processors that are operable independently from the processor 820 (e.g., the application processor (AP)) and supports a direct (e.g., wired) communication or a wireless communication. According to an embodiment, the communication module 890 may include a wireless communication module 892 (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 894 (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). A corresponding one of these communication modules may communicate with the external electronic device via the first network 898 (e.g., a short-range communication network, such as Bluetooth ™< , wireless-fidelity (Wi-Fi) direct, or infrared data association (IrDA)) or the second network 899 (e.g., a long-range communication network, such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., LAN or wide area network (WAN)). These various types of communication modules may be implemented as a single component (e.g., a single chip), or may be implemented as multi components (e.g., multi chips) separate from each other. The wireless communication module 892 may identify and authenticate the electronic device 801 in a communication network, such as the first network 898 or the second network 899, using subscriber information (e.g., international mobile subscriber identity (IMSI)) stored in the subscriber identification module 896.

[0147] The wireless communication module 892 may support a 5G network, after a 4G network, and next-generation communication technology, e.g., new radio (NR) access technology. The NR access technology may support enhanced mobile broadband (eMBB), massive machine type communications (mMTC), or ultra-reliable and low-latency communications (URLLC). The wireless communication module 892 may support a high-frequency band (e.g., the mmWave band) to achieve, e.g., a high data transmission rate. The wireless communication module 892 may support various technologies for securing performance on a high-frequency band, such as, e.g., beamforming, massive multiple-input and multiple-output (massive MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module 892 may support various requirements specified in the electronic device 801, an external electronic device (e.g., the electronic device 804), or a network system (e.g., the second network 899). According to an embodiment, the wireless communication module 892 may support a peak data rate (e.g., 20Gbps or more) for implementing eMBB, loss coverage (e.g., 864dB or less) for implementing mMTC, or U-plane latency (e.g., 0.5ms or less for each of downlink (DL) and uplink (UL), or a round trip of 8ms or less) for implementing URLLC.

[0148] The antenna module 897 may transmit or receive a signal or power to or from the outside (e.g., the external electronic device) of the electronic device 801. According to an embodiment, the antenna module 897 may include an antenna including a radiating element composed of a conductive material or a conductive pattern formed in or on a substrate (e.g., a printed circuit board (PCB)). According to an embodiment, the antenna module 897 may include a plurality of antennas (e.g., array antennas). In such a case, at least one antenna appropriate for a communication scheme used in the communication network, such as the first network 898 or the second network 899, may be selected, for example, by the communication module 890 (e.g., the wireless communication module 892) from the plurality of antennas. The signal or the power may then be transmitted or received between the communication module 890 and the external electronic device via the selected at least one antenna. According to an embodiment, another component (e.g., a radio frequency integrated circuit (RFIC)) other than the radiating element may be additionally formed as part of the antenna module 897.

[0149] According to various embodiments, the antenna module 897 may form a mmWave antenna module. According to an embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on a first surface (e.g., the bottom surface) of the printed circuit board, or adjacent to the first surface and capable of supporting a designated high-frequency band (e.g., the mmWave band), and a plurality of antennas (e.g., array antennas) disposed on a second surface (e.g., the top or a side surface) of the printed circuit board, or adjacent to the second surface and capable of transmitting or receiving signals of the designated high-frequency band.

[0150] At least some of the above-described components may be coupled mutually and communicate signals (e.g., commands or data) therebetween via an inter-peripheral communication scheme (e.g., a bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)).

[0151] According to an embodiment, commands or data may be transmitted or received between the electronic device 801 and the external electronic device 804 via the server 808 coupled with the second network 899. Each of the electronic devices 802 or 804 may be a device of a same type as, or a different type, from the electronic device 801. According to an embodiment, all or some of operations to be executed at the electronic device 801 may be executed at one or more of the external electronic devices 802, 804, or 808. For example, if the electronic device 801 should perform a function or a service automatically, or in response to a request from a user or another device, the electronic device 801, instead of, or in addition to, executing the function or the service, may request the one or more external electronic devices to perform at least part of the function or the service. The one or more external electronic devices receiving the request may perform the at least part of the function or the service requested, or an additional function or an additional service related to the request, and transfer an outcome of the performing to the electronic device 801. The electronic device 801 may provide the outcome, with or without further processing of the outcome, as at least part of a reply to the request. To that end, a cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device 801 may provide ultra low-latency services using, e.g., distributed computing or mobile edge computing. In another embodiment, the external electronic device 804 may include an internet-of-things (IoT) device. The server 808 may be an intelligent server using machine learning and / or a neural network. According to an embodiment, the external electronic device 804 or the server 808 may be included in the second network 899. The electronic device 801 may be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology or IoT-related technology.

[0152] Fig. 9 is a block diagram 900 illustrating the display module 860 according to various embodiments.

[0153] Referring to Fig. 9, the display module 860 may include a display 910 and a display driver integrated circuit (DDI) 930 to control the display 910. The DDI 930 may include an interface module 931, memory 933 (e.g., buffer memory), an image processing module 935, or a mapping module 937. The DDI 930 may receive image information that contains image data or an image control signal corresponding to a command to control the image data from another component of the electronic device 801 via the interface module 931. For example, according to an embodiment, the image information may be received from the processor 820 (e.g., the main processor 821 (e.g., an application processor) or the auxiliary processor 823 (e.g., a graphics processing unit) operated independently from the function of the main processor 821. The DDI 930 may communicate, for example, with touch circuitry 850 or the sensor module 876 via the interface module 931. The DDI 930 may also store at least part of the received image information in the memory 933, for example, on a frame by frame basis. The image processing module 935 may perform pre-processing or post-processing (e.g., adjustment of resolution, brightness, or size) with respect to at least part of the image data. According to an embodiment, the pre-processing or post-processing may be performed, for example, based at least in part on one or more characteristics of the image data, image display characteristics or one or more characteristics of the display 910. The mapping module 937 may generate a voltage value or a current value corresponding to the image data pre-processed or post-processed by the image processing module 935. According to an embodiment, the generating of the voltage value or current value may be performed, for example, based at least in part on one or more attributes of the pixels (e.g., an array, such as an RGB stripe or a pentile structure, of the pixels, or the size of each subpixel). At least some pixels of the display 910 may be driven, for example, based at least in part on the voltage value or the current value such that visual information (e.g., a text, an image, or an icon) corresponding to the image data may be displayed via the display 910.

[0154] According to an embodiment, the display module 860 may further include the touch circuitry 950. The touch circuitry 950 may include a touch sensor 951 and a touch sensor IC 953 to control the touch sensor 951. The touch sensor IC 953 may control the touch sensor 951 to sense a touch input or a hovering input with respect to a certain position on the display 910. To achieve this, for example, the touch sensor 951 may detect (e.g., measure) a change in a signal (e.g., a voltage, a quantity of light, a resistance, or a quantity of one or more electric charges) corresponding to the certain position on the display 910. The touch circuitry 950 may provide input information (e.g., a position, an area, a pressure, or a time) indicative of the touch input or the hovering input detected via the touch sensor 951 to the processor 820. According to an embodiment, at least part (e.g., the touch sensor IC 953) of the touch circuitry 950 may be formed as part of the display 910 or the DDI 930, or as part of another component (e.g., the auxiliary processor 823) disposed outside the display module 860.

[0155] According to an embodiment, the display module 860 may further include at least one sensor (e.g., a fingerprint sensor, an iris sensor, a pressure sensor, or an illuminance sensor) of the sensor module 876 or a control circuit for the at least one sensor. In such a case, the at least one sensor or the control circuit for the at least one sensor may be embedded in one portion of a component (e.g., the display 910, the DDI 930, or the touch circuitry 850)) of the display module 860. For example, when the sensor module 876 embedded in the display module 860 includes a biometric sensor (e.g., a fingerprint sensor), the biometric sensor may obtain biometric information (e.g., a fingerprint image) corresponding to a touch input received via a portion of the display 910. As another example, when the sensor module 876 embedded in the display module 860 includes a pressure sensor, the pressure sensor may obtain pressure information corresponding to a touch input received via a partial or whole area of the display 910. According to an embodiment, the touch sensor 951 or the sensor module 876 may be disposed between pixels in a pixel layer of the display 910, or over or under the pixel layer.

[0156] The electronic device according to various embodiments may be one of various types of electronic devices. The electronic devices may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. According to an embodiment of the disclosure, the electronic devices are not limited to those described above.

[0157] It should be appreciated that various embodiments of the present disclosure and the terms used therein are not intended to limit the technological features set forth herein to particular embodiments and include various changes, equivalents, or replacements for a corresponding embodiment. With regard to the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It is to be understood that a singular form of a noun corresponding to an item may include one or more of the things unless the relevant context clearly indicates otherwise. As used herein, each of such phrases as "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C," may include any one of or all possible combinations of the items enumerated together in a corresponding one of the phrases. As used herein, such terms as "1st" and "2nd," or "first" and "second" may be used to simply distinguish a corresponding component from another, and does not limit the components in other aspect (e.g., importance or order). It is to be understood that if an element (e.g., a first element) is referred to, with or without the term "operatively" or "communicatively", as "coupled with," or "connected with" another element (e.g., a second element), it means that the element may be coupled with the other element directly (e.g., wiredly), wirelessly, or via a third element.

[0158] As used in connection with various embodiments of the disclosure, the term "module" may include a unit implemented in hardware, software, or firmware, and may interchangeably be used with other terms, for example, "logic," "logic block," "part," or "circuitry". A module may be a single integral component, or a minimum unit or part thereof, adapted to perform one or more functions. For example, according to an embodiment, the module may be implemented in a form of an application-specific integrated circuit (ASIC).

[0159] Various embodiments as set forth herein may be implemented as software (e.g., the program 840) including one or more instructions that are stored in a storage medium (e.g., internal memory 836 or external memory 838) that is readable by a machine (e.g., the electronic device 801). For example, a processor (e.g., the processor 820) of the machine (e.g., the electronic device 801) may invoke at least one of the one or more instructions stored in the storage medium, and execute it, with or without using one or more other components under the control of the processor. This allows the machine to be operated to perform at least one function according to the at least one instruction invoked. The one or more instructions may include a code generated by a complier or a code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Wherein, the term "non-transitory" simply means that the storage medium is a tangible device, and does not include a signal (e.g., an electromagnetic wave), but this term does not differentiate between a case in which data is semi-permanently stored in the storage medium and a case in which the data is temporarily stored in the storage medium.

[0160] According to an embodiment, a method according to various embodiments of the disclosure may be included and provided in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or be distributed (e.g., downloaded or uploaded) online via an application store (e.g., PlayStore ™< ), or between two user devices (e.g., smart phones) directly. If distributed online, at least part of the computer program product may be temporarily generated or at least temporarily stored in the machine-readable storage medium, such as memory of the manufacturer's server, a server of the application store, or a relay server.

[0161] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include a single entity or multiple entities, and some of the multiple entities may be separately disposed in different components. According to various embodiments, one or more of the above-described components may be omitted, or one or more other components may be added. Alternatively or additionally, a plurality of components (e.g., modules or programs) may be integrated into a single component. In such a case, according to various embodiments, the integrated component may still perform one or more functions of each of the plurality of components in the same or similar manner as they are performed by a corresponding one of the plurality of components before the integration. According to various embodiments, operations performed by the module, the program, or another component may be carried out sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations may be executed in a different order or omitted, or one or more other operations may be added.

Claims

1. An electronic device comprising : a display including a display driving integrated circuit and display panel; memory including one or more storage mediums storing instructions; and at least one processor including one or more processing circuits, wherein the instructions, when executed individually or collectively by the at least one processor, cause the electronic device to : while a first image is displayed on the display panel, obtain a second image generated by using multiple images as an image to be changed from the first image on the display panel; at least temporarily store the second image in the memory, based on an event, wherein the event includes setting a reference refresh rate higher than a refresh rate for the second image; transmit the second image to the display driving integrated circuit to display the second image on the display panel; and while the second image is displayed on the display panel, transmit the second image obtained from the memory again to the display driving integrated circuit to display the second image again on the display panel based on the reference refresh rate.

2. The electronic device of claim 1, wherein the event includes changing a display panel brightness level from a first brightness level to a second brightness level that is different from the first brightness level, within a predetermined number of frames.

3. The electronic device of any preceding claim, wherein the event includes identifying that a time for which the first image is displayed on the display panel is longer than a reference time.

4. The electronic device of any preceding claim, wherein the event includes that the refresh rate for the second image is lower than a refresh rate for the first image.

5. The electronic device of any preceding claim, wherein the event includes changing an amount of light emitted from subpixels of the display panel configured to emit a specified color from a first light amount level to a second light amount level that is different from the first light amount level, within a predetermined number of frames.

6. The electronic device of any preceding claim, wherein the at least one processor includes at least one first processor and at least one second processor, wherein the instructions, when executed by the second processor, cause the electronic device to: obtain a first partial image from the at least one first processor; obtain a third image by combining the first partial image with the second image obtained from the memory; transmit the third image to the display driving integrated circuit.

7. The electronic device of claim 6, wherein the instructions, when executed by the second processor, cause the electronic device to: while the third image is displayed on the display panel, obtain a second partial image different from the first partial image from the at least one first processor; obtain a fourth image by combining the second partial image with the second image obtained from the memory; transmit the fourth image to the display driving integrated circuit.

8. The electronic device of any one of claims 1 to 5, wherein the at least one processor includes at least one first processor and at least one second processor, wherein the instructions, when executed by the second processor, cause the electronic device to: obtain a third image different from the second image from the at least one first processor; delete, in response to obtaining the third image, the second image stored in the memory and transmit data for the third image to the display driving integrated circuit.

9. The electronic device of any preceding claim, wherein the at least one processor further comprises an internal memory comprising a circuit including the storage medium of the memory in which the second image is stored.

10. The electronic device of any preceding claim, wherein the instructions for at least temporarily storing the second image in the memory, when executed individually or collectively by the one or more processors, cause the electronic device to change the first image stored in the memory into the second image.

11. The electronic device of any preceding claim, wherein the instructions for at least temporarily storing the second image in the memory, when executed individually or collectively by the one or more processors, when there is an empty space for the second image in the memory, cause the electronic device to store the second image in the empty space.

12. The electronic device of any one of claims 1 to 5, wherein the at least one processor includes at least one first processor and at least one second processor, wherein the instructions, when executed by the at least one second processor, cause the electronic device to: display the second image on the display panel through the display driving integrated circuit, until reception of a third image different from the second image through the at least one first processor.

13. The electronic device of claim 12, wherein the instructions, when executed by the second processor, cause the electronic device to display the second image stored in the memory on the display panel based on the reference refresh rate while displaying the second image on the display panel.

14. A non-transitory computer-readable medium storing instructions, wherein the instructions are configured to, when executed by at least one processor of a wearable device, cause the at least one processor to: while a first image is displayed on a display panel of the electronic device, obtain a second image generated by using multiple images as an image to be changed from the first image on the display panel; at least temporarily store the second image in a memory of the electronic device, based on an event, wherein the event includes setting a reference refresh rate higher than a refresh rate for the second image; transmit the second image to a display driving integrated circuit of the electronic device to display the second image on the display panel; and while the second image is displayed on the display panel, transmit the second image obtained from the memory again to the display driving integrated circuit to display the second image again on the display panel based on the reference refresh rate.

15. A method of an electronic device, comprising: while a first image is displayed on a display panel of the electronic device, obtaining a second image generated by using multiple images as an image to be changed from the first image on the display panel; at least temporarily storing the second image in a memory of the electronic device, based on an event, wherein the event includes setting a reference refresh rate higher than a refresh rate for the second image; transmitting the second image to a display driving integrated circuit of the electronic device to display the second image on the display panel; and while the second image is displayed on the display panel, transmitting the second image obtained from the memory again to the display driving integrated circuit to display the second image again on the display panel based on the reference refresh rate.

Images