Monitoring circuit for a programmable gate assembly, assembly comprising a monitoring circuit, processor, and gate assembly, and method for operating such an assembly

Abstract

The invention relates to a monitoring circuit (20) for a programmable gate assembly (10). The gate assembly (10) is designed to carry out a function (22) and use at least one signal (S1, K1) in order to carry out the function (22). A processor (30) is provided which is designed to carry out a master function (32) and to transmit the value of the at least one signal (S1, K1) to the gate assembly (10) and / or to obtain the value of the at least one signal (S1, K1) from the gate assembly (10) in order to carry out the master function (32) The monitoring circuit (20) is designed to exchange the value of the at least one signal (S1, K1) with the gate assembly (10), wherein the exchange of the value of the signal (S1) is carried out independently of the function (22) carried out on the gate assembly (10). The monitoring circuit (20) is additionally designed to exchange the value of the at least one signal (S1, K1) with the processor (30). The invention also relates to an assembly which comprises the monitoring circuit, the processor, and the gate assembly and to a method for operating such an assembly.

Description

[0001] Monitoring circuit for a programmable gate arrangement, arrangement with monitoring circuit, processor and gate arrangement, and method for operating

[0002] Such an arrangement

[0003] Technical field

[0004] The application relates to a monitoring circuit for a programmable gate arrangement, an arrangement with a monitoring circuit, a processor and a programmable gate arrangement, and a method for operating such an arrangement.

[0005] Background

[0006] A programmable gate array is a digital integrated circuit located on a board into which a logic circuit can be loaded. The logic circuit can execute functions and process signals. An example of a programmable gate array is an FPGA (Field Programmable Gate Array). Another example of a programmable gate array is an SoC (System on Chip) component.

[0007] Programmable gate arrays are used, for example, in Rapid Control Prototyping (RCP) or Hardware in the Loop (HiL) real-time systems. Simulation models of such real-time systems are examples of functions that can be executed on the programmable gate arrays. Signal values ​​of the simulation models can be queried by a user during simulation runtime, for example, via dSPACE ControlDesk, and output to the user.

[0008] EP3244326 describes a shadow register of an FPGA designed to store the value of an FPGA signal. The signal value can be read during the runtime of an FPGA function, with the reading of the shadow register being functionally independent of the function's execution. EP2765528 describes a method that enables access to the value of an FPGA signal at runtime. For this purpose, FPGA state data is read during operation, and the signal value is determined from it.

[0009] Overview

[0010] A programmable gate arrangement is configured to execute a function and to use at least one signal to execute the function. A processor is configured to execute a higher-level function and to transfer a value of the at least one signal to the gate arrangement and / or to receive a value of the at least one signal from the gate arrangement to execute the higher-level function. A monitoring circuit is configured to exchange a value of the at least one signal with the gate arrangement, wherein the exchange of the value of the signal occurs independently of the function executed on the gate arrangement. The monitoring circuit is further configured to exchange the value of the at least one signal with the processor.

[0011] The exchange of the value of the signal between the gate arrangement and the monitoring circuit preferably takes place via a memory of the gate arrangement.

[0012] The programmable gate array, particularly an FPGA or SoC component, is often used for time-critical simulation calculations, such as hardware-in-the-loop (HIL) simulations. One function of the gate array may include the execution of these time-critical simulations, which are executed cyclically at runtime—e.g., at a clock frequency of the gate array.

[0013] The processor executes the higher-level function, which interacts with the function executed on the gate array, e.g., for time-critical and / or computationally intensive components. During the execution of the higher-level function, the processor passes at least one value of at least one signal to the gate array and / or receives at least one value of at least one signal from the gate array. The exchange of values ​​between the processor and the gate array for executing the function or the higher-level function takes place via dedicated communication interfaces. These can be, for example, registers, buffers, or bus interfaces.

[0014] In contrast, the exchange of the signal value between the gate array and the monitoring circuit occurs independently of the execution of the function on the gate array. This is advantageous because the execution of the function, e.g., the simulation, is not disrupted. A further advantage compared to the state of the art is the increased flexibility of the information exchange between the gate array and its peripherals.

[0015] To exchange the value in one direction from the gate arrangement to the monitoring circuit, a shadow register associated with the signal can be provided, which is configured and intended to store the value of the associated signal. The shadow register is a memory of the programmable gate arrangement in which a value of the associated signal is stored while the function of the gate arrangement is being executed. The shadow register has a transmission channel to the monitoring circuit, via which the value stored in the shadow register can be transmitted to the monitoring circuit. In one embodiment of the invention, the latter transmission channel is implemented using a so-called ICAP interface in the gate arrangement. ICAP (Internal Configuration Access Port) is an interface provided by XILINX for reading and modifying configuration data, which can contain predefined runtime values.Other FPGA manufacturers are expected to offer comparable or similarly documented interfaces in the coming years.

[0016] To exchange the value in one direction from the monitoring circuit to the gate arrangement, a dedicated memory of the gate arrangement can be provided, which can be read-accessed by the function executed on the gate arrangement. The monitoring circuit can write-access this area and write the value to be exchanged by writing into the memory. In one embodiment, the memory is designed as a shift register chain. The dedicated memory has a transmission channel to the monitoring circuit, via which the value to be written can be transmitted from the monitoring circuit. The exchange of the value of the at least one signal comprises, in particular, reading and / or writing the at least one signal by the monitoring circuit. The exchange of the value can, for example, comprise the monitoring circuit reading the value of the signal from a memory of the gate arrangement.Reading the signal value from the gate array's memory occurs independently of the function executed on the gate array. Alternatively or additionally, exchanging the value can involve, for example, writing the value to a gate array's memory. Writing the signal value to the gate array's memory occurs independently of the function executed on the gate array.

[0017] In one embodiment, the gate arrangement is configured to receive a value of the at least one signal for processing from the processor, process the value of the signal during the execution of the function, and output the processed value of the signal to the processor. This makes it possible to execute parts of the higher-level function as a function of the gate arrangement. Signal values ​​calculated by the function of the gate arrangement can then be further used by the higher-level function of the processor.

[0018] In embodiments, a value of the at least one signal is present in the gate arrangement. Alternatively or additionally, the gate arrangement is configured to derive a value of the at least one signal from a read sensor value. The signal can be a value used by the function, such as a measured value or a value of a variable of the function. A signal can also be a purely calculated value, e.g., a value converted from a measured value or an intermediate value.

[0019] In embodiments of the monitoring circuit, the at least one signal can be embodied as a constant, and the gate arrangement is configured to use the constant during the execution of the function. A constant comprises values ​​that are not intended to be changed during the execution of the function, but can be changed by the monitoring circuit. The monitoring circuit is configured to write a value of the at least one constant into a memory of the gate arrangement, wherein the writing of the value of the constant occurs independently of the function executed on the gate arrangement. The monitoring circuit is further configured to receive the value to be written for the constant from the processor. Values ​​of constants can, for example, be parameter values ​​with which a simulation is parameterized. This offers the advantage that the processor can use the constant, e.g.from the execution of the higher-level function, without interfering with the execution of the function of the gate arrangement.

[0020] It is further proposed that the monitoring circuit be configured to read the value of the constant from a memory of the gate array and output the read value to the processor. This enables the processor to access the current value of the constant present in the gate array. This can be done from the currently executing higher-level function without interfering with the execution of the function of the gate array. The value of the constant can, for example, be predefined or derived from a calculation on the gate array or read from a sensor connected to the gate array.

[0021] In embodiments, the monitoring circuit is configured to receive a value of the constant to be written from an operating unit, wherein the operating unit is configured to receive the value to be written from a user. This allows the additional possibility of having the value of the at least one constant to be written determined by a user.

[0022] The monitoring circuit is configured, for example, to output a read value of the signal to the control unit, wherein the control unit is configured to output the read value to a user. These embodiments offer the additional possibility of making at least one signal read from the gate arrangement accessible to the user.

[0023] In embodiments, the monitoring circuit is configured to receive information about the signal whose value is to be read from the memory of the gate arrangement from the processor. This information allows the monitoring circuit, in particular, to identify the signal to be read. This is particularly relevant when there are multiple readable signals, since in such cases the monitoring circuit must be informed which of the readable signals it should read. The information about the signal can also be information about the memory where the value of the signal is stored and, for example, was made available for reading by the monitoring circuit.

[0024] Additionally, the monitoring circuit can be configured to receive information about the signal to be read from the control unit. The monitoring circuit can then be further configured to read the value of the signal for which it has received the information from a memory of the gate arrangement and then transmit the read value to the control unit, e.g., for output to the user. As described above, the information allows the monitoring circuit, for example, to identify the signal to be read.

[0025] An arrangement comprises the described monitoring circuit as well as the processor and the programmable gate arrangement.

[0026] It is proposed that the value of the signal received by the monitoring circuit be usable by the processor when executing the higher-level function. This allows access to, for example, a variable of the gate array's function, for monitoring purposes, without disrupting or delaying the execution of the function on the gate array.

[0027] In embodiments, the value of the constant passed by the processor to the monitoring circuit can be generated by the processor during the execution of the higher-level function. This allows one or more constants stored in the gate array and used to execute the function to be changed without affecting the execution of the actual function.

[0028] In a further embodiment, the gate arrangement has at least one memory arrangement that can be addressed via configuration bits and data bits. The monitoring circuit is configured to read and / or write to the at least one memory arrangement. Such a memory arrangement has at least one memory area, which is preferably designed as a so-called block RAM of the programmable gate arrangement. The gate arrangement preferably has a converter between the monitoring circuit and the at least one memory arrangement, which converter is configured to serialize the configuration bits and the data bits and transmit them in serial form. Furthermore, the converter can be configured to deserialize the configuration bits and data bits received in serial form.

[0029] It is further proposed that the gate arrangement have a transmission channel between the converter and the at least one memory arrangement, which is configured to transmit serialized configuration bits and data bits. This enables the transmission of the serial data converted by the converter to the memory arrangement. It is further proposed that the gate arrangement have a further transmission channel between the at least one memory arrangement and the converter, which is configured to transmit serialized configuration bits and data bits.

[0030] The memory arrangement can further comprise a deserializer for each memory area, via which the configuration bits and data bits received serially via the transmission channel can be deserialized in order to then address the memory area in a suitable parallel format. The memory arrangement can further comprise a serializer for each memory area, via which the configuration bits and data bits received in parallel from the memory area can be serialized in order to then be transmitted to the converter in a suitable serial format via the further transmission channel.

[0031] The converter and the provided transmission channels enable access to the memory area or areas of the memory array, requiring only a few transmission channels between the converter and the memory array. For example, it is possible to use one transmission channel for transmission from the converter to a memory area and another transmission channel for transmission from the memory area to the converter, i.e., two transmission channels per memory area. In a further embodiment, more than two transmission channels are allocated per memory area. The latter embodiment is characterized by the fact that, although more routing resources are consumed in the gate array, a higher total data transmission rate is regularly enabled, for example, by allocating more than two transmission channels.In embodiments, the arrangement comprises an operating unit which is configured to receive the value of the signal to be written from a user and to transmit it to the monitoring circuit and / or to receive the read value of the signal from the monitoring circuit and to output it to the user.

[0032] This makes it possible to output the signal value read from the gate array's memory to a user via the control unit. Alternatively or additionally, it is possible to receive the signal value from the user via the control unit, which is to be written to the gate array's memory.

[0033] A method for operating the described arrangement comprises:

[0034] Reading the value of the signal of the gate arrangement from a memory of the gate arrangement by the monitoring circuit, wherein the reading of the value of the signal occurs independently of the function performed by the gate arrangement, passing the value from the monitoring circuit to the processor and using the value of the signal during the execution of the higher-level function, and / or

[0035] Generating the value of the signal by the processor during the execution of the higher-level function, passing the value of the signal from the processor to the monitoring circuit and writing the value of the signal into a memory of the gate arrangement by the monitoring circuit, wherein the writing of the value of the signal occurs independently of the function executed by the gate arrangement.

[0036] Character list

[0037] Embodiments are shown in the figures and are explained in more detail in the following description.

[0038] Figure 1 shows schematically an arrangement which comprises a programmable gate arrangement, a processor and an operating unit,

[0039] Figures 2-4 show a schematic representation of examples of exchangeable values ​​in a modeling language and

[0040] Figure 5 is a schematic view of a programmable gate array with memory array.

[0041] The same reference numerals are used throughout the figures for identical or similar elements. The illustrations in the figures may not be to scale.

[0042] Character description

[0043] Figure 1 schematically shows an arrangement comprising a programmable gate arrangement 10, a processor 30 and an operating unit 50.

[0044] The processor 30 is arranged on a processor board and has a real-time library RLI, which provides interfaces to a higher-level function 32 and to a driver 20.D. The processor 30 is configured to execute the higher-level function 32. Variables 34 are used to execute the higher-level function 32. Exchange values ​​36 are also used to execute the higher-level function 32. In the driver 20.D of a monitoring circuit 20 of the programmable gate arrangement 10, mirrored values ​​36.M of the exchange values ​​36 of the higher-level function 32 are present. The mirrored values ​​36.M and 36 are kept constant by the driver 20.D. The exchange values ​​36 are used by the higher-level function 32 and / or the driver 20.D checks, using suitable methods, whether the mirrored values ​​36.M have the same value as the exchange values ​​36.Once the exchange values ​​36 are mirrored with the mirrored values ​​36.M, their identity check is preferably omitted until a predefined condition, e.g., the expiration of a predefined time interval or a predefined number of simulation steps, is met. For example, in the embodiment of the invention according to Figure 1, there are two types of mirrored values ​​36.M and exchange values ​​36. The first type of exchange values ​​36 with corresponding mirrored values ​​36.M is used in the direction from the higher-level function 32 to the programmable gate arrangement 10. The second type of exchange values ​​36 with corresponding mirrored values ​​36.M is used in the direction from the programmable gate arrangement 10 to the higher-level function 32. This is indicated in Figure 1 by arrows in two directions between the exchange values ​​36 and the driver 20.D of the monitoring circuit 20. In the driver 20.D thus stores mirrored values ​​36. M, which are intended for exchange with the monitoring circuit 20 of the programmable gate arrangement 10.

[0045] Mirroring the values ​​between the exchange value range 36 and the mirrored values ​​36.M can be implemented in various ways. One possibility involves directly using the variable with the exchange value 36 of the higher-level function 32 by the driver 20.D as the mirrored value 36.M. Another possibility involves both the exchange value 36 and the mirrored value 36.M being present, and both values ​​36 and 36.M being written during write operations. A preferred further possibility involves both values ​​36 and 36.M being present, but pointing to the same memory locations on the processor board.

[0046] The driver 20.D has an additional interface DAQS. A DAQ data exchange with the control unit 50 can take place via this interface DAQS. For this purpose, the DAQS interface can receive and store information ML about values ​​to be acquired from the control unit 50 via the DAQ interface. The values ​​received from the driver 20.D can be temporarily stored in the buffer MB of the DAQS interface, and the values ​​from the buffer MB can be transferred to the control unit 50 via the data exchange DAQ.

[0047] The programmable gate arrangement 10 is configured to execute a function 22. The function 22 has a data exchange with the higher-level function 32. This data exchange within the scope of the execution of the function 22 and the higher-level function 32 is not shown in Figure 1. For example, signals S1 are exchanged, which are used by the function 22 during the execution of the function 22. The function 22 can also be configured to change the value of the signals S1, to receive the value of the signals S1 from the higher-level function 32 and / or to process the values ​​of the signals S1 and to output values ​​derived from the signals S1 back to the higher-level function 32. Signals of the function 22 can also be designed as constants K1. The function 22 is capable of using and processing constants K1.Changing the values ​​of constants Kl is not provided for data exchange with the higher-level function 32 during the execution of function 22. Such described data exchange for executing the function and the higher-level function can be performed, for example, via known registers, buffers, or bus interfaces. These interfaces must be specified when creating the gate array 10 and are provided in the hardware. This enables very fast data exchange, which, however, can only be subsequently changed with great effort. This change takes a long time and is therefore costly.

[0048] The programmable gate array 10 has input / output interfaces IO. These input / output interfaces IO can be used, for example, to read sensor values ​​or output values ​​through the programmable gate array 10. The input / output interface IO can be an analog interface, for example. The gate array can, for example, calculate values ​​of signals S1 from sensor values.

[0049] The signals S1 of function 22, which may also include constants K1, can be accessed by the monitoring circuit 20 independently of the execution of the function 22. In particular, the monitoring circuit 20 can read signals S1 and / or write constants K1. The monitoring circuit 20 is controlled by the driver 20.D of the processor 30. CMD commands can be used to inform the monitoring circuit 20 which signals S1 should be read out and / or which constants K1 should be modified. Via the read values ​​RV, values ​​of the signals S1 and / or the constants K1 can then be transferred from the monitoring circuit 20 to the driver 20.D. The contents of the CMD commands can, for example, have mirrored values ​​36.M. In a similar way, the read values ​​RV can be stored in the mirrored values ​​36.M. After the mirrored values ​​36.M have been stored using the driver 20.D, the values ​​are then available for use by the higher-level function 32. Similarly, the higher-level function 32 can write values ​​via the exchange values ​​36 using driver 20. D into the mirrored values ​​36. M, which are then transmitted to the monitoring circuit 20. The transmitted commands CMD can include information about which signals S1 should be read by the monitoring circuit 20 and / or which constants Kl should be rewritten with which values.

[0050] Figure 1 indicates that a processor 30 can interact with multiple programmable gate arrays 10. For example, the higher-level function 32 can incorporate a function 22 of a programmable gate array 10 into its execution. It is also possible for additional functions of additional gate arrays to be incorporated into the execution of the higher-level function 32. This is indicated in Figure 1 by additional gate arrays.

[0051] The programmable gate array 10 contains an interface environment IS, which in particular includes the monitoring circuit 20 and functional memory 22, which includes the memories where, for example, the signals S1 are provided for reading by the monitoring circuit 20. Such memories are also referred to as shadow registers. The interface environment IS can also include the memories that store the constants K1.

[0052] The operating unit 50 has, for example, a screen area 52. An input unit 54 configured to accept inputs from a user can be provided in the screen area. The input unit 54 can be configured, for example, as a touch-sensitive screen. Other input methods are conceivable, for example, via a keyboard, mouse, or others. The screen area 52 further has an output unit 56, via which values ​​58 can be output. A data exchange DAQ is provided for the operating unit 50 via the DAQS interface of the processor 30.

[0053] As shown, signals S1 of the gate arrangement can be accessed via the monitoring circuit 20 both by the higher-level function 32 of the processor and by a user via the operating unit 50. This has the advantage that the same monitoring circuit 20 can be used for both types of access and no separate interfaces need to be provided for each processor 30 and operating unit 50.

[0054] The monitoring circuit 20 is configured such that the exchange of signals S1, including the constants K1, occurs without interfering with the execution of function 22. The implementation of the monitoring circuit 20 is designed to be independent of the function 22 on the programmable gate array 10. This is achieved in particular by storing the values ​​of signals S1 in so-called shadow registers. The values ​​of the signals S1 are stored in these shadow registers, from where they can then be retrieved by the monitoring circuit 20. The retrieval does not affect the execution of function 22, but occurs independently of it.

[0055] Figure 2 shows an example of how signals S1 of function 22 can be accessed within the higher-level function 32 via the monitoring circuit 20. Figure 2 shows example data for this purpose, as it may be present in a simulation model of the higher-level function 32. The example data in Figure 2 is initially a single value in the top row. The second row of Figure 2 shows an example of a vector. The third row of Figure 2 shows an example of a matrix. The fourth row of Figure 2 shows an example of a bus. This data can be present in the simulation model of the higher-level function 32 in the form shown. In order to identify this data as exchange values ​​36, it can be specially identified, for example, in the naming. This could be done, for example, by a prefix that is placed in front of the variable name.If this prefix is ​​present, the displayed values ​​from the exchange value range 36 are mirrored into the mirrored range of the mirrored values ​​36.M of the driver 20.D. In the range of the mirrored values ​​36.M, these are regularly updated via the monitoring circuit 20. The respectively updated values ​​36M are mirrored into the range of the exchange values ​​36 via the driver 20.D. This allows the exchange values ​​36 present in the simulation model of the higher-level function 32 to be updated via the driver 20.D and the monitoring circuit 20, so that the exchange values ​​36 are present in the higher-level function as they are currently present in the gate arrangement 10 as signals S1, optionally comprising the constants K1. Figure 3 shows an example of the other direction of data exchange.Again, the first line of Figure 3 shows a simple variable, the second line of Figure 3 a vector, the third line of Figure 3 a matrix, and the fourth line of Figure 3 a data bus. In the selected and illustrated example, these values ​​are represented in the simulation model of the higher-level function 32, e.g., as a data sink. It is also possible to select a different format to symbolize that a value is to be written. Write operations are performed in the area of ​​the mirrored values ​​36.M via the area of ​​the exchange values ​​36. The values ​​36.M in the form of mirrored values ​​are then written into the memory of the gate arrangement 10 via the monitoring circuit 20. This applies in particular to constants K1 of the function 22, for which new values ​​can be written via the monitoring circuit 20 and the driver 20.D.This can be done via so-called data sinks, as shown in Figure 3.

[0056] Figure 4 also shows examples of data sinks that can occur in the simulation model of the higher-level function 32. Again, they are shown in this order: simple variable, vector, matrix, data bus.

[0057] In contrast to Figure 3, the values ​​shown in Figure 4 also have a validity signal "Enbl", technically referred to as an "enable signal" Enbl, which can be applied to a validity signal input En-in, technically referred to as an "enable port" En-in. The respective enable port En-in shown is an assigned control input for the respective assigned data sink, which signals to a corresponding signal input Dt-in of the data sink that the value applied to the signal input Dt-in is either valid or not. A positive or negative logic can be specified for the enable port En-in. For example, with positive logic, it is possible to provide that a signal applied to the signal input of the data sink is only to be considered valid if a positive voltage level with a predefined voltage magnitude is applied to the enable port En-in of the data sink, i.e., a validation signal Enbl is applied.

[0058] The variables shown in Figures 3 and 4 can also be identified, as already described for Figure 2, by selecting a prefix for their name so that they are provided for exchange with the gate arrangement 10 via the monitoring circuit 20 via the area with the exchange values ​​36. In the programmable gate arrangement 10, memories for storing a constant K1 can be designed, for example, as a flip-flop. If larger memory areas are required to store a large constant K1, memory areas 60 (Figure 5) such as so-called BlockRAM blocks can also be used. BlockRAM blocks are particularly common in FPGAs. They can be used individually or are automatically interconnected during the synthesis of the gate arrangement 10 when larger amounts of memory are required.A typical application for a large constant Kl is, for example, that an engine characteristic map of an engine to be simulated by the higher-level function 32 and function 22 is to be stored as a constant Kl. This large amount of memory can, for example, be stored in multiple memory areas 60 (Figure 5), e.g., BlockRAM blocks, abbreviated as "BlockRAM." When implementing the gate array 10 as an FPGA, storage as a look-up table is a good option. It may be that these constants Kl still need to be changed at runtime. At runtime means during the execution of the higher-level function 32 and function 22. In this case, memory areas 60, such as BlockRAM, must be accessed to exchange constants Kl, for example, to write the constant Kl.

[0059] Figure 5 shows an example of the gate array 10 with multiple memory areas 60. These memory areas 60 are, for example, the aforementioned BlockRAM of the programmable gate array 10, for example, an FPGA. Such a memory area 60 is characterized in that it can be addressed by configuration bits and data bits. The configuration bits define where in the memory area 60 the data bits are to be stored. At least one parallel interface is provided for accessing the memory areas 60. In the example shown, two parallel interfaces are provided, one for writing and one for reading. The configuration bits and the data bits are exchanged in parallel with the memory area 60 via the parallel interfaces. Within the memory array 23, the parallel interface shown is connected between a deserializer "Des" or "Des"a serializer "Ser" and a connected memory area 60 is generally not disadvantageous if the deserializer or serializers are arranged close to the memory area 60. The same applies to a parallel interface between the monitoring circuit 20 and a serializer "Ser" in the converter 24 or deserializer "Des" in the converter 24 for the respective connection of the monitoring circuit 20 to the converter 24.

[0060] If such a memory area 60 is to be addressed via the monitoring circuit 20, for example, for data exchange, the configuration bits and the data bits must be transmitted from the monitoring circuit 20 to the memory area 60, and read data must be transmitted from the memory area 60 to the monitoring circuit 20. This is necessary, for example, if signals S1 stored in the memory area 60, for example, constants K1, are to be read and / or written by the monitoring circuit 20.

[0061] It is now proposed that the memory areas 60 be contained in a memory array 23. In addition to the memory areas 60, the memory array 23 has deserializers Des and serializers Ser. One deserializer Des is provided for each memory area 60. One serializer Ser is provided for each memory area 60. The deserializer Des of the memory area 60 has the task of receiving the configuration bits and the data bits in serial form, parallelizing them, and transmitting them to the memory area 60 via the parallel interface. In the opposite direction, the serializer Ser has the task of receiving and serializing parallel data, i.e. the configuration bits and the data bits from the memory area 60 in parallel form.

[0062] A converter 24 is provided for communication between monitoring circuit 20 and memory array 23. Converter 24 includes a serializer Ser and a demultiplexer Demux. Converter 24 also includes a deserializer Des and a multiplexer Mux.

[0063] The serializer Ser of the converter 24 is responsible for serializing parallel data output by the monitoring circuit 20, for example, parallel configuration bits and data bits for one of the memory areas 60. The serialized data bits and configuration bits are assigned to the specific memory area 60 via the demultiplexer Demux and transmitted via a serial data line to the respective deserializer Des of the memory array 23 assigned to the specific memory area 60. Similarly, according to the embodiment of Figure 5, the monitoring circuit 20 receives parallel data from the deserializer Des of the converter 24. This parallel data was composed of serial data by the deserializer Des of the converter 24. This data comprises configuration bits and data bits of the respective memory area 60.These configuration bits and data bits of the respective memory area 60 were received in serial form by the multiplexer Mux. This multiplexer Mux is capable of receiving the serial data bits and configuration bits of the respective memory areas 60 and switching between these memory areas. In the embodiment of Figure 5, it is preferred that the multiplexer Mux receives the serial configuration bits and data bits from the respective serializer Ser assigned to the corresponding memory area 60.

[0064] The advantage of the arrangement shown in Figure 5 is that only one serial line per memory area 60 needs to be provided between the converter 24 and the memory array 23. Compared to parallel transmission via a parallel line, transmission resources can thus be saved. This is an efficient implementation for the gate array 10. In particular, the so-called routing resources of the gate array 10 are saved. Moreover, this arrangement is technically simple to implement.

[0065] List of reference symbols

[0066] 10 programmable gate array

[0067] 20 Monitoring circuit

[0068] 20. D Driver of the monitoring circuit

[0069] 22 Function

[0070] 23 Memory arrangement

[0071] 24 converters

[0072] 30 processor

[0073] 32 higher-level function

[0074] 34 variables

[0075] 36 exchange values

[0076] 36. M mirrored values

[0077] 50 control unit

[0078] 52 screen area

[0079] 54 Input unit

[0080] 56 Output unit

[0081] 58 Output of values

[0082] 60 memory area

[0083] RLI Real-time Library

[0084] DAQS interface to the control unit

[0085] DAQ data exchange with the control unit

[0086] Data Data

[0087] Dt-in signal input of the data sink

[0088] Enbl Validation signal, technically known as Enable-

[0089] Signal refers

[0090] En-in validation signal port, technically known as

[0091] Enable port

[0092] ML selection

[0093] MB cache

[0094] CMD command

[0095] RV read values

[0096] IF Interface Environment 10 Input / Output

[0097] SI Signal

[0098] Kl constant

[0099] RD Reading

[0100] WR Writing

[0101] Mux Multiplexer

[0102] Demux Demultiplexer

[0103] Ser Serializer

[0104] The deserializer

Claims

CLAIMS 1. Monitoring circuit (20) for a programmable gate arrangement (10), wherein the gate arrangement (10) is configured to execute a function (22) and to use at least one signal (Sl, Kl) to execute the function (22), wherein a processor (30) is provided which is configured to execute a higher-level function (32) and to transfer a value of the at least one signal (Sl, Kl) to the gate arrangement (10) and / or to receive a value of the at least one signal (Sl, Kl) from the gate arrangement (10) to execute the higher-level function (32), wherein the monitoring circuit (20) is configured to exchange a value of the at least one signal (Sl, Kl) with the gate arrangement (10), wherein the exchange of the value of the signal (Sl, Kl) takes place independently of the function (22) executed on the gate arrangement (10), wherein the monitoring circuit (20) is configured to determine the value of the at least one signal (Sl,Kl) with the processor (30)., 2. Monitoring circuit according to claim 1, wherein the exchange of the value of the at least one signal (Sl, Kl) comprises reading and / or writing the at least one signal (Sl, Kl) by the monitoring circuit (20).

3. Monitoring circuit according to claim 1 or 2, wherein the gate arrangement (10) is arranged to receive a value of the at least one signal (Sl, Kl) for processing from the processor (30), to process the value of the signal during the execution of the function and to output the processed value of the signal (Sl, Kl) to the processor (30).

4. Monitoring circuit according to one of the preceding claims, wherein a value of the at least one signal (Sl, Kl) is present in the gate arrangement (10) and / or the gate arrangement (10) is configured to derive a value of the at least one signal (Sl, Kl) from a read-out sensor value.

5. Monitoring circuit according to one of the preceding claims, wherein the signal (Kl) is embodied as a constant (Kl), wherein the gate arrangement (10) is configured to use the constant (Kl) during the execution of the function (22), wherein the monitoring circuit (20) is configured to write a value of the at least one constant (Kl) of the gate arrangement (10), wherein the writing of the value of the constant (Kl) takes place independently of the function (22) executed on the gate arrangement (10), wherein the monitoring circuit (20) is configured to receive the value to be written for the constant (Kl) from the processor (30).

6. Monitoring circuit according to claim 5, wherein the monitoring circuit (20) is further configured to read out the value of the constant (Kl) and to output the read-out value to the processor (30).

7. Monitoring circuit according to claim 5 or 6, wherein the monitoring circuit (20) is configured to receive a value of the constant (Kl) to be written from an operating unit (50), wherein the operating unit is configured (50) to receive the value to be written from a user.

8. Monitoring circuit according to one of the preceding claims, wherein the monitoring circuit (20) is configured to output a read value of the signal (Sl, Kl) to the operating unit (50), wherein the operating unit is configured (50) to output the read value to a user.

9. Monitoring circuit according to one of the preceding claims, wherein the monitoring circuit (20) is arranged to receive information about the signal (Sl, Kl), the value of which is to be read out, from the processor (30).

10. Arrangement with the monitoring circuit (20) according to one of the preceding claims, as well as with the processor (30) and the programmable gate arrangement (10).

11. Arrangement according to claim 10, wherein the value of the signal received by the monitoring circuit (20) can be used by the processor (30) in the execution of the higher-level function (32).

12. Arrangement according to claim 10 or 11, wherein the value of the constant (Kl) transferred to the monitoring circuit (20) can be generated by the processor (30) during the execution of the higher-level function (32).

13. Arrangement according to one of claims 10 to 12, wherein the gate arrangement (10) has at least one memory arrangement (23) which can be addressed via configuration bits and data bits, and the monitoring circuit (20) is set up to read and / or write to the at least one memory arrangement (23), wherein the gate arrangement (10) has a converter (24) between the monitoring circuit (20) and the at least one memory arrangement (23), which converter is set up to serialize the configuration bits and the data bits and to transmit them in serial form.

14. Arrangement according to claim 13, wherein the gate arrangement (10) has a transmission channel between the converter (24) and the at least one memory arrangement (23) which is arranged to transmit serialized configuration bits and data bits.

15. Arrangement according to one of claims 10 to 14, further comprising an operating unit (50) which is configured to receive the value of the signal (Sl, Kl) to be written from a user and to transmit it to the monitoring circuit (20) and / or to receive the read-out value of the signal (Sl, Kl) from the monitoring circuit (20) and to output it to the user.

16. A method for operating an arrangement according to one of claims 10 to 15, comprising: Reading the value of the signal (Sl, Kl) of the gate arrangement (10) by the monitoring circuit (20), wherein the reading of the value of the signal (Sl, Kl) is independent of the operation carried out by the gate arrangement (10) Function (22) is carried out, transferring the value from the monitoring circuit (20) to the processor (30) and using the value of the signal (Sl, Kl) during the execution of the higher-level function (32), and / or generating the value of the signal (Sl, Kl) by the processor (30) during the execution of the higher-level function (32), transferring the value of the signal (Sl, Kl) from the processor (30) to the monitoring circuit (20) and writing the value of the signal (Sl, Kl) by the monitoring circuit (20), wherein the writing of the value of the signal (Sl, Kl) is carried out independently of the function (22) carried out by the gate arrangement (10).

Images