Peak-to-average ratio (PAR)-based analog predistortion (APD) in a front-end module

Abstract

Peak-to-average ratio (PAR)-based analog predistortion (APD) in a front-end module (FEM) is disclosed. In one aspect, a FEM acquires a PAR measurement and adjusts operating parameters (i.e., APD) within the FEM to create a normalized distortion profile that may simplify digital predistortion in a baseband processor (BBP). PAR measurements may be triggered by various events such as on a per symbol, per slot, or per frame basis and may be tied to changes in a supply voltage level or command to change the supply voltage. Providing such APD may improve efficiency of the operation of the FEM. Likewise providing a normalized distortion profile may simplify design requirements for the BBP.

Description

PEAK-TO-A VERAGE RATIO (PAR)-BASED ANALOG PREDISTORTION (APD) IN A FRONT-END MODULEPRIORITY APPLICATION

[0001] The present application is related to U.S. Provisional Patent Application Serial No. 63 / 482,093 filed on January 30, 2023, and entitled “PEAK-TO-AVERAGE RATIO (PAR)-BASED ANALOG PREDISTORTION (APD) IN A FRONT-END MODULE,” the contents of which is incorporated herein by reference in its entirety.BACKGROUNDI. Field of the Disclosure

[0002] The technology of the disclosure relates generally to front-end modules and, more particularly, to ways to normalize a distortion profile for a front-end module in a transceiver.II. Background

[0003] Computing devices abound in modern society, and more particularly, mobile communication devices have become increasingly common. The prevalence of these mobile communication devices is driven in part by the many functions that are now enabled on such devices. Increased processing capabilities in such devices means that mobile communication devices have evolved from pure communication tools into sophisticated mobile entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find ways to increase bandwidth for data transmission. This pressure has led to ever evolving wireless standards. Each new wireless standard places new demands on the circuitry of the wireless transmitters. Such demands provide room for innovation.SUMMARY

[0004] Aspects disclosed in the detailed description include peak-to-average ratio (PAR)-based analog predistortion (APD) in a front-end module (FEM). In particular, exemplary aspects of the present disclosure contemplate acquiring a PAR measurement in the FEM and adjusting operating parameters (i.e., APD) within the FEM to create anormalized distortion profile that may simplify digital predistortion (DPD) in a baseband processor (BBP). PAR measurements may be triggered by various events such as on a per symbol, per slot, or per frame basis and may be tied to changes in a supply voltage level or command to change the supply voltage. Providing such APD may improve efficiency of the operation of the FEM. Likewise providing a normalized distortion profile may simplify design requirements for the BBP.

[0005] In this regard in one aspect, a method of normalizing a distortion profile for a FEM is disclosed. The method comprises measuring a PAR in the FEM. The method also comprises adjusting an operating parameter to change the distortion profile for the FEM.

[0006] In another aspect, a FEM is disclosed. The FEM comprises a power amplifier chain having a PAR characteristic. The FEM also comprises a PAR detector coupled to the power amplifier chain to measure the PAR characteristic. The FEM also comprises a control circuit coupled to the PAR detector. The control circuit is configured, based on measurements from the PAR detector, to adjust an operating parameter of the FEM.

[0007] In another aspect, a wireless communication device is disclosed. The wireless communication device includes a transmission chain comprising a FEM. The FEM includes a power amplifier chain having a PAR characteristic and a PAR detector coupled to the power amplifier chain to measure the PAR characteristic. The FEM further includes a control circuit coupled to the PAR detector and configured to, based on measurements from the PAR detector, adjust an operating parameter of the FEM.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a conventional front-end module (FEM) coupled to a baseband processor (BBP) through a radio frequency front end (RFFE) bus as part of a transmission chain;

[0009] Figure 2 is a signal diagram showing supply voltage changes versus time relative to slots and symbols for various types of power control circuits, along with supply voltage change commands that may appear on the RFFE bus;

[0010] Figure 3 is a block diagram of a FEM coupled to a BBP that uses information from an RFFE bus to assist in triggering peak-to-average ratio (PAR) measurements in the FEM according to exemplary aspects of the present disclosure;

[0011] Figure 4 is a block diagram of a FEM with a PAR detector that measures PAR within the FEM to adjust operating parameters of the FEM according to exemplary aspects of the present disclosure;

[0012] Figure 5 is a block diagram of a BBP-FEM pair with a PAR detector that measures PAR within the FEM to adjust operating parameters of the of the FEM according to exemplary aspects of the present disclosure;

[0013] Figure 6 is a block diagram of a hybrid complementary metal oxide semiconductor (CMOS)-bipolar FEM that may implement portions of the present disclosure in the different technologies;

[0014] Figure 7 is a block diagram similar to Figure 6 but with a different distribution of aspects of the present disclosure between the different technologies;

[0015] Figure 8 is a block diagram of a hybrid CMOS-bipolar FEM with an integrated PAR detector;

[0016] Figure 9 is a block diagram of the PAR detector of the present disclosure being used in a receive portion of a FEM; and

[0017] Figure 10 is a block diagram of a mobile terminal, which may include the FEM of Figures 3-9 according to the present disclosure.DETAILED DESCRIPTION

[0018] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0019] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As usedherein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0020] It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

[0021] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms usedherein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0024] Aspects disclosed in the detailed description include peak-to-average ratio (PAR)-based analog predistortion (APD) in a front-end module (FEM). In particular, exemplary aspects of the present disclosure contemplate acquiring a PAR measurement in the FEM and adjusting operating parameters (i.e., APD) within the FEM to create a normalized distortion profile that may simplify digital predistortion (DPD) in a baseband processor (BBP). PAR measurements may be triggered by various events such as on a per symbol, per slot, or per frame basis and may be tied to changes in a supply voltage level or command to change the supply voltage. Providing such APD may improve efficiency of the operation of the FEM. Likewise providing a normalized distortion profile may simplify design requirements for the BBP.

[0025] Before addressing exemplary aspects of the present disclosure, a brief overview of a conventional FEM coupled to a BBP is provided with reference to Figure 1 along with a discussion of existing signals that may pass therebetween over a radio frequency front end (RFFE) bus to control voltage signals with reference to the timing diagram of Figure 2. A discussion of exemplary aspects of the present disclosure begins below with reference to Figure 3.

[0026] In this regard, Figure 1 is a block diagram of a transmission chain 100. The transmission chain 100 may include a BBP 102 and a FEM 104. The BBP 102 communicates with the FEM 104 through an RFFE bus 106. Accordingly, the BBP 102 has a bus interface 108, which may be a digital RFFE interface. The FEM 104 may include a bus interface 110 that couples to a digital control circuit 112. The digital control circuit 112 may control aspects of a power amplifier chain 114. The power amplifier chain 114 may include a bias circuit 116, which may provide a static bias to a power amplifier stage 118 within the power amplifier chain 114.

[0027] More typically, the FEM 104 may include a power management integrated circuit (PMIC) that receives power management signals such as envelope tracking (ET) or average power tracking (APT) that sets the bias level in such a way so as to maintain efficiency by keeping the supply voltage at a level appropriate to the desired level of the signal to be transmitted.

[0028] Newer generations of cellular communications such as fifth generation - new radio (5G-NR) have introduced much more aggressive timing requirements for signal transmission. Carrier spacing of 15-240 kilohertz (kHz) and symbols as short as 4.46 microseconds (ps) are contemplated. The allocation between transmission symbols (uplink symbols) and receive signals (downlink symbols) may vary and changes can be done on a symbol-to-symbol basis, mandating fast settlings within the system. Likewise, the uplink modulations may vary from quadrature phase shift keying (QPSK) up to 256 quadrature amplitude modulation (QAM).

[0029] While ET or APT information may pass from the BBP 102 to the FEM 104, there is currently no transfer of information relating to the modulation type between the BBP 102 and the FEM 104. It should be appreciated that the PAR of the signal may vary significantly depending on the modulation scheme used. PAR has fundamental implications on the linearity of the behavior of the power amplifier chain 114. Because the PAR may impact the compression of the power amplifier stage 118, this absence of communication impacts the operation of the BBP 102. Specifically, there is likely to be more distortion in the power amplifier chain 114, and the BBP 102 is likely to have more DPD to offset this non-linear behavior in the power amplifier chain 114.

[0030] What is transferred between the BBP 102 and the FEM 104 is better illustrated in the timing diagram 200 of Figure 2. Specifically, Figure 2 illustrates a supply voltage (also referred to as Vcc) change command for various types of APT systems. In line 202, corresponding to a traditional slow APT, there may be two supply voltage change commands 204A, 204B per frame 206 on the RFFE bus 106. Similarly, in a slot- tracking fast APT line 208, there may be multiple supply voltage change commands 210(1)- 210(M) per frame 212. This may cause changes in a supply voltage and power level, as seen by line 214. It should be appreciated that the line 214 is merely an example, and the actual changes may vary according to the needs of the wireless system. Each time there is a supply voltage change, there is a corresponding command 216 on the RFFE bus 106.

[0031] Again, it should be appreciated that there is currently no provision for transferring modulation scheme information from the BBP 102 to the FEM 104. Likewise, there is no transfer of expected PAR information from the BBP 102 to the FEM 104.

[0032] Exemplary aspects of the present disclosure contemplate adding a PAR detector in the FEM to detect a PAR characteristic of a power amplifier chain and using information derived therefrom to make changes to operating parameters within the FEM to assist in making a normalized distortion profile for the FEM across multiple frequencies and multiple modulation types. This normalized distortion profile allows the BBP to use a smaller set of DPD coefficients making overall operation simpler for the BBP (as well as saving memory space or the like). There are a variety of places the PAR detector may be positioned and there are a variety of adjustments that can be made. These variations are explored in the Figures below.

[0033] In this regard, Figure 3 is a block diagram of a transmission chain 300 that includes a BBP 302 and a FEM 304 coupled by an RFFE bus 306. The BBP 302 may include a bus interface 308, a control circuit 310, and a digital signal processor (DSP) 312. While not shown, the BBP 302 may also include memory.

[0034] With continued reference to Figure 3, the FEM 304 may include a bus interface 314 coupled to the RFFE bus 306, a power amplifier chain 316, and a PAR detector 318. The bus interface 314 extracts a trigger event from the RFFE bus 306 as better explained below and causes a trigger sense circuit 320 to cause the PAR detector 318 to measure the PAR in the power amplifier chain 316.

[0035] The RFFE bus 306 is also coupled to a power management integrated circuit (PMIC) 322. The PMIC 322 may include a bus interface 324 and receive supply voltage change commands to adjust a supply voltage provided to the power amplifier chain 316. These supply voltage change commands may be sent from the BBP 302 to the PMIC 322 over the RFFE bus 306 and may be detected by the bus interface 314 and used as trigger events for the trigger sense circuit 320. What is not present on the RFFE bus 306 is any overt indication of a signal modulation scheme or an expected PAR value.

[0036] Figure 4 provides more detail about the FEM 304. In particular, the FEM 304 may include a trigger extraction circuit 400 coupled to the bus interface 314. The trigger extraction circuit 400 may send a command to the PAR detector 318. Likewise, the trigger extraction circuit 400 may provide this information to a decode circuit 402, which may calculate a value of the supply voltage written to the PMIC 322. The output of the PAR detector 318 may be provided to a comparator 404, which compares the measured value to the calculated supply voltage. The comparator 404 may be coupled to an APDcontrol circuit 406, which may adjust operating parameters of the power amplifier chain 316. Additionally, the information from the PAR detector 318 may be provided back to the bus interface 314 and sent back out through the RFFE bus 306 to an external point (such as the BBP 302) for use as needed or desired.

[0037] Figure 5 provides still more detail of the transmission chain 300. The BBP 302 may include a DPD circuit 500 that is associated with a memory 502 that stores coefficients for the DPD to be applied. Exemplary aspects of the present disclosure normalize the distortion profile so that fewer sets of coefficients are required in the BBP 302. This reduction in DPD coefficient sets allows memory size to be reduced, which may also have the benefit of reducing power consumption.

[0038] With continued reference to Figure 5, the APD control circuit 406 may adjust, by way of example, a bias circuit 504 that biases one or more power amplifiers in the power amplifier chain 316. In addition, or as an alternative, the APD control circuit 406 may tune a load line 506.

[0039] As noted above, the PAR detector 318 may be positioned at various locations in the FEM 304. Figure 6 shows three possible locations. Specifically, the power amplifier chain 316 may include a driver amplifier stage 600 and an output stage 602 with an interstage node 604 therebetween. While not shown, there may be an intermediate amplifier stage located at the interstage node 604. The PAR detector 318 may be positioned in front of the driver amplifier stage 600 at an input node 606, at the interstage node 604, or after the output stage 602 at an output node 608. While not shown, there may be a bias circuit 504 that may control the driver amplifier stage 600 or the output stage 602 or both. If the PAR detector 318 is at the input node 606, the lower signal levels at this point in the power amplifier chain 316 may require more sophisticated detector circuitry. If the PAR detector 318 is at the interstage node 604, a suitable compromise between signal levels and ease of detection may be achieved. If the PAR detector 318 is at the output node 608, the signal is easy to detect, but there may be compression of the signal, which may negatively impact PAR estimation. Other tradeoffs may exist for biasing the driver amplifier stage 600 or the output stage 602.

[0040] Figure 7 shows one possible implementation in a hybrid complementary metal oxide semiconductor (CMOS)-bipolar technology system 700. In particular, the output stage 602 may be made from a bipolar technology such as gallium arsenide (GaAs). Thedriver amplifier stage 600 and the bias circuits 504A, 504B are within a CMOS die 702. The PAR detector 318 may also be in the CMOS die 702. The load line 506 tuning may be bipolar or made on a silicon on insulator (Sol) die 704.

[0041] More detail about the PAR detector 318 is provided in Figure 8, where the PAR detector 318 may include a peak power detector 800 and an average power detector 802. A digital controller 804 may subtract or compute the PAR based on signals from the peak power detector 800 and the average power detector 802. Also, note that tuning the load line 506 may be done through switched capacitors.

[0042] Note that while the above discussion has focused on a transmit chain, it should be appreciated that aspects of the present disclosure may also be applied to a receive chain, as shown by Figure 9, where a receive chain 900 may include a low noise amplifier (LNA) 902 having a bias circuit 904. A PAR detector 906 may provide a PAR measurement that is used to set the bias of the bias circuit 904.

[0043] With reference to Figure 10, the concepts described above may be implemented in various types of user elements 1000, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near field communications. The user elements 1000 will generally include a control system 1002, a BBP 1004, transmit circuitry 1006, receive circuitry 1008, antenna switching circuitry 1010, multiple antennas 1012, and user interface circuitry 1014. In a non- limiting example, the control system 1002 can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example. In this regard, the control system 1002 can include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receive circuitry 1008 receives radio frequency signals via the antennas 1012 and through the antenna switching circuitry 1010 from one or more base stations. An LNA and a filter of the receive circuitry 1008 cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0044] The BBP 1004 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed on greater detail below. The BBP 1004 is generally implemented in one or more DSPs and ASICs.

[0045] For transmission, the BBP 1004 receives digitized data, which may represent voice, data, or control information, from the control system 1002, which it encodes for transmission. The encoded data is output to the transmit circuitry 1006, where a digital- to-analog converter(s) (DAC) converts the digitally-encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 1012 through the antenna switching circuitry 1010 to the antennas 1012. The multiple antennas 1012 and the replicated transmit and receive circuitries 1006, 1008 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

[0046] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0047] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosurewill be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

AMENDED CLAIMS received by the International Bureau on 13 May 2024 (13.05.2024)1. (Currently Amended) A method of normalizing a distortion profile for die containing an amplifier chain a front end module (FEM), comprising: measuring a peak-to-average ratio (PAR) of a signal to be amplified by the amplifier chain in the die in the FEM; and adj usting a bias of a power amplifier in the amplifier chain and adjusting a load line tuning to provide analog predistortion to the signal so as to conform the signal to a normalized profile known to a precursor circuit an operating parameter to change the distortion profile for the FEM.

2. (Canceled)3. (Currently Amended) The method of claim 1, wherein adjusting the bias operating parameter comprises changing biases for multiple power amplifiers.

4. (Canceled)5. (Currently Amended) The method of claim [[4]] j_, wherein adjusting the load line tuning comprises using switched capacitors to adjust the load line tuning.

6. (Currently Amended) The method of claim 1, wherein measuring the PAR comprises measuring the PAR with a PAR detector positioned between two amplifiers in the die FEM.

7. (Currently Amended) The method of claim 1 , further comprising detecting a trigger event on an external bus coupled to the die FEM.

8. (Currently Amended) The method of claim 7, wherein detecting the trigger event comprises snooping a radio frequency front end (RFFE) bus coupled to the die FEM.AMENDED SHEET (ARTICLE 19)9. (Original) The method of claim 7, wherein detecting the trigger event comprises detecting a supply voltage change command.

10. (Currently Amended) The method of claim 1, further comprising sending PAR information to the precursor circuit, wherein the precursor circuit comprises a baseband processor (BBP) from the die FEM.

11. (Currently Amended) A die front end module (FEM) comprising: a power amplifier chain having a signal comprising a peak-to-average (PAR) characteristic; a PAR detector coupled to the power amplifier chain to measure the PAR characteristic of the signal; and a control circuit coupled to the PAR detector and configured to: based on measurements from the PAR detector, provide analog predistortion to the signal to make a normalized predistortion profile for the signal, wherein to provide the analog predistortion, the control circuit is configured to: adjust a bias of an amplifier in the power amplifier chain; and adjust a load line tuning for the amplifier chain an operating parameter of the FEM.

12. (Currently Amended) The die FEM of claim 11, wherein the power amplifier chain comprises at least two power amplifiers having an interstage node and the PAR detector is coupled to the interstage node.

13. (Currently Amended) The die FEM of claim 11, wherein the power amplifier chain comprises a transmit power amplifier chain.

14. (Currently Amended) The die FEM of claim 11, wherein the power amplifier chain comprises a low noise amplifier (LNA) receive amplifier.AMENDED SHEET (ARTICLE 19)15. (Currently Amended) The die FEM of claim 11, further comprising a bus interface configured to be coupled to a communication bus and wherein the control circuit is further configured to snoop on the communication bus through the bus interface.

16. (Currently Amended) The die FEM of claim 15, wherein the control circuit is further configured to detect a trigger event that triggers detection with the PAR detector through snooping on the communication bus.

17. (Currently Amended) The die FEM of claim 11, wherein the power amplifier chain comprises a bias circuit.

18. (Canceled)19. (Canceled)20. (Currently Amended) A wireless communication device comprising: a transmission chain comprising a die front end module (FEM) comprising: a power amplifier chain having a signal comprising a peak-to-average (PAR) characteristic; a PAR detector coupled to the power amplifier chain to measure the PAR characteristic of the signal; and a control circuit coupled to the PAR detector and configured to: based on measurements from the PAR detector, provide analog predistortion to the signal to make a normalized predistortion profile for the signal, wherein to provide the analog predistortion, the control circuit is configured to: adjust a bias of an amplifier in the power amplifier chain; and adjust a load line tuning for the amplifier chain an operating parameter of the FEM.AMENDED SHEET (ARTICLE 19)STATEMENT UNDER ARTICLE 19(1)Applicant herein amends claims 1, 11, and 20.Claims 2, 4, 18, and 19 are canceled.Claims 3, 5-8, and 10 are amended to conform to the changes to claim 1 and cancelation of claims 2 and 4.Claims 12-17 are amended herein to correct the preamble based on the amendment to claim 11.The amendment to claims 1, 11, and 20 is based on claims 2, 4, 18, and 19 of the Application as filed, as well as paragraphs 0024 and 0041 of the application as filed.

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