Amplifier circuit

Abstract

It is desirable to increase the output power of an amplifier circuit.SOLUTION: A unit amplifier including a first transistor having a first control terminal to which a first input signal is input and configured to generate a first output signal, a second transistor having a second control terminal to which a second input signal is input and configured to generate a second output signal differential from the first output signal, a third transistor provided in parallel with the first transistor and configured to generate a third output signal differential from the first output signal, and a fourth transistor provided in parallel with the second transistor and configured to generate a fourth output signal differential from the second output signal, the first output signal and the fourth output signal are merged and output to a first output transmission line, and the second output signal and the third output signal are merged and output to a second output transmission line.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an amplifier circuit. [Background technology]

[0002] Conventionally, there is known a driving circuit that amplifies two complementary input signals having opposite phases to each other and outputs two complementary output signals having opposite phases to each other (see, for example, Patent Document 1). Also, there is known a semiconductor integrated circuit that suppresses the occurrence of distortion of data signals and gain peaking in frequency characteristics that occurs in wiring between the preceding and succeeding stages in an integrated circuit that has a feedback amplifier circuit in the preceding stage that includes feedback that returns a part of the output signal to the input side (see, for example, Patent Document 2). Also, F T A circuit including a doubler circuit is known (see, for example, Patent Document 3). [Prior art document] [Patent documents] [Patent Document 1] JP 2018-170705 A [Patent Document 2] International Publication No. 2012 / 141008 [Patent Document 3] Japanese Patent Publication No. 2015-526979 [Non-patent literature] [Non-Patent Document 1] H. Wakita, et al., "36-GHz-bandwidth quad-channel driver module using compact QFN package for optical coherent systems," 2015 IEEE 24th Electrical Performance of Electronic Packaging and Systems (EPEPS), San Jose, CA, USA, 2015, Page 213-216 [Non-Patent Document 2] T. Tatsumi, et al., "Development of Electro-Absorption Modulator Driver ICs for 25G / 40G Transmission," SEI Technical Review, no. 74, 2012, Pages 66-70. [Non-Patent Document 3] J.B. Beyer, et al., "MESFET Distributed Amplifier Design Guidelines," IEEE Transactions on Microwave Theory and Techniques, vol. 32, Issue 3, March 1984, Pages 268-275. [Non-Patent Document 4] Y. Ayasli, et al., "Capacitively Coupled Traveling-Wave Power Amplifier," IEEE Transactions on Microwave Theory and Techniques, vol. 32, Issue 12, Dec. 1984, Page 1704-1709. Summary of the Invention [Problem to be solved by the invention]

[0003] In an amplifier circuit, it is desirable to increase the output power. [Means for solving the problem]

[0004] To solve the above problems, a first aspect of the present invention provides an amplifier circuit including a differential input transmission path including a first input transmission path and a second input transmission path, a differential output transmission path including a first output transmission path and a second output transmission path, and at least one unit amplifier provided between the differential input transmission path and the differential output transmission path. In the amplifier circuit, the unit amplifier may have a first transistor that receives a first input signal from the first input transmission path at a first control terminal and generates a first output signal, and a second transistor that receives a second input signal from the second input transmission path at a second control terminal and generates a second output signal that is differential with respect to the first output signal. In any of the amplifier circuits above, the unit amplifier may have a third transistor that is provided in parallel with the first transistor and generates a third output signal that is differential with respect to the first output signal. In any of the amplifier circuits above, the unit amplifier may have a fourth transistor that is provided in parallel with the second transistor and generates a fourth output signal that is differential with respect to the second output signal. In any of the above amplifier circuits, the unit amplifier may combine the first output signal and the fourth output signal and output the combined signal to the first output transmission path, and may combine the second output signal and the third output signal and output the combined signal to the second output transmission path.

[0005] In any of the above amplifier circuits, a bias signal may be input to the third control terminal of the third transistor and the fourth control terminal of the fourth transistor without passing through the differential input transmission path.

[0006] In any of the above amplifier circuits, the unit amplifier may include a first series resistor connected in series with the third control terminal of the third transistor. In any of the above amplifier circuits, the unit amplifier may include a first series capacitor connected in series with the first series resistor between the first series resistor and a ground terminal. In any of the above amplifier circuits, the unit amplifier may include a first parallel resistor that is provided in parallel with the first series capacitor and to which the bias signal is input.

[0007] In any of the above amplifier circuits, the unit amplifier may include a second series resistor connected in series with the fourth control terminal of the fourth transistor. In any of the above amplifier circuits, the unit amplifier may include a second series capacitor connected in series with the second series resistor between the second series resistor and a ground terminal. In any of the above amplifier circuits, the unit amplifier may include a second parallel resistor provided in parallel with the second series capacitor and receiving the bias signal.

[0008] In any of the above amplifier circuits, the unit amplifier may include a third series capacitor connected in series with the first control terminal of the first transistor, and a fourth series capacitor connected in series with the second control terminal of the second transistor.

[0009] In any of the above amplifier circuits, the input capacitance of the first transistor and the capacitance of the third series capacitor may be equal. In any of the above amplifier circuits, the input capacitance of the second transistor and the capacitance of the fourth series capacitor may be equal.

[0010] In any of the above amplifier circuits, the unit amplifier may include a third parallel resistor connected in parallel with the third series capacitor. In any of the above amplifier circuits, the unit amplifier may include a fourth parallel resistor connected in parallel with the fourth series capacitor.

[0011] In any of the above amplifier circuits, the unit amplifier may include a first connection resistor connected to a third control terminal of the third transistor. In any of the above amplifier circuits, the unit amplifier may include a second connection resistor connected to a fourth control terminal of the fourth transistor.

[0012] In any of the above amplifier circuits, the unit amplifier may include a first connection capacitor connected to the third control terminal of the third transistor. In any of the above amplifier circuits, the unit amplifier may include a second connection capacitor connected to the fourth control terminal of the fourth transistor.

[0013] In any of the above amplifier circuits, the unit amplifier may include a first bypass resistor connected between the first control terminal and a first ground terminal of the first transistor. In any of the above amplifier circuits, the unit amplifier may include a second bypass resistor connected between the second control terminal and a second ground terminal of the second transistor.

[0014] In any of the above amplifier circuits, the third parallel resistor and the first bypass resistor may have the same resistance value. In any of the above amplifier circuits, the fourth parallel resistor and the second bypass resistor may have the same resistance value.

[0015] In any of the above amplifier circuits, the unit amplifier may include a fifth transistor connected between the first and fourth transistors and the first output transmission path, and a sixth transistor connected between the second and third transistors and the second output transmission path.

[0016] In any of the above amplifier circuits, the unit amplifier may include a third connection resistor connected to a fifth control terminal of the fifth transistor. In any of the above amplifier circuits, the unit amplifier may include a third connection capacitor connected to the fifth control terminal of the fifth transistor. In any of the above amplifier circuits, the unit amplifier may include a fourth connection resistor connected to a sixth control terminal of the sixth transistor. In any of the above amplifier circuits, the unit amplifier may include a fourth connection capacitor connected to the sixth control terminal of the sixth transistor.

[0017] In any of the above amplifier circuits, the unit amplifier may include a seventh transistor connected between the first transistor and the first output transmission path. In any of the above amplifier circuits, the unit amplifier may include an eighth transistor connected between the second transistor and the second output transmission path. In any of the above amplifier circuits, the unit amplifier may include a ninth transistor connected between the third transistor and the second output transmission path. In any of the above amplifier circuits, the unit amplifier may include a tenth transistor connected between the fourth transistor and the first output transmission path.

[0018] In any of the above amplifier circuits, the unit amplifier may include a fifth connection resistor connected to the seventh control terminal of the seventh transistor. In any of the above amplifier circuits, the unit amplifier may include a fifth connection capacitor connected to the seventh control terminal of the seventh transistor. In any of the above amplifier circuits, the unit amplifier may include a sixth connection resistor connected to the eighth control terminal of the eighth transistor. In any of the above amplifier circuits, the unit amplifier may include a sixth connection capacitor connected to the eighth control terminal of the eighth transistor. In any of the above amplifier circuits, the unit amplifier may include a seventh connection resistor connected to the ninth control terminal of the ninth transistor. In any of the above amplifier circuits, the unit amplifier may include a seventh connection capacitor connected to the ninth control terminal of the ninth transistor. In any of the above amplifier circuits, the unit amplifier may include an eighth connection resistor connected to the tenth control terminal of the tenth transistor. In any of the above amplifier circuits, the unit amplifier may include an eighth connection capacitor connected to the tenth control terminal of the tenth transistor.

[0019] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also be inventions. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a diagram illustrating an example of an amplifier circuit 100 according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing an example of a power amplifier stage 90. [Figure 3] FIG. 2 is a circuit diagram showing an example of a unit amplifier 200 in a comparative example. [Figure 4] 2 is a circuit diagram showing an example of a unit amplifier 20 according to an embodiment of the present invention. FIG. [Figure 5A] 4 is a small signal equivalent circuit diagram on the input side when the unit amplifier 200 of the comparative example shown in FIG. 3 is used. FIG. [Figure 5B] 4 is a small signal equivalent circuit diagram on the output side when the unit amplifier 200 of the comparative example shown in FIG. 3 is used. FIG. [Figure 6A] 5 is a small signal equivalent circuit diagram on the input side when the unit amplifier 20 of the embodiment shown in FIG. 4 is used. FIG. [Figure 6B] 5 is a small signal equivalent circuit diagram on the output side when the unit amplifier 20 of the embodiment shown in FIG. 4 is used. FIG. [Figure 7] FIG. 5 is a detailed circuit diagram of the unit amplifier 20 of the embodiment shown in FIG. 4. [Figure 8A] FIG. 10 is a circuit diagram showing a modified example of the unit amplifier 20 according to the embodiment. [Figure 8B] FIG. 2 is a circuit diagram showing an example of an RC circuit 50. [Figure 8C] 8B is a circuit diagram showing a specific example of the unit amplifier 20 of FIG. 8A. [Figure 8D] FIG. 8D is a detailed circuit diagram of the unit amplifier 20 shown in FIG. 8C. [Figure 9A] 8B is a circuit diagram showing a modified example of the unit constituent section 40 in the unit amplifier 20 shown in FIG. 8A. FIG. [Figure 9B] 9B is a detailed circuit diagram of the unit amplifier 20 including the unit constituent section 40 shown in FIG. 9A. FIG. [Figure 10A] FIG. 9 is a small signal equivalent circuit diagram on the input side when using the unit amplifier 20 of the embodiment shown in FIGS. 8A to 8D. [Figure 10B] FIG. 10 is a small signal equivalent circuit diagram on the input side when the unit amplifier 20 of the embodiment shown in FIG. 9A or 9B is used. [Figure 11A] FIG. 10 is a circuit diagram showing another modified example of the unit amplifier 20 according to the embodiment. [Figure 11B] FIG. 11B is a detailed circuit diagram of the unit amplifier 20 shown in FIG. 11A. [Figure 12A] FIG. 10 is a circuit diagram showing another modified example of the unit amplifier 20 according to the embodiment. [Figure 12B] FIG. 12B is a detailed circuit diagram of the unit amplifier 20 shown in FIG. 12A. [Figure 13A] FIG. 10 is a circuit diagram showing another modified example of the unit amplifier 20 according to the embodiment. [Figure 13B] FIG. 10 is a circuit diagram showing another modified example of the unit amplifier 20 according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. In this specification and drawings, elements having substantially the same function and configuration are designated by the same reference numerals to avoid redundant description, and elements not directly related to the present invention are not shown. Furthermore, in a single drawing, elements having the same function and configuration may be designated by the same reference numeral, and the reference numerals may be omitted for other elements.

[0022] In this specification, when we say "same" or "equal," it may include cases where there is an error due to manufacturing variations, etc. The error is, for example, within 10%.

[0023] FIG. 1 is a diagram illustrating an example of an amplifier circuit 100 according to an embodiment of the present invention. The amplifier circuit 100 amplifies and outputs an input signal. The amplifier circuit 100 may be a high-frequency differential amplifier. The amplifier circuit 100 in FIG. 1 is a fully differential amplifier that receives a differential signal and outputs a differential signal. In this specification, "differential" may mean that the signals differ in phase by 180°. However, this angle may include an error of about 5°. In FIG. 1, the phase of one signal in the differential signal is set to 0°, and the phase of the other signal is set to 180°.

[0024] As an example, the amplifier circuit 100 is provided between a signal generator and a device under test, such as a semiconductor device, in a test apparatus for testing the device under test, and amplifies a high-frequency test signal. The signal generator generates a test signal to be input to the device under test. However, the amplifier circuit 100 is not limited to use in test apparatuses, and may be used in a wide range of devices for amplifying high-frequency signals, such as optical modulator drivers and transceivers. High-frequency differential amplifiers are used in a variety of devices because they are advantageous for common-mode noise removal. The high frequency may be a frequency of 1 GHz or higher.

[0025] The amplifier circuit 100 includes a block 70. In this example, the block 70 has a gain amplifier stage 80 and a power amplifier stage 90. The gain amplifier stage 80 is primarily used to obtain gain. The gain amplifier stage 80 may be a variable gain amplifier. The power amplifier stage 90 is used to obtain the power of the output signal. That is, the gain amplifier stage 80 and the power amplifier stage 90 enable the entire block 70 to obtain gain and output power. Furthermore, by dividing the block 70 into the gain amplifier stage 80 and the power amplifier stage 90, the input capacitance of the block 70 is reduced, which facilitates the design of pre-stage circuits such as frequency converters. A distributed amplifier may be used for the power amplifier stage 90. Using a distributed amplifier makes it possible to achieve wideband operation and low input / output return loss.

[0026] 2 is a circuit diagram showing an example of a power amplifier stage 90. The power amplifier stage 90 in this example is a distributed amplifier. In this specification, a power amplifier stage 90 of a high-frequency differential amplifier that employs a distributed amplifier may be referred to as a high-frequency differential distributed amplifier. The power amplifier stage 90 in this example includes a differential input transmission line 12, a differential output transmission line 14, a termination circuit 18, and a unit amplifier 20.

[0027] The differential input transmission line 12 includes a first input transmission line 12-1 and a second input transmission line 12-2. An input signal is transmitted to the first input transmission line 12-1, and an input signal that is differential with respect to the first input transmission line 12-1 is transmitted to the second input transmission line 12-2. In Figure 2, the inductance component of the differential input transmission line 12 is represented by Lin.

[0028] The power amplifier stage 90 is provided with at least one unit amplifier 20 between the differential input transmission path 12 and the differential output transmission path 14. The power amplifier stage 90 of this example is provided with n unit amplifiers 20. The configuration of the unit amplifiers 20 will be described later. The n unit amplifiers 20 are provided in parallel with each other between the differential input transmission path 12 and the differential output transmission path 14. The n unit amplifiers 20 may have the same circuit configuration.

[0029] The differential output transmission path 14 includes a first output transmission path 14-1 and a second output transmission path 14-2. The first output transmission path 14-1 transmits an output signal generated by the unit amplifier 20, and the second output transmission path 14-2 transmits an output signal that is differential with respect to the first output transmission path 14-1. In Figure 2, the inductance component of the differential output transmission path 14 is represented by Lout.

[0030] The input signals transmitted through the differential input transmission line 12 are sequentially input to the unit amplifier 20 closest to the input terminal. The circuit parameters are set so that the signals output from each unit amplifier 20 are in phase on the differential output transmission line 14. As a result, the signals output from each unit amplifier 20 are combined on the differential output transmission line 14, and the current is amplified.

[0031] The termination circuits 18 are provided at the ends of the differential input transmission path 12 and the differential output transmission path 14. The characteristic impedance of the termination circuit 18 may be set to be equal to the characteristic impedance of the unit amplifier 20. By providing the termination circuit 18, signals can be transmitted without reflection on each transmission path. As will be described later, the termination circuit 18 may be a circuit in which a resistor and a capacitor are connected in series, or may be an inductance, or may be a transistor. However, the termination circuit 18 does not necessarily have to be provided.

[0032] 3 is a circuit diagram showing an example of a unit amplifier 200 in the comparative example. The unit amplifier 200 of this example has a first transistor Tr1, a second transistor Tr2, and a current source 30. The first transistor Tr1 and the second transistor Tr2 are connected in parallel to the common current source 30.

[0033] The first transistor Tr1 has a first control terminal 21. In this example, the first transistor Tr1 is a bipolar transistor, and the first control terminal 21 is a base terminal. The first transistor Tr1 receives a first input signal Si1 from the first input transmission line 12-1 at the first control terminal 21, and generates a first output signal So1. The first output signal So1 is transmitted to the first output transmission line 14-1.

[0034] The second transistor Tr2 also has a second control terminal 22. In this example, the second transistor Tr2 is also a bipolar transistor, and the second control terminal 22 is a base terminal. A second input signal Si2, which is differential with respect to the first input signal Si1, is input to the second control terminal 22 of the second transistor Tr2 from the second input transmission line 12-2, and the second transistor Tr2 generates a second output signal So2, which is differential with respect to the second input signal Si2. The second output signal So2 is transmitted to the second output transmission line 14-2.

[0035] The half circuit of a high frequency differential distributed amplifier is equivalent to a single phase distributed amplifier. Therefore, the characteristics of both can be expressed by the same equation. The formula for the output power Po of a single phase distributed amplifier is shown below.

number

[0036] The output current Io can be simply expressed by the following formula.

number

[0037] Next, a simple formula for the cutoff frequency fc of a distributed amplifier is shown below.

number

[0038] From equations (1) and (2), it is necessary to increase the transistor size in order to increase the output power Po. However, increasing the transistor size also increases the input capacitance Cin, which, from equation (3), results in a decrease in the cutoff frequency fc. In other words, there is a trade-off between the output power and cutoff frequency of a high-frequency differential distributed amplifier.

[0039] FIG. 4 is a circuit diagram showing an example of a unit amplifier 20 in an embodiment of the present invention. The unit amplifier 20 of this example has a first transistor Tr1, a second transistor Tr2, a third transistor Tr3, a fourth transistor Tr4, a first current source 30-1, and a second current source 30-2. Each transistor has a control terminal, as in FIG. 3. Each transistor of this example is a current-driven bipolar transistor, but is not limited to this. Each transistor Tr1 to Tr4 may also be a voltage-driven element such as a MOSFET.

[0040] The first transistor Tr1 receives a first input signal Si1 from the first input transmission line 12-1 at its first control terminal 21 and generates a first output signal So1. The second transistor Tr2 receives a second input signal Si2 from the second input transmission line 14-2 at its second control terminal 22 and generates a second output signal So2 that is differential with respect to the first output signal So1. The first input signal Si1 and the second input signal Si2 are differential signals. In this example, each signal is a current, but may also be a voltage.

[0041] The third transistor Tr3 is provided in parallel with the first transistor Tr1 and generates a third output signal So3 that is differential with respect to the first output signal So1. The third transistor Tr3 and the first transistor Tr1 are connected in parallel with each other to a common first current source 30-1.

[0042] The fourth transistor Tr4 is connected in parallel to the second transistor Tr2 and generates a fourth output signal So4 that is differential with the second output signal So2. The fourth transistor Tr4 and the second transistor Tr2 are connected in parallel to a common second current source 30-2. The first current source 30-1 and the second current source 30-2 are connected in parallel to each other.

[0043] In the unit amplifier 20 of this example, the first output signal So1 and the fourth output signal So4 are joined together and output to the first output transmission path 14-1. Similarly, the second output signal So2 and the third output signal So3 are joined together and output to the second output transmission path 14-2.

[0044] Because the first input signal Si1 and the second input signal Si2 are differential signals, when the first transistor Tr1 is on, the second transistor Tr2 is off. In this specification, the state in which current flows through each transistor is referred to as on, and the state in which no current flows through each transistor is referred to as off. Because the fourth transistor Tr4 and the second transistor Tr2 are connected to a common second current source 30-2, when the second transistor Tr2 is off (the second output signal So2 is zero), the fourth output signal So4 flows through the fourth transistor Tr4. As a result, when the first transistor Tr1 is on, the first output signal So1 and the fourth output signal So4 are generated simultaneously, and the current of the signal output to the first output transmission line 14-1 increases (So1 + So4). The same is true for the signal output to the second output transmission line 14-2 (So2 + So3). In other words, the output current Io in equation (1) increases, and the output power Po can be increased.

[0045] The third control terminal 23 of the third transistor Tr3 and the fourth control terminal 24 of the fourth transistor Tr4 are not connected to the differential input transmission path 12, and may receive signals different from the first input signal Si1 and the second input signal Si2. In this example, the bias signal Iref is input to the third control terminal 23 and the fourth control terminal 24 without passing through the differential input transmission path 12. The bias signal Iref may be a signal exhibiting a constant value. The bias signal Iref may be a current or a voltage. In this example, the bias signal Iref is a constant current. When the first transistor Tr1 is on, the third transistor Tr3 is also capable of passing current. However, due to the large current from the first transistor Tr1, almost no current flows through the third transistor Tr3, and the third transistor Tr3 is turned off. Similarly, when the second transistor Tr2 is on, the fourth transistor Tr4 is also capable of passing current. However, due to the large current from the second transistor Tr2, almost no current flows through the fourth transistor Tr4, and the fourth transistor Tr4 is turned off.

[0046] The input capacitance (base-emitter capacitance Cπ in this example) of the third transistor Tr3 and the fourth transistor Tr4 is not connected to the differential input transmission path 12. For this reason, the input capacitance Cin (see equation (3)) of the unit amplifier 20 shown in FIG. 4 remains the same as that of the unit amplifier 200 shown in FIG. 3, and the cutoff frequency fc does not decrease. In other words, the unit amplifier 20 of this example can improve the trade-off between output power Po and cutoff frequency fc. The characteristics of each of the transistors Tr1 to Tr4, such as size (channel width) and input capacitance, may be the same as one another.

[0047] 5A is a small-signal equivalent circuit diagram on the input side when the unit amplifier 200 of the comparative example shown in FIG. 3 is used. FIG. 5A shows the input capacitance Cin of the unit amplifier 200. While FIG. 5A shows the first input transmission line 12-1 side, the second input transmission line 12-2 side may be similar. In FIG. 5A, the unit amplifier 200 includes an inductance component Lin of the first input transmission line 12-1. Furthermore, the termination circuit 18 of this example has a resistor and a capacitor connected in series.

[0048] Fig. 5B is a small-signal equivalent circuit diagram on the output side when using the unit amplifier 200 of the comparative example shown in Fig. 3. Fig. 5B shows the mutual inductance gm of the transistors of the unit amplifier 200, the output capacitance Cout appearing on the output side, and the output resistance Rout appearing on the output side. In Fig. 5B, the unit amplifier 200 includes the inductance component Lout of the differential output transmission path 14. The termination circuit 18 of this example also has a resistor and capacitor connected in series.

[0049] Figure 6A is a small-signal equivalent circuit diagram on the input side when using the unit amplifier 20 of the embodiment shown in Figure 4. The symbols in Figure 6A are the same as those in Figure 5A. As described above, the third control terminal 23 of the third transistor Tr3 and the fourth control terminal 24 of the fourth transistor Tr4 are not connected to the differential input transmission path 12, so the input capacitance Cin remains the same as in the case of Figure 5A.

[0050] FIG. 6B is a small-signal equivalent circuit diagram on the output side when using the unit amplifier 20 of the embodiment shown in FIG. 4. The symbols in FIG. 6B are the same as those in FIG. 5B. Because the unit amplifier 20 of the embodiment includes a third transistor Tr3 and a fourth transistor Tr4, the mutual inductance gm of the transistors included in the unit amplifier 20 is twice (2gm) compared to the unit amplifier 200 of the comparative example. In other words, the output power can be doubled while maintaining the cutoff frequency fc. Note that in FIG. 6B, the output resistance Rout is halved and the output capacitance Cout is doubled compared to FIG. 5B. However, as described above, the input capacitance Cin is the dominant term relative to the cutoff frequency fc, so the effects of these factors can be ignored.

[0051] Figure 7 is a detailed circuit diagram of the unit amplifier 20 of the embodiment shown in Figure 4. Description of the same configuration as in Figure 4 will be omitted. The unit amplifier 20 of this example has a first series resistor R01, a first series capacitor C01, and a first parallel resistor R11.

[0052] The first series resistor R01 is connected in series with the third control terminal 23 of the third transistor Tr3. The first series capacitor C01 is connected in series with the first series resistor R01 between the first series resistor R01 and the ground terminal. The first parallel resistor R11 is provided in parallel with the first series capacitor C01 and receives the bias signal Iref. The first parallel resistor R11 may be connected in series with the first series resistor R01.

[0053] This allows the high-frequency signal to flow to the first series capacitor C01 side, shielding the terminal to which the bias signal Iref is input. The resistance value of the first parallel resistor R11 may be greater than the resistance value of the first series resistor R01.

[0054] The unit amplifier 20 may further include a second series resistor R02, a second series capacitor C02, and a second parallel resistor R12. In this example, the second series resistor R02 is connected in series with the fourth control terminal 24 of the fourth transistor Tr4. The second series capacitor C02 is connected in series with the second series resistor R02 between the second series resistor R02 and the ground terminal. The second parallel resistor R12 is provided in parallel with the second series capacitor C02 and receives the bias signal Iref. The second parallel resistor R12 may be connected in series with the second series resistor R02.

[0055] This allows the high frequency signal to flow to the second series capacitor C02 side, shielding the terminal to which the bias signal Iref is input. The resistance value of the second parallel resistor R12 may be greater than the resistance value of the second series resistor R02.

[0056] 8A is a circuit diagram showing a modified example of the unit amplifier 20 according to the embodiment. The unit amplifier 20 of this example has a unit component section 40 and an RC circuit 50. The unit component section 40 may include either the unit amplifier 20 shown in FIG. 4 or the unit amplifier 20 shown in FIG. 7.

[0057] The unit amplifier 20 of this example has four RC circuits 50. A first input signal Si1 is input to the RC circuit 50-1 from the first input transmission line 12-1. A second input signal Si2 is input to the RC circuit 50-2 from the second input transmission line 12-1. A bias signal Iref is input to the RC circuits 50-3 and 50-4.

[0058] 8B is a circuit diagram showing an example of the RC circuit 50. The RC circuit 50 has a resistor Rg and a capacitor Cg connected in parallel.

[0059] FIG. 8C is a circuit diagram showing a specific example of unit amplifier 20 of FIG. 8A. Unit component 40 of this example has the same structure as unit amplifier 20 shown in FIG. 4. Description of components similar to those in FIG. 4 will be omitted. Unit amplifier 20 of this example has third series capacitor C03 and fourth series capacitor C04. Third series capacitor C03 is included in RC circuit 50-1, and fourth series capacitor C04 is included in RC circuit 50-2.

[0060] The third series capacitor C03 is connected in series with the first control terminal 21 of the first transistor Tr1. The fourth series capacitor C04 is connected in series with the second control terminal 22 of the second transistor Tr2. When capacitances are connected in series, the combined capacitance becomes small. In this example, the combined capacitance of the input capacitance of the first transistor Tr1 (e.g., the base-emitter capacitance Cπ) and the third series capacitor C03 becomes the input capacitance Cin of the unit amplifier 20, and therefore the input capacitance Cin becomes small. As a result, it is possible to increase the size of the first transistor Tr1 while maintaining the cutoff frequency fc, or to increase the number of unit amplifiers 20. The same applies to the second transistor Tr2 and the fourth series capacitor C04.

[0061] The input capacitance of the first transistor Tr1 may be equal to the capacitance of the third series capacitor C03. Similarly, the input capacitance of the second transistor Tr2 may be equal to the capacitance of the fourth series capacitor C04. From the equation for the combined capacitance when the capacitances are connected in series, the above relationship indicates that the combined capacitance is smallest. In other words, the input capacitance Cin can be minimized.

[0062] The unit amplifier 20 may further include a third parallel resistor R13 and a fourth parallel resistor R14. The third parallel resistor R13 is connected in parallel with the third series capacitor C03. The fourth parallel resistor R14 is connected in parallel with the fourth series capacitor C04. A first input signal Si1 is input to the ends of the third parallel resistor R13 and the third series capacitor C03 opposite the first control terminal 21. A second input signal Si2 is input to the ends of the fourth parallel resistor R14 and the fourth series capacitor C04 opposite the second control terminal 22.

[0063] Because capacitors do not transmit DC (direct current) signals, the third series capacitor C03 does not transmit the first DC input signal Si1, and the fourth series capacitor C04 does not transmit the second DC input signal Si2. By further providing a third parallel resistor R13 and a fourth parallel resistor R14, DC input signals can be transmitted.

[0064] The impedance of the third parallel resistor R13 at a high frequency among the operating frequencies (for example, the upper limit of the operating frequencies specified in the specifications) may be 10 or more times, 100 or more times, or 1000 or more times greater than the impedance of the third series capacitor C03. The impedance of the fourth parallel resistor R14 at a high frequency among the operating frequencies may be 10 or more times, 100 or more times, or 1000 or more times greater than the impedance of the fourth series capacitor C04. The high frequency may be 1 GHz, 10 GHz, 20 GHz, or 100 GHz or greater.

[0065] The unit amplifier 20 may further include a first connection resistor R21 and a second connection resistor R22. The first connection resistor R21 is connected to a third control terminal 23 of the third transistor Tr3. The second connection resistor R22 is connected to a fourth control terminal 24 of the fourth transistor Tr4. This improves the circuit imbalance in each of the transistors Tr1 to Tr4, thereby improving the characteristics.

[0066] The unit amplifier 20 may further include a first connection capacitor C21 and a second connection capacitor C22. The first connection capacitor C21 is connected to the third control terminal 23 of the third transistor Tr3. The second connection capacitor C22 is connected to the fourth control terminal 24 of the fourth transistor Tr4. This improves the circuit imbalance in each of the transistors Tr1 to Tr4, thereby improving the characteristics.

[0067] In this example, the first connection resistor R21 and the first connection capacitor C21 are connected in parallel between the third control terminal 23 and the terminal to which the bias signal Iref is input. In this example, the second connection resistor R22 and the second connection capacitor C22 are connected in parallel between the fourth control terminal 24 and the terminal to which the bias signal Iref is input. The third parallel resistor R13 and the third series capacitor C03 correspond to the RC circuit 50-1, the fourth parallel resistor R14 and the fourth series capacitor C04 correspond to the RC circuit 50-2, the first connection resistor R21 and the first connection capacitor C21 correspond to the RC circuit 50-3, and the second connection resistor R22 and the second connection capacitor C22 correspond to the RC circuit 50-4.

[0068] Figure 8D is a detailed circuit diagram of the unit amplifier 20 shown in Figure 8C. Description of components similar to those in Figure 8C will be omitted. The unit amplifier 20 of this example has a first additional capacitor C41, a first additional resistor R41, a second additional resistor R42, a second additional capacitor C42, a third additional resistor R43, and a fourth additional resistor R44.

[0069] The first additional capacitor C41 and the first additional resistor R41 are connected in series between the first connecting resistor R21 and the ground terminal, and between the first connecting capacitor C21 and the ground terminal. The second additional resistor R42 is connected in parallel with the first additional capacitor C41 and the first additional resistor R41, and receives the bias signal Iref. The resistance of the second additional resistor R42 may be greater than the resistances of the first connecting resistor R21 and the first additional resistor R41. This allows the high-frequency signal to flow to the first additional capacitor C41 side, shielding the terminal to which the bias signal Iref is input.

[0070] The second additional capacitor C42 and the third additional resistor R43 are connected in series between the second connecting resistor R22 and the second connecting capacitor C22 and the ground terminal. The fourth additional resistor R44 is connected in parallel with the second additional capacitor C42 and the third additional resistor R43 and receives the bias signal Iref. The resistance of the fourth additional resistor R44 may be greater than the resistances of the second connecting resistor R22 and the third additional resistor R43. This allows the high-frequency signal to flow to the second additional capacitor C42 side, shielding the terminal to which the bias signal Iref is input.

[0071] Figure 9A is a circuit diagram showing a modified example of unit component 40 in unit amplifier 20 shown in Figure 8A. Unit amplifier 20 of this example differs from the other modified examples in that unit component 40 is provided with a first bypass resistor R31 and a second bypass resistor R32.

[0072] The first bypass resistor R31 is connected between the first control terminal 21 of the first transistor Tr1 and the first ground terminal 61. The second bypass resistor R32 is connected between the second control terminal 22 of the second transistor Tr2 and the second ground terminal 62. The ground terminal may be the emitter terminal or the source terminal of the transistor.

[0073] The unit amplifier 20 may include a third bypass resistor R33 and a fourth bypass resistor R34 in the unit component 40. In this example, the third bypass resistor R33 is connected between the third control terminal 23 and the third ground terminal 63 of the third transistor Tr3. The fourth bypass resistor R34 is connected between the fourth control terminal 24 and the fourth ground terminal 64 of the fourth transistor Tr4.

[0074] FIG. 9B is a detailed circuit diagram of a unit amplifier 20 including the unit component 40 shown in FIG. 9A. The unit amplifier 20 of this example has a configuration that combines the circuit configuration shown in FIG. 8D with the unit component 40 shown in FIG. 9A. The circuit configurations shown in FIGS. 8A to 8D and the circuit configuration shown in FIG. 9A may be combined in any manner. For example, a first bypass resistor R31 and a second bypass resistor R32 may be provided in the unit component 40 of a unit amplifier 20 that has a third series capacitor C03, a third parallel resistor R13, a fourth series capacitor C04, and a fourth parallel capacitor R14.

[0075] Figure 10A is a small-signal equivalent circuit diagram on the input side when using unit amplifier 20 of the embodiment shown in Figures 8A to 8D. Description of configurations similar to those in Figures 5A and 6A will be omitted. Unit amplifier 20 of this example has third series capacitor C03 and third parallel resistor R13, and these circuit elements appear on the input side.

[0076] As mentioned above, the capacitance of the third series capacitor C03 is often set to the same value as the input capacitance Cin of the first transistor. At high frequencies, the impedance of the third series capacitor C03 is sufficiently smaller than the impedance of the third parallel resistor R13, making the third parallel resistor R13 negligible. In this case, the third series capacitor C03 and the input capacitance Cin of the first transistor are connected in series, so the voltage of the input signal Si1 is divided in half and applied to the third series capacitor C03 and the input capacitance Cin of the first transistor.

[0077] On the other hand, at low frequencies (e.g., MHz or less), the impedance of the third series capacitor C03 is significantly greater than the impedance of the third parallel resistor R13. Therefore, due to the voltage division relationship, the voltage applied to the input capacitance Cin of the first transistor increases. In other words, the value of the input voltage applied to the input capacitance Cin of the first transistor changes between low and high frequencies, degrading the gain flatness of the amplifier. In other words, the lower limit of the operating frequency is determined by the impedance of the RC circuit 50.

[0078] FIG. 10B is a small-signal equivalent circuit diagram on the input side when using the unit amplifier 20 of the embodiment shown in FIG. 9A or 9B. The unit amplifier 20 of this example includes a bypass resistor R31, forming a series connection of RC parallel circuits. The resistance values ​​of the third parallel resistor R13 and the first bypass resistor R31 may be equal. In this case, even at low frequencies, the voltage of the input signal Si1 is divided in half and applied to the third parallel resistor R13 and the first bypass resistor R31, improving gain flatness. In other words, the effects of providing the RC circuit 50 can be obtained from DC (0 Hz).

[0079] The second input transmission line 12-2 may have a similar configuration. That is, the resistance value of the fourth parallel resistor R14 may be equal to the resistance value of the second bypass resistor R32. This provides the same effect as described above. Furthermore, the resistance values ​​of the third bypass resistor R33 and the fourth bypass resistor R34 may also be equal to the resistance values ​​of the first bypass resistor R31 and the second bypass resistor R32. This improves the circuit imbalance in each transistor, thereby improving the characteristics.

[0080] 11A is a circuit diagram showing another modified example of the unit amplifier 20 according to the embodiment. The unit amplifier 20 of this example differs from the unit amplifier 20 of FIG. 4 in that it includes a fifth transistor Tr5 and a sixth transistor Tr6.

[0081] The fifth transistor Tr5 is connected between the first transistor Tr1 and the fourth transistor Tr4 and the first output transmission line 14-1. The sixth transistor Tr6 is connected between the second transistor Tr2 and the third transistor Tr3 and the second output transmission line 14-2. This reduces the influence of the Miller effect, allowing the operating frequency to be expanded to higher frequencies.

[0082] In this example, a first bias signal Iref_1 is input to the third control terminal 23 of the third transistor Tr3 and the fourth control terminal 24 of the fourth transistor Tr4. The first bias signal Iref_1 may be the same as the bias signal Iref shown in FIG. 4, etc. In this example, a second bias signal Iref_2 is input to the fifth control terminal 25 of the fifth transistor Tr5 and the sixth control terminal 26 of the sixth transistor Tr6. The second bias signal Iref_2 may be a signal indicating a constant value. The second bias signal Iref_2 may be a current or a voltage. In this example, the second bias signal Iref_2 is a constant current. The second bias signal Iref_2 may be the same as the first bias signal Iref_1.

[0083] Fig. 11B is a detailed circuit diagram of the unit amplifier 20 shown in Fig. 11A. The unit amplifier 20 of this example further includes a third connection resistor R23, a third connection capacitor C23, a fourth connection resistor R24, and a fourth connection capacitor C24.

[0084] The third connection resistor R23 is connected to the fifth control terminal 25 of the fifth transistor Tr5. The second bias signal Iref_2 may be input to the other end of the third connection resistor R23. The third connection capacitor C23 is connected to the fifth control terminal 25 of the fifth transistor Tr5. The other end of the third connection capacitor C23 may be connected to the ground terminal. This allows the high-frequency signal to flow to the third connection capacitor C23 side, and shields the terminal to which the second bias signal Iref_2 is input.

[0085] The fourth connection resistor R24 ​​is connected to the sixth control terminal 26 of the sixth transistor Tr6. The second bias signal Iref_2 may be input to the other end of the fourth connection resistor R24. The fourth connection capacitor C24 is connected to the sixth control terminal 26 of the sixth transistor Tr6. The other end of the fourth connection capacitor C24 may be connected to the ground terminal. This allows the high-frequency signal to flow to the fourth connection capacitor C24 side, and shields the terminal to which the second bias signal Iref_2 is input.

[0086] 7, the unit amplifier 20 may include a first series resistor R01, a first series capacitor C01, a first parallel resistor R11, a second series resistor R02, a second series capacitor C02, and a second parallel resistor R12. In this case, a first bias signal Iref_1 may be input to the first parallel resistor R11 and the second parallel resistor R12.

[0087] 12A is a circuit diagram showing another modified example of the unit amplifier 20 according to the embodiment. The unit amplifier 20 of this example differs from the unit amplifier 20 of FIG. 4 in that it includes a seventh transistor Tr7, an eighth transistor Tr8, a ninth transistor Tr9, and a tenth transistor Tr10.

[0088] The seventh transistor Tr7 is connected between the first transistor Tr1 and the first output transmission path 14-1. The eighth transistor Tr8 is connected between the second transistor Tr2 and the second output transmission path 14-2. The ninth transistor Tr9 is connected between the third transistor Tr3 and the second output transmission path 14-2. The tenth transistor Tr10 is connected between the fourth transistor Tr4 and the first output transmission path 14-1.

[0089] This configuration also reduces the influence of the Miller effect, allowing the operating frequency to be extended to higher frequencies.A second bias signal Iref_2 may be input to a seventh control terminal 27 of the seventh transistor Tr7, an eighth control terminal 28 of the eighth transistor Tr8, a ninth control terminal 29 of the ninth transistor Tr9, and a tenth control terminal 31 of the tenth transistor Tr10.

[0090] Figure 12B is a detailed circuit diagram of the unit amplifier 20 shown in Figure 12A. The unit amplifier 20 of this example further includes a fifth connection resistor R25, a fifth connection capacitor C25, a sixth connection resistor R26, a sixth connection capacitor C26, a seventh connection resistor R27, a seventh connection capacitor C27, an eighth connection resistor R28, and an eighth connection capacitor C28.

[0091] The fifth connection resistor R25 is connected to the seventh control terminal 27 of the seventh transistor Tr7. The second bias signal Iref_2 may be input to the other end of the fifth connection resistor R25. The fifth connection capacitor C25 is connected to the seventh control terminal 27 of the seventh transistor Tr7. The other end of the fifth connection capacitor C25 may be connected to the ground terminal.

[0092] The sixth connection resistor R26 is connected to the eighth control terminal 28 of the eighth transistor Tr8. The second bias signal Iref_2 may be input to the other end of the sixth connection resistor R26. The sixth connection capacitor C26 is connected to the eighth control terminal 28 of the eighth transistor Tr8. The other end of the sixth connection capacitor C26 may be connected to the ground terminal.

[0093] The seventh connection resistor R27 is connected to the ninth control terminal 29 of the ninth transistor Tr9. The second bias signal Iref_2 may be input to the other end of the seventh connection resistor R27. The seventh connection capacitor C27 is connected to the ninth control terminal 29 of the ninth transistor Tr9. The other end of the seventh connection capacitor C27 may be connected to the ground terminal.

[0094] The eighth connection resistor R28 is connected to the tenth control terminal 31 of the tenth transistor Tr10. The second bias signal Iref_2 may be input to the other end of the eighth connection resistor R28. The eighth connection capacitor C28 is connected to the tenth control terminal 31 of the tenth transistor Tr10. The other end of the eighth connection capacitor C28 may be connected to the ground terminal. This allows the high-frequency signal to flow to each connection capacitor side, and shields the terminal to which the second bias signal Iref_2 is input.

[0095] 7, the unit amplifier 20 may include a first series resistor R01, a first series capacitor C01, a first parallel resistor R11, a second series resistor R02, a second series capacitor C02, and a second parallel resistor R12. In this case, a first bias signal Iref_1 may be input to the first parallel resistor R11 and the second parallel resistor R12.

[0096] FIG. 13A is a circuit diagram showing another modified example of the unit amplifier 20 according to the embodiment. The modified examples shown in FIGS. 8A to 8D and the modified examples shown in FIGS. 11A and 11B may be combined in any manner. For example, the unit amplifier 20 shown in FIG. 11A or 11B may be used for the unit component 40 of FIG. 8A. The combination shown in FIG. 13A may also be used. This allows the effects of each modified example to be obtained. Note that in each combination, the bypass resistors shown in FIGS. 9A and 9B may be provided.

[0097] FIG. 13B is a circuit diagram showing another modified example of the unit amplifier 20 according to the embodiment. The modified examples shown in FIGS. 8A to 8D and the modified examples shown in FIGS. 12A and 12B may be combined in any manner. For example, the unit amplifier 20 shown in FIG. 12A or 12B may be used for the unit component 40 of FIG. 8A. The combination shown in FIG. 13B may also be used. This allows the effects of each modified example to be obtained. Note that in each combination, the bypass resistors shown in FIGS. 9A and 9B may be provided.

[0098] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included within the technical scope of the present invention. [Explanation of symbols]

[0099] 12...differential input transmission path, 14...differential output transmission path, 18...termination circuit, 20...unit amplifier, 21...first control terminal, 22...second control terminal, 23...third control terminal, 24...fourth control terminal, 25...fifth control terminal, 26...sixth control terminal, 27...seventh control terminal, 28...eighth control terminal, 29...ninth control terminal, 30...current source, 31...tenth control terminal, 40...unit component, 50...RC circuit, 61...first ground terminal, 62...second ground terminal, 63...third ground terminal, 64...fourth ground terminal, 70...block, 80...gain amplifier stage, 90...power amplifier stage, 100...amplifier circuit, 200...unit amplifier

Claims

1. a differential input transmission path including a first input transmission path and a second input transmission path; a differential output transmission path including a first output transmission path and a second output transmission path; at least one unit amplifier provided between the differential input transmission path and the differential output transmission path; Equipped with The unit amplifier includes: a first transistor that receives a first input signal from the first input transmission line at a first control terminal and generates a first output signal; a second transistor receiving a second input signal from the second input transmission line at a second control terminal and generating a second output signal that is differential with the first output signal; a third transistor disposed in parallel with the first transistor and configured to generate a third output signal that is differential with respect to the first output signal; a fourth transistor provided in parallel with the second transistor and generating a fourth output signal that is differential with respect to the second output signal; and The first output signal and the fourth output signal are combined and output to the first output transmission path, and the second output signal and the third output signal are combined and output to the second output transmission path. Amplification circuit.

2. A bias signal is input to the third control terminal of the third transistor and the fourth control terminal of the fourth transistor without passing through the differential input transmission line.

2. The amplifier circuit according to claim 1.

3. The unit amplifier includes: a first series resistor connected in series with the third control terminal of the third transistor; a first series capacitor connected in series with the first series resistor between the first series resistor and a ground terminal; a first parallel resistor provided in parallel with the first series capacitor and receiving the bias signal; The amplifier circuit of claim 2 further comprising:

4. The unit amplifier includes: a second series resistor connected in series with the fourth control terminal of the fourth transistor; a second series capacitor connected in series with the second series resistor between the second series resistor and a ground terminal; a second parallel resistor provided in parallel with the second series capacitor and receiving the bias signal; The amplifier circuit of claim 2 further comprising:

5. The unit amplifier includes: a third series capacitor connected in series with the first control terminal of the first transistor; a fourth series capacitor connected in series with the second control terminal of the second transistor; Further provided with 5. The amplifier circuit according to claim 1.

6. the input capacitance of the first transistor is equal to the capacitance of the third series capacitor, The input capacitance of the second transistor is equal to the capacitance of the fourth series capacitor.

6. The amplifier circuit according to claim 5.

7. The unit amplifier includes: a third parallel resistor connected in parallel with the third series capacitor; a fourth parallel resistor connected in parallel with the fourth series capacitor; The amplifier circuit of claim 6 further comprising:

8. The unit amplifier includes: a first connection resistor connected to a third control terminal of the third transistor; a second connection resistor connected to the fourth control terminal of the fourth transistor; The amplifier circuit of claim 7 further comprising:

9. The unit amplifier includes: a first connecting capacitor connected to the third control terminal of the third transistor; a second connecting capacitor connected to the fourth control terminal of the fourth transistor; The amplifier circuit of claim 8 further comprising:

10. The unit amplifier includes: a first bypass resistor connected between the first control terminal and a first ground terminal of the first transistor; a second bypass resistor connected between the second control terminal and a second ground terminal of the second transistor; The amplifier circuit of claim 7 further comprising:

11. a resistance value of the third parallel resistor and a resistance value of the first bypass resistor are equal, The resistance value of the fourth parallel resistor and the resistance value of the second bypass resistor are equal. The amplifier circuit according to claim 10.

12. The unit amplifier includes: a fifth transistor connected between the first transistor and the first output transmission path, and between the fourth transistor and the first output transmission path; a sixth transistor connected between the second transistor and the third transistor and the second output transmission line; The amplifier circuit according to claim 1 , further comprising:

13. The unit amplifier includes: a third connection resistor connected to a fifth control terminal of the fifth transistor; a third connecting capacitor connected to the fifth control terminal of the fifth transistor; a fourth connection resistor connected to a sixth control terminal of the sixth transistor; a fourth connecting capacitor connected to the sixth control terminal of the sixth transistor; The amplifier circuit of claim 12 further comprising:

14. The unit amplifier includes: a seventh transistor connected between the first transistor and the first output transmission path; an eighth transistor connected between the second transistor and the second output transmission path; a ninth transistor connected between the third transistor and the second output transmission path; a tenth transistor connected between the fourth transistor and the first output transmission path; The amplifier circuit according to claim 1 , further comprising:

15. The unit amplifier includes: a fifth connection resistor connected to a seventh control terminal of the seventh transistor; a fifth connecting capacitor connected to the seventh control terminal of the seventh transistor; a sixth connection resistor connected to an eighth control terminal of the eighth transistor; a sixth connecting capacitor connected to the eighth control terminal of the eighth transistor; a seventh connection resistor connected to the ninth control terminal of the ninth transistor; a seventh connection capacitor connected to the ninth control terminal of the ninth transistor; an eighth connection resistor connected to a tenth control terminal of the tenth transistor; an eighth connecting capacitor connected to the tenth control terminal of the tenth transistor; The amplifier circuit of claim 14 further comprising:

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