Pixel circuit, driving method, display substrate, display panel, and display device

Abstract

A pixel circuit, a driving method, a display substrate, a display panel and a display device are provided. The pixel circuit includes a light-emitting element, a driving circuit, a first light-emitting control circuit, a first control circuit and a second control circuit; the first control circuit provides a first control voltage to the second control node under the control of a first reset control signal, and controls the first light-emitting control line to provide a first light-emitting control signal to the first control node under the control of the potential of the second control node; the second control circuit writes a second control voltage to a third control node under the control of a second reset control signal, and controls the second light-emitting control line to provide a second light-emitting control signal to the first control node under the control of the potential of the third control node. The present disclosure solves the column-wise defect of the original pixel circuit.

Description

CROSS REFERENCE OF RELATED APPLICATION

[0001] This application claims priority to PCT application with filing date of March 31, 2023 and application number PCT / CN2023 / 085358.TECHNICAL FIELD

[0002] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, a display substrate, a display panel and a display device.BACKGROUND

[0003] The related pixel circuit including a micro light-emitting diode or a mini light-emitting diode adopts a first data line and a second data line, wherein the first data line is configured to provide a light-emitting time data voltage, and the second data line is configured to provide a display data voltage, and the first data line and the second data line are arranged between two columns of pixel circuits, so that the number of side signals is large, and due to the coupling influence of the signal on the first data line and the signal on the second data line in the charging compensation stage, the voltage jump caused by the display data voltage in the charging compensation stage will cause column-wise defects in the related pixel circuit.SUMMARY

[0004] TIn one aspect, an embodiment of the present disclosure provides a pixel circuit, including a light-emitting element and a pixel driving circuit; the pixel driving circuit includes a driving circuit, a first light-emitting control circuit, a first control circuit, a second control circuit and a data writing circuit;

[0005] The driving circuit is configured to generate a driving current for driving the light-emitting element; the first light-emitting control circuit is electrically connected to the first control node, the first end of the driving circuit and the light-emitting element respectively, and is configured to control the connection between the first end of the driving circuit and the light-emitting element under the control of the potential of the first control node; the first control circuit is electrically connected to the data line, the first reset control line, the first light-emitting control line, the first control node and the second control node respectively, and is configured to provide the first control voltage provided by the data line to the second control node under the control of the first reset control signal provided by the first reset control line, and control the first light-emitting control line to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node; the second control circuit is electrically connected to the data line, the second reset control line, the second light-emitting control line, the first control node and the third control node respectively, and is configured to write the second control voltage provided by the data line into the third control node under the control of the second reset control signal provided by the second reset control line, and control the second light-emitting control line to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node; the data writing circuit is electrically connected to the scan line, the data line and the second end of the driving circuit respectively, and is configured to write the display data voltage provided by the data line into the second end of the driving circuit under the control of the scan signal provided by the scan line; the first control circuit, the second control circuit and the data writing circuit are configured to access the corresponding voltage signals on the data line in a time-sharing manner; the pulse width of the scanning signal, the pulse width of the first reset control signal and the pulse width of the second reset control signal are the same; or at least two of the pulse width of the scanning signal, the pulse width of the first reset control signal and the pulse width of the second reset control signal are different.

[0006] Optionally, the scan line, the first reset control line and the second reset control line are respectively electrically connected to different GOA circuits in the same GOA module, and are respectively connected to driving signals provided by the different GOA circuits; or, the scanning line, the first reset control line, and the second reset control line are respectively electrically connected to a GOA circuit in different GOA modules, and respectively access the driving signals provided by the GOA circuit in the GOA modules; or, two of the scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits in the first GOA module, and are respectively connected to driving signals provided by different GOA circuits in the first GOA module; the other of the scan line, the first reset control line, and the second reset control line is electrically connected to a GOA circuit in the second GOA module, and is connected to a driving signal provided by a GOA circuit in the second GOA module.

[0007] Optionally, the first control circuit includes a first writing control circuit, a first energy storage circuit and a second writing control circuit; the first writing control circuit is electrically connected to the first reset control line, the data line and the second control node respectively, and is configured to provide the first control voltage provided by the data line to the second control node under the control of the first reset control signal; the first energy storage circuit is electrically connected to the second control node and is used for energy storage circuit; the second writing control circuit is electrically connected to the second control node, the first light-emitting control line and the first control node respectively, and is configured to control the first light-emitting control line to provide a first light-emitting control signal to the first control node under the control of the potential of the second control node.

[0008] Optionally, the second control circuit includes a third writing control circuit, a second energy storage circuit and a fourth writing control circuit; the third writing control circuit is electrically connected to the second reset control line, the data line and the third control node respectively, and writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal; the second energy storage circuit is electrically connected to the third control node and is configured to store electrical energy; the fourth writing control circuit is electrically connected to the third control node, the second light-emitting control line and the first control node respectively, and is configured to control the second light-emitting control line to provide a second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0009] Optionally, the first writing control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second writing control circuit includes a second transistor; a gate of the first transistor is electrically connected to the first reset control line, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the second control node; the first plate of the first capacitor is electrically connected to the second control node, and the second plate of the first capacitor is electrically connected to the first initial voltage line; a gate of the second transistor is electrically connected to the second control node, a first electrode of the second transistor is electrically connected to the first light-emitting control line, and a second electrode of the second transistor is electrically connected to the first control node.

[0010] Optionally, the third writing control circuit includes a third transistor, the second energy storage circuit includes a second capacitor, and the fourth writing control circuit includes a fourth transistor; the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the third control node; the first plate of the second capacitor is electrically connected to the third control node, and the second plate of the second capacitor is electrically connected to the second initial voltage line; a gate of the fourth transistor is electrically connected to the third control node, a first electrode of the fourth transistor is electrically connected to the second light-emitting control line, and a second electrode of the fourth transistor is electrically connected to the first control node.

[0011] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a second light-emitting control circuit; the second light-emitting control circuit is electrically connected to the first light-emitting control line, the power voltage line and the second end of the driving circuit respectively, and is configured to control the connection between the power voltage line and the second end of the driving circuit under the control of the first light-emitting control signal.

[0012] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a compensation control circuit and a third energy storage circuit; the compensation control circuit is electrically connected to the scan line, the control end of the driving circuit and the first end of the driving circuit respectively, and is configured to control the control end of the driving circuit to be connected to the first end of the driving circuit under the control of the scan signal; the third energy storage circuit is electrically connected to the control end of the driving circuit and is used for storing electric energy.

[0013] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a first reset circuit; the first reset circuit is electrically connected to the third reset control line, the third initial voltage line and the control end of the driving circuit respectively, and is configured to write the third initial voltage provided by the third initial voltage line into the control end of the driving circuit under the control of the third reset control signal provided by the third reset control line.

[0014] Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit; the second reset circuit is electrically connected to a fourth reset control line, a fourth initial voltage line and the first electrode of the light-emitting element, respectively, and is configured to write a fourth initial voltage provided by the fourth initial voltage line into the first electrode of the light-emitting element under the control of a fourth reset control signal provided by the fourth reset control line; a second electrode of the light-emitting element is electrically connected to the first voltage line.

[0015] Optionally, the third reset control line is the first reset control line or the second reset control line; the fourth reset control line is the first reset control line or the second reset control line.

[0016] Optionally, the second light-emitting control circuit includes a fifth transistor; a gate of the fifth transistor is electrically connected to the first light-emitting control line, a first electrode of the fifth transistor is electrically connected to the power voltage line, and a second electrode of the fifth transistor is electrically connected to the second end of the driving circuit.

[0017] Optionally, the data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor; and the driving circuit includes a driving transistor; the gate of the sixth transistor is electrically connected to the scan line, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor; the gate of the seventh transistor is electrically connected to the scan line, the first electrode of the seventh transistor is electrically connected to the gate of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the driving transistor; the first plate of the third capacitor is electrically connected to the gate of the driving transistor, and the second plate of the third capacitor is electrically connected to the power voltage line.

[0018] Optionally, the first reset circuit includes an eighth transistor; the gate of the eighth transistor is electrically connected to the third reset control line, the first electrode of the eighth transistor is electrically connected to the third initial voltage line, and the second electrode of the eighth transistor is electrically connected to the control end of the driving circuit.

[0019] Optionally, the second reset circuit includes a ninth transistor; a gate of the ninth transistor is electrically connected to the fourth reset control line, a first electrode of the ninth transistor is electrically connected to the fourth initial voltage line, and a second electrode of the ninth transistor is electrically connected to a first electrode of the light-emitting element.

[0020] Optionally, the pixel circuit described in at least one embodiment of the present disclosure includes a multiplexing control circuit; the multiplexing control circuit is electrically connected to the multiplexing control end, the voltage output end of the source driver and the data line respectively, and is configured to control the connection between the voltage output end and the data line under the control of the multiplexing control signal provided by the multiplexing control end.

[0021] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit, wherein the display phase includes a first writing phase and a second writing phase; the driving method includes:

[0022] In the first writing phase, the first control circuit provides the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node;

[0023] In the second writing stage, the second control circuit writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal, and the second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0024] Optionally, the driving method described in at least one embodiment of the present disclosure includes: when performing medium and high grayscale display, in the first writing stage, the first control circuit controlling the first light-emitting control signal to the first control node under a control of the potential of the second control node, and in the second writing stage, the second control circuit controlling the second light-emitting control signal to be stopped from being provided to the first control node under the control of the potential of the third control node; when performing low grayscale display, in the first writing stage, the first control circuit stops controlling the provision of the first light-emitting control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls the provision of the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0025] In a third aspect, an embodiment of the present disclosure provides a display substrate, including a base substrate and a plurality of rows and columns of the above-mentioned pixel circuits arranged in a display area on the base substrate.

[0026] Optionally, the pixel circuits in the same column are arranged between two columns of data lines; the data lines extend along the first direction; the pixel circuit of the a-th row is arranged between the a-th row scanning line and the a-th row first voltage line, where a is a positive integer; the a-th row of scan lines and the a-th row of first voltage lines extend along a second direction; the first direction and the second direction intersect.

[0027] Optionally, the pixel circuit includes a light-emitting element and a pixel driving circuit; a gap is provided between at least two adjacent pixel driving circuits in the second direction, and at least one of the light-emitting elements is provided in the gap; the orthographic projection of the light-emitting element on the base substrate does not overlap with the pixel driving circuit on the base substrate.

[0028] Optionally, the display substrate described in at least one embodiment of the present disclosure further includes a first signal line; most of the signal lines included in the first signal line extend along the second direction; the first signal line is bent around the light-emitting element to form a first avoidance space, and at least a part of the light-emitting element is disposed in the first avoidance space.

[0029] Optionally, the display substrate described in at least one embodiment of the present disclosure includes a plurality of rows of light-emitting units, and the light-emitting units include at least three of the light-emitting elements; a gap is bent toward the first side around at least one of the light-emitting elements in the odd-numbered rows of light-emitting units to form a first avoidance space; a gap is bent toward the second side around at least one of the light-emitting elements in the light-emitting units of even rows to form another first avoidance space;

[0030] The first side and the second side are opposite sides.

[0031] Optionally, the pixel circuit includes a light-emitting element and a pixel driving circuit; the light-emitting element is arranged on a side of the pixel driving circuit away from the base substrate; the orthographic projection of the light-emitting element on the base substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the base substrate.

[0032] Optionally, the display substrate described in at least one embodiment of the present disclosure further includes a light-emitting control signal generating module and a second signal line, the light-emitting control signal generating module includes a multi-stage light-emitting control signal generating circuit; the light-emitting control signal generating circuit is arranged in the display area; the display substrate comprises a plurality of rows and columns of pixel driving groups, and the pixel driving group comprises at least one pixel driving circuit; at least one level of the light-emitting control signal generating circuit is located between adjacent pixel driving groups; most of the signal lines included in the second signal line extend along the first direction; at least one of the second signal lines is bent around the at least one level of light-emitting control signal generating circuit to form a second avoidance space, and a part of the at least one level of light-emitting control signal generating circuit is arranged in the second avoidance space.

[0033] Optionally, an orthographic projection of the light-emitting control signal generating circuit on the base substrate does not overlap with an orthographic projection of the pixel driving group on the base substrate.

[0034] Optionally, the display substrate described in at least one embodiment of the present disclosure further includes a gate driving module, the gate driving module includes a multi-stage gate driving circuit; the gate driving circuit is arranged in the display area; the display substrate comprises a plurality of rows and columns of pixel driving groups, and the pixel driving group comprises at least one pixel driving circuit; at least one level of the gate driving circuit is located between adjacent pixel driving groups.

[0035] Optionally, the display substrate described in at least one embodiment of the present disclosure further includes a second signal line; most of the signal lines included in the second signal line extend along the first direction; at least one of the second signal lines is bent around the at least one gate driving circuit to form a third avoidance space, and a part of the at least one gate driving circuit is disposed in the third avoidance space.

[0036] Optionally, the orthographic projection of the gate driving circuit on the base substrate does not overlap with the orthographic projection of the pixel driving group on the base substrate. In a fourth aspect, an embodiment of the present disclosure provides a display panel, comprising the above-mentioned display substrate.

[0037] Optionally, the display panel described in at least one embodiment of the present disclosure further includes a source driver, a plurality of columns of data lines and a multiplexing circuit; a plurality of pixel circuits located in the same column are electrically connected to the data line in the same column; the multiplexing circuit is electrically connected to multiple voltage output ends, multiple multiplexing control ends and the multiple columns of data lines of the source driver respectively, and is configured to write the voltage signal provided by the source driver through its voltage output end into the data line under the control of the multiplexing control signal provided by the multiplexing control end.

[0038] Optionally, the multiplexing circuit is electrically connected to N multiplexing control ends respectively, and the multiplexing circuit includes M multiplexing sub-circuits, where N and M are integers greater than 1; each of the multiplexing sub-circuits is electrically connected to the voltage output end of the source driver, the N multiplexing control ends and the N columns of data lines, and is configured to control the voltage signal provided by the voltage output end to be transmitted to the nth data line in the N columns of data lines under the control of the nth multiplexing control signal provided by the nth multiplexing control end; n is a positive integer less than or equal to N.

[0039] In a fifth aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned display panel, wherein a display period includes a first writing time period and a second writing time period; the first writing time period includes a first data writing time period and a second data writing time period, and the second writing time period includes a third data writing time period and a fourth data writing time period; the driving method includes: in a first data writing time period, the multiplexing sub-circuit writing the first control voltage provided by the source driver through the source driver's voltage output end into the data line under the control of the reset control signal; in the second data writing time period, the first control circuit provides the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node; in a third data writing time period, the multiplexing sub-circuit writing the second control voltage provided by the source driver through the source driver's voltage output end into the data line under the control of the reset control signal; in the fourth data writing time period, the second control circuit writes the second control voltage provided by the data line to the third control node under the control of the second reset control signal, and the second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0040] Optionally, the first data writing time period and the second data writing time period are set successively, and the third data writing time period and the fourth data writing time period are set successively; or, the first data writing time period is included in the second data writing time period, and the third data writing time period is included in the fourth data writing time period.

[0041] In a sixth aspect, an embodiment of the present disclosure provides a display device, comprising the above-mentioned display panel.BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG.1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG.2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG.3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG.4 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG.5 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG.4 of the present disclosure; FIG.6 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG4 of the present disclosure; FIG.7 is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG.4 of the present disclosure; FIG.8A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG.8B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG.9 is a layout diagram of a pixel circuit of one embodiment shown in FIG. 4; FIG.10 is a layout diagram of the first gate metal layer in FIG.9; FIG.11 is a layout diagram of the semiconductor layer in FIG.9; FIG.12 is a layout diagram of the second gate metal layer in FIG.9; FIG.13 is a layout diagram of the source / drain metal layer in FIG.9; FIG.14A is a structural diagram of a display substrate according to at least one embodiment of the present disclosure; FIG.14B is a layout diagram of the first gate metal layer in FIG.14A; FIG. 14C is a schematic diagram showing the signal lines disposed in the first gate metal layer and the positions of the light-emitting elements in FIG. 14A. FIG.15 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure; FIG.16 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure; FIG.17 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure; FIG.18 is a structural diagram of a display substrate according to at least one embodiment of the present disclosure; FIG.19 is a structural diagram of a display panel according to at least one embodiment of the present disclosure; FIG.20 is a structural diagram of a display panel according to at least one embodiment of the present disclosure; FIG.21 is a circuit diagram of a display panel according to at least one embodiment of the present disclosure; FIG.22 is a working timing diagram of at least one embodiment of the display panel shown in FIG.21 of the present disclosure; FIG.23 is a timing diagram of operation of at least one embodiment of the display panel shown in FIG.21 of the present disclosure; FIG.24 is a timing diagram of operation of at least one embodiment of the display panel shown in FIG.21 of the present disclosure; FIG.25 is a timing diagram of operation of at least one embodiment of the display panel shown in FIG.21 of the present disclosure; and FIG. 26 is an operation timing diagram of a display panel according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0044] The transistor of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor except the gate, one of the electrodes is called the first electrode and the other is called the second electrode.

[0045] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0046] As shown in FIG. 1, the pixel circuit described in at least one embodiment of the present disclosure includes a light-emitting element E0 and a pixel driving circuit; the pixel driving circuit includes a driving circuit 10, a first light-emitting control circuit 11, a first control circuit 12, a second control circuit 13 and a data writing circuit 32;

[0047] The driving circuit 10 is configured to generate a driving current for driving the light-emitting element E0;

[0048] The first light-emitting control circuit 11 is electrically connected to the first control node N1, the first end of the driving circuit 10 and the light-emitting element E0 respectively, and is configured to control the connection between the first end of the driving circuit 10 and the light-emitting element E0 under the control of the potential of the first control node N1;

[0049] The first control circuit 12 is electrically connected to the data line DT, the first reset control line RA, the first light-emitting control line E1, the first control node N1 and the second control node N2, respectively, and is configured to provide the first control voltage provided by the data line DT to the second control node N2 under the control of the first reset control signal provided by the first reset control line RA, and control the first light-emitting control line E1 to provide the first light-emitting control signal to the first control node N1 under the control of the potential of the second control node N2;

[0050] The second control circuit 13 is electrically connected to the data line DT, the second reset control line RB, the second light-emitting control line Hf, the first control node N1 and the third control node N3, respectively, and is configured to write the second control voltage provided by the data line DT into the third control node N3 under the control of the second reset control signal provided by the second reset control line RB, and control the second light-emitting control line Hf to provide a second light-emitting control signal to the first control node N1 under the control of the potential of the third control node N3;

[0051] The data writing circuit 32 is electrically connected to the scan line G1, the data line DT and the second end of the driving circuit 10 respectively, and is configured to write the display data voltage provided by the data line DT into the second end of the driving circuit 10 under the control of the scan signal provided by the scan line G1;

[0052] The first control circuit 12, the second control circuit 13 and the data writing circuit 32 are configured to access the corresponding voltage signal on the data line DT in a time-sharing manner;

[0053] The pulse width of the scanning signal, the pulse width of the first reset control signal and the pulse width of the second reset control signal are the same; or at least two of the pulse width of the scanning signal, the pulse width of the first reset control signal and the pulse width of the second reset control signal are different.

[0054] In at least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure, only one data line is configured to provide the display data voltage Data_I and the light-emitting time control data voltage Data_T in a time-sharing manner, which can reduce the number of side signals and solve the problem of grayscale signal loss when adding multiplexing transistors. In addition, the integration of the display data voltage Data_I and the light-emitting time control data voltage Data_T also avoids the coupling effect of the two signals in the charging compensation stage, reduces the voltage jump caused by the display data voltage Data_I in the charging compensation stage, and thus solves the column-wise defect of the original pixel circuit.

[0055] In at least one embodiment of the present disclosure, the scan line, the first reset control line and the second reset control line are electrically connected to different GOA circuits in the same GOA module, and are respectively connected to driving signals provided by the different GOA circuits; or, the scanning line, the first reset control line, and the second reset control line are respectively electrically connected to a GOA circuit in different GOA modules, and respectively access the driving signals provided by the GOA circuit in the GOA modules; or,

[0056] Two of the scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits in the first GOA module, and are respectively connected to driving signals provided by different GOA circuits in the first GOA module; the other of the scan line, the first reset control line, and the second reset control line is electrically connected to a GOA circuit in the second GOA module, and is connected to a driving signal provided by a GOA circuit in the second GOA module.

[0057] In a specific implementation, the GOA module may include a plurality of mutually cascaded GOA circuits; each level of the GOA circuit provides a corresponding driving signal;

[0058] The driving signal output end of the a-1th level GOA circuit can be electrically connected to the input terminal of the ath level GOA circuit, so as to provide an input signal to the ath level GOA circuit; a is a positive integer.

[0059] In at least one embodiment of the present disclosure,

[0060] The pulse width of the scan signal, the pulse width of the first reset control signal and the pulse width of the second reset control signal may be the same, and different levels of GOA circuits in the same GOA module may provide corresponding driving signals for the scan line, the first reset control line and the second reset control line, respectively, so as to reduce the number of GOA modules used and facilitate the realization of a narrow frame; or,

[0061] The pulse width of the scan signal, the pulse width of the first reset control signal and the pulse width of the second reset control signal may be different from each other, and one level of GOA circuit in different GOA modules may provide corresponding driving signals for the scan line, the first reset control line and the second reset control line respectively; or,

[0062] Two of the pulse width of the scan signal, the pulse width of the first reset control signal, and the pulse width of the second reset control signal may be the same, and different levels of GOA circuits in the first GOA module may provide corresponding driving signals for two of the scan line, the first reset control line, and the second reset control line, and one of the GOA circuits in the second GOA module may provide a corresponding driving signal for the other of the scan line, the first reset control line, and the second reset control line.

[0063] For example, the pulse width of the first reset control signal and the pulse width of the second reset control signal may be the same, the pulse width of the scan signal may be different from the pulse width of the first reset control signal, different levels of GOA circuits in the first GOA module may provide the first reset control signal and the second reset control signal for the first reset control line and the second reset control line respectively, and one level of GOA circuit in the second GOA module may provide the scan signal for the scan line.

[0064] In at least one embodiment of the present disclosure, the first control voltage and the second control voltage may be light-emitting time control data voltages.

[0065] Optionally, the light-emitting element may be a Mini LED (mini light-emitting diode) or a Micro LED (micro light-emitting diode), but is not limited thereto. In a specific implementation, the light-emitting element may also be an organic light-emitting diode.

[0066] When one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure is in operation.

[0067] When performing a medium or high grayscale display, the first light-emitting control line E1 is controlled to provide a first light-emitting control signal to the first control node N1, and different light-emitting currents are generated by inputting different display data voltage values;

[0068] When performing low grayscale display, a light-emitting current + light-emitting time control method is adopted to provide the second light-emitting control signal on the second light-emitting control line Hf to the first control node N1. The second light-emitting control signal is a high-frequency signal to reduce the flicker problem under low grayscale.

[0069] In one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure, when in operation, the display phase may include a first writing phase and a second writing phase; the driving method includes: In the first writing stage, the first control circuit 12 provides the first control voltage provided by the data line DT to the second control node N2 under the control of the first reset control signal, and the first control circuit 12 controls whether to provide the first light-emitting control signal to the first control node N1 under the control of the potential of the second control node N2; In the second writing stage, the second control circuit 13 writes the second control voltage provided by the data line DT into the third control node N3 under the control of the second reset control signal, and the second control circuit 13 controls whether to provide the second light-emitting control signal to the first control node N1 under the control of the potential of the third control node N3.

[0070] When one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure is in operation.

[0071] When performing medium and high grayscale display, in the first writing stage, the first control circuit 12 controls the first light-emitting control signal to be provided to the first control node N1 under the control of the potential of the second control node N2, and in the second writing stage, the second control circuit 13 controls the second light-emitting control signal to be stopped from being provided to the first control node N1 under the control of the potential of the third control node N3;

[0072] When performing low grayscale display, in the first writing stage, the first control circuit 12 stops controlling the provision of the first light-emitting control signal to the first control node N1 under the control of the potential of the second control node N2, and in the second writing stage, the second control circuit 13 controls the provision of the second light-emitting control signal to the first control node N1 under the control of the potential of the third control node N3.

[0073] In at least one embodiment of the present disclosure, the first control circuit includes a first writing control circuit, a first energy storage circuit, and a second writing control circuit;

[0074] The first writing control circuit is electrically connected to the first reset control line, the data line and the second control node respectively, and is configured to provide the first control voltage provided by the data line to the second control node under the control of the first reset control signal;

[0075] The first energy storage circuit is electrically connected to the second control node and is used for energy storage circuit;

[0076] The second writing control circuit is electrically connected to the second control node, the first light-emitting control line and the first control node respectively, and is configured to control the first light-emitting control line to provide a first light-emitting control signal to the first control node under the control of the potential of the second control node.

[0077] In a specific implementation, the first control circuit may include a first writing control circuit, a first energy storage circuit, and a second writing control circuit, the first writing control circuit controls writing the first control voltage into the second control node, and the second writing control circuit controls writing the first light-emitting control signal into the first control node.

[0078] In at least one embodiment of the present disclosure, the second control circuit includes a third writing control circuit, a second energy storage circuit, and a fourth writing control circuit;

[0079] The third writing control circuit is electrically connected to the second reset control line, the data line and the third control node respectively, and writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal;

[0080] The second energy storage circuit is electrically connected to the third control node and is configured to store electrical energy;

[0081] The fourth writing control circuit is electrically connected to the third control node, the second light-emitting control line and the first control node respectively, and is configured to control the second light-emitting control line to provide a second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0082] In a specific implementation, the second control circuit may include a third writing control circuit, a second energy storage circuit and a fourth writing control circuit, the third writing control circuit controls writing the second control voltage into the third control node, and the fourth writing control circuit controls providing the second light-emitting control signal to the first control node.

[0083] As shown in Fig.2, based on one embodiment of the pixel circuit shown in FIG. 1,

[0084] The first control circuit includes a first writing control circuit 21, a first energy storage circuit 22 and a second writing control circuit 23;

[0085] The first writing control circuit 21 is electrically connected to the first reset control line RA, the data line DT and the second control node N2 respectively, and is configured to provide the first control voltage provided by the data line DT to the second control node N2 under the control of the first reset control signal;

[0086] The first energy storage circuit 22 is electrically connected to the second control node N2 and is used for storing electrical energy;

[0087] The second writing control circuit 23 is electrically connected to the second control node N2, the first light-emitting control line L1 and the first control node N1 respectively, and is configured to control the first light-emitting control line E1 to provide a first light-emitting control signal to the first control node N1 under the control of the potential of the second control node N2;

[0088] The second control circuit includes a third writing control circuit 24, a second energy storage circuit 25 and a fourth writing control circuit 26;

[0089] The third writing control circuit 24 is electrically connected to the second reset control line RB, the data line DT and the third control node N3 respectively, and writes the second control voltage provided by the data line DT into the third control node N3 under the control of the second reset control signal;

[0090] The second energy storage circuit 25 is electrically connected to the third control node N3 and is configured to store electrical energy;

[0091] The fourth writing control circuit 26 is electrically connected to the third control node N3, the second light-emitting control line Hf and the first control node N1 respectively, and is configured to control the second light-emitting control line Hf to provide a second light-emitting control signal to the first control node N1 under the control of the potential of the third control node N3.

[0092] Optionally, the first writing control circuit includes a first transistor, the first energy storage circuit includes a first capacitor, and the second writing control circuit includes a second transistor; a gate of the first transistor is electrically connected to the first reset control line, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the second control node; the first plate of the first capacitor is electrically connected to the second control node, and the second plate of the first capacitor is electrically connected to the first initial voltage line; a gate of the second transistor is electrically connected to the second control node, a first electrode of the second transistor is electrically connected to the first light-emitting control line, and a second electrode of the second transistor is electrically connected to the first control node.

[0093] Optionally, the third writing control circuit includes a third transistor, the second energy storage circuit includes a second capacitor, and the fourth writing control circuit includes a fourth transistor; the first electrode of the third transistor is electrically connected to the data line, and the second electrode of the third transistor is electrically connected to the third control node;

[0094] The first plate of the second capacitor is electrically connected to the third control node, and the second plate of the second capacitor is electrically connected to the second initial voltage line; a gate of the fourth transistor is electrically connected to the third control node, a first electrode of the fourth transistor is electrically connected to the second light-emitting control line, and a second electrode of the fourth transistor is electrically connected to the first control node.

[0095] The pixel circuit in at least one embodiment of the present disclosure further includes a second light-emitting control circuit;

[0096] The second light-emitting control circuit is electrically connected to the first light-emitting control line, the power voltage line and the second end of the driving circuit respectively, and is configured to control the connection between the power voltage line and the second end of the driving circuit under the control of the first light-emitting control signal.

[0097] In a specific implementation, the pixel circuit may further include a second light-emitting control circuit, which controls the connection between the power voltage line and the second end of the driving circuit under the control of the first light-emitting control signal.

[0098] The pixel circuit in at least one embodiment of the present disclosure further includes a data writing circuit, a compensation control circuit and a third energy storage circuit;

[0099] The data writing circuit is electrically connected to the scan line, the data line and the second end of the driving circuit respectively, and is configured to write the display data voltage provided by the data line into the second end of the driving circuit under the control of the scan signal provided by the scan line;

[0100] The compensation control circuit is electrically connected to the scan line, the control end of the driving circuit and the first end of the driving circuit respectively, and is configured to control the control end of the driving circuit to be connected to the first end of the driving circuit under the control of the scan signal;

[0101] The third energy storage circuit is electrically connected to the control end of the driving circuit and is used for storing electric energy.

[0102] In a specific implementation, the pixel circuit may further include a data writing circuit, a compensation control circuit and a third energy storage circuit. The data writing circuit, under the control of a scanning signal, writes the display data voltage into the second end of the driving circuit. The compensation control circuit, under the control of a scanning signal, controls the control end of the driving circuit to be connected to the first end of the driving circuit to perform threshold voltage compensation control.

[0103] The pixel circuit in at least one embodiment of the present disclosure further includes a first reset circuit;

[0104] The first reset circuit is electrically connected to the third reset control line, the third initial voltage line and the control end of the driving circuit respectively, and is configured to write the third initial voltage provided by the third initial voltage line into the control end of the driving circuit under the control of the third reset control signal provided by the third reset control line.

[0105] In a specific implementation, the pixel circuit may further include a first reset circuit;

[0106] Under the control of the third reset control signal, the first reset circuit writes the third initial voltage into the control end of the driving circuit, so that the drive transistor included in the driving circuit can be turned on when the charging compensation phase begins.

[0107] The pixel circuit in at least one embodiment of the present disclosure further includes a second reset circuit;

[0108] The second reset circuit is electrically connected to the fourth reset control line, the fourth initial voltage line and the first electrode of the light-emitting element respectively, and is configured to write the fourth initial voltage provided by the fourth initial voltage line into the first electrode of the light-emitting element under the control of the fourth reset control signal provided by the fourth reset control line;

[0109] a second electrode of the light-emitting element is electrically connected to the first voltage line.

[0110] Optionally, the first voltage line may be a low voltage line, but is not limited thereto.

[0111] In a specific implementation, the pixel circuit may further include a second reset circuit; under the control of a fourth reset control signal, the second reset circuit writes a fourth initial voltage into the first electrode of the light-emitting element to control the light-emitting element not to emit light and clear the residual charge in the first electrode of the light-emitting element.

[0112] Optionally, the third reset control line is the first reset control line or the second reset control line;

[0113] The fourth reset control line is the first reset control line or the second reset control line.

[0114] In at least one embodiment of the present disclosure, the third reset control line may be the first reset control line or the second reset control line, and the fourth reset control line may be the first reset control line or the second reset control line, so as to reduce the number of control lines used.

[0115] As shown in Fig.3, based on one embodiment of the pixel circuit shown in FIG.2, the pixel circuit described in at least one embodiment of the present disclosure further includes a second light-emitting control circuit 31, a compensation control circuit 33, a third energy storage circuit 34, a first reset circuit 35 and a second reset circuit 36;

[0116] The second light-emitting control circuit 31 is electrically connected to the first light-emitting control line E1, the power voltage line VDD and the second end of the driving circuit 10 respectively, and is configured to control the connection between the power voltage line VDD and the second end of the driving circuit 10 under the control of the first light-emitting control signal provided by the first light-emitting control line E1;

[0117] The compensation control circuit 33 is electrically connected to the scan line G1, the control end of the driving circuit 10 and the first end of the driving circuit 10 respectively, and is configured to control the control end of the driving circuit 10 to be connected to the first end of the driving circuit 10 under the control of the scan signal;

[0118] The third energy storage circuit 34 is electrically connected to the control end of the driving circuit 10 and is used for storing electric energy.

[0119] The first reset circuit 35 is electrically connected to the first reset control line RA, the third initial voltage line I3 and the control end of the driving circuit 10 respectively, and is configured to write the third initial voltage provided by the third initial voltage line I3 into the control end of the driving circuit 10 under the control of the first reset control signal provided by the first reset control line RA;

[0120] The second reset circuit 36 is electrically connected to the first reset control line RA, the fourth initial voltage line I4 and the first electrode of the light-emitting element E0 respectively, and is configured to write the fourth initial voltage provided by the fourth initial voltage line I4 into the first electrode of the light-emitting element E0 under the control of the first reset control signal provided by the first reset control line RA;

[0121] The second electrode of the light-emitting element E0 is electrically connected to the first voltage line.

[0122] In one embodiment shown in FIG. 3, the third reset control line is the first reset control line, and the fourth reset control line is the first reset control line.

[0123] In a specific implementation, the third reset control line and the fourth reset control line may both be second reset control lines, or the third reset control line is the first reset control line and the fourth reset control line is the second reset control line; or the third reset control line is the second reset control line and the fourth reset control line is the first reset control line.

[0124] In at least one embodiment of the present disclosure, the first initial voltage line, the second initial voltage line, the third initial voltage line and the fourth initial voltage line may be the same initial voltage line to reduce the number of initial voltage lines used.

[0125] Optionally, the second light-emitting control circuit includes a fifth transistor;

[0126] A gate of the fifth transistor is electrically connected to the first light-emitting control line, a first electrode of the fifth transistor is electrically connected to the power voltage line, and a second electrode of the fifth transistor is electrically connected to the second end of the driving circuit.

[0127] Optionally, the data writing circuit includes a sixth transistor, the compensation control circuit includes a seventh transistor, the third energy storage circuit includes a third capacitor; and the driving circuit includes a driving transistor;

[0128] The gate of the sixth transistor is electrically connected to the scan line, the first electrode of the sixth transistor is electrically connected to the data line, and the second electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor;

[0129] The gate of the seventh transistor is electrically connected to the scan line, the first electrode of the seventh transistor is electrically connected to the gate of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the driving transistor;

[0130] The first plate of the third capacitor is electrically connected to the gate of the driving transistor, and the second plate of the third capacitor is electrically connected to the power voltage line.

[0131] Optionally, the first reset circuit includes an eighth transistor;

[0132] The gate of the eighth transistor is electrically connected to the third reset control line, the first electrode of the eighth transistor is electrically connected to the third initial voltage line, and the second electrode of the eighth transistor is electrically connected to the control end of the driving circuit.

[0133] Optionally, the second reset circuit includes a ninth transistor;

[0134] A gate of the ninth transistor is electrically connected to the fourth reset control line, a first electrode of the ninth transistor is electrically connected to the fourth initial voltage line, and a second electrode of the ninth transistor is electrically connected to a first electrode of the light-emitting element. one embodiment of the pixel circuit shown in FIG. 3, the first writing control circuit includes a first transistor M1, the first energy storage circuit includes a first capacitor C1, and the second writing control circuit includes a second transistor M2;

[0135] The gate of the first transistor M1 is electrically connected to the first reset control line RA, the source of the first transistor M1 is electrically connected to the data line DT, and the drain of the first transistor M1 is electrically connected to the second control node N2;

[0136] The first plate of the first capacitor C1 is electrically connected to the second control node N2, and the second plate of the first capacitor C1 is electrically connected to the initial voltage line I0; the initial voltage line I0 is configured to provide an initial voltage Vinit;

[0137] The gate of the second transistor M2 is electrically connected to the second control node N2, the source of the second transistor M2 is electrically connected to the first light-emitting control line E1, and the drain of the second transistor M2 is electrically connected to the first control node N1;

[0138] The third writing control circuit includes a third transistor M3, the second energy storage circuit includes a second capacitor C2, and the fourth writing control circuit includes a fourth transistor M4;

[0139] The gate of the third transistor M3 is electrically connected to the second reset control line RB, the source of the third transistor M3 is electrically connected to the data line DT, and the drain of the third transistor M3 is electrically connected to the third control node N3;

[0140] The first plate of the second capacitor C2 is electrically connected to the third control node N3, and the second plate of the second capacitor C2 is electrically connected to the initial voltage line I0;

[0141] A gate of the fourth transistor M4 is electrically connected to the third control node N3, a source of the fourth transistor M4 is electrically connected to the second light-emitting control line Hf, and a drain of the fourth transistor M4 is electrically connected to the first control node N1;

[0142] The second light-emitting control circuit includes a fifth transistor M5;

[0143] The gate of the fifth transistor M5 is electrically connected to the first light-emitting control line E1, the source of the fifth transistor M5 is electrically connected to the power voltage line VDD, and the drain of the fifth transistor M5 is electrically connected to the source of the driving transistor M0;

[0144] The data writing circuit includes a sixth transistor M6, the compensation control circuit includes a seventh transistor M7, the third energy storage circuit includes a third capacitor C3; the driving circuit includes a driving transistor M0;

[0145] The gate of the sixth transistor M6 is electrically connected to the scan line G1, the source of the sixth transistor M6 is electrically connected to the data line DT, and the drain of the sixth transistor M6 is electrically connected to the drain of the driving transistor M0;

[0146] The gate of the seventh transistor M7 is electrically connected to the scan line G1, the source of the seventh transistor M7 is electrically connected to the gate of the driving transistor M0, and the drain of the seventh transistor M7 is electrically connected to the drain of the driving transistor M0;

[0147] The first plate of the third capacitor C3 is electrically connected to the gate of the driving transistor M0, and the second plate of the third capacitor C3 is electrically connected to the power voltage line VDD;

[0148] The first reset circuit includes an eighth transistor M8;

[0149] The gate of the eighth transistor M8 is electrically connected to the first reset control line RA, the source of the eighth transistor M8 is electrically connected to the initial voltage line 10, and the drain of the eighth transistor M8 is electrically connected to the gate of the driving transistor M0;

[0150] The second reset circuit includes a ninth transistor M9;

[0151] The gate of the ninth transistor M9 is electrically connected to the first reset control line RA, the source of the ninth transistor M9 is electrically connected to the initial voltage line 10, and the drain of the ninth transistor M9 is electrically connected to the anode of the micro light-emitting diode ML;

[0152] The cathode of the micro light-emitting diode ML is electrically connected to the low voltage line VSS;

[0153] The first light-emitting control circuit includes a tenth transistor M10;

[0154] The gate of M10 is electrically connected to the first control node N1, the source of M10 is electrically connected to the drain of M0, and the drain of M10 is electrically connected to the anode of ML.

[0155] In at least one embodiment of the pixel circuit shown in FIG. 4, all transistors are p-type transistors, but the present invention is not limited thereto.

[0156] In at least one embodiment of the pixel circuit shown in FIG. 4, the light-emitting element is a micro light-emitting diode ML, but the present invention is not limited thereto.

[0157] In at least one embodiment of the pixel circuit shown in FIG. 4, the gate of M8 may also be electrically connected to the second reset control line RB. In this case, in the second writing phase S2, M8 is turned on to initialize the potential of the gate of M0.

[0158] In at least one embodiment of the pixel circuit shown in FIG. 4, the gate signal of M6, the gate signal of M1, and the gate signal of M3 are separated to realize time-sharing writing of the display data voltage, the first control voltage, and the second control voltage. The first control voltage and the second control voltage can be the luminous time control data voltage.

[0159] As shown in FIG. 5, when at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure is in operation, the display cycle includes a first writing stage S1, a second writing stage S2, a charging compensation stage S3, and a light-emitting stage S4 which are successively arranged;

[0160] In the first writing stage S1, RA provides a low voltage signal, RB provides a high voltage signal, G1 provides a high voltage signal, EM and Hf provide high voltage signals, DT provides a first control voltage, M1 is turned on to write the first control voltage Data_T1 into the second control node N2, when performing a medium-high grayscale display, the first control voltage is a low voltage signal, M2 is turned on to control the connection between E1 and the first control node N1; when performing a low grayscale display, the first control voltage is a high voltage signal, M2 is turned off, and C1 maintains the potential of the second control node N2;

[0161] In the first writing stage S1, RA provides a low voltage signal, M8 and M9 are turned on, and I0 provides an initial voltage Vinit to the gate of M0 and the anode of ML, so that at the beginning of the charge compensation stage, M0 can be turned on and control ML not to emit light, and clear the residual charge on the anode of ML;

[0162] In the second writing stage S2, RA provides a high voltage signal, RB provides a low voltage signal, G1 provides a high voltage signal, EM and Hf provide high voltage signals, DT provides a second control voltage, and M3 is turned on to write the second control voltage Data_T2 into the third control node N3; when performing medium and high grayscale display, the second control voltage is a high voltage signal, and M4 is turned off; when performing low grayscale display, the second control voltage is a low voltage signal, M4 is turned on to control the connection between Hf and N1, and C2 maintains the potential of the third control node N3;

[0163] In the charging compensation stage S3, RA provides a high voltage signal, RB provides a high voltage signal, G1 provides a low voltage signal, EM and Hf provide a high voltage signal, DT provides a display data voltage Data_I, M6 and M7 are turned on, and the display data voltage Data_I is written into the source of M0, and the gate of M3 is connected to the drain of M3;

[0164] At the beginning of the charging compensation stage S3, M0 is turned on, and the display data voltage Data_I charges C3 through the turned-on M0 and M7 until M0 is turned off. At this time, the potential of the gate of M0 is Data_I+Vth, and Vth is the threshold voltage of M0;

[0165] In the light-emitting stage S4, EM provides a low voltage signal, and in a partial time period included in the light-emitting stage S4, Hf provides a low voltage signal;

[0166] When the medium and high grayscale display is performed, N1 is connected to EM, and in the light-emitting stage S4, M3 drives ML to emit light;

[0167] When low grayscale display is performed, N1 is connected to Hf, and when Hf outputs a low voltage signal, M3 drives ML to emit light.

[0168] As shown in FIG5, the low-level pulse width of the first reset control signal provided by RA, the low-level pulse width of the second reset control signal provided by RB, and the low-level pulse width of the scan signal provided by G1 are equal. Therefore, the first reset control signal, the second reset control signal and the scan signal can be provided by one GOA (Gate On Array, array substrate row drive) circuit to reduce the number of GOA circuits used, thereby facilitating the realization of a narrow frame.

[0169] In at least one embodiment of the present disclosure, the low level pulse width of the first reset control signal provided by RA, the low level pulse width of the second reset control signal provided by RB, and the low level pulse width of the scan signal provided by G1 are adjustable, and the low level pulse widths may be inconsistent.

[0170] In at least one embodiment of the present disclosure, the low-level pulse width of the scan signal provided by G1 may be greater than or equal to 2 µs, so as to fully perform charging and threshold voltage compensation.

[0171] In at least one embodiment of the pixel circuit shown in Figure 4. The difference between Figure 6 and Figure 5 is that the low-level pulse width of the scanning signal provided by G1 is longer, the low-level pulse width of the scanning signal provided by G1 is greater than the low-level pulse width of the first reset control signal provided by RSTA, and the low-level pulse width of the scanning signal provided by G1 is greater than the low-level pulse width of the second reset control signal provided by RSTB, so as to increase the charging compensation time and fully perform threshold voltage compensation.

[0172] As shown in FIG6, the low level pulse width of the first reset control signal is the same as the low level pulse width of the second reset control signal, and the low level pulse width of the scanning signal is greater than the low level pulse width of the first reset control signal;

[0173] The first reset control signal may be provided by the nth level GOA circuit of the first GOA module, the second reset control signal may be provided by the n+1th level GOA circuit of the first GOA module, and the scan signal may be provided by the mth level GOA circuit in the second GOA module; n and m are positive integers.

[0174] In at least one embodiment shown in FIG. 6, the first reset control signal provided by RA may be interchanged with the second reset control signal provided by RB.

[0175] As shown in FIG. 7, when at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure is in operation, the display cycle includes a first writing stage S1, a second writing stage S2, a charging compensation stage S3, and a light-emitting stage S4 which are successively arranged;

[0176] In the first writing stage S1, RA provides a high voltage signal, RB provides a low voltage signal, G1 provides a high voltage signal, EM and Hf provide high voltage signals, DT provides a first control voltage Data_T1, M1 is turned off, M3 is turned on, DT provides the first control voltage Data_T1 to the third control node N3, C2 maintains the potential of the third control node N3, when performing a medium-high grayscale display, the first control voltage Data_T1 is a high voltage signal, when performing a low grayscale display, the first control voltage Data_T1 is a low voltage signal, M4 is turned on, and the first control node N1 is connected to Hf;

[0177] In the second writing stage S2, RA provides a low voltage signal, RB provides a high voltage signal, G1 provides a high voltage signal, EM and Hf provide high voltage signals, DT provides a second control voltage Data_T2, M1 is turned on, M3 is turned off, DT provides the second control voltage Data_T2 to the second control node N2, and C1 maintains the potential of the second control node N2; when performing medium and high grayscale display, the second control voltage Data_T2 is a low voltage signal, M2 is turned on, and the first control node N1 is connected to E1; when performing low grayscale display, the second control voltage Data_T2 is a high voltage signal;

[0178] In the charging compensation stage S3, RA provides a high voltage signal, RB provides a high voltage signal, G1 provides a low voltage signal, EM and Hf provide a high voltage signal, DT provides a display data voltage Data_I, M6 and M7 are turned on, and the display data voltage Data_I is written into the source of M0, and the gate of M3 is connected to the drain of M3;

[0179] At the beginning of the charging compensation stage S3, M0 is turned on, and the display data voltage Data_I charges C3 through the turned-on M0 and M7 until M0 is turned off. At this time, the potential of the gate of M0 is Data_I+Vth, and Vth is the threshold voltage of M0;

[0180] In the light-emitting stage S4, EM provides a low voltage signal, and in a partial time period included in the light-emitting stage S4, Hf provides a low voltage signal;

[0181] When the medium and high grayscale display is performed, N1 is connected to EM, and in the light-emitting stage S4, M3 drives ML to emit light;

[0182] When low grayscale display is performed, N1 is connected to Hf, and when Hf outputs a low voltage signal, M3 drives ML to emit light.

[0183] In FIG7, the low-level pulse width of the scanning signal provided by G1 is greater than the low-level pulse width of the first reset control signal, and the low-level pulse width of the scanning signal provided by G1 is greater than the low-level pulse width of the second reset control signal, so that the charging compensation phase lasts for a long time and can fully compensate for the threshold voltage of the driving transistor. In actual operation, the low-level pulse width of the scanning signal provided by G1, the low-level pulse width of the first reset control signal, and the low-level pulse width of the second reset control signal can also be equal.

[0184] In at least one embodiment of the present invention, the low-level pulse width of the scanning signal, the low-level pulse width of the first reset control signal and the low-level pulse width of the second reset control signal can be equal, and the second reset control signal can be provided by the nth-level GOA circuit of the first GOA module, the first reset control signal can be provided by the n+1th-level GOA circuit of the first GOA module, and the scanning signal can be provided by the n+2th-level GOA circuit of the first GOA module to reduce the number of GOA modules used and facilitate the realization of a narrow frame; n is a positive integer.

[0185] The difference between one embodiment of the pixel circuit shown in FIG. 8A of the present disclosure and at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure is that: the gate of M8 and the gate of M9 are both electrically connected to the second reset control line RB.

[0186] The pixel circuit in at least one embodiment of the present disclosure further includes a multiplexing control circuit;

[0187] The multiplexing control circuit is electrically connected to the multiplexing control end, the voltage output end of the source driver and the data line respectively, and is configured to control the connection between the voltage output end and the data line under the control of the multiplexing control signal provided by the multiplexing control end.

[0188] In a specific implementation, the pixel circuit may further include a multiplexing control circuit, which controls the voltage output end of the source driver to be electrically connected to the data line under the control of a multiplexing control signal, thereby reducing the number of voltage output ends of the source driver.

[0189] As shown in Fig.8B, based on the pixel circuit in one embodiment of the pixel circuit shown in FIG.3, the pixel circuit according to at least one embodiment of the present disclosure may further include a multiplexing control circuit 80;

[0190] The multiplexing control circuit 80 is electrically connected to the multiplexing control end MX, the voltage output end CH of the source driver SD, and the data line DT respectively, and is configured to control the connection between the voltage output end CH and the data line DT under the control of the multiplexing control signal provided by the multiplexing control end MX.

[0191] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the display stage includes a first writing stage and a second writing stage; the driving method includes:

[0192] In the first writing phase, the first control circuit provides the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node;

[0193] In the second writing stage, the second control circuit writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal, and the second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0194] The driving method in at least one embodiment of the present disclosure includes:

[0195] When performing medium and high grayscale display, in the first writing stage, the first control circuit controls the first light-emitting control signal to be provided to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls the second light-emitting control signal to be stopped from being provided to the first control node under the control of the potential of the third control node;

[0196] When performing low grayscale display, in the first writing stage, the first control circuit stops controlling the provision of the first light-emitting control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controls the provision of the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0197] The display substrate in the present disclosure includes a base substrate and a plurality of rows and columns of the above-mentioned pixel circuits arranged in a display area on the base substrate.

[0198] In at least one embodiment of the present disclosure, pixel circuits located in the same column are arranged between two columns of data lines; the data lines extend along a first direction;

[0199] The pixel circuit of the a-th row is arranged between the a-th row scanning line and the a-th row first voltage line, where a is a positive integer;

[0200] The a- th row of scan lines and the a-th row of first voltage lines extend along a second direction;

[0201] The first direction and the second direction intersect.

[0202] Optionally, the first direction may be a vertical direction, and the second direction may be a horizontal direction, but is not limited thereto.

[0203] In the related art, two columns of data lines are arranged between two adjacent columns of pixel circuits, one column of data lines is configured to provide a light-emitting time data voltage, and the other column of data lines is configured to provide a display data voltage. However, in at least one embodiment of the present disclosure, only one column of data lines is arranged between two adjacent columns of pixel circuits.

[0204] Fig.9 is a layout diagram of one embodiment of the pixel circuit shown in Fig. 4. Fig. 10 is a layout diagram of the first gate metal layer in Fig. 9, Fig. 11 is a layout diagram of the semiconductor layer in Fig. 9, Fig. 12 is a layout diagram of the second gate metal layer in Fig. 9, and Fig. 13 is a layout diagram of the source-drain metal layer in Fig. 9.

[0205] In at least one embodiment of the present disclosure, the first gate metal layer, the semiconductor layer, the second gate metal layer and the source-drain metal layer may be arranged in sequence along a direction away from the substrate.

[0206] As shown in Figure 9, the line labeled VSS is a low voltage line, the line labeled DT is a data line, the line labeled I0 is an initial voltage line, the line labeled RA is a first reset control line, the line labeled RB is a second reset control line, the line labeled E1 is a first light-emitting control line, and the line labeled G1 is a scan line.

[0207] In one embodiment shown in FIG. 9, the second light-emitting control line Hf may include a first light-emitting control line portion Hf1 extending in a vertical direction and a second light-emitting control line portion Hf2 extending in a horizontal direction which are electrically connected to each other.

[0208] As shown in FIG9, VSS, I0, RB, RA, E1, VDD, and G1 all extend in the horizontal direction;

[0209] DT extends in the vertical direction;

[0210] The first capacitor C1 and the second capacitor C2 are arranged between VSS and I0;

[0211] M3 is set between RB and I0;

[0212] M1, M8, M9, M4 and M2 are all set between RA and VDD;

[0213] C3, M5, M10, M6, M0 and M7 are all arranged between E1 and G1.

[0214] In FIG10, C2b 1 is the first plate part of the second capacitor, C1b1 is the first plate part of the first capacitor, C3b1 is the first plate part of the third capacitor, and G0a is the bottom gate of M0.

[0215] In Figure 11, A0 is the active graphic of M0, A1 is the active graphic of M1, A2 is the active graphic of M2, A3 is the active graphic of M3, A4 is the active graphic of M4, A5 is the active graphic of M5, A6 is the active graphic of M6, A7 is the active graphic of M7, A8 is the active graphic of M8, A9 is the active graphic of M9, and A10 is the active graphic of M10.

[0216] In FIG12, G0b is the top gate of G0, C1a is the first plate of the first capacitor, C2a is the first plate of the second capacitor, and C3a is the first plate of the third capacitor.

[0217] In FIG. 13, C2b2 is the second plate part of the second capacitor, C1b2 is the second plate part of the first capacitor, and C3b2 is the second plate part of the third capacitor.

[0218] In at least one embodiment of FIGS. 9-13, C1b1 is electrically connected to C1b2, and C1b1 and C1b2 form the second electrode plate of C1, C2b1 is electrically connected to C2b2, and C2b1 and C2b2 form the second electrode plate of C2, and C3b1 is electrically connected to C3b2, and C3b1 and C3b2 form the second electrode plate of C3.

[0219] In at least one embodiment of the present disclosure, the pixel circuit includes a light-emitting element and a pixel driving circuit;

[0220] A gap is provided between at least two adjacent pixel driving circuits in the second direction, and at least one of the light-emitting elements is provided in the gap;

[0221] The orthographic projection of the light-emitting element on the base substrate does not overlap with the pixel driving circuit on the base substrate.

[0222] In a specific implementation, a gap is provided between at least two adjacent pixel driving circuits in the second direction, at least one light-emitting element is provided in the gap, and the light-emitting element and the pixel driving circuit do not overlap in a direction perpendicular to the base substrate.

[0223] Optionally, the second direction may be a horizontal direction, but is not limited thereto.

[0224] In at least one embodiment of the present disclosure, the light-emitting element may be disposed in a gap between pixel driving circuits so that the light-emitting element and the pixel driving circuit do not affect each other.

[0225] The display substrate in at least one embodiment of the present disclosure further includes a first signal line; most of the signal lines included in the first signal line extend along the second direction;

[0226] The first signal line is bent around the light-emitting element to form a first avoidance space, and at least a part of the light-emitting element is disposed in the first avoidance space.

[0227] In a specific implementation, the display substrate may further include a first signal line, and the first signal line is bent around the light-emitting element to form a first avoidance space, so that the light-emitting element is disposed in the first avoidance space.

[0228] In at least one embodiment of the present disclosure, most of the first signal lines extend in a horizontal direction, and the first signal lines bend downward or upward around the light-emitting elements to form a first avoidance space to facilitate layout of the light-emitting elements.

[0229] Optionally, the first signal line may include a low voltage line, an initial voltage line, a first reset control line, a second reset control line, a first light-emitting control line and a scan line.

[0230] The display substrate in at least one embodiment of the present disclosure comprises a plurality of rows of light-emitting units, wherein the light-emitting units comprise at least three light-emitting elements; a gap is bent toward the first side around at least one of the light-emitting elements in the odd-numbered rows of light-emitting units to form a first avoidance space; a gap is bent toward the second side around at least one of the light-emitting elements in the even-numbered rows of light-emitting units to form another first avoidance space;

[0231] The first side and the second side are opposite sides.

[0232] Optionally, the first side may be a lower side, and the second side may be an upper side; or, the first side may be an upper side, and the second side may be a lower side; but the present invention is not limited thereto.

[0233] As shown in FIG.14A, the display substrate described in at least one embodiment of the present disclosure may include a first row and a first column of light-emitting units, a first row and a second column of light-emitting units, a first row and a third column of light-emitting units, a first row and a fourth column of light-emitting units, a first row and a fifth column of light-emitting units, a first row and a sixth column of light-emitting units, a second row and a first column of light-emitting units, a second row and a second column of light-emitting units, a second row and a third column of light-emitting units, a second row and a fourth column of light-emitting units, a second row and a fifth column of light-emitting units, a second row and a sixth column of light-emitting units, a third row and a first column of light-emitting units, a third row and a second column of light-emitting units, a third row and a third column of light-emitting units, a third row and a fourth column of light-emitting units, a third row and a fifth column of light-emitting units, and a third row and a sixth column of light-emitting units;

[0234] The first row and first column light-emitting unit includes, from top to bottom, a first row and first column blue light-emitting element B11, a first row and first column green light-emitting element G11, and a first row and first column red light-emitting element R11;

[0235] The first row and second column light-emitting unit includes, from top to bottom, a first row and second column blue light-emitting element B12, a first row and second column green light-emitting element G12, and a first row and second column red light-emitting element R12;

[0236] The first row and third column light-emitting unit includes, from top to bottom, a first row and third column blue light-emitting element B13, a first row and third column green light-emitting element G13, and a first row and third column red light-emitting element R13;

[0237] The first row and fourth column light-emitting unit includes, from top to bottom, a first row and fourth column blue light-emitting element B14, a first row and fourth column green light-emitting element G14, and a first row and fourth column red light-emitting element R14;

[0238] The second row and fifth column light-emitting unit includes, from top to bottom, the second row and fifth column blue light-emitting element B25, the second row and fifth column green light-emitting element G25, and the second row and fifth column red light-emitting element R25;

[0239] The second row and sixth column light-emitting unit includes, from top to bottom, a second row and sixth column blue light-emitting element B26, a second row and sixth column green light-emitting element G26, and a second row and sixth column red light-emitting element R26;

[0240] The second row and first column light-emitting unit includes, from top to bottom, a second row and first column blue light-emitting element B21, a second row and first column green light-emitting element G21, and a second row and first column red light-emitting element R21;

[0241] The second row and second column light-emitting unit includes, from top to bottom, a second row and second column blue light-emitting element B22, a second row and second column green light-emitting element G22, and a second row and second column red light-emitting element R22;

[0242] The second row and third column light-emitting unit includes, from top to bottom, a second row and third column blue light-emitting element B23, a second row and third column green light-emitting element G23, and a second row and third column red light-emitting element R23;

[0243] The second row and fourth column light-emitting unit includes, from top to bottom, a second row and fourth column blue light-emitting element B24, a second row and fourth column green light-emitting element G24, and a second row and fourth column red light-emitting element R24;

[0244] The second row and fifth column light-emitting unit includes, from top to bottom, the second row and fifth column blue light-emitting element B25, the second row and fifth column green light-emitting element G25, and the second row and fifth column red light-emitting element R25;

[0245] The second row and sixth column light-emitting unit includes, from top to bottom, a second row and sixth column blue light-emitting element B26, a second row and sixth column green light-emitting element G26, and a second row and sixth column red light-emitting element R26;

[0246] In FIG.14A, a first pixel driving unit is labeled P1, a second pixel driving unit is labeled P2, a third pixel driving unit is labeled P3, a fourth pixel driving unit is labeled P4, a fifth pixel driving unit is labeled P5, a sixth pixel driving unit is labeled P6, a seventh pixel driving unit is labeled P7, an eighth pixel driving unit is labeled P8, and a ninth pixel driving unit is labeled P9;

[0247] Each pixel driving unit includes at least one pixel driving circuit;

[0248] The line labeled VSS is a low voltage line, the line labeled I0 is an initial voltage line, the line labeled RB is a second reset control line, the line labeled RA is a first reset control line, the line labeled VDD is a power voltage line, the line labeled E1 is a first light-emitting control line, and the line labeled G1 is a scan line;

[0249] VSS, I0, RA, E1 and G1 may be formed in the first gate metal layer;

[0250] RB and VDD may be formed in the second gate metal layer;

[0251] Most of the low voltage line portions included in VSS, most of the initial voltage line portions included in I0, most of the second reset control line portions included in RB, most of the first reset control line portions included in RA, most of the power voltage line portions included in VDD, most of the first light emission control line portions included in E1, and most of the scan line portions included in G1 extend in the horizontal direction;

[0252] R11, G11, B11, R21, G21 and B21 are arranged in the gap on the left side of the first pixel driving unit;

[0253] R12, G12, B12, R22, G22 and B22 are disposed in a gap between the second pixel driving unit and the third pixel driving unit;

[0254] R13, G13, B13, R23, G23 and B23 are disposed in a gap between the third pixel driving unit and the fourth pixel driving unit;

[0255] R14, G14, B14, R24, G24 and B24 are disposed in a gap between the fifth pixel driving unit and the sixth pixel driving unit;

[0256] R15, G15, B15, R25, G25 and B25 are disposed in a gap between the sixth pixel driving unit and the seventh pixel driving unit;

[0257] R16, G16, B16, R26, G26 and B26 are disposed in a gap between the eighth pixel driving unit and the ninth pixel driving unit;

[0258] The orthographic projection of each of the light-emitting elements on the base substrate does not overlap with the pixel driving circuit included in each pixel driving unit on the base substrate.

[0259] In at least one embodiment of the present disclosure, each light-emitting element may be an LED (light-emitting diode).

[0260] FIG. 14B is a layout diagram of the first gate metal layer in FIG. 14A, and FIG. 14C is a schematic diagram of the signal lines disposed in the first gate metal layer in FIG. 14A, as well as the positions of the light-emitting elements.

[0261] As shown in FIG. 14B, in order to place R11, the initial voltage line I0 is bent downward to form a first avoidance space A11; as shown in FIG. 14C, part of R11 is disposed in A11;

[0262] As shown in FIG. 14B, in order to place R12, the initial voltage line I0 is bent downward to form a second first avoidance space A21; as shown in FIG. 14C, part of R12 is disposed in A21;

[0263] As shown in FIG. 14B, in order to place R13, the initial voltage line I0 is bent downward to form a third first avoidance space A31; as shown in FIG. 14C, part of R13 is disposed in A31;

[0264] As shown in FIG. 14B, in order to place R14, the initial voltage line I0 is bent downward to form a fourth first avoidance space A41; as shown in FIG. 14C, part of R14 is disposed in A41;

[0265] As shown in FIG. 14B, in order to place R15, the initial voltage line I0 is bent downward to form a fifth first avoidance space A51; as shown in FIG. 14C, part of R15 is disposed in A51;

[0266] As shown in FIG. 14B, in order to place R16, the initial voltage line I0 is bent downward to form a sixth first avoidance space A61; as shown in FIG. 14C, part of R16 is disposed in A61;

[0267] As shown in FIG. 14B, in order to place B21, the first light-emitting control line E1 is bent upward to form the seventh first avoidance space A71; as shown in FIG. 14C, part of B21 is disposed in A71;

[0268] As shown in FIG. 14B, in order to place B22, the first light-emitting control line E1 is bent upward to form an eighth first avoidance space A81; as shown in FIG. 14C, part of B22 is disposed in A81;

[0269] As shown in FIG. 14B, in order to place B23, the first light-emitting control line E1 is bent upward to form a ninth first avoidance space A91; as shown in FIG. 14C, part of B23 is disposed in A91;

[0270] As shown in FIG. 14B, in order to place B24, the first light-emitting control line E1 is bent upward to form a tenth first avoidance space A101; as shown in FIG. 14C, part of B24 is disposed in A101;

[0271] As shown in FIG. 14B, in order to place B25, the first light-emitting control line E1 is bent upward to form an eleventh first avoidance space A111; as shown in FIG. 14C, part of B25 is disposed in A111;

[0272] As shown in FIG. 14B, in order to place B26, the first light-emitting control line E1 is bent upward to form a twelfth first avoidance space A121; as shown in FIG. 14C, part of B26 is disposed in A121.

[0273] In at least one embodiment of the present disclosure, each light-emitting element may be disposed between each pixel driving unit, and the pixel driving unit may include at least one pixel driving circuit;

[0274] Optionally, the display substrate may include a second signal line;

[0275] Most of the signal lines included in the second signal line extend along the first direction;

[0276] The second signal line is bent around the light-emitting element to form a fourth avoidance space, and at least a part of the light-emitting element is disposed in the fourth avoidance space.

[0277] In a specific implementation, the display substrate may include a second signal line that mostly extends in a vertical direction, and the second signal line may be bent around the light-emitting element to form a fourth avoidance space to facilitate placement of the light-emitting element.

[0278] In at least one embodiment of the present disclosure, the pixel circuit includes a light-emitting element and a pixel driving circuit;

[0279] The light-emitting element is arranged on a side of the pixel driving circuit away from the base substrate;

[0280] The orthographic projection of the light-emitting element on the base substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the base substrate.

[0281] In a specific implementation, the pixel driving circuit may be disposed between the light-emitting element and the base substrate, and the orthographic projection of the light-emitting element on the base substrate at least partially overlaps with the orthographic projection of the pixel driving circuit on the base substrate.

[0282] As shown in FIG.15, the unit labeled P1 is a first pixel driving unit;

[0283] P1 includes a plurality of pixel driving circuits;

[0284] The blue light-emitting element labeled B11 is in the first row and first column, the green light-emitting element labeled G11 is in the first row and first column, and the red light-emitting element labeled R11 is in the first row and first column;

[0285] The blue light-emitting element labeled B12 is in the first row and second column, the green light-emitting element labeled G12 is in the first row and second column, and the red light-emitting element labeled R12 is in the first row and second column;

[0286] The blue light-emitting element labeled B13 is in the first row and third column, the green light-emitting element labeled G13 is in the first row and third column, and the red light-emitting element labeled R13 is in the first row and third column;

[0287] The blue light-emitting element labeled B14 is in the first row and fourth column, the green light-emitting element labeled G14 is in the first row and fourth column, and the red light-emitting element labeled R14 is in the first row and fourth column;

[0288] The blue light-emitting element labeled B21 is in the first column of the second row, the green light-emitting element labeled G21 is in the first column of the second row, and the red light-emitting element labeled R21 is in the first column of the second row;

[0289] The blue light-emitting element labeled B22 is in the second row and second column, the green light-emitting element labeled G22 is in the second row and second column, and the red light-emitting element labeled R22 is in the second row and second column;

[0290] The blue light-emitting element labeled B23 is in the second row and third column, the green light-emitting element labeled G23 is in the second row and third column, and the red light-emitting element labeled R23 is in the second row and third column;

[0291] The blue light-emitting element labeled B24 is in the second row and fourth column, the green light-emitting element labeled G24 is in the second row and fourth column, and the red light-emitting element labeled R24 is in the second row and fourth column;

[0292] The orthographic projection of R11 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G11 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B11 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0293] The orthographic projection of R12 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G12 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B12 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0294] The orthographic projection of R13 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G13 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B13 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0295] The orthographic projection of R14 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G14 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B14 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0296] The orthographic projection of R21 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G21 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B21 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0297] The orthographic projection of R22 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G22 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B22 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0298] The orthographic projection of R23 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G23 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B23 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate;

[0299] The orthographic projection of R24 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of G24 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate; the orthographic projection of B24 on the substrate at least partially overlaps with the orthographic projection of P1 on the substrate.

[0300] In at least one embodiment shown in Figure 15, the first pixel driving unit, R11, G11, B11, R12, G12, B12, R13, G13, B13, R14, G14, B14, R21, G21, B21, R22, G22, B22, R23, G23, B23, R24, G24 and B14 form a pixel driving group.

[0301] The display substrate in at least one embodiment of the present disclosure further includes a light-emitting control signal generating module and a second signal line, wherein the light-emitting control signal generating module includes a multi-stage light-emitting control signal generating circuit; the light-emitting control signal generating circuit is arranged in the display area;

[0302] The display substrate comprises a plurality of rows and columns of pixel driving groups, and the pixel driving group comprises at least one pixel driving circuit;

[0303] At least one level of the light-emitting control signal generating circuit is located between adjacent pixel driving groups;

[0304] Most of the signal lines included in the second signal line extend along the first direction;

[0305] At least one of the second signal lines is bent around the at least one level of light-emitting control signal generating circuit to form a second avoidance space, and a part of the at least one level of light-emitting control signal generating circuit is arranged in the second avoidance space.

[0306] In a specific implementation, the at least one light-emitting control signal generating circuit included in the light-emitting control signal generating module can be located between adjacent pixel driving groups, and at least one second signal line is bent around the at least one light-emitting control signal generating circuit to form a second avoidance space, and a part of the at least one light-emitting control signal generating circuit is arranged in the second avoidance space to place the at least one light-emitting control signal generating circuit; the light-emitting control signal generating circuit can be arranged in the display area to facilitate the realization of a narrow frame.

[0307] In one embodiment of the present disclosure, the orthographic projection of the light-emitting control signal generating circuit on the base substrate does not overlap with the orthographic projection of the pixel driving group on the base substrate.

[0308] In a specific implementation, the light-emitting control signal generating circuit and the pixel driving group do not overlap in a direction perpendicular to the base substrate, so that the light-emitting control signal generating circuit and the pixel driving group do not affect each other.

[0309] Optionally, the second signal line may include a data line and a second light-emitting control line, but is not limited thereto.

[0310] In at least one embodiment of the present disclosure, the second light-emitting control line may extend in a vertical direction; or, the second light-emitting control line may include a first light-emitting control line portion extending in a vertical direction and a second light-emitting control line portion extending in a horizontal direction.

[0311] In a specific implementation, the display substrate may further include a first signal line, most of the signal lines included in the first signal line extend along the second direction;

[0312] At least one of the first signal lines is bent around the at least one level of light-emitting control signal generating circuit to form a fifth avoidance space, and a part of the at least one level of light-emitting control signal generating circuit is arranged in the fifth avoidance space.

[0313] In a specific implementation, the display substrate may include a first signal line that mostly extends in a horizontal direction, and the first signal line may be bent around the light-emitting control signal generating circuit to form a fifth avoidance space to facilitate placement of the light-emitting control signal generating circuit.

[0314] The display substrate at least one embodiment of the present disclosure further includes a gate driving module, wherein the gate driving module includes a multi-stage gate driving circuit; the gate driving circuit is disposed in the display area;

[0315] The display substrate comprises a plurality of rows and columns of pixel driving groups, and the pixel driving group comprises at least one pixel driving circuit;

[0316] At least one level of the gate driving circuit is located between adjacent pixel driving groups.

[0317] In a specific implementation, at least one gate driving circuit included in the gate driving module is arranged between adjacent pixel driving groups. The gate driving circuit can be arranged in the display area, which is conducive to achieving a narrow frame.

[0318] The display substrate in at least one embodiment of the present disclosure further includes a second signal line; most of the signal lines included in the second signal line extend along the first direction;

[0319] At least one of the second signal lines is bent around the at least one gate driving circuit to form a third avoidance space, and a part of the at least one gate driving circuit is disposed in the third avoidance space.

[0320] In a specific implementation, at least one second signal line is bent around the at least one gate driving circuit to form a third avoidance space, and part of the at least one gate driving circuit is arranged in the third avoidance space to place the at least one gate driving circuit.

[0321] In at least one embodiment of the present disclosure, an orthographic projection of the gate driving circuit on the base substrate does not overlap with an orthographic projection of the pixel driving group on the base substrate.

[0322] In a specific implementation, the gate driving circuit and the pixel driving group do not overlap in a direction perpendicular to the base substrate, so that the gate driving circuit and the pixel driving group do not affect each other.

[0323] In at least one embodiment of the present disclosure, the display substrate may further include a first signal line, most of the signal lines included in the first signal line extend along the second direction;

[0324] At least one of the first signal lines is bent around the at least one gate driving circuit to form a sixth avoidance space, and a part of the at least one gate driving circuit is disposed in the sixth avoidance space.

[0325] In a specific implementation, the display substrate may include a first signal line that mostly extends in a horizontal direction, and the first signal line may be bent around the gate driving circuit to form a sixth avoidance space to facilitate placement of the gate driving circuit.

[0326] As shown in FIG.16, the pixel driving group labeled F11 is the first row and first column, the pixel driving group labeled F12 is the first row and second column, and the pixel driving group labeled F13 is the first row and third column;

[0327] The pixel driving group marked with F21 is the second row and first column, the pixel driving group marked with F22 is the second row and second column repeating unit, and the pixel driving group marked with F23 is the second row and third column;

[0328] The circuit labeled EA1 is a first-stage light-emitting control signal generating circuit, and the circuit labeled EA2 is a second-stage light-emitting control signal generating circuit;

[0329] The first-stage gate driving circuit is labeled GA1, the second-stage gate driving circuit is labeled GA2, and the third-stage gate driving circuit is labeled GA3;

[0330] EA1 and EA2 are set between F11, F21, F21 and F22;

[0331] GA1, GA2 and GA3 are arranged between F12, F22, F13 and F23.

[0332] In at least one embodiment of the present disclosure, the pixel driving group may include 2 rows and 2 columns of pixel driving circuits, two rows and three columns of pixel driving circuits, two rows and four columns of pixel driving circuits, or three rows and three columns of pixel circuits. The specific values of the number of rows and columns of the pixel driving circuits included in the pixel driving group are not limited. In FIG16, HF1 is the first second light-emitting control line, DT1 is the first data line, HF2 is the second second light-emitting control line, DT2 is the second data line, HF3 is the third second light-emitting control line, DT3 is the third data line, HF4 is the fourth second light-emitting control line, DT4 is the fourth data line, HF5 is the fifth second light-emitting control line, DT5 is the fifth data line, HF6 is the sixth second light-emitting control line, DT6 is the sixth data line, HF7 is the seventh second light-emitting control line, DT7 is the seventh data line, HF8 is the eighth second light-emitting control line, DT8 is the eighth data line, HF9 is the ninth second light-emitting control line, DT9 is the ninth data line, and HF10 is the tenth second Light-emitting control lines, labeled DT10 is the tenth data line, labeled HF11 is the eleventh second light-emitting control line, labeled DT11 is the eleventh data line, labeled HF12 is the twelfth second light-emitting control line, labeled DT12 is the twelfth data line; labeled HF13 is the thirteenth second light-emitting control line, labeled DT13 is the thirteenth data line, labeled HF14 is the fourteenth second light-emitting control line, labeled DT14 is the fourteenth data line, labeled HF15 is the fifteenth second light-emitting control line, labeled DT15 is the fifteenth data line, labeled HF16 is the sixteenth second light-emitting control line, labeled DT16 is the sixteenth data line, labeled HF17 is the seventeenth second light-emitting control line, labeled DT17 is the seventeenth data line, labeled HF18 is the eighteenth second light-emitting control line, labeled DT18 is the eighteenth data line;

[0333] As shown in FIG.16, most of the second light-emitting control line portions of each second light-emitting control line extend in the vertical direction, and most of the data line portions of each data line extend in the vertical direction;

[0334] EA1 and EA2 are set between DT6 and HF7;

[0335] DT6 bends to the left to form the first second avoidance space A12;

[0336] HF7 bends to the right to form the second avoidance space A22;

[0337] Part of EA1 and part of EA2 are arranged in A12, and part of EA1 and part of EA2 are arranged in A22;

[0338] HF6 bends to the left, DT5 bends to the left, HF5 bends to the left, DT4 bends to the left, and HF4 bends to the left, so that the distance between HF6 and DT6, the distance between DT5 and HF6, the distance between HF5 and DT5, the distance between DT4 and HF5, and the distance between HF4 and DT4 are approximately equal, so as to evenly distribute the signal lines;

[0339] DT7 bends right, HF8 bends right, DT8 bends right, HF9 bends right, DT9 bends right, HF10 bends right, DT10 bends right, HF11 bends right, DT11 bends right, HF12 bends right, DT12 bends right, so that the distance between HF7 and DT7, the distance between DT7 and HF8, the distance between HF8 and DT8, the distance between DT8 and HF9, and the distance between HF9 and DT9 are roughly equal to evenly distribute the signal lines.

[0340] As shown in FIG.17, the first-stage gate driving circuit is labeled GA1, the second-stage gate driving circuit is labeled GA2, and the third-stage gate driving circuit is labeled GA3;

[0341] GA1, GA2 and GA3 are arranged between F12, F22, F13 and F23.

[0342] DT12 bends to the left to form the first third avoidance space A13;

[0343] HF13 bends to the right to form the second third avoidance space A23;

[0344] A part of GA1, a part of GA2, and a part of GA3 are disposed in A13;

[0345] A part of GA1, a part of GA2, and a part of GA3 are disposed in A23.

[0346] In at least one embodiment of the present disclosure, a third area is provided on a side of the display area close to the Fanout area, and a pixel driving circuit is provided in the third area, but a light-emitting control signal generating circuit and a gate driving circuit are not provided. Therefore, in a first area close to the third area in the display area, the number of stages of the light-emitting control signal generating circuit provided between adjacent pixel driving groups is greater than the number of stages of the light-emitting control signal generating circuit provided between adjacent pixel driving groups in a second area other than the first area and the third area in the display area.

[0347] In a first area included in the display area, the number of gate driving circuits set between adjacent pixel driving groups is greater than the number of gate driving circuits set between adjacent pixel driving groups in a second area of the display area.

[0348] For example, in the first region, between adjacent pixel driving groups, a three-level or four-level light-emitting control signal generating circuit may be provided, and in the second region, between adjacent pixel driving groups, a two-level light-emitting control signal generating circuit may be provided;

[0349] In the first region, between adjacent pixel drive groups, a three-stage or four-stage gate driving circuit may be provided, and in the second region, between adjacent pixel drive groups, a two-stage gate circuit may be provided;

[0350] But it is not limited to this.

[0351] As shown in FIG.18, the area labeled A0 is the display area, the area labeled A1 is the first area, the area labeled A2 is the second area, the area labeled A3 is the third area, and the area labeled FA is the fan-out area;

[0352] The display area A0 includes a first area A1, a second area A2 and a third area A3;

[0353] In FIG.18, the pixel driving group labeled F11 is the first row and first column, the pixel driving group labeled F12 is the first row and second column, the pixel driving group labeled F13 is the first row and third column, the pixel driving group labeled F14 is the first row and fourth column, and the pixel driving group labeled F15 is the first row and fifth column;

[0354] The pixel driving group labeled F21 is the second row and first column, the pixel driving group labeled F22 is the second row and second column, the pixel driving group labeled F23 is the second row and third column, the pixel driving group labeled F24 is the second row and fourth column, and the pixel driving group labeled F25 is the second row and fifth column;

[0355] The pixel driving group labeled F31 is the third row and first column, the pixel driving group labeled F32 is the third row and second column, the pixel driving group labeled F33 is the third row and third column, the pixel driving group labeled F34 is the third row and fourth column, and the pixel driving group labeled F35 is the third row and fifth column;

[0356] The pixel driving group labeled F41 is the fourth row and first column, the pixel driving group labeled F42 is the fourth row and second column, the pixel driving group labeled F43 is the fourth row and third column, the pixel driving group labeled F44 is the fourth row and fourth column, and the pixel driving group labeled F45 is the fourth row and fifth column;

[0357] The pixel driving group labeled F51 is the first column of the fifth row, the pixel driving group labeled F52 is the second column of the fifth row, the pixel driving group labeled F53 is the third column of the fifth row, the pixel driving group labeled F54 is the fourth column of the fifth row, and the pixel driving group labeled F55 is the fifth column of the fifth row;

[0358] The pixel driving group labeled F61 is the pixel driving group of the sixth row and the first column, the pixel driving group labeled F62 is the pixel driving group of the sixth row and the second column, the pixel driving group labeled F63 is the pixel driving group of the sixth row and the third column, the pixel driving group labeled F64 is the pixel driving group of the sixth row and the fourth column, and the pixel driving group labeled F65 is the pixel driving group of the sixth row and the fifth column;

[0359] The pixel driving group labeled F71 is the pixel driving group of the seventh row and the first column, the pixel driving group labeled F72 is the pixel driving group of the seventh row and the second column, the pixel driving group labeled F73 is the pixel driving group of the seventh row and the third column, the pixel driving group labeled F74 is the pixel driving group of the seventh row and the fourth column, and the pixel driving group labeled F75 is the pixel driving group of the seventh row and the fifth column;

[0360] F71, F72, F73, F74 and F75 are arranged in the third area A3;

[0361] Each of the above pixel driving groups includes at least one pixel driving circuit;

[0362] The first row and first column light-emitting control signal generating circuit EA11 and the second row and first column light-emitting control signal generating circuit EA21 are arranged between F11, F12, F21 and F22;

[0363] The third row and first column light-emitting control signal generating circuit EA31 and the fourth row and first column light-emitting control signal generating circuit EA41 are arranged between F21, F22, F31 and F32;

[0364] The fifth row and first column light control signal generating circuit EA51 and the sixth row and first column light control signal generating circuit EA61 are arranged between F31, F32, F41 and F42;

[0365] The seventh row and first column light control signal generating circuit EA71, the eighth row and first column light control signal generating circuit EA81 and the ninth column and first column light control signal generating circuit EA91 are arranged between F41, F42, F51 and F52;

[0366] The tenth row and first column light control signal generating circuit EA111, the eleventh row and first column light control signal generating circuit EA111, the twelfth row and first column light control signal generating circuit EA121 and the thirteenth row and first column light control signal generating circuit EA131 are arranged between F51, F52, F61 and F62;

[0367] The first row and first column gate driving circuit GA11 and the second row and first column gate driving circuit EA21 are arranged between F12, F13, F22 and F23;

[0368] The third row and first column gate driving circuit GA31 and the fourth row and first column gate driving circuit GA41 are disposed between F22, F23, F32 and F33;

[0369] The fifth row and first column gate driving circuit GA51 and the sixth row and first column gate circuit GA61 are disposed between F32, F33, F42 and F43;

[0370] The seventh row and first column gate driving circuit GA71, the eighth row and first column gate driving circuit GA81, and the ninth column and first column gate driving circuit GA91 are disposed between F42, F43, F52, and F53;

[0371] The tenth row and first column gate driving circuit GA111, the eleventh row and first column gate driving circuit GA111, the twelfth row and first column gate driving circuit GA121 and the thirteenth row and first column gate driving circuit GA131 are arranged between F52, F53, F62 and F63;

[0372] The first row and second column light-emitting control signal generating circuit EA12 and the second row and second column light-emitting control signal generating circuit EA22 are arranged between F13, F14, F23 and F24;

[0373] The third row and second column light control signal generating circuit EA31 and the fourth row and second column light control signal generating circuit EA42 are arranged between F23, F24, F33 and F34;

[0374] The fifth row and second column light control signal generating circuit EA52 and the sixth row and second column light control signal generating circuit EA62 are arranged between F33, F34, F43 and F44;

[0375] The seventh row and second column light control signal generating circuit EA72, the eighth row and second column light control signal generating circuit EA82 and the ninth column and second column light control signal generating circuit EA92 are arranged between F43, F44, F53 and F54;

[0376] The tenth row and second column light control signal generating circuit EA112, the eleventh row and second column light control signal generating circuit EA112, the twelfth row and second column light control signal generating circuit EA122 and the thirteenth row and second column light control signal generating circuit EA132 are arranged between F53, F54, F63 and F64;

[0377] The first row and second column gate driving circuit GA12 and the second row and second column gate driving circuit EA22 are arranged between F14, F15, F24 and F25;

[0378] The third row and second column gate driving circuit GA32 and the fourth row and second column gate driving circuit GA42 are disposed between F24, F25, F34 and F35;

[0379] The fifth row and second column gate driving circuit GA52 and the sixth row and second column gate circuit GA62 are disposed between F34, F35, F44 and F45;

[0380] The seventh row and second column gate driving circuit GA72, the eighth row and second column gate driving circuit GA82, and the ninth column and second column gate driving circuit GA92 are disposed between F44, F45, F54, and F55;

[0381] The gate driving circuit GA112 of the second column in the tenth row, the gate driving circuit GA112 of the second column in the eleventh row, the gate driving circuit GA122 of the second column in the twelfth row, and the gate driving circuit GA132 of the second column in the thirteenth row are arranged between F54, F55, F64, and F65;

[0382] As shown in FIG18, F51, F52, F53, F54, F55, F61, F62, F63, F64, F65, EA71, EA81, EA91, EA101, EA111, EA121, EA131, GA71, GA81, GA91, GA101, GA111, GA121, GA131, EA72, EA82, EA92, EA102, EA112, EA122, EA132, GA72, GA82, GA92, GA102, GA112, GA122 and GA132 are all arranged in the first area A1, the first area A1 is close to the third area A3, and the third area A3 is close to the fan-out area FA;

[0383] In the first area A1, in adjacent pixel driving groups, three or four levels of light emission control signal generating circuits are provided, and three or four levels of gate driving circuits are provided.

[0384] In Fig. 18, the row and column numbers of each pixel driving group are only used as examples to illustrate the positions of each pixel driving group, and are not the actual rows and columns corresponding to the pixel driving groups. The display panel described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0385] The display panel described in at least one embodiment of the present disclosure further includes a source driver, a plurality of columns of data lines and a multiplexing circuit;

[0386] A plurality of pixel circuits located in the same column are electrically connected to the data line in the same column;

[0387] The multiplexing circuit is electrically connected to multiple voltage output ends, multiple multiplexing control ends and the multiple columns of data lines of the source driver respectively, and is configured to write the voltage signal provided by the source driver through its voltage output end into the data line under the control of the multiplexing control signal provided by the multiplexing control end.

[0388] In a specific implementation, the display panel may further include a source driver, a plurality of columns of data lines and a multiplexing circuit. Under the control of a multiplexing control signal, the multiplexing circuit writes a voltage signal provided by the source driver through its voltage output end into the data line.

[0389] As shown in FIG19, the display panel described in at least one embodiment of the present disclosure further includes a source driver SD, a multiplexing circuit 90, a first column data line DL1, a second column data line DL2, a third column data line DL3, a fourth column data line DL4, a fifth column data line DL5, a sixth column data line DL6, a seventh column data line DL7, an eighth column data line DL8, a ninth column data line DL9, a tenth column data line DL10, an eleventh column data line DL11, a twelfth column data line DL12, a thirteenth column data line DL13, a fourteenth column data line DL14, a fifteenth column data line DL15, a sixteenth column data line DL16, a seventeenth column data line DL17, and an eighteenth column data line DL18;

[0390] The source driver SD includes a first voltage output end CH1, a second voltage output end CH2 and a third voltage output end CH3;

[0391] The first voltage output end CH1, the second voltage output end CH2 and the third voltage output end CH3 are electrically connected to the input terminal of the multiplexing circuit 90 respectively;

[0392] end of the multiplexing circuit 90 is electrically connected to DL1, DL2, DL3, DL4, DL5, DL6, DL7, DL8, DL9, DL10, DL11, DL12, DL13, DL14, DL15, DL16, DL17 and DL18 respectively;

[0393] The multiplexing circuit 90 is electrically connected to the first multiplexing control end MX1, the second multiplexing control end MX2, the third multiplexing control end MX3, the fourth multiplexing control end MX4, the fifth multiplexing control end MX5 and the sixth multiplexing control end MX6, respectively, and is configured to control the connection or disconnection between each voltage output end and each data line under the control of the multiplexing control signal provided by each multiplexing control end.

[0394] In at least one embodiment of the present disclosure, the multiplexing circuit is electrically connected to N multiplexing control ends respectively, and the multiplexing circuit includes M multiplexing sub-circuits, where N and M are integers greater than 1;

[0395] Each of the multiplexing sub-circuits is electrically connected to the voltage output end of the source driver, the N multiplexing control ends and the N columns of data lines, and is configured to control the voltage signal provided by the voltage output end to be transmitted to the nth data line in the N columns of data lines under the control of the nth multiplexing control signal provided by the nth multiplexing control end; n is a positive integer less than or equal to N.

[0396] In a specific implementation, when the multiplexing circuit is electrically connected to N multiplexing control ends respectively, the multiplexing circuit may include M multiplexing sub-circuits; under the control of the nth multiplexing control signal, the multiplexing sub-circuit provides the voltage signal provided by the voltage output end of the source driver to the data line.

[0397] In one embodiment of the display panel shown in FIG. 19, the multiplexing circuit includes a first multiplexing sub-circuit 101, a second multiplexing sub-circuit 102 and a third multiplexing sub-circuit 103;

[0398] The first multiplexing sub-circuit 101 is electrically connected to the first multiplexing control end MX1, the second multiplexing control end MX2, the third multiplexing control end MX3, the fourth multiplexing control end MX4, the fifth multiplexing control end MX5 and the sixth multiplexing control end MX6, the first voltage output end CH1, the first column data line DL1, the fourth column data line DL4, the seventh column data line DL7, the tenth column data line DL10, the thirteenth column data line DL13 and the sixteenth column data line DL16, respectively, and is configured to control the connection between CH1 and DL1 under the control of the first multiplexing control signal provided by MX1. Under the control of the second multiplexing control signal provided by MX2, the connection between CH1 and DL4 is controlled; under the control of the third multiplexing control signal provided by MX3, the connection between CH1 and DL7 is controlled; under the control of the fourth multiplexing control signal provided by MX4, the connection between CH1 and DL10 is controlled; under the control of the fifth multiplexing control signal provided by MX5, the connection between CH1 and DL13 is controlled; under the control of the sixth multiplexing control signal provided by MX6, the connection between CH1 and DL16 is controlled;

[0399] The second multiplexing sub-circuit 102 is electrically connected to the first multiplexing control end MX1, the second multiplexing control end MX2, the third multiplexing control end MX3, the fourth multiplexing control end MX4, the fifth multiplexing control end MX5 and the sixth multiplexing control end MX6, the first voltage output end CH1, the second column data line DL2, the fifth column data line DL5, the eighth column data line DL8, the eleventh column data line DL11, the fourteenth column data line DL14 and the seventeenth column data line DL17, respectively, and is configured to control CH1 and DL2 under the control of the first multiplexing control signal provided by MX1. Under the control of the second multiplexing control signal provided by MX2, the connection between CH1 and DL5 is controlled; under the control of the third multiplexing control signal provided by MX3, the connection between CH1 and DL8 is controlled; under the control of the fourth multiplexing control signal provided by MX4, the connection between CH1 and DL11 is controlled; under the control of the fifth multiplexing control signal provided by MX5, the connection between CH1 and DL14 is controlled; under the control of the sixth multiplexing control signal provided by MX6, the connection between CH1 and DL17 is controlled;

[0400] The third multiplexing sub-circuit 103 is electrically connected to the first multiplexing control end MX1, the second multiplexing control end MX2, the third multiplexing control end MX3, the fourth multiplexing control end MX4, the fifth multiplexing control end MX5 and the sixth multiplexing control end MX6, the first voltage output end CH1, the third column data line DL3, the sixth column data line DL6, the ninth column data line DL9, the twelfth column data line DL12, the fifteenth column data line DL15 and the eighteenth column data line DL18, respectively, and is configured to control CH1 and DL3 under the control of the first multiplexing control signal provided by MX1. Under the control of the second multiplexing control signal provided by MX2, CH1 and DL6 are controlled to be connected or disconnected. Under the control of the third multiplexing control signal provided by MX3, CH1 and DL9 are controlled to be connected or disconnected. Under the control of the fourth multiplexing control signal provided by MX4, CH1 and DL12 are controlled to be connected or disconnected. Under the control of the fifth multiplexing control signal provided by MX5, CH1 and DL15 are controlled to be connected or disconnected. Under the control of the sixth multiplexing control signal provided by MX6, CH1 and DL18 are controlled to be connected or disconnected.

[0401] In one embodiment of the display panel shown in FIG. 20, the first multiplexing subcircuit may include a first multiplexing transistor T1, a second multiplexing transistor T2, a third multiplexing transistor T3, a fourth multiplexing transistor T4, a fifth multiplexing transistor T5, and a sixth multiplexing transistor T6;

[0402] The gate of T1 is electrically connected to MX1, the source of T1 is electrically connected to CH1, and the drain of T1 is electrically connected to DL1;

[0403] The gate of T2 is electrically connected to MX2, the source of T2 is electrically connected to CH1, and the drain of T2 is electrically connected to DL4;

[0404] The gate of T3 is electrically connected to MX3, the source of T3 is electrically connected to CH1, and the drain of T3 is electrically connected to DL7;

[0405] The gate of T4 is electrically connected to MX4, the source of T4 is electrically connected to CH1, and the drain of T4 is electrically connected to DL10;

[0406] The gate of T5 is electrically connected to MX5, the source of T5 is electrically connected to CH1, and the drain of T5 is electrically connected to DL13;

[0407] The gate of T6 is electrically connected to MX6, the source of T6 is electrically connected to CH1, and the drain of T6 is electrically connected to DL16;

[0408] The second multiplexing sub-circuit may include a seventh multiplexing transistor T7, an eighth multiplexing transistor T8, a ninth multiplexing transistor T9, a tenth multiplexing transistor T10, an eleventh multiplexing transistor T11 and a twelfth multiplexing transistor T12;

[0409] The gate of T7 is electrically connected to MX1, the source of T7 is electrically connected to CH2, and the drain of T7 is electrically connected to DL2;

[0410] The gate of T8 is electrically connected to MX2, the source of T8 is electrically connected to CH2, and the drain of T8 is electrically connected to DL5;

[0411] The gate of T9 is electrically connected to MX3, the source of T9 is electrically connected to CH2, and the drain of T9 is electrically connected to DL8;

[0412] The gate of T10 is electrically connected to MX4, the source of T10 is electrically connected to CH2, and the drain of T10 is electrically connected to DL11;

[0413] The gate of T11 is electrically connected to MX5, the source of T11 is electrically connected to CH2, and the drain of T11 is electrically connected to DL14;

[0414] The gate of T12 is electrically connected to MX6, the source of T12 is electrically connected to CH2, and the drain of T12 is electrically connected to DL17;

[0415] The third multiplexing sub-circuit may include a thirteenth multiplexing transistor T13, a fourteenth multiplexing transistor T14, a fifteenth multiplexing transistor T15, a sixteenth multiplexing transistor T16, a seventeenth multiplexing transistor T17 and an eighteenth multiplexing transistor T18;

[0416] The gate of T13 is electrically connected to MX1, the source of T13 is electrically connected to CH3, and the drain of T13 is electrically connected to DL3;

[0417] The gate of T14 is electrically connected to MX2, the source of T14 is electrically connected to CH3, and the drain of T14 is electrically connected to DL6;

[0418] The gate of T15 is electrically connected to MX3, the source of T15 is electrically connected to CH3, and the drain of T15 is electrically connected to DL9;

[0419] The gate of T16 is electrically connected to MX4, the source of T16 is electrically connected to CH3, and the drain of T16 is electrically connected to DL12;

[0420] The gate of T17 is electrically connected to MX5, the source of T17 is electrically connected to CH3, and the drain of T17 is electrically connected to DL15;

[0421] The gate of T18 is electrically connected to MX6, the source of T18 is electrically connected to CH3, and the drain of T18 is electrically connected to DL18.

[0422] In one embodiment of the display panel shown in FIG. 21, all transistors are p-type transistors, but the present invention is not limited thereto.

[0423] In one embodiment of the display panel shown in FIG. 21, DL1, DL4, DL7, DL10, DL13 and DL16 may be red data lines, DL2, DL5, DL8, DL11, DL14 and DL17 may be green data lines, and DL3, DL6, DL9, DL12, DL15 and DL18 may be blue data lines, but the present invention is not limited thereto;

[0424] The red data line may be a data line providing a data voltage for a red pixel circuit, the green data line may be a data line providing a data voltage for a green pixel circuit, and the blue data line may be a data line providing a data voltage for a blue pixel circuit.

[0425] When the one embodiment of the display panel shown in FIG. 21 of the present disclosure is in operation.

[0426] When MX1 provides a low voltage signal, MX2, MX3, MX4, MX5 and MX6 all output high voltage signals, T1, T7 and T13 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL1, CH2 is connected to DL2, and CH3 is connected to DL3;

[0427] When MX2 provides a low voltage signal, MX1, MX3, MX4, MX5 and MX6 all output high voltage signals, T2, T8 and T14 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL4, CH2 is connected to DL5, and CH3 is connected to DL6;

[0428] When MX3 provides a low voltage signal, MX1, MX2, MX4, MX5 and MX6 all output high voltage signals, T3, T9 and T15 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL7, CH2 is connected to DL8, and CH3 is connected to DL9;

[0429] When MX4 provides a low voltage signal, MX1, MX2, MX3, MX5 and MX6 all output high voltage signals, T4, T10 and T16 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL10, CH2 is connected to DL11, and CH3 is connected to DL12;

[0430] When MX5 provides a low voltage signal, MX1, MX2, MX3, MX4 and MX6 all output high voltage signals, T5, T11 and T17 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL13, CH2 is connected to DL14, and CH3 is connected to DL15;

[0431] When MX6 provides a low voltage signal, MX1, MX2, MX3, MX4 and MX5 all output high voltage signals, T6, T12 and T18 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL16, CH2 is connected to DL17, and CH3 is connected to DL18.

[0432] As shown in FIG. 22, when at least one embodiment of the display panel shown in FIG. 21 of the present disclosure is in operation, the display cycle includes a first writing time period XT1, a second writing time period XT2, a third writing time period XT3 and a light-emitting stage FT which are successively set;

[0433] The first writing time period XT1 includes a first data writing time period t11 and a second data writing time period t12 which are set successively;

[0434] The second writing time period XT2 includes a third data writing time period t21 and a fourth data writing time period t22 which are arranged successively;

[0435] The third writing time period XT3 includes a fifth data writing time period t31 and a sixth data writing time period t32 which are arranged successively;

[0436] In the first data writing period t11, MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals;

[0437] When MX1 outputs a low voltage signal, T1, T7 and T13 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL1, CH2 is connected to DL2, CH3 is connected to DL3, CH1 provides a first light-emitting time control data voltage to DL1, CH2 provides a second light-emitting time control data voltage to DL2, and CH3 provides a third light-emitting time control data voltage to DL3;

[0438] When MX2 outputs a low voltage signal, T2, T8 and T14 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL4, CH2 is connected to DL5, CH3 is connected to DL6, CH1 provides the fourth light-emitting time control data voltage to DL4, CH2 provides the fifth light-emitting time control data voltage to DL5, and CH3 provides the ninth light-emitting time control data voltage to DL6;

[0439] When MX3 outputs a low voltage signal, T3, T9 and T15 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL7, CH2 is connected to DL8, CH3 is connected to DL9, CH1 provides the fourth light-emitting time control data voltage to DL7, CH2 provides the fifth light-emitting time control data voltage to DL8, and CH3 provides the ninth light-emitting time control data voltage to DL9;

[0440] When MX4 provides a low voltage signal, T4, T10 and T16 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL10, CH2 is connected to DL11, CH3 is connected to DL12, CH1 provides the tenth light-emitting time control data voltage to DL10, CH2 provides the eleventh light-emitting time control data voltage to DL11, and CH3 provides the twelfth light-emitting time control data voltage to DL12;

[0441] When MX5 provides a low voltage signal, T5, T11 and T17 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL13, CH2 is connected to DL14, CH3 is connected to DL15, CH1 provides the thirteenth light-emitting time control data voltage to DL13, CH2 provides the fourteenth light-emitting time control data voltage to DL14, and CH3 provides the fifteenth light-emitting time control data voltage to DL15;

[0442] When MX6 provides a low voltage signal, T6, T12 and T18 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL16, CH2 is connected to DL17, CH3 is connected to DL18, CH1 provides the sixteenth light-emitting time control data voltage to DL16, CH2 provides the seventeenth light-emitting time control data voltage to DL17, and CH3 provides the eighteenth light-emitting time control data voltage to DL18;

[0443] Since each data line has a parasitic capacitor, each light-emitting time controls the data voltage to be charged to the parasitic capacitor of each data line;

[0444] In the second data writing period t12, RA provides a low voltage signal, RB provides a high voltage signal, and the first transistor M1 in the pixel circuit is turned on to write the light-emitting time control data voltage on each data line into the second control node N2;

[0445] In the third data writing period t21, MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals;

[0446] When MX1 outputs a low voltage signal, T1, T7 and T13 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL1, CH2 is connected to DL2, CH3 is connected to DL3, CH1 provides the nineteenth light-emitting time control data voltage to DL1, CH2 provides the twentieth light-emitting time control data voltage to DL2, and CH3 provides the twenty-first light-emitting time control data voltage to DL3;

[0447] When MX2 outputs a low voltage signal, T2, T8 and T14 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL4, CH2 is connected to DL5, CH3 is connected to DL6, CH1 provides the twenty-second light-emitting time control data voltage to DL4, CH2 provides the twenty-third light-emitting time control data voltage to DL5, and CH3 provides the twenty-fourth light-emitting time control data voltage to DL6;

[0448] When MX3 outputs a low voltage signal, T3, T9 and T15 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL7, CH2 is connected to DL8, CH3 is connected to DL9, CH1 provides the twenty-fifth light-emitting time control data voltage to DL7, CH2 provides the twenty-sixth light-emitting time control data voltage to DL8, and CH3 provides the twenty-seventh light-emitting time control data voltage to DL9;

[0449] When MX4 provides a low voltage signal, T4, T10 and T16 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL10, CH2 is connected to DL11, CH3 is connected to DL12, CH1 provides the 28th light-emitting time control data voltage to DL10, CH2 provides the 29th light-emitting time control data voltage to DL11, and CH3 provides the 30th light-emitting time control data voltage to DL12;

[0450] When MX5 provides a low voltage signal, T5, T11 and T17 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL13, CH2 is connected to DL14, CH3 is connected to DL15, CH1 provides a thirty-first light-emitting time control data voltage to DL13, CH2 provides a thirty-second light-emitting time control data voltage to DL14, and CH3 provides a thirty-third light-emitting time control data voltage to DL15;

[0451] When MX6 provides a low voltage signal, T6, T12 and T18 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL16, CH2 is connected to DL17, CH3 is connected to DL18, CH1 provides a thirty-fourth light-emitting time control data voltage to DL16, CH2 provides a thirty-fifth light-emitting time control data voltage to DL17, and CH3 provides a thirty-sixth light-emitting time control data voltage to DL18;

[0452] Since each data line has a parasitic capacitor, each light-emitting time controls the data voltage to be charged to the parasitic capacitor of each data line;

[0453] In the fourth data writing period t22, RB provides a low voltage signal, RA provides a high voltage signal, and M3 in the pixel circuit is turned on to write the light-emitting time control data voltage on each data line into the third control node N3;

[0454] In the fifth data writing period t31, MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals;

[0455] When MX1 outputs a low voltage signal, T1, T7 and T13 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL1, CH2 is connected to DL2, CH3 is connected to DL3, CH1 provides a first display data voltage to DL1, CH2 provides a second display data voltage to DL2, and CH3 provides a third display data voltage to DL3;

[0456] When MX2 outputs a low voltage signal, T2, T8 and T14 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL4, CH2 is connected to DL5, CH3 is connected to DL6, CH1 provides the fourth display data voltage to DL4, CH2 provides the fifth display data voltage to DL5, and CH3 provides the sixth display data voltage to DL6;

[0457] When MX3 outputs a low voltage signal, T3, T9 and T15 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL7, CH2 is connected to DL8, CH3 is connected to DL9, CH1 provides the seventh display data voltage to DL7, CH2 provides the eighth display data voltage to DL8, and CH3 provides the ninth display data voltage to DL9;

[0458] When MX4 provides a low voltage signal, T4, T10 and T16 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL10, CH2 is connected to DL11, CH3 is connected to DL12, CH1 provides the tenth display data voltage to DL10, CH2 provides the eleventh display data voltage to DL11, and CH3 provides the twelfth display data voltage to DL12;

[0459] When MX5 provides a low voltage signal, T5, T11 and T17 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL13, CH2 is connected to DL14, CH3 is connected to DL15, CH1 provides the thirteenth display data voltage to DL13, CH2 provides the fourteenth display data voltage to DL14, and CH3 provides the fifteenth display data voltage to DL15;

[0460] When MX6 provides a low voltage signal, T6, T12 and T18 are turned on, other multiplexed transistors are turned off, CH1 is connected to DL16, CH2 is connected to DL17, CH3 is connected to DL18, CH1 provides the sixteenth display data voltage to DL16, CH2 provides the seventeenth display data voltage to DL17, and CH3 provides the eighteenth display data voltage to DL18;

[0461] Since each data line has a parasitic capacitor, each light-emitting time controls the data voltage to be charged to the parasitic capacitor of each data line;

[0462] In the sixth data writing period t32, G1 provides a low voltage signal, and M6 and M7 in the pixel circuit are turned on to perform charging and threshold voltage compensation, thereby realizing display data voltage writing;

[0463] In the light-emitting stage FT, E1 provides a low voltage signal, and M5 is turned on to control the connection between the power voltage line VDD and the source of the driving transistor M0;

[0464] When performing medium and high grayscale display, M2 in the pixel circuit is turned on to control the connection between the first light-emitting control line E1 and the first control node N1;

[0465] When low grayscale display is performed, M4 in the pixel circuit is turned on to control the second light-emitting control line Hf to be connected to the first control node N1.

[0466] When the display substrate in at least one embodiment of the present disclosure is in operation, it can also control RA to provide a high voltage signal and RB to provide a low voltage signal in the second data writing time period, and control RA to provide a low voltage signal and RB to provide a high voltage signal in the fourth data writing time period.

[0467] In at least one embodiment of the present disclosure, the turn-on time of each multiplexed control end can be reduced, and the storage of the data voltage for controlling the luminous time on the data line can be completed quickly, so as to increase the turn-on time of RA, the turn-on time of RB and the turn-on time of G1, so as to provide more sufficient time for writing the data voltage inside the pixel circuit, charging and threshold voltage compensation.

[0468] In at least one embodiment of the present disclosure, through GOA (Gate On Array, array substrate row drive) timing control, all low-level stages of the second light-emitting control line Hf are in the light-emitting stage, thereby preventing the potential of the second light-emitting control signal from being pulled down by high frequency to cause coupling influence on the writing of the display data voltage and disturb the gate voltage of the driving transistor, thereby reducing one transistor for preventing the Hf coupling influence compared with the related pixel circuit.

[0469] In a specific implementation, due to the existence of parasitic capacitance on the data lines, the data lines may be coupled with each other and change the voltage.

[0470] As shown in FIG. 23, when performing medium and high grayscale display, if in the second data writing period, RB provides a low voltage signal and RA provides a high voltage signal, in the fourth data writing stage, RA provides a low voltage signal and RB provides a high voltage signal;

[0471] In the first data writing period t11, the data voltage Vdata connected to DL1 may be 18V;

[0472] In the third data writing period t21, the data voltage Vdata connected to DL1 may be 0V;

[0473] In the fifth data writing period t31, the data voltage Vdata connected to DL1 may be 13V;

[0474] When MX1 is turned on, DL1 writes the data voltage, and DL1 maintains the potential at the previous moment after MX1 is turned off, such as the ideal voltage VDL10 of DL1 in Figure 23. The 18V voltage signal and the 0V voltage signal are signals that control the access of the first light-emitting control line and the second light-emitting control line, respectively, and have little effect on the grayscale display. When the jump from 0V to 13V is the turn-on moment of G1, the voltage on DL1 will jump with the voltage on DL4, which will affect the data voltage writing and cause the write voltage to be a higher potential, thereby causing the pixels electrically connected to DL1 to display darker than expected.

[0475] In FIG. 23, VDL40 is the ideal voltage on DL4, and VDL1 is the actual voltage on DL1.

[0476] As shown in FIG. 24, when performing medium and high grayscale display, if in the second data writing period t12, RA provides a low voltage signal and RB provides a high voltage signal, in the fourth data writing period t22, RB provides a low voltage signal and RA provides a high voltage signal;

[0477] In the first data writing period t11, the data voltage Vdata connected to DL1 may be 0V;

[0478] In the third data writing period t21, the data voltage Vdata connected to DL1 may be 18V;

[0479] In the fifth data writing period t31, the data voltage Vdata connected to DL1 may be 13V;

[0480] Through the above settings, when G1 is turned on, the data voltage on DL1 jumps from 18V to 13V, which reduces the jump amplitude of the data voltage and improves the problem of pixel display differences.

[0481] As shown in FIG. 25, when at least one embodiment of the display panel shown in FIG. 21 of the present disclosure is in operation, a display cycle includes a first writing time period, a second writing time period, a third writing time period and a light-emitting stage FT which are successively set;

[0482] The first writing time period includes a first data writing time period t11 and a second data writing time period t12; the first data writing time period is included in the second data writing time period t12;

[0483] The second writing time period includes a third data writing time period t21 and a fourth data writing time period t22; the third data writing time period t21 is included in the fourth data writing time period t22; t31 and a sixth data writing time period t32 which are set successively;

[0484] In the first data writing time period t11, MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals, and the transistor controlled by MX1, the transistor controlled by MX2, the transistor controlled by MX3, the transistor controlled by MX4, the transistor controlled by MX5 and the transistor controlled by MX6 are sequentially turned on to write the corresponding light emission time control data voltage;

[0485] In the second data writing period t12, RA provides a low voltage signal, RB and G1 provide a high voltage signal, and the first transistor M1 in the pixel circuit is turned on to write the light emission time control data voltage on each data line into the second control node N2;

[0486] In the third data writing time period t21, MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals, and the transistor controlled by MX1, the transistor controlled by MX2, the transistor controlled by MX3, the transistor controlled by MX4, the transistor controlled by MX5 and the transistor controlled by MX6 are sequentially turned on to write the corresponding light emission time control data voltage;

[0487] In the fourth data writing period t22, RB provides a low voltage signal, RA and G1 provide a high voltage signal, and M3 in the pixel circuit is turned on to write the light-emitting time control data voltage on each data line into the third control node N3;

[0488] In the fifth data writing period t31, MX1, MX2, MX3, MX4, MX5 and MX6 sequentially output low voltage signals, and the transistors controlled by MX1, MX2, MX3, MX4, MX5 and MX6 are sequentially turned on to write corresponding display data voltages;

[0489] In the sixth data writing period t32, G1 provides a low voltage signal, RA and RB provide a high voltage signal, and M6 and M7 in the pixel circuit are turned on to perform charging and threshold voltage compensation to achieve display data voltage writing;

[0490] In the light-emitting stage FT, EM outputs a low voltage signal;

[0491] During a part of the time period included in the light-emitting phase FT, Hf outputs a low voltage signal;

[0492] When performing a medium to high grayscale display, in the light-emitting stage FT, the driving transistor M0 in the pixel circuit drives the micro light-emitting diode ML to emit light;

[0493] When low grayscale display is performed, in the light-emitting stage FT, when Hf provides a low voltage signal, the driving transistor M0 in the pixel circuit drives the micro light-emitting diode ML to emit light.

[0494] In FIG. 25, the light-emitting control line labeled E1_N is the next row adjacent to E1.

[0495] In the related art, current + time control is usually configured to emit light for a short time at a fixed current to achieve low grayscale display. However, after emitting light for a short time within a frame display time, the LED (light-emitting diode) enters a black state, and the human eye can clearly feel the flicker, causing discomfort to the viewer. Based on this, at least one embodiment of the present disclosure provides a pixel circuit that controls the light emission time at high frequency, disperses the short light emission time into a frame time, and reduces flicker.

[0496] In at least one embodiment of the present disclosure, since the light control signal provided by E1 continues to be a low voltage signal for a relatively long time, the light control signal provided by Hf is a high-frequency pulse signal during the entire time that E1 continues to be a low voltage signal.

[0497] FIG. 26 is an operation timing diagram of a display panel according to at least one embodiment of the present disclosure.

[0498] In Figure 26, ESTV is the first starting voltage, ECK is the first clock signal, ECB is the second clock signal, GSTV is the second starting voltage, GCK is the third clock signal, GCB is the fourth clock signal, Hf is the second light-emitting control line, MX1 is the first multiplexing control end, MX2 is the second multiplexing control end, MX3 is the third multiplexing control end, MX4 is the fourth multiplexing control end, MX5 is the fifth multiplexing control end, MX6 is the sixth multiplexing control end, and Vdata is the data voltage.

[0499] The driving method in the present disclosure is applied to the above-mentioned display panel, wherein the display period includes a first writing time period and a second writing time period; the first writing time period includes a first data writing time period and a second data writing time period, and the second writing time period includes a third data writing time period and a fourth data writing time period; the driving method includes: in a first data writing time period, the multiplexing sub-circuit writing the first control voltage provided by the source driver through the source driver's voltage output end into the data line under the control of the reset control signal; in the second data writing time period, the first control circuit provides the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controls whether to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node; in a third data writing time period, the multiplexing sub-circuit writing the second control voltage provided by the source driver through the source driver's voltage output end into the data line under the control of the reset control signal; in the fourth data writing time period, the second control circuit writes the second control voltage provided by the data line to the third control node under the control of the second reset control signal, and the second control circuit controls whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

[0500] In at least one embodiment of the present disclosure, the first data writing time period and the second data writing time period are set successively, and the third data writing time period and the fourth data writing time period are set successively; or,

[0501] The first data writing time period is included in the second data writing time period, and the third data writing time period is included in the fourth data writing time period.

[0502] The display device described in the embodiment of the present disclosure includes the above-mentioned display panel.

[0503] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit, comprising a light-emitting element and a pixel driving circuit; the pixel driving circuit comprises a driving circuit, a first light-emitting control circuit, a first control circuit, a second control circuit and a data writing circuit; the driving circuit is configured to generate a driving current for driving the light-emitting element; the first light-emitting control circuit is electrically connected to a first control node, a first end of the driving circuit and the light-emitting element, and is configured to control a connection between the first end of the driving circuit and the light-emitting element under a control of a potential of the first control node; the first control circuit is electrically connected to a data line, a first reset control line, a first light-emitting control line, the first control node and the second control node, and is configured to provide a first control voltage provided by the data line to the second control node under a control of a first reset control signal provided by the first reset control line, and control the first light-emitting control line to provide a first light-emitting control signal to the first control node under a control of a potential of the second control node; the second control circuit is electrically connected to the data line, a second reset control line, a second light-emitting control line, the first control node and a third control node, and is configured to write a second control voltage provided by the data line into the third control node under a control of a second reset control signal provided by the second reset control line, and control the second light-emitting control line to provide a second light-emitting control signal to the first control node under a control of a potential of the third control node; the data writing circuit is electrically connected to a scan line, the data line and a second end of the driving circuit, and is configured to a the display data voltage provided by the data line into the second end of the driving circuit under a control of a scan signal provided by the scan line; the first control circuit, the second control circuit and the data writing circuit are configured to access the corresponding voltage signal on the data line in a time-sharing manner; a pulse width of the scanning signal, a pulse width of the first reset control signal and a pulse width of the second reset control signal are the same; or at least two of the pulse width of the scanning signal, the pulse width of the first reset control signal and the pulse width of the second reset control signal are different.

2. The pixel circuit according to claim 1, wherein the scan line, the first reset control line and the second reset control line are electrically connected to different GOA circuits in the same GOA module, and respectively access driving signals provided by the different GOA circuits; or the scanning line, the first reset control line, and the second reset control line are respectively electrically connected to a GOA circuit in different GOA modules, and respectively access the driving signals provided by the GOA circuit in the GOA modules; or, two of the scan line, the first reset control line, and the second reset control line are electrically connected to different GOA circuits in the first GOA module, and respectively access the driving signals provided by different GOA circuits in the first GOA module; the other of the scan line, the first reset control line, and the second reset control line is electrically connected to a GOA circuit in the second GOA module, and access a driving signal provided by the GOA circuit in the second GOA module.

3. The pixel circuit according to claim 1 or 2, wherein the first control circuit comprises a first writing control circuit, a first energy storage circuit and a second writing control circuit; the first writing control circuit is electrically connected to a first reset control line, the data line and a second control node, and is configured to provide the first control voltage provided by the data line to the second control node under a control of the first reset control signal; the first energy storage circuit is electrically connected to the second control node and is used for an energy storage circuit; the second writing control circuit is electrically connected to the second control node, the first light-emitting control line and the first control node respectively, and is configured to control the first light-emitting control line to provide a first light-emitting control signal to the first control node under the control of the potential of the second control node.

4. The pixel circuit according to claim 1 or 2, wherein the second control circuit comprises a third writing control circuit, a second energy storage circuit and a fourth writing control circuit; the third writing control circuit is electrically connected to the second reset control line, the data line and the third control node, and writes the second control voltage provided by the data line into the third control node under the control of the second reset control signal; the second energy storage circuit is electrically connected to the third control node and is configured to store electrical energy; the fourth writing control circuit is electrically connected to the third control node, the second light-emitting control line and the first control node, and is configured to control the second light-emitting control line to provide a second light-emitting control signal to the first control node under a control of the potential of the third control node.

5. The pixel circuit according to claim 3, wherein the first writing control circuit comprises a first transistor, the first energy storage circuit comprises a first capacitor, and the second writing control circuit comprises a second transistor; a gate of the first transistor is electrically connected to the first reset control line, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the second control node; a first plate of the first capacitor is electrically connected to the second control node, and a second plate of the first capacitor is electrically connected to the first initial voltage line; a gate of the second transistor is electrically connected to the second control node, a first electrode of the second transistor is electrically connected to the first light-emitting control line, and a second electrode of the second transistor is electrically connected to the first control node.

6. The pixel circuit according to claim 4, wherein the third writing control circuit comprises a third transistor, the second energy storage circuit comprises a second capacitor, and the fourth writing control circuit comprises a fourth transistor; a gate of the third transistor is electrically connected to the second reset control line, a first electrode of the third transistor is electrically connected to the data line, and a second electrode of the third transistor is electrically connected to the third control node; a first plate of the second capacitor is electrically connected to the third control node, and a second plate of the second capacitor is electrically connected to the second initial voltage line; a gate of the fourth transistor is electrically connected to the third control node, a first electrode of the fourth transistor is electrically connected to the second light-emitting control line, and a second electrode of the fourth transistor is electrically connected to the first control node.

7. The pixel circuit according to claim 1, further comprising a second light-emitting control circuit; the second light-emitting control circuit is electrically connected to the first light-emitting control line, a power voltage line and a second end of the driving circuit, and is configured to control a connection between the power voltage line and the second end of the driving circuit under the control of the first light-emitting control signal.

8. The pixel circuit according to claim 1 or 2, further comprising a compensation control circuit and a third energy storage circuit; the compensation control circuit is electrically connected to the scan line, the control end of the driving circuit and the first end of the driving circuit, and is configured to control the control end of the driving circuit to be connected to the first end of the driving circuit under the control of the scan signal; the third energy storage circuit is electrically connected to the control end of the driving circuit and is used for storing electric energy.

9. The pixel circuit according to claim 1 or 2, further comprising a first reset circuit; the first reset circuit is electrically connected to a third reset control line, a third initial voltage line and a control end of the driving circuit, and is configured to write the third initial voltage provided by the third initial voltage line into the control end of the driving circuit under a control of a third reset control signal provided by the third reset control line.

10. The pixel circuit according to claim 9, further comprising a second reset circuit; the second reset circuit is electrically connected to a fourth reset control line, a fourth initial voltage line and the first electrode of the light-emitting element, and is configured to write a fourth initial voltage provided by the fourth initial voltage line into the first electrode of the light-emitting element under the control of a fourth reset control signal provided by the fourth reset control line; a second electrode of the light-emitting element is electrically connected to the first voltage line.

11. The pixel circuit according to claim 10, wherein the third reset control line is the first reset control line or the second reset control line; the fourth reset control line is the first reset control line or the second reset control line.

12. The pixel circuit according to claim 7, wherein the second light emission control circuit comprises a fifth transistor; a gate of the fifth transistor is electrically connected to the first light-emitting control line, a first electrode of the fifth transistor is electrically connected to the power voltage line, and a second electrode of the fifth transistor is electrically connected to the second end of the driving circuit.

13. The pixel circuit according to claim 8, wherein the data writing circuit comprises a sixth transistor, the compensation control circuit comprises a seventh transistor, the third energy storage circuit comprises a third capacitor; and the driving circuit comprises a driving transistor; a gate of the sixth transistor is electrically connected to the scan line, a first electrode of the sixth transistor is electrically connected to the data line, and a second electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor; a gate of the seventh transistor is electrically connected to the scan line, the first electrode of the seventh transistor is electrically connected to the gate of the driving transistor, and the second electrode of the seventh transistor is electrically connected to the first electrode of the driving transistor; a first plate of the third capacitor is electrically connected to the gate of the driving transistor, and the second plate of the third capacitor is electrically connected to the power voltage line.

14. The pixel circuit according to claim 9, wherein the first reset circuit comprises an eighth transistor; a gate of the eighth transistor is electrically connected to the third reset control line, a first electrode of the eighth transistor is electrically connected to the third initial voltage line, a the second electrode of the eighth transistor is electrically connected to the control end of the driving circuit.

15. The pixel circuit according to claim 10, wherein the second reset circuit comprises a ninth transistor; a gate of the ninth transistor is electrically connected to the fourth reset control line, a first electrode of the ninth transistor is electrically connected to the fourth initial voltage line, and a second electrode of the ninth transistor is electrically connected to a first electrode of the light-emitting element.

16. The pixel circuit according to claim 1 or 2, comprising a multiplexing control circuit; the multiplexing control circuit is electrically connected to the multiplexing control end, the voltage output end of the source driver and the data line respectively, and is configured to control the connection between the voltage output end and the data line under the control of the multiplexing control signal provided by the multiplexing control end.

17. A driving method, applied to the pixel circuit according to any one of claims 1 to 16, wherein the display phase comprises a first writing phase and a second writing phase; the driving method comprises: in a first writing phase, the first control circuit providing the first control voltage provided by the data line to the second control node under a control of the first reset control signal, and the first control circuit controlling whether to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node; in a second writing stage, the second control circuit writing the second control voltage provided by the data line into the third control node under the control of the second reset control signal, and the second control circuit controlling whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

18. The driving method according to claim 17, comprising: when performing medium and high grayscale display, in the first writing stage, the first control circuit controlling the first light-emitting control signal to the first control node under a control of the potential of the second control node, and in the second writing stage, the second control circuit controlling the second light-emitting control signal to be stopped from being provided to the first control node under the control of the potential of the third control node; when performing low grayscale display, in the first writing stage, the first control circuit stopping controlling a provision of the first light-emitting control signal to the first control node under the control of the potential of the second control node, and in the second writing stage, the second control circuit controlling a provision of the second light-emitting control signal to the first control node under the control of the potential of the third control node.

19. A display substrate comprising a base substrate and a plurality rows and columns of the pixel circuits according to any one of claims 1 to 16 arranged in a display area on the base substrate.

20. The display substrate according to claim 19, wherein the pixel circuits in the same column are arranged between two columns of data lines; the data lines extend along the first direction; the pixel circuit of the a-th row is arranged between the a-th row scanning line and the a-th row first voltage line, wherein a is a positive integer; the a-th row of scan line and the a-th row of first voltage line extend along a second direction; the first direction and the second direction intersect.

21. The display substrate according to claim 19, wherein the pixel circuit comprises a light-emitting element and a pixel driving circuit; a gap is provided between at least two adjacent pixel driving circuits in the second direction, and at least one of the light-emitting elements is provided in the gap; an orthographic projection of the light-emitting element on the base substrate does not overlap with the pixel driving circuit on the base substrate.

22. The display substrate according to claim 21, further comprising a first signal line; most of the signal lines of the first signal line extend along the second direction; the first signal line is bent around the light-emitting element to form a first avoidance space, and at least a part of the light-emitting element is disposed in the first avoidance space.

23. The display substrate according to claim 22, comprising a plurality of rows of light-emitting units, wherein the light-emitting units comprise at least three of the light-emitting elements; a gap is bent toward the first side around at least one of the light-emitting elements in the odd-numbered rows of light-emitting units to form a first avoidance space; a gap is bent toward the second side around at least one of the light-emitting elements in the light-emitting units of even rows to form another first avoidance space; the first side and the second side are opposite sides.

24. The display substrate according to claim 19, wherein the pixel circuit comprises a light-emitting element and a pixel driving circuit; the light-emitting element is arranged on a side of the pixel driving circuit away from the base substrate; an orthographic projection of the light-emitting element on the base substrate at least partially overlaps with an orthographic projection of the pixel driving circuit on the base substrate.

25. The display substrate according to claim 19, further comprising a light-emitting control signal generating module and a second signal line, wherein the light-emitting control signal generating module comprises a multi-stage light-emitting control signal generating circuit; and the light-emitting control signal generating circuit is arranged in the display area; the display substrate comprises a plurality of rows and columns of pixel driving groups, and the pixel driving group comprises at least one pixel driving circuit; at least one level of the light-emitting control signal generating circuit is located between adjacent pixel driving groups; most of the signal line included in the second signal lines extend along the first direction; at least one of the second signal lines is bent around the at least one level of light-emitting control signal generating circuit to form a second avoidance space, and a part of the at least one level of light-emitting control signal generating circuit is arranged in the second avoidance space.

26. The display substrate according to claim 25, wherein an orthographic projection of the light-emitting control signal generating circuit on the base substrate does not overlap with an orthographic projection of the pixel driving group on the base substrate.

27. The display substrate according to claim 19, further comprising a gate driving module, wherein the gate driving module comprises a multi-stage gate driving circuit; the gate driving circuit is arranged in the display area; the display substrate comprises a plurality of rows and columns of pixel driving groups, and the pixel driving group comprises at least one pixel driving circuit; at least one level of the gate driving circuit is located between adjacent pixel driving groups.

28. The display substrate according to claim 27, further comprising a second signal line; most of the signal lines of the second signal line extend along the first direction; at least one of the second signal lines is bent around the at least one gate driving circuit to form a third avoidance space, and a part of the at least one gate driving circuit is disposed in the third avoidance space.

29. The display substrate according to claim 27 or 28, wherein an orthographic projection of the gate driving circuit on the base substrate does not overlap with an orthographic projection of the pixel driving group on the base substrate.

30. A display panel comprising the display substrate according to any one of claims 19 to 29.

31. The display panel according to claim 30, further comprising a source driver, a plurality of column data lines and a multiplexing circuit; a plurality of pixel circuits located in the same column are electrically connected to the data line in the same column; the multiplexing circuit is electrically connected to multiple voltage output ends, multiple multiplexing control ends and the multiple columns of data lines of the source driver respectively, and is configured to write the voltage signal provided by the source driver through its voltage output end into the data line under the control of the multiplexing control signal provided by the multiplexing control end.

32. The display panel according to claim 31, wherein the multiplexing circuit is electrically connected to N multiplexing control ends respectively, the multiplexing circuit comprises M multiplexing sub-circuits, and N and M are integers greater than 1; each of the multiplexing sub-circuits is electrically connected to the voltage output end of the source driver, the N multiplexing control ends and the N columns of data lines, and is configured to control the voltage signal provided by the voltage output end to be transmitted to the nth data line in the N columns of data lines under the control of the nth multiplexing control signal provided by the nth multiplexing control end; n is a positive integer less than or equal to N.

33. A driving method, applied to the display panel according to claim 31 or 32, wherein the display period comprises a first writing time period and a second writing time period; the first writing time period comprises a first data writing time period and a second data writing time period, and the second writing time period comprises a third data writing time period and a fourth data writing time period; the driving method comprises: in a first data writing time period, the multiplexing sub-circuit writing the first control voltage provided by the source driver through the source driver's voltage output end into the data line under the control of the reset control signal; in the second data writing time period, the first control circuit providing the first control voltage provided by the data line to the second control node under the control of the first reset control signal, and the first control circuit controlling whether to provide the first light-emitting control signal to the first control node under the control of the potential of the second control node; in a third data writing time period, the multiplexing sub-circuit writing the second control voltage provided by the source driver through the source driver's voltage output end into the data line under the control of the reset control signal; in the fourth data writing time period, the second control circuit writing the second control voltage provided by the data line to the third control node under the control of the second reset control signal, and the second control circuit controlling whether to provide the second light-emitting control signal to the first control node under the control of the potential of the third control node.

34. The driving method according to claim 33, wherein the first data writing time period and the second data writing time period are arranged successively, and the third data writing time period and the fourth data writing time period are arranged successively; or the first data writing time period is included in the second data writing time period, and the third data writing time period is included in the fourth data writing time period.

35. A display device comprising the display panel according to any one of claims 30 to 32.

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