Capacitive micromachined ultrasonic transducer and manufacturing methods thereof

Abstract

Systems, devices, methods, and processes relating to a capacitive machined ultrasound transducer (CMUT) are provided. A process of fabricating a CMUT includes: (a) applying a thermal silicon oxide layer to a first silicon wafer; (b) performing a patterned etch of the silicon oxide layer; and (c) repeating step (b) one or more times to create a silicon oxide structure on the first silicon wafer. The process can further include: (d) performing a thermal oxide application after the steps are formed; (e) removing oxide bulge formed during step (a) from one or more of the one or more corners; and (f) attaching a second silicon wafer to the silicon oxide structure to form a CMUT cell with an interior cavity.

Description

[0001] CAPACITIVE MICROMACHINED ULTRASONIC TRANSDUCER AND MANUFACTURING METHODS THEREOF

[0002] DESCRIPTION

[0003] Related Applications

[0004]

[0001] This application claims benefit of United States Provisional Patent Application Serial Number 63 / 450,490 (Docket No. USD-010-PR1), titled “Capacitive Micromachined Ultrasonic Transducer and Manufacturing Methods Thereof’, filed March 7, 2023, the content of which is incorporated herein by reference in its entirety for all purposes.

[0005]

[0002] This application claims benefit of United States Provisional Patent Application Serial Number 63 / 556,111 (Docket No. USD-011-PR1), titled “Ultrasound System”, filed February 21, 2024, the content of which is incorporated herein by reference in its entirety for all purposes.

[0006]

[0003] This application is related to United States Provisional Application Serial Number 62 / 728,616, (Docket No. USD-001-PR), titled “Medical Device with CMUT Array and Solid State Cooling, and Associated Methods and Systems - with Thermal Analysis”, filed September 7, 2018, the content of which is incorporated by reference in its entirety for all purposes.

[0007]

[0004] This application is related to United States Application Serial Number 16 / 130,896, (Docket no. USD-001 -US), titled “Medical Device with CMUT Array and Solid State Cooling, and Associated Methods and Systems”, filed September 13, 2018, United States Patent Number 11,154,730, issued October 26, 2021, the content of which is incorporated by reference in its entirety for all purposes.

[0008]

[0005] This application is related to United States Patent Application Serial Number 17 / 479,011 (Docket No. USD-001-US-CON1), titled “Medical Device with CMUT Array and Solid State Cooling, And Associated Methods and Systems”, filed September 20, 2021, United States Publication Number US2022 / 0072338, published March 10, 2022, the content of which is incorporated herein by reference in its entirety for all purposes.

[0009]

[0006] This application is related to International PCT Patent Application Serial Number PCT / US2018 / 050943, (Docket No. USD-001-PCT), titled “Medical Device with CMUT Array and Solid State Cooling, and Associated Methods and Systems” filed September 13, 2018, Publication Number WO 2019 / 055699, published March 21, 2019, the content of which is incorporated by reference in its entirety for all purposes.

[0010]

[0007] This application is related to United States Provisional Patent Application Serial Number 63 / 126,078 (Docket No. USD-003-PR1), titled “Tissue Interface System”, filed December 16, 2020, the content of which is incorporated herein by reference in its entirety for all purposes.

[0011]

[0008] This application is related to United States Application Serial Number 18 / 039,978, (Docket no. USD-003-US), titled “Tissue Interface System”, filed June 2, 2023, United States Publication Number US 2023 / 0414299, published December 28, 2023, the content of which is incorporated by reference in its entirety for all purposes.

[0012]

[0009] This application is related to International PCT Patent Application Serial Number PCT / US2021 / 063743, (Docket No.USD-003 -PCT), titled “Tissue Interface System”, filed December 16, 2021, Publication Number WO 2022 / 133054, published June 23, 2022, the content of which is incorporated by reference in its entirety for all purposes.

[0013]

[0010] This application is related to United States Provisional Patent Application Serial Number 63 / 195,292 (Docket No. USD-004-PR1), titled “Tissue Treatment System”, filed June 1, 2021, the content of which is incorporated herein by reference in its entirety for all purposes.

[0014]

[0011] This application is related to United States Application Serial Number 18 / 564,181, (Docket no. USD-004-US), titled “Tissue Treatment System”, filed November 27, 2023, United States Publication Number , published , the content of which is incorporated by reference in its entirety for all purposes.

[0015]

[0012] This application is related to International PCT Patent Application Serial Number PCT / US22 / 031746, (Docket No.USD-004-PCT), titled “Tissue Treatment System”, filed June 1, 2022, Publication Number WO 2022 / 256388, published December 8, 2022, the content of which is incorporated by reference in its entirety for all purposes.

[0016]

[0013] This application is related to United States Provisional Patent Application Serial Number 63 / 286,161 (Docket No. USD-008-PR1), titled “Capacitive Micromachined Ultrasonic Transducer”, filed December 6, 2021, the content of which is incorporated herein by reference in its entirety for all purposes.

[0017]

[0014] This application is related to International PCT Patent Application Serial Number PCT / US22 / 051937, (Docket No. USD-008-PCT), titled “Capacitive Micromachined Ultrasonic Transducer” filed December 6, 2022, Publication Number WO 2023 / 107433, published June 15, 2023, the content of which is incorporated by reference in its entirety for all purposes.

[0018] Field of the Inventive Concepts

[0019]

[0015] The present inventive concepts relate generally to ultrasonic transducers, such as capacitive micromachined ultrasonic transducers (CMUTs).

[0020] BACKGROUND

[0021]

[0016] Capacitive Micromachined Ultrasonic Transducers (CMUTs) are an alternative to piezoelectric ultrasonic transducers. CMUTs can be used in a variety of applications, including medical imaging, other imaging, therapeutics, high intensity focused ultrasound (HIFU), and chemical sensing applications. CMUTs can be used to transmit and / or receive ultrasound. CMUTs used to transmit ultrasound energy have a transmit output pressure. CMUTs used in receiving applications have a receive sensitivity. Improvements to transmit output pressure and / or receive sensitivity for CMUTs are desirable.

[0022] SUMMARY

[0023]

[0017] Embodiments of the systems, devices, and methods described herein can be directed to systems, devices, and methods for a capacitive machined ultrasound transducer (CMUT).

[0024]

[0018] According to an aspect of the present inventive concepts, a process of fabricating a CMUT comprises: (a) applying a thermal silicon oxide layer to a first silicon wafer; (b) performing a patterned etch of the silicon oxide layer; and (c) repeating step (b) one or more times to create a silicon oxide structure on the first silicon wafer. The silicon oxide structure can include one or more steps.

[0025]

[0019] In some embodiments, the process further comprises (d) performing a thermal oxide application after the steps are formed.

[0020] According to another aspect of the present inventive concepts, a process of fabricating a CMUT comprises: (a) applying a thermal silicon oxide layer to a first silicon wafer; (b) performing a patterned etch of the oxide layer; (c) repeating steps (a) and (b) to form a silicon oxide structure on the first silicon wafer, such that the silicon oxide structure includes one or more steps; and (d) performing a thermal oxide application after the steps are formed, wherein the etchings of the repeated steps (b) results in an exposed portion of the first silicon wafer.

[0026]

[0021] In some embodiments, the silicon oxide structure that includes steps comprises a dielectric layer of the CMUT.

[0027]

[0022] In some embodiments, the one or more steps comprise one or more corners, and the process further comprises: (e) removing oxide bulge formed during step (a) from one or more of the one or more comers. Step (e) can be performed with a patterned etch. Step (e) can be performed prior to step (d). Step (e) can be performed after step (d). The silicon oxide structure can further comprise one or more supports each comprising one or more comers. Step (e) can include removing the oxide bulge formed during step (a) from one or more of the comers of the one or more supports.

[0028]

[0023] In some embodiments, the process further comprises (f) attaching a second silicon wafer to the silicon oxide structure to form a CMUT cell with an interior cavity. The process can further comprise applying an oxide layer to the second silicon wafer prior to step (f). The oxide layer on the second silicon wafer can comprise a thickness of at least lOnm and / or no more than lOOnm. The oxide layer can be positioned on the second silicon wafer toward the interior of the cavity of the CMUT.

[0029]

[0024] In some embodiments, the first silicon wafer comprises one or more corners, and at least one corner can comprise a non-sharp geometry.

[0030]

[0025] According to another aspect of the present inventive concepts, a device comprises one or more CMUTs of the present inventive concepts. The device can comprise a medical device. The sensor can comprise two or more sensors in a redundant arrangement. The sensor can comprise a first set of the one or more CMUTs and a second set of the one or more CMUTs, and the first set and the second set can be configured in a redundant arrangement. The sensor can comprise two or more CMUT arrays, and each CMUT array can comprise at least one of the one or more CMUTs. The two or more CMUT arrays can comprise a first CMUT array in a first configuration and a second CMUT array in a second configuration that is different than the first configuration. The first array can include a first CMUT with a first configuration, and the second array can include a second CMUT with a second configuration that is different than the first configuration. The first CMUT can comprise a first bottom electrode configuration and a first plate configuration, the second CMUT can comprise a second bottom electrode configuration and a second plate configuration, and the first plate configuration can be different than the second plate configuration and / or the first bottom electrode configuration can be different than the second bottom electrode configuration. The first array and the second array can comprise different geometric arrangement of CMUTs, different types of CMUTs, and / or different quantity of CMUTs.

[0031]

[0026] The technology described herein, along with the attributes and attendant advantages thereof, will best be appreciated and understood in view of the following detailed description taken in conjunction with the accompanying drawings in which representative embodiments are described by way of example.

[0032] Incorporation by Reference

[0033]

[0027] All publications, patents, and patent applications mentioned in this specification are herein incorporated by reference to the same extent as if each individual publication, patent, or patent application was specifically and individually indicated to be incorporated by reference. The content of all publications, patents, and patent applications mentioned in this specification are herein incorporated by reference in their entirety for all purposes.

[0034] BRIEF DESCRIPTION OF THE DRAWINGS

[0035]

[0028] Fig. 1 illustrates a schematic view of a system including a device with at least one capacitive micromachined ultrasonic transducer (CMUT), consistent with the present inventive concepts.

[0036]

[0029] Figs. 1A and IB illustrate cross-sectional views of two examples of current (e.g. commercially available) CMUT structures, consistent with the present inventive concepts.

[0030] Fig. 2 illustrates a top view of a plate of a CMUT including a sensing electrode, consistent with the present inventive concepts.

[0037]

[0031] Fig. 3 illustrates an array of transducers comprising CMUT components and sensing transducers, consistent with the present inventive concepts.

[0038]

[0032] Figs. 4A-5D illustrate various cross-sectional views of CMUT component configurations comprising shaped plates, consistent with the present inventive concepts.

[0033] Figs. 6A-6I illustrate various charts and graphs of CMUT output and other performance characteristics, consistent with the present inventive concepts.

[0039]

[0034] Figs. 7A-10D illustrate various cross-sectional views of piston-based CMUT components comprising shaped plates and / or shaped bottom electrodes, consistent with the present inventive concepts.

[0040]

[0035] Figs. 11A-20 illustrate various charts and graphs of CMUT output and other performance characteristics, consistent with the present inventive concepts.

[0041]

[0036] Figs. 21A-28D illustrate various cross-sectional views of CMUT components configured for use in airborne applications and comprising shaped plates and / or shaped bottom electrodes, consistent with the present inventive concepts.

[0042]

[0037] Figs. 29A-29D illustrate top views of a portion of CMUT components including fluidic trenches in various patterns, consistent with the present inventive concepts.

[0043]

[0038] Figs. 30A-30Y illustrate various charts and graphs of CMUT output and other performance characteristics, consistent with the present inventive concepts.

[0044]

[0039] Fig. 31 illustrates a cross-sectional view of an embodiment of a CMUT with a shaped dielectric, consistent with the present inventive concepts.

[0045]

[0040] Fig. 31A illustrates a schematic representing the capacitance of a CMUT, consistent with the present inventive concepts.

[0046]

[0041] Figs. 31B and 31C illustrate cross-sectional views of various CMUT components comprising shaped dielectric layers, consistent with the present inventive concepts.

[0047]

[0042] Fig. 32 illustrates a cross-sectional view of a CMUT comprising a multi-layer dielectric, consistent with the present inventive concepts.

[0048]

[0043] Fig. 33 illustrates a set of steps of a method of manufacturing a CMUT with a stepped profile dielectric layer, consistent with the present inventive concepts.

[0049]

[0044] Fig. 34 illustrates a set of steps of a method of manufacturing a CMUT with a stepped profile bottom electrode and a stepped profile dielectric layer, consistent with the present inventive concepts.

[0050]

[0045] Figs. 35A-35D illustrate cross-sectional views of CMUT configurations to be analyzed and graphs of transmit and receive sensitivity of the illustrated CMUT configurations, consistent with the present inventive concepts.

[0051]

[0046] Fig. 36 illustrates a set of steps of a method of manufacturing a CMUT comprising a shaped bottom electrode, consistent with the present inventive concepts.

[0047] Fig. 37 illustrates a set of steps of a method of forming a sloping silicon layer, consistent with the present inventive concepts.

[0052]

[0048] Fig. 38 illustrates a set of steps of a method of forming a shaped silicon layer, consistent with the present inventive concepts.

[0053]

[0049] Fig. 39 illustrates a set of steps of a method of fabricating a CMUT with a shaped plate, consistent with the present inventive concepts.

[0054]

[0050] Fig. 40 illustrates a set of steps of a method of fabricating a CMUT with a shaped bottom electrode, consistent with the present inventive concepts.

[0055]

[0051] Fig. 41 illustrates a set of steps of a method of fabricating a CMUT with a shaped bottom electrode, consistent with the present inventive concepts.

[0056]

[0052] Fig. 42 illustrates a set of steps of a method of fabricating CMUTs with shaped plates, consistent with the present inventive concepts.

[0057]

[0053] Fig. 43 illustrates a set of steps of a method of fabricating top plates for a CMUT, consistent with the present inventive concepts.

[0058]

[0054] Fig. 44 illustrates a set of steps of a method of fabricating top plates for a CMUT, consistent with the present inventive concepts.

[0059]

[0055] Figs. 45A-45D illustrate sectional schematic views of various CMUT designs, and graphs of CMUT performance, consistent with the present inventive concepts.

[0060]

[0056] Figs. 46A-46N illustrate various examples of the geometry of a component before and after an oxidation process to be used in the fabrication of CMUTs, consistent with the present inventive concepts.

[0061]

[0057] Figs. 47A and 47B illustrate top and side views, respectively, of a CMUT plate including a solid piston, consistent with the present inventive concepts.

[0062]

[0058] Figs. 48A and 48B illustrate top and side views, respectively, of a CMUT plate including a non-solid piston, consistent with the present inventive concepts.

[0063]

[0059] Fig. 49 illustrates a series of steps of a method of manufacturing a CMUT with a shaped profile, consistent with the present inventive concepts.

[0064]

[0060] Fig. 50 illustrates another series of steps of a method of manufacturing a CMUT with a shaped profile, consistent with the present inventive concepts.

[0065]

[0061] Figs. 51A and 51B illustrate a set of steps of a method of fabricating a CMUT with a shaped bottom electrode, consistent with the present inventive concepts.

[0066]

[0062] Fig. 52 illustrates a set of steps of a method of fabricating a CMUT with a shaped bottom electrode, consistent with the present inventive concepts.

[0063] Figs. 53A-54B illustrate various top and side views of different embodiments of CMUT arrays, consistent with the present inventive concepts.

[0067]

[0064] Figs. 55A and 55B illustrate sectional views of embodiments of CMUTs including micropillars, consistent with the present inventive concepts.

[0068]

[0065] Fig. 56 illustrates a top view of a CMUT array, consistent with the present inventive concepts.

[0069] DETAILED DESCRIPTION OF THE DRAWINGS

[0070]

[0066] Reference will now be made in detail to the present embodiments of the technology, examples of which are illustrated in the accompanying drawings. Similar reference numbers may be used to refer to similar components. However, the description is not intended to limit the present disclosure to particular embodiments, and it should be construed as including various modifications, equivalents, and / or alternatives of the embodiments described herein.

[0071]

[0067] It will be understood that the words "comprising" (and any form of comprising, such as "comprise" and "comprises"), "having" (and any form of having, such as "have" and "has"), "including" (and any form of including, such as "includes" and "include") or "containing" (and any form of containing, such as "contains" and "contain") when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0072]

[0068] It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various limitations, elements, components, regions, layers and / or sections, these limitations, elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one limitation, element, component, region, layer or section from another limitation, element, component, region, layer or section. Thus, a first limitation, element, component, region, layer or section discussed below could be termed a second limitation, element, component, region, layer or section without departing from the teachings of the present application.

[0073]

[0069] It will be further understood that when an element is referred to as being "on", "attached", "connected" or "coupled" to another element, it can be directly on or above, or connected or coupled to, the other element, or one or more intervening elements can be present. In contrast, when an element is referred to as being "directly on", "directly attached", "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g. "between" versus "directly between," "adjacent" versus "directly adjacent," etc.).

[0074]

[0070] As used herein, the terms “operably attached”, “operably connected”, “operatively coupled” and similar terms related to attachment of components shall refer to attachment of two or more components that results in one, two, or more of: electrical attachment; fluid attachment; magnetic attachment; mechanical attachment; optical attachment; sonic attachment; and / or other operable attachment arrangements. The operable attachment of two or more components can facilitate the transmission between the two or more components of: power; signals; electrical energy; fluids or other flowable materials; magnetism; mechanical linkages; light; sound such as ultrasound; and / or other materials and / or components.

[0075]

[0071] It will be further understood that when a first element is referred to as being "in", "on" and / or "within" a second element, the first element can be positioned: within an internal space of the second element, within a portion of the second element (e.g. within a wall of the second element); positioned on an external and / or internal surface of the second element; and combinations of one or more of these.

[0076]

[0072] As used herein, the term “proximate”, when used to describe proximity of a first component or location to a second component or location, is to be taken to include one or more locations near to the second component or location, as well as locations in, on and / or within the second component or location. For example, a component positioned proximate an anatomical site (e.g. a target tissue location), shall include components positioned near to the anatomical site, as well as components positioned in, on and / or within the anatomical site.

[0073] Spatially relative terms, such as "beneath," "below," "lower," "above," "upper" and the like may be used to describe an element and / or feature's relationship to another element(s) and / or feature(s) as, for example, illustrated in the figures. It will be further understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientation depicted in the figures. For example, if the device in a figure is turned over, elements described as "below" and / or "beneath" other elements or features would then be oriented "above" the other elements or features. The device can be otherwise oriented (e.g. rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0074] The terms “reduce”, “reducing”, “reduction” and the like, where used herein, are to include a reduction in a quantity, including a reduction to zero. Reducing the likelihood of an occurrence shall include prevention of the occurrence. Correspondingly, the terms “prevent”, “preventing”, and “prevention” shall include the acts of “reduce”, “reducing”, and “reduction”, respectively.

[0077]

[0075] The term "and / or" where used herein is to be taken as specific disclosure of each of the two specified features or components with or without the other. For example "A and / or B" is to be taken as specific disclosure of each of (i) A, (ii) B and (iii) A and B, just as if each is set out individually herein.

[0078]

[0076] The term “one or more”, where used herein can mean one, two, three, four, five, six, seven, eight, nine, ten, or more, up to any number.

[0079]

[0077] The terms “and combinations thereof’ and “and combinations of these” can each be used herein after a list of items that are to be included singly or collectively. For example, a component, process, and / or other item selected from the group consisting of: A; B; C; and combinations thereof, shall include a set of one or more components that comprise: one, two, three or more of item A; one, two, three or more of item B; and / or one, two, three, or more of item C.

[0080]

[0078] In this specification, unless explicitly stated otherwise, “and” can mean “or”, and “or” can mean “and”. For example, if a feature is described as having A, B, or C, the feature can have A, B, and C, or any combination of A, B, and C. Similarly, if a feature is described as having A, B, and C, the feature can have only one or two of A, B, or C.

[0081]

[0079] As used herein, when a quantifiable parameter is described as having a value “between” a first value X and a second value Y, it shall include the parameter having a value of: at least X, no more than Y, and / or at least X and no more than Y. For example, a length of between 1 and 10 shall include a length of at least 1 (including values greater than 10), a length of less than 10 (including values less than 1), and / or values greater than 1 and less than 10.

[0082]

[0080] The expression “configured (or set) to” used in the present disclosure may be used interchangeably with, for example, the expressions “suitable for”, “having the capacity to”, “designed to”, “adapted to”, “made to” and “capable of’ according to a situation. The expression “configured (or set) to” does not mean only “specifically designed to” in hardware. Alternatively, in some situations, the expression “a device configured to” may mean that the device “can” operate together with another device or component.

[0081] As used herein, the term “threshold” refers to a maximum level, a minimum level, and / or range of values correlating to a desired or undesired state. In some embodiments, a system parameter is maintained above a minimum threshold, below a maximum threshold, within a threshold range of values, and / or outside a threshold range of values, such as to cause a desired effect (e.g. efficacious therapy) and / or to prevent or otherwise reduce (hereinafter “prevent”) an undesired event (e.g. a device and / or clinical adverse event). In some embodiments, a system parameter is maintained above a first threshold (e.g. above a first temperature threshold to cause a desired therapeutic effect to tissue) and below a second threshold (e.g. below a second temperature threshold to prevent undesired tissue damage). In some embodiments, a threshold value is determined to include a safety margin, such as to account for patient variability, system variability, tolerances, and the like. As used herein, “exceeding a threshold” relates to a parameter going above a maximum threshold, below a minimum threshold, within a range of threshold values and / or outside of a range of threshold values.

[0083]

[0082] As described herein, “room pressure” shall mean pressure of the environment surrounding the systems and devices of the present inventive concepts. Positive pressure includes pressure above room pressure or simply a pressure that is greater than another pressure, such as a positive differential pressure across a fluid pathway component such as a valve. Negative pressure includes pressure below room pressure or a pressure that is less than another pressure, such as a negative differential pressure across a fluid component pathway such as a valve. Negative pressure can include a vacuum but does not imply a pressure below a vacuum. As used herein, the term “vacuum” can be used to refer to a full or partial vacuum, or any negative pressure as described hereabove.

[0084]

[0083] The term “diameter” where used herein to describe a non-circular geometry is to be taken as the diameter of a hypothetical circle approximating the geometry being described. For example, when describing a cross section, such as the cross section of a component, the term “diameter” shall be taken to represent the diameter of a hypothetical circle with the same cross-sectional area as the cross section of the component being described.

[0085]

[0084] The terms “major axis” and “minor axis” of a component where used herein are the length and diameter, respectively, of the smallest volume hypothetical cylinder which can completely surround the component.

[0086]

[0085] As used herein, the term “functional element” is to be taken to include one or more elements constructed and arranged to perform a function. A functional element can comprise a sensor and / or a transducer. In some embodiments, a functional element is configured to deliver energy and / or otherwise treat tissue (e.g. a functional element configured as a treatment element). Alternatively or additionally, a functional element (e.g. a functional element comprising a sensor) can be configured to record one or more parameters, such as a patient physiologic parameter; a patient anatomical parameter (e.g. a tissue geometry parameter); a patient environment parameter; and / or a system parameter. In some embodiments, a sensor or other functional element is configured to perform a diagnostic function (e.g. to gather data used to perform a diagnosis). In some embodiments, a functional element is configured to perform a therapeutic function (e.g. to deliver therapeutic energy and / or a therapeutic agent). In some embodiments, a functional element comprises one or more elements constructed and arranged to perform a function selected from the group consisting of: deliver energy; extract energy (e.g. to cool a component); deliver a drug or other agent; manipulate a system component or patient tissue; record or otherwise sense a parameter such as a patient physiologic parameter or a system parameter; and combinations of one or more of these. A functional element can comprise a fluid and / or a fluid delivery system. A functional element can comprise a reservoir, such as an expandable balloon or other fluid-maintaining reservoir. A “functional assembly” can comprise an assembly constructed and arranged to perform a function, such as a diagnostic and / or therapeutic function. A functional assembly can comprise an expandable assembly. A functional assembly can comprise one or more functional elements.

[0087]

[0086] The term “transducer” where used herein is to be taken to include any component or combination of components that receives energy or any input, and produces an output. For example, a transducer can include an electrode that receives electrical energy, and distributes the electrical energy to tissue (e.g. based on the size of the electrode). In some configurations, a transducer converts an electrical signal into any output, such as: light (e.g. a transducer comprising a light emitting diode or light bulb), sound (e.g. a transducer comprising a piezo crystal configured to deliver ultrasound energy); pressure (e.g. an applied pressure or force); heat energy; cryogenic energy; chemical energy; mechanical energy (e.g. a transducer comprising a motor or a solenoid); magnetic energy; and / or a different electrical signal (e.g. different than the input signal to the transducer). Alternatively or additionally, a transducer can convert a physical quantity (e.g. variations in a physical quantity) into an electrical signal. A transducer can include any component that delivers energy and / or an agent to tissue, such as a transducer configured to deliver one or more of: electrical energy to tissue (e.g. a transducer comprising one or more electrodes); light energy to tissue (e.g. a transducer comprising a laser, light emitting diode and / or optical component such as a lens or prism); mechanical energy to tissue (e.g. a transducer comprising a tissue manipulating element); sound energy to tissue (e.g. a transducer comprising a piezo crystal); chemical energy; electromagnetic energy; magnetic energy; and combinations of one or more of these.

[0087] As used herein, the term “fluid” can refer to a liquid, gas, gel, or any flowable material, such as a material which can be propelled through a lumen and / or opening.

[0088]

[0088] As used herein, the term “material” can refer to a single material, or a combination of two, three, four, or more materials.

[0089]

[0089] It is appreciated that certain features of the inventive concepts, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the inventive concepts which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination. For example, it will be appreciated that all features set out in any of the claims (whether independent or dependent) can be combined in any given way.

[0090]

[0090] It is to be understood that at least some of the figures and descriptions of the inventive concepts have been simplified to focus on elements that are relevant for a clear understanding of the inventive concepts, while eliminating, for purposes of clarity, other elements that those of ordinary skill in the art will appreciate may also comprise a portion of the inventive concepts. However, because such elements are well known in the art, and because they do not necessarily facilitate a better understanding of the inventive concepts, a description of such elements is not provided herein.

[0091]

[0091] Terms defined in the present disclosure are only used for describing specific embodiments of the present disclosure and are not intended to limit the scope of the present disclosure. Terms provided in singular forms are intended to include plural forms as well, unless the context clearly indicates otherwise. All of the terms used herein, including technical or scientific terms, have the same meanings as those generally understood by an ordinary person skilled in the related art, unless otherwise defined herein. Terms defined in a generally used dictionary should be interpreted as having meanings that are the same as or similar to the contextual meanings of the relevant technology and should not be interpreted as having ideal or exaggerated meanings, unless expressly so defined herein. In some cases, terms defined in the present disclosure should not be interpreted to exclude the embodiments of the present disclosure.

[0092]

[0092] Provided herein are capacitive micromachined ultrasound transducers (CMUTs), as well as methods of CMUT manufacture, and devices and systems into which these CMUTs are integrated. The CMUT can include an electrode; and a plate covering the electrode to form a cavity. The electrode can comprise a contoured electrode and / or the plate can comprise a contoured plate. A voltage applied across the electrode and the plate deflects the plate. The cavity comprises a non-uniform cavity spacing between the plate and the electrode, the cavity spacing being largest within a central region of the plate.

[0093]

[0093] Referring now to Fig. 1, a schematic view of a system including a device with at least one capacitive micromachined ultrasonic transducer (CMUT) is illustrated, consistent with the present inventive concepts. System 10 of Fig. 1 includes various components, such as one or more devices, device 100 shown. Device 100 can comprise one or more ultrasound sensors, such as US sensor 500, also shown. Device 100 can also include processing unit 110, and user interface 120, each as described herein. Device 100 can include functional element 199, as shown. Functional element 199 can comprise one or more sensors, one or more transducers, and / or one or more other functional elements. Device 100 can comprise a consumer electronic device such as a cellphone, a tablet, a personal computer, and / or other electronic device. In some embodiments, device 100 comprises a medical device, such as a medical device selected from the group consisting of a device that delivers ultrasound energy to tissue (e.g. to stimulate tissue, ablate tissue, and / or image tissue); a drug delivery device; a cardiac pacing device; a nerve ablation device; and combinations of these. In some embodiments, device 100 comprises a medical device that is configured to deliver ultrasound energy (e.g. via one or more CMUTs of CMUT 510), where the ultrasound energy is configured to image tissue, ablate tissue, or both image and ablate tissue.

[0094]

[0094] US Sensor 500 of the present inventive concepts can comprise one or more CMUT components (or CMUT “cells” herein), CMUT 510 shown. CMUT 510 and / or other components of sensor 500 can be constructed and arranged as described in reference to Figs. 1, 1A, or any of Figs. 2 thru 50. CMUT 510 can be manufactured using one or more of the following processes: an oxidation process; an etching process; and / or a doping process, such as are described herein. In some embodiments, US sensor 500 comprises electronic assemblies and / or other components that are operably attached to CMUT 510, drive circuitry 520. Drive circuitry 520 can comprise power sources, signal generators, data converters (e.g. analog to digital and / or digital to analog data converters), and / or other components configured to operate CMUT 510 in the various modes of operation described herein. In some embodiments, sensor 500 comprises an array of two or more CMUTs 510, array 5010. CMUT 510 can be configured for use in immersion applications (e.g. when CMUT 510 comprises at least one or more sealed CMUT transducers) and / or airborne applications (e.g. when CMUT 510 comprises at least one or more air-coupled CMUT transducers).

[0095]

[0095] Capacitive micromachined ultrasonic transducers (CMUTs) have emerged as an alternative to piezoelectric-based ultrasound transducers in various applications, such as: medical imaging, therapeutics, high intensity focused ultrasound (HIFU), chemical sensing, and air-coupled applications. Currently available CMUT transducers include combinations of flat plates and flat electrodes that have been widely used in CMUT -based components. The plate of a CMUT deflects significantly when a large direct current (DC) voltage and / or an alternative current (AC) voltage is applied for achieving high sensitivities and / or high output pressure. When the plate deflects, only the central region, a small part of the whole plate, experiences the maximum electrical field. This limitation results in reduced electromechanical coupling efficiency and thus both limited transmit and receive sensitivities.

[0096] In some embodiments, device 100 comprises processing unit 110. Processing unit 110 can comprise at least one microprocessor, computer, and / or another electronic controller, processor 111 shown. Processing unit 110 can also include one, two, or more algorithms, algorithm 115. Algorithm 115 can comprise one or more machine learning, neural network, and / or other artificial intelligence algorithms (“Al algorithm” herein). Processing unit 110 can comprise one or more memory storage modules, memory 112 shown, such as for storing instructions for performing algorithm 115 and / or for storing other system 10 information (e.g. calibration and / or other manufacturing information, and / or system 10 use information). Processor 111, via algorithm 115, can perform one or more of the processes described herein, such as a process performed in response to one or more commands the user inputs into system 10 (e.g. via user interface 120 described herein). In some embodiments, algorithm 115 (e.g. an Al algorithm) is configured to adjust the drive signals produced by drive circuitry 520, such as to optimize or otherwise modify the performance of CMUT 510 (e.g. a CMUT 510 comprising one or more CMUTs 510). In some embodiments, algorithm 115 is configured to analyze one or more parameters of a patient that is receiving ultrasound energy from CMUT 510, such as one, two, or more physiologic parameters recorded by a functional element 199 comprising one, two, or more sensors. In these embodiments, algorithm 115 can be configured to adjust the drive signals produced by drive circuitry 520, such as to improve an image and / or improve a treatment provided by device 100. Processing unit 110 can receive one or more signals (e.g. signals comprising data), such as signals received from US sensor 500. Processing unit 110 can be configured to perform one or more mathematical operations based on the received signals, and to produce a result. Processing unit 110 can be configured to perform and / or facilitate the performance of (either or both “perform” herein) one or more functions of system 10, such as to perform: energy deliveries (e.g. ultrasonic energy delivery via US sensor 500 such as to ablate or stimulate tissue); data collections (e.g. image data creation and / or collection); data analyses; signal processing; procedure planning; and / or other functions (singly or collectively “system 10 functions” herein).

[0096]

[0097] Device 100 can include one, two, or more interfaces for providing and / or receiving information to and / or from a user of system 10, user interface 120 shown. User interface 120 can include one, two, or more user input and / or user output components. For example, user interface 120 can comprise a joystick, keyboard, mouse, touchscreen, and / or another human interface device, user input device 121 shown. In some embodiments, user interface 120 comprises a display (e.g. a touchscreen display), such as display 122, also shown. In some embodiments, processor 111 can provide a graphical user interface, GUI 123, to be presented on and / or provided by display 122. User interface 120 can include an input and / or output device selected from the group consisting of a speaker; an indicator light, such as an LED indicator; a haptic feedback device; a foot pedal; a switch such as a momentary switch; a microphone; a camera, for example when processor 111 enables eye tracking and / or other input via image processing; and combinations of these.

[0097]

[0098] CMUT 510 is described herein in reference to the corresponding orientation shown in the figures. For example, when referencing the bottom of CMUT 510, the portion of CMUT 510 positioned toward the bottom of the page is being described. A CMUT can consist of a “plate” suspended over a “bottom electrode”, with a space therebetween (e.g. a vacuum gap and / or a fluid filled space). For example, CMUT 510 can comprise a first conductive layer, bottom electrode 511 (also referred to herein as substrate 511), and a second conductive layer, plate 512 (also referred to herein as top electrode 512). Bottom electrode 511 and plate 512 can be axially separated defining a space therebetween, cavity 513 (e.g. a cavity maintained at vacuum or other negative pressure as compared to environmental pressure). In some embodiments, an insulating layer, dielectric layer 514 is positioned between bottom electrode 511 and plate 512. For example, a dielectric layer 514 can be positioned on substrate 511, a dielectric layer 514 can be positioned on plate 512, or two dielectric layers 514 can be included, a first layer 514a positioned on substrate 511 and a second layer 514b positioned on plate 512. In embodiments with a single dielectric layer 514, the layer 514 can comprise a thickness of at least 5nm or lOnm and / or a thickness of no more than 800nm, 600nm, or 400nm, such as a thickness of approximately 200nm. In embodiments, with a first dielectric layer 514a (e.g. positioned on substrate 511), and a second dielectric 514b (e.g. positioned on plate 512), the layer 514a can comprise a thickness of at least 5nm or lOnm and / or a thickness of no more than 800nm, 600nm, or 400nm, and the dielectric 514b can comprise a thickness of at least 2nm or 5nm and / or a thickness of no more than 250nm or 150nm. Either or both layers can comprise silicon dioxide. In some embodiments, dielectric layer 514 comprises two layers with a combined thickness of no more than 1050nm, 800nm, 600nm or 400nm. Each dielectric layer 514 can comprise a minimum thickness (e.g. at least 5nm) such as to reduce field emission (e.g. electrons passing thru cavity 513). In some embodiments, plate 512 comprises a shaped plate 512s which comprises a plate 512 comprising a shaped (“shaped”, “contoured” and / or “non-flat”) geometry as described herein. In some embodiments, bottom electrode 511 comprises a shaped bottom electrode 511s (e.g. also referred to as shaped substrate 511s) which comprises a bottom electrode 511 comprising a shaped (“shaped”, “contoured” and / or “nonflat”) geometry as described herein. In some embodiments, dielectric layer 514 comprises a shaped dielectric layer 514s (also referred to as “shaped layer 514s) which comprises a dielectric layer 514 comprising a shaped (“shaped”, “contoured” and / or “non-flat”) geometry as described herein. For example, dielectric layer 514 can be positioned on the top surface of bottom electrode 511 (at the bottom of cavity 513), or on the bottom surface of plate 512 (at the top of cavity 513). In some embodiments, the axial spacing between bottom electrode 511 and plate 512 is maintained by one or more supports, support 515 shown. Support 515 can comprise a hollow ring (e.g. a circular ring) that can be positioned along the perimeter of electrode 511 and plate 512, such that cavity 513 is positioned within support 515.

[0098]

[0099] Substrate 511 can be constructed of one, two, or more of various similar and / or dissimilar materials, such as silicon and / or glass. In some embodiments, substrate 511 comprises a thickness that is no more than 70%, 60%, 50%, and / or 40% of the length of the smallest wavelength of the operating frequencies of the associated CMUT 510. In some embodiments, substrate 511 comprises a thickness that is less than 50% of the length of the smallest wavelength of the operating frequencies, such as to reduce the effect of acoustic resonances in the substrate on CMUT 510 performance.

[0099]

[0100] Cavity 513 can comprise one, two, or more forms of cross-sectional geometries, such as circle, oval, rectangle, square, hexagon, triangle, and combinations of one, two, or more of these. Cavity 513 can comprise a height of at least lOnm, 25nm, or 40nm, and / or a height of no more than 5pm, 7pm, and / or 10pm. In some embodiments, cavity 513 comprises a height of at least lOOnm, and / or no more than 500nm.

[0100]

[0101] Dielectric layer 514 can comprise one, two, or more of various similar and / or dissimilar materials, such as silicon oxide and / or silicon nitride (e.g. a multi-layer construction comprises both silicon nitride and silicon oxide). Dielectric layer 514 can comprise a material with a high dielectric constant value (“k value”), such as hafnium oxide. Dielectric layer 514 can comprise a thickness that is determined such that the maximum electric field experienced by the dielectric layer 514 during operation is a particular fraction of the dielectric strength of the layer 514, such as a fraction of at least 15%, 22%, or 30% and / or a fraction of no more than 40%, 50%, 60%, 70%, 77% or 85% of the dielectric strength of the layer 514.

[0101]

[0102] Support 515 can comprise one, two, or more of various similar and / or dissimilar materials, such as silicon oxide and / or silicon nitride. In some embodiments, a first support 515a comprises a first material, and a second support 515b comprises a second material, different than the first material.

[0102]

[0103] Plate 512 can be constructed of one, two, or more of various similar and / or dissimilar materials, such as silicon, silicon nitride, and / or diamond. In some embodiments, plate 512 comprises a thickness that is at least 0.2%, 0.5%, or 1% of the width of cavity 513, and / or a thickness that is no more than 20%, 30%, or 40% of the width of the cavity.

[0103]

[0104] In some embodiments, plate 512 comprises two or more layers, such as at least one conductive layer (e.g. a layer forming a top electrode) and one or more non-conductive layers. For example, plate 512 can comprise a stack of two non-conductive layers with a conductive layer therebetween. The edges of plate 512 can be attached to support 515. Plate 512 is configured to axially deflect toward and / or away from bottom electrode 511. In some embodiments, plate 512 deflects in response to a driven electric signal applied between bottom electrode 511 and top electrode 512 (e.g. when CMUT 510 is configured in a “transmit mode”). As used herein, a signal (e.g. an AC signal, a DC signal, and / or a signal comprising AC and DC components) that is applied (e.g. by processing unit 110) between top plate 512 and bottom electrode 511 can be described as being applied “across” CMUT 510. Alternatively or additionally, an electric signal can be generated between bottom electrode 511 and top electrode 512 (e.g. and received by processing unit 110) as one or more pressure waves received by CMUT 510 cause plate 512 to deflect axially (e.g. oscillate with respect to bottom electrode 511 when CMUT 510 is configured in a “receive mode”).

[0104]

[0105] The performance of CMUT 510 can be defined by one or more metrics, such as the transmit sensitivity, receive sensitivity, and / or the maximum output pressure. Transmit sensitivity can be defined as the pressure output per volt applied across CMUT 510. Receive sensitivity can be defined as the output current from CMUT 510 referenced to the incident pressure of the pressure wave causing actuation (e.g. deflection) of plate 512 (e.g. the output current per Pascal of incident pressure). The maximum output pressure is defined as the maximum pressure a CMUT 510 can produce while operating in its transmit mode. As described herein, the edges of plate 512 can be fixed to support 515, such that the axial movement at the edges of plate 512 is zero, and the axial movement of plate 512 is greatest in the center of CMUT 510 (furthest from the fixed edges). The maximum output pressure of a CMUT (e.g. CMUT 510) can be limited by the height of cavity 513 (e.g. the “gap height”).

[0105]

[0106] In some embodiments, the maximum output pressure of CMUT 510 can be increased if a larger portion of plate 512 is displaced when a signal is applied to CMUT 510 (e.g. greater average displacement for the same maximum displacement). The average displacement of plate 512 is determined by the geometry and / or properties of the materials of CMUT 510, as described herein. In some embodiments, CMUT 510 comprises a contoured (e.g. including one, two, or more stepped, curved, and / or other non-flat portions) electrode, shaped electrode 511s, that results in an increased average displacement of plate 512 due to the increased electrostatic forces applied to the outer portion of plate 512 relative to its center. Alternatively or additionally, CMUT 510 can include a contoured (e.g. including one, two, or more stepped, curved, and / or other non-flat portions) plate, shaped plate 512s, to similarly achieve these increased electrostatic forces upon plate 512. In some embodiments, electrode 511 and / or plate 512 comprise at least one planar portion, at least one concave portion, and / or at least one convex portion. The shaped plate 512s allows for a decreased gap height near the edges of plate 512 relative to the center of plate 512. This decrease in gap height increases the electric field near the edges of plate 512, resulting in increased electrostatic forces, such as at least a 2%, 5%, 20%, 25%, and / or 50% increase in electrostatic forces as compared to a similar component (e.g. a component of similar size or materials of construction) that comprises a non-contoured (e.g. flat) geometry. A decrease in gap height can increase the transmit sensitivity (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%), as the average plate displacement per volt is increased. A decreased gap height can also increase the receive sensitivity (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%), as the change in capacitance due to movement of plate 512 is greater. The increased transmit and receive sensitivities of these shaped designs of the present inventive concepts is achieved without physically limiting the maximum displacement of plate 512, thus without limiting the maximum output pressure of CMUT 510 (e.g. as compared to a CMUT geometry including a flat electrode 511 and flat plate 512, which achieves increased sensitivity as gap height is increased, but at the expense of decreasing maximum output pressure). Examples of CMUT 510 assemblies and other components including a plate 512 comprising a shaped profile are described in reference to various figures provided and described herein.

[0106]

[0107] Each of shaped plate 512s and / or shaped substrate 511s can comprise a contoured (shaped) profile comprising a “stepped profile”, such as a stepped profile that includes: at least 2 levels (e.g. at least 2 steps), at least 3 levels, or at least 4 levels. In some embodiments, shaped plate 512s comprises a stepped portion (e.g. stepped portion 5123 described herein) that is constructed and arranged as described in reference to Figs. 4B, 5A, 8 A, 10A, 22A, 24A, 26A, 28 A, and / or otherwise herein. Alternatively or additionally, substrate 511s can comprise a stepped portion (e.g. stepped portion 5113 described herein) profile that is constructed and arranged as described in reference to Figs. 7B, 9B, 12B, 23B, 25B, and / or otherwise herein. In some embodiments, one or more (e.g. all) of the steps of a shaped plate 512s and / or a shaped substrate 511s comprise a thickness that is at least 5% or at least 10% of the height of the gap of cavity 513 of CMUT 510. In some embodiments, one or more (e.g. all) of the steps of a shaped plate 512s and / or a shaped substrate 511s comprise a thickness that is no more than 50%, 60%, or 70% of the thickness of plate 512. One or more (e.g. all) of the steps of a shaped plate 512s and / or a shaped substrate 511s can comprise one, two, or more of various similar and / or dissimilar materials, such as silicon. The steps of a shaped plate 512s and / or a shaped substrate 511s can comprise the same or different materials as the remaining portion of the shaped plate 512s and / or the shaped substrate 511s, respectively. In some embodiments, the transition between at least a pair of steps comprises a transition that is smoothed and / or rounded. In some embodiments, two or more steps have approximately an equal width. In some embodiments, two or more steps have approximately an equal width, while a center step (e.g. the step closest to the center of cavity 513) has a larger width, such as a width approximately twice the width of the two or more steps with approximately an equal width. In some embodiments, one or more “comers” (e.g. the comers closer to the middle of cavity 513) of one or more steps are positioned at locations proximate but just below the maximum deflection profile of plate 512, so that these steps produce a large effect without impeding deflection of plate 512.

[0107]

[0108] Each of shaped plate 512s and / or shaped substrate 511s can comprise a contoured (shaped) profile comprising a “sloped profile” including one or more portions with a tapered, or sloping geometry. In some embodiments, shaped plate 512s comprises a sloped portion (e.g. sloped portion 5124 described herein) that is constructed and arranged as described in reference to Figs. 4C, 5B, 8B, 10B, 22B, 24B, 26B, 28B, and / or otherwise herein. Alternatively or additionally, substrate 511s can comprise a sloped portion (e.g. sloped portion 5114 described herein) that is constructed and arranged as described in reference to Figs. 7C, 9C, 12C, 23C, 25C, and / or otherwise herein. The sloped portion of a shaped plate 512s and / or a shaped substrate 511s can comprise the same or different materials as the remaining portion of the shaped plate 512s and / or the shaped substrate 511s, respectively.

[0108]

[0109] Each of shaped plate 512s and / or shaped substrate 511s can comprise a contoured (shaped) profile comprising a “curved profile” including one or more portions with a curved geometry. In some embodiments, shaped plate 512s comprises a curved portion (e.g. curved portion 5125 described herein) that is constructed and arranged as described in reference to Figs. 4D-E, 5C-D, 8C-D, 10C-D, 22C-D, 24C-D, 26C-D, 28C-D, and / or otherwise herein. Alternatively or additionally, substrate 511s can comprise a curved portion (e.g. curved portion 5115 described herein) that is constructed and arranged as described in reference to Figs. 7D-E, 9D-E, 12D-E, 23D-E, 25D-E, and / or otherwise herein. The curved portion of a shaped plate 512s and / or a shaped substrate 511s can comprise the same or different materials as the remaining portion of the shaped plate 512s and / or the shaped substrate 511s, respectively.

[0109]

[0110] In some embodiments, CMUT 510 has increased (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%) average displacement of plate 512 based on the geometry (e.g. the thickness) and / or the physical properties (e.g. the permittivity) of dielectric layer 514. Examples of CMUT 510 components comprising variations to dielectric layer 514 are described in reference to Figs. 31-35B and otherwise herein.

[0110]

[0111] Device 100 can comprise a device (e.g., a medical device) that comprises a sensor 500 comprising multiple sensors 500 that are in a redundant arrangement, such as when image signals received by a first sensor 500a are compared to signals received by a second sensor 500b, such as a comparison to confirm integrity of the image signals received. Alternatively or additionally, a device 100 can comprise a device (e.g., a medical device) in which one or more sensors 500 each include multiple sets of CMUTs 510 that are in a redundant arrangement, such as when image signals received by a first set of CMUTs 510 are compared to signals received by a second set of CMUTs 510, such as a comparison to confirm integrity of the image signals received.

[0111]

[0112] Device 100 (e.g., a medical device) can comprise one or more sensors 500 that each include one or more arrays 5010. In these embodiments, each array 5010 of one or more CMUTs 510 can include a first CMUT 510a of a particular configuration, and at least a second CMUT 510b of a different configuration. For example, the different configurations of the CMUT 510 can comprise differences in the geometry and / or size of bottom electrode 511 and / or plate 512. Alternatively or additionally, device 100 can comprise one or more sensors 500 that each include one, two, or more arrays 5010, in which a first array 5010a has a different configuration than at least a second array 5010b. For example, the different configurations of the arrays 5010 can comprise: differences in the geometric arrangement of CMUTs 510; differences in the type of CMUTs 510 (e.g., differences in the components, geometry, and / or other configuration of the CMUTs 510); and / or differences in the quantity of CMUTs 510.

[0112]

[0113] Referring additionally to Figs. 1A and IB, cross-sectional views of two examples of current (e.g. commercially available) CMUT structures are illustrated, consistent with the present inventive concepts. Fig. 1A shows a CMUT 510’ which includes a substrate, substrate 511 comprising a conductive material (e.g. doped silicon), and an insulating layer, dielectric layer 514, which is positioned on substrate 511 and comprises a dielectric material (e.g. silicon nitride). Support 515 extends vertically from dielectric layer 514 and also comprises a dielectric material (e.g. silicon nitride). Plate 512 is positioned on top of support 515, such that cavity 513 is formed between dielectric layer 514 and plate 512. Plate 512 of CMUT 510’ comprises a multi-layer construction, and includes a first conductive layer, layer 5121, that comprises a conductive material (e.g. aluminum), and a first insulative layer, layer 5122, that comprises a dielectric material (e.g. silicon nitride). Layer 5121 can comprise a construction and arrangement to avoid significant impact of layer 5121 on plate 512. In some embodiments, layer 5121 comprises a thickness that is less than 50%, 40%, or 33% of the thickness of plate 512. Layer 5121 can comprise one, two, or more of various materials, such as similar and / or different materials. In some embodiments, layer 5121 comprises one, two, or more materials selected from the group consisting of aluminum; titanium; chromium; gold; aluminum containing copper and / or silicon (e.g. up to 2% copper and / or silicon); indium tin oxide and / or other transparent conductive material; and combinations of these. Layer 5121 can comprise a multi-layer construction, such as a layer of titanium and a layer of aluminum (e.g. as a diffusion barrier). Layer 5122 can comprise a thickness that is at least 0.2%, 0.5%, or 1% of the width of cavity 513. Layer 5122 can comprise one, two, or more various materials, such as similar and / or dissimilar materials. Layer 5122 can comprise silicon nitride.

[0113]

[0114] Fig. IB shows another embodiment of a CMUT 510” comprising a substrate 511 that comprises a conductive material (e.g. doped silicon). Also included are dielectric layer 514 and support 515, each as shown, and each comprising a dielectric material (e.g. silicon oxide). Plate 512 is positioned on top of support 515, such that cavity 513 is formed between dielectric layer 514 and plate 512. Plate 512 of CMUT 510” comprises a multi-layer construction, including a first conductive layer, layer 5121a, that comprises a conductive material (e.g. doped silicon), and a second conductive layer, layer 5121b, that comprises another conductive material (e.g. aluminum).

[0114]

[0115] Figs. 1A and IB illustrate two of many possible structures of a CMUT 510 of the present inventive concepts. Each layer and / or component of CMUT 510 can comprise one or more materials, portions, and / or can comprise various geometries, such as are described herein. For example, CMUT 510 can comprise one, two, or more of the component configurations of the present inventive concepts described herein, such as component configurations selected from the group consisting of a contoured (e.g. non-flat) dielectric layer; a dielectric layer with a high k (i.e. relative dielectric constant) value, such as a k value of greater than 5, such as greater than 10, 100, 500, 1000, or 5000; a combination of dielectric materials, such as a combination of standard dielectric materials and / or dielectric materials with a high k value, such as a k value greater than 3.8, such as greater than 5,10, 100, 1000, or 5000; a shaped plate; a shaped bottom electrode; a piston component; a combination of shaped plate, dielectric layer, and / or shaped bottom electrode; a vented cavity; a cavity comprising fluidic trenches; and combinations of these. Each of these configuration options can be configured to operate in collapsed mode, conventional mode, a variable voltage mode such as a low-voltage mode, and / or other modes of CMUT operation, such as are described herein.

[0115]

[0116] In some embodiments, CMUT 510 of the present inventive concepts is configured to operate in a “conventional mode”. In conventional mode, plate 512 is supported by supports 515, and vibrates similar to a drumhead, without touching the bottom surface of cavity 513. Alternatively or additionally, CMUT 510 can be configured to operate in a “collapsed mode”. In collapsed mode, the center portion of plate 512 is in contact with the bottom surface of cavity 513 (e.g. plate 512 is pulled via an applied DC voltage into contact with the bottom of cavity 513). In operation, the portion of plate 512 between supports 515 and the contacting center portion (e.g. a “ring” portion of plate 512) vibrates while the center portion remains in contact with the bottom of cavity 513.

[0116]

[0117] In some embodiments, CMUT 510 comprises a “vented CMUT”, such as a CMUT including one or more openings between cavity 513 and the surrounding environment, vent 516 described herein. In some embodiments, cavity 513 of a vented CMUT 510 comprises one or more trenches or other fluid pathways, trench 517, which can be constructed and arranged to manipulate fluid (e.g. air) within the cavity 513, as CMUT 510 is actuated. Various embodiments of CMUT 510 comprising a vented CMUT are described in reference to Figs. 21A-28D and otherwise herein. Embodiments of CMUT 510 including a trench 517 that includes one or more trenches and / or other fluid pathways (“trench” or “trenches” herein), are described in reference to Figs. 23 A-28D and otherwise herein.

[0117]

[0118] Vent 516 can comprise one, two, or more similar and / or different cross-sectional geometries, such as a circle, oval, rectangle, square, triangle, and / or combinations of these. In some embodiments, vent 516 comprises a major axis with a length that is less than 10%, less than 7.5%, less than 5.0%, less than 2.5%, and / or less than 1.5% of the length of the major axis of CMUT 510 (e.g. vent 516 comprises a circle with a diameter that is less than 10%, less than 7.5%, less than 5.0%, less than 2.5%, and / or less than 1.5% of the length of the major axis of CMUT 510).

[0118]

[0119] Trench 517 can comprise one or more trenches or other fluid pathways with a depth that is at least 0.5pm, 1.0pm, or 2pm, and / or a depth that is no more than 15pm, 25pm, or 35pm.

[0120] In some embodiments, CMUT 510 is configured to operate in a “low-voltage mode”. For example, a 100V, 50V, or 10V pull-in voltage can be applied to cause CMUT 510 to be configured in a collapsed mode (e.g. versus typical collapse voltages in excess of 100V). In some embodiments, CMUT 510 can be configured to operate in a low-voltage mode when device 100 comprises a portable device (e.g. a battery-operated device configured for operation in a low-power mode, as described herebelow). For example, device 100 can comprise a battery-operated device, such as when functional element 199 comprises a battery (or other energy storage device), for example a 3.2V battery. In these embodiments, various components of device 100 can each be configured to operate at a voltage that is below a threshold, such as below 100V, 50V, 25V, or 10V. In some embodiments, CMUT 510 comprises a shaped bottom electrode 511s, a shaped top electrode (e.g. shaped plate 512s), and / or a shaped dielectric layer 514s that is configured (e.g. enables) CMUT 510 to operate in a low-voltage mode. In some embodiments, device 100 can be configured to operate in a “low-power mode”, such as when one or more components of device 100 is configured to operate with a relatively low-power consumption. CMUT 510 can be configured to operate in a low-voltage collapsed mode in order to limit power consumption (e.g., compared to a higher voltage collapsed mode operation), such as when device 100 comprises a battery- operated device.

[0119]

[0121] In some embodiments, CMUT 510 is configured for operation at 5MHz with a 90V pull-in voltage. In these embodiments, CMUT 510 can comprise one or more of the specifications selected from the group consisting of plate 512 radius of 29pm; plate 512 silicon layer thickness of 1.7pm; plate 512 aluminum layer thickness of 300nm; gap height of 230nm; dielectric layer 514 thickness (e.g. oxide insulator thickness) of 220nm; and combinations of these. For example, a CMUT with one or more (e.g. all) of these specifications can have a transmit sensitivity (e.g. at 80% of pull-in) of at least 9.9kPa / V.

[0120]

[0122] In some embodiments, CMUT 510 is configured for operation at 5MHZ with a 45 V pull-in voltage. In these embodiments, CMUT 510 can comprise one or more of the specifications selected from the group consisting of plate 512 radius of 29pm; plate 512 silicon layer thickness of 1.7pm; plate 512 aluminum layer thickness of 300nm; gap height of 160nm; dielectric layer 514 thickness (e.g. oxide insulator thickness) of lOOnm; and combinations of these. Simulations performed by the applicant showed this CMUT configuration achieved a sensitivity of 12.1 kPa / V at 5 MHz and a bias voltage of 36.2 V (80% of pull-in).

[0123] In some embodiments, CMUT 510 of the present inventive concepts is configured for use in airborne applications and / or immersion applications (e.g. one or more devices 100 including one or more CMUTs 510 are configured for use in airborne applications and / or immersion applications). For example, CMUT 510 can be used in harsh environments, such as high pressure, high temperature, and / or toxic environments, such as inside of a gas pipeline, in chemical facilities, and / or in aerospace applications, such as in spacecraft and / or vehicles, structures, or instruments designed for use on Mars or other extraterrestrial planets.

[0121]

[0124] In some embodiments, CMUT 510 of the present inventive concepts is configured to deliver HIFU energy. For example, plate 510 can comprise a relatively thick metal layer (e.g. for low ohmic heating), such as a layer of approximately 400nm. In these embodiments, CMUT 510 can be configured to provide a minimum output pressure (e.g. a minimum dependent on frequency of operation). CMUT 510 can be configured to operate at a pull-in voltage of no more than 200V, such as to be compatible with standard electronic components such as switches and preamplifiers. In some embodiments, CMUT 510 is configured to perform at a low-voltage (e.g. a voltage less than 200V), which results in a lower electric field during use (e.g. to reduce stress on components of CMUT 510), and also reduced requirements of transmit and receive electronics attached to CMUT 510.

[0122]

[0125] The shape of plate 510 has an effect on the mass and spring constants of plate 510, and hence the applicable frequency and bandwidth of operation. The second harmonic of plate 512 can limit the bandwidth of the CMUT 510 and contribute to the nonlinearity of the CMUT response to an excitation voltage. Increasing the frequency of the second harmonic relative to the fundamental frequency can therefore increase (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%) the bandwidth of CMUT 510 and / or decrease (e.g. a decrease of at least 2%, 5%, 10%, 25%, and / or 50%) the nonlinearity of the CMUT response, which are each often desirable. The shape (e.g. the cross-sectional shape) of plate 510 can be configured to increase the second harmonic frequency (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%) while keeping the fundamental frequency constant.

[0123]

[0126] CMUT 510 can comprise a convex lens (e.g. with a speed of sound lower than the speed of sound in tissue) configured to focus ultrasound beams in elevation (e.g. ID arrays). The convex lens can comprise a thickness that is several times the wavelength of sound used, and is limited by attenuation of the ultrasound waves passing therethrough. This attenuation results in heating of the lens, as well as a reduction in output pressure of CMUT 510. In some embodiments, CMUT 510 comprises a Fresnel lens that has a reduced thickness as compared to a corresponding convex lens, and thus comparatively results in reduced attenuation in the lens (e.g. a decrease of at least 2%, 5%, 10%, 25%, and / or 50%) and increased output pressure (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%).

[0124]

[0127] In some embodiments, US sensor 500 is configured to operate in a closed loop fashion, such as when US sensor 500 comprises a CMUT 510 that is constructed and arranged to provide active feedback (e.g. to processing unit 110) related to the position of plate 512 during operation of CMUT 510. A challenge with CMUTs is that the sensitivity of plate displacement to voltage is highly non-linear. The plate displacement is much more sensitive to voltage changes when operating at high voltages. This is the case for both AC driving voltages and DC bias voltages. This sensitivity makes it difficult to have the plate move across the full gap during transmit (e.g. while operating close to a voltage that would transition CMUT 510 into collapsed mode), maximizing the output pressure. Also, while in receive mode, it is difficult to hold the plate displacement very close to collapse, without going into collapse. In some embodiments, it is difficult to operate multiple CMUTs 510 within an array (e.g. array 5010 described herein) close to collapsed mode without one or more CMUTs 510 unintentionally going into collapse due to variability between CMUTs 510 within the array. In order to avoid these issues, system 10 can include feedback regarding plate 512 position, which provides improved control of the plate displacement (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50% in accuracy of control of plate displacement), and thus improved performance and avoidance of issues (e.g. avoiding collapse). The feedback signal can be provided by several different configurations of CMUT 510. The feedback signal can provide a measure of the plate displacement relative to the gap height. In some embodiments, the feedback signal can be used to set the DC bias voltage very close to the collapse voltage to maximize the receive sensitivity when CMUT 510 is operating in receive mode. Additionally or alternatively, the feedback signal can be used to set the AC driving signal so that the maximum plate displacement is a large fraction of the gap height, and higher output pressures can be obtained.

[0125]

[0128] In airborne applications, CMUT 510 bandwidth can be smaller than in nonairborne applications (e.g. immersion applications), necessitating better alignment of the operating frequency with the resonance frequency of the device in which CMUT 510 is integrated. In these applications, system 10 can track the resonance frequency, such that the optimal frequency can be used to transmit and receive. System 10 can be configured to transmit at the short-circuit resonance and receive at the open-circuit resonance of CMUT 510. The operating frequency of CMUT 510 can be changed in real time (e.g. while in use and / or during a calibration step) via the spring softening effect that results by changing the DC bias voltage. In some embodiments, multiple CMUTs 510 can be implemented to operate in groups (e.g. pairs) of CMUTs 510, where each CMUT 510 of the group is configured to operate as a transmitter or a receiver, but not both. In these embodiments, each CMUT 510 within a group of transmitters and receivers can be configured to operate at the same frequency, and the transmit and receive sensitivities can be optimized for the one or more transmitter-configured CMUTs 510, and the one or more receiver-configured CMUTs 510, respectively, at the operating frequency. Since the output impedance of a transmitter is low, a CMUT 510 operated as a transmitter has enhanced performance at short circuit resonance. Input impedance of a receiver is high (e.g. as compared to the output impedance of a transmitter), and reception is often optimal at the open circuit resonance frequency. Due to the narrow bandwidth, the DC bias can be adjusted to operate at the frequency with maximum dynamic range for a single CMUT 510 configured to both transmit and receive. If multiple CMUTs 510 are arranged in a group including CMUTs 510 configured to transmit or receive (i.e. not both transmit and receive, as described above), operation for each can be performed at the same frequency, and construction and arrangement of each transmitter CMUT 510 and receiver CMUT 510 can be optimized for operation at that frequency.

[0126]

[0129] CMUT 510 can be operated at a wide range of frequencies (e.g. drive frequencies or other operating frequencies). In some embodiments, CMUT 510 is operated at one or more frequencies that are set based on the particular application in which CMUT 510 is used, such as a particular application in which device 100 or another system 10 component is used. In some embodiments, system 10 comprises one or more CMUTs 510 that are operated at a frequency of at least 5MHz, and / or a frequency of no more than 10MHz. CMUTs 510 that include a vacuum gap (e.g. non-vented cavity as described in reference to Fig. 4A and otherwise herein) can be configured to operate at a frequency of at least 10kHz, 250kHz, or 500kHz and / or a frequency of no more than 50MHz or 100MHz. CMUTs 510 that comprise a vented arrangement (e.g. for operation in airborne applications as described in reference to Figs. 21 A-28D and otherwise herein) can be configured to operate at a frequency of at least 20kHz and / or a frequency of no more than 500kHz.

[0127]

[0130] In some embodiments, US sensor 500 (e.g. CMUT 510) comprises a sensing electrode (e.g. in addition to bottom electrode 511 and plate 512), that is configured to provide a signal (e.g. to processing unit 110) related to the position of plate 512, for example as described in reference to Fig. 2 herein. The sense electrode can be used in a closed-loop active feedback mode to adjust the AC or DC voltages. Alternatively or additionally, the sense electrode can be used for periodic calibration of the US sensor 500, such as a calibration that is performed (e.g. automatically performed by system 10) at least once per week, once per day, once per hour, once per minute, once per second, five times per second, or 50 times per second. For example, an AC voltage could be applied in increments of increasing amplitude while the signal from the sense electrode is measured. The displacement of plate 512 as a function of AC voltage is nonlinear, and the shape of the nonlinear curve can be used as a measure of the displacement of the plate as a fraction of the gap height.

[0128]

[0131] In some embodiments, US sensor 500 comprises one or more components configured to provide one or more signals used to calibrate sensor 500, calibration circuitry 530. In some embodiments, calibration circuitry 530 is configured to calibrate the pull-in voltage of one or more CMUTs 510. The pull-in voltage can vary across an array of CMUTs 510, for example because of nonuniformity in the CMUT 510 dimensions across the array. A self-calibration structure (e.g. calibration circuitry 530) can be included to measure the pull-in voltage of one or more CMUTs 510, such that system 10 (e.g. via algorithm 115) can tune the DC bias and / or transmit voltages. In some embodiments, a calibration structure is configured to provide an estimate of the pull-in voltage of one or more CMUTs 510 within an array, based on a measured pull-in voltage of the calibration structure. In some embodiments, an array of CMUTs 510 can comprise one, two, or more calibration structures, each configured to provide an estimate of the pull-in voltage of one or more CMUTs 510 (e.g. CMUTs 510 proximate the calibration structure within the array). In some embodiments, calibration circuitry 530 comprises a string of CMUTs with varying gap height and / or radii. This string of CMUTs can be connected in parallel, and the capacitance versus the voltage of the CMUTs can be measured. System 10 can be configured to detect a jump in capacitance each time a CMUT “pulls in”. The voltage at each capacitance jump can be fit to a model to extract device parameters (e.g. the gap height). Alternatively or additionally, calibration structures with a single design can be used to measure the collapse voltage of one or more CMUTs 510 of the array.

[0129]

[0132] In some embodiments, CMUT 510 comprises one or more support structures, piston 518 shown. Piston 518 and piston-based CMUTs 510 can be constructed and arranged as described in reference to Figs. 7, 8, 9, 10, 25, 26, 27, 28, 47, and 48. Piston 518 can be configured to make a portion of plate 512 stiffer, such that bending of plate 512 primarily occurs in the portions of plate 512 not supported by piston 518. This stiffening makes plate 512 “piston-like”, with increased average displacement of plate 512 relative to the maximum displacement, which can be used to increase the sensitivity and maximum output pressure of CMUT 510. Piston 518 can comprise one, two, or more components that comprise one, two, or more of various similar and / or dissimilar materials, such as silicon (e.g. silicon deposited by chemical vapor deposition), aluminum, titanium, chromium, tungsten, and / or gold. In some embodiments, piston 518 comprises a thickness that is at least 20%, 35%, or 50% of the thickness of plate 512, and / or a thickness that is no more than 5 times, 7 times, or 10 times the thickness of plate 512. In some embodiments, when CMUT 510 is arranged to operate in a non-collapsed mode (e.g. as described in reference to Figs. 7 and 8), piston 518 can comprise a width of at least 15%, 22%, or 30% of the width of plate 512, and / or a width that is no more than 80%, 87%, or 95% of the width of plate 512. In some embodiments, when CMUT 510 is arranged to operate in a collapsed mode (e.g. as described in reference to Figs. 9A-E), piston 518 can comprise a width that is at least 5%, 10%, or 15% of the width of plate 512, and / or a width that is no more than 25%, 32%, 40%, 44%, or 47% of the width of plate 512.

[0130]

[0133] In some embodiments, CMUT 510 is manufactured directly onto a CMOS wafer (e.g., such that CMUT 510 is integrated into the CMOS device at the wafer level). For example, it can be advantageous to directly integrate CMUT 510 into a CMOS wafer using wafer level processing. In some embodiments, a sacrificial release process, such as a sacrificial release process described in reference to Fig. 39 and otherwise herein, can be used when integrating a CMUT directly on a CMOS wafer. Integration of CMUT 510 into a CMOS device can provide improved sensitivity and / or manufacturing cost optimization. In some embodiments, CMUT 510 is manufactured using wafer level processing onto a previously processed (e.g., complete and / or partially complete) CMOS wafer. When performing wafer level processing on completed CMOS wafers there is a limited temperature budget. Typically, wafer level processing cannot exceed 400°C during any process step. The sacrificial method described herein can be completed with low temperature processing only, staying below the thermal budget of the CMOS wafer, for example when CMUT 510 is manufactured without exceeding 400°C, such as 350°C or 300°C. In some embodiments, when CMUT 510 is manufactured onto a CMOS wafer with CMOS electronics already on the wafer, the wafer would not be capable of surviving an oxidation furnace to grow additional thermal oxide without exceeding the temperature limit of the CMOS. CMUT 510 can be manufactured using low temperature bonding options configured to bond a thermal oxide layer (e.g., an oxide layer created at high temperatures) to a CMOS wafer without exposing the CMOS to those high temperatures.

[0131]

[0134] Referring now to Fig. 2, a top view of a plate of a CMUT including a sensing electrode is illustrated, consistent with the present inventive concepts. In some embodiments, CMUT 510 comprises a third electrode, sense electrode 5127 (e.g. in addition to a top and bottom electrode). Sense electrode 5127 can be positioned on the top or bottom of CMUT 510, for example when sense electrode 5127 is positioned proximate to the center of plate 512, as shown. Sense electrode 5127 can comprise an area that is no more than 20%, 30%, or 40% of the area of cavity 513. In some embodiments, sense electrode 5127 is electrically insulated from plate 512 and / or the bottom electrode 511 of CMUT 510 (e.g. when sense electrode 5127 is positioned on the top or the bottom of CMUT 510, respectively). For example, plate 512 can comprise a segmented plate, comprising one or more channels, as shown, where sense electrode 5127 and conductors (also referred to as “traces”) operably connected (e.g. electrically connected) to sense electrode 5127 can be positioned. In some embodiments, sense electrode 5127 is small compared to the top and / or bottom electrodes of CMUT 510 (e.g. bottom electrode 511 and / or plate 512 configured to actuate CMUT 510 to transmit and / or receive signals). In some embodiments, sense electrode 5127 produces a signal (e.g. a current) which depends on the displacement of plate 512. This signal can be used as a feedback signal to control the DC bias and / or the transmit voltage on the electrodes. In some embodiments, plate 512 comprises a portion including a nitride, carbide, diamond, and / or other dielectric material. In some embodiments, sense electrode 5127 is positioned on the bottom of the cavity of CMUT 510 (e.g. cavity 513 not shown but described herein). For example, sense electrode 5127 can be positioned within the cavity when CMUT 510 comprises a relatively large transducer (e.g. where there is relatively more room within the cavity to create the electrode pattern), such as when CMUT 510 is configured as an air transducer (e.g. typically comprising a large transducer, such as a transducer with a major axis (e.g. a diameter) of more than 0.5cm, or more than 1cm). For example, an air transducer used in ranging applications would typically operate in the 40 kHz to 100 kHz range. At these frequencies, the wavelength of the ultrasound wave is 8.5 mm and 3.4 mm, respectively. For a single CMUT 510 to be used in these types of applications, the major axis (e.g. diameter) of CMUT 510 would be many wavelengths across (e.g. greater than 1cm).

[0132]

[0135] Referring now to Fig. 3, an array of transducers comprising CMUT components and sensing transducers is illustrated, consistent with the present inventive concepts. US sensor 500 can comprise one or more arrays of ultrasound transducers, array element 5010, such as array elements 5010a and 5010b shown. Array elements 5010a, b can each comprise one or more CMUT components (e.g. at least 5, 10, or 20 CMUTs 510). In some embodiments, array elements 5010a, b each comprise one or more sensors, sensors 5011 (e.g. at least 5, 10, or 20 sensors 5011). Sensors 5011 can comprise ultrasound components (e.g. CMUT components) configured to acoustically couple to one or more CMUTs 510 of array elements 5010a, b. In some embodiments, array elements 5010a, b are configured to operate in a closed loop mode, for example when the signal generated by sensors 5011 provides a feedback signal that is used by sensor 500 (e.g. via algorithm 115) to control the signals (e.g. the drive signals) provided to one or more CMUTs 510. In some embodiments, one or more grounded guard lines (e.g. grounded electrical traces) can be positioned between CMUT 510 and sensors 5011 to reduce electrical crosstalk. In some embodiments, a device 100 comprises at least 3, 6, or 8 array elements 5010.

[0133]

[0136] Referring now to Figs. 4A-5D, various cross-sectional views of CMUT component configurations comprising shaped plates are illustrated, consistent with the present inventive concepts. CMUTs 510 shown can comprise similar components to CMUT 510 described in reference to Fig. 1 and otherwise herein.

[0134]

[0137] Fig. 4A shows a CMUT 510 comprising a CMUT configured to operate in a conventional mode (a “conventional mode CMUT” herein), and including a flat plate and flat bottom electrode.

[0135]

[0138] Fig. 4B shows a CMUT 510 comprising a conventional mode CMUT with a shaped plate comprising a stepped profile (e.g. including one or more “profile steps”). CMUT 510 of Fig. 4B comprises a plate 512s with a stepped profile comprising steps 5123 which includes 2 steps, ring-shaped steps 5123a and 5123b as shown. In some embodiments, one or more of steps 5123 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a plate 512s with 3, 4, or more steps.

[0139] Fig. 4C shows a CMUT 510 comprising a conventional mode CMUT with a shaped plate comprising a sloped profile (e.g. a piece-wise linear profile including one or more sloping portions).

[0136]

[0140] Fig. 4D shows a CMUT 510 comprising a conventional mode CMUT with a shaped plate comprising a curved profile.

[0137]

[0141] Fig. 4E shows a CMUT 510 comprising a conventional mode CMUT with a shaped plate comprising a curved profile, where the edge of the plate contacts the edge of the bottom electrode (e.g. the edge of plate 512 contacts insulating layer 514 that is positioned on bottom electrode 511).

[0138]

[0142] A CMUT 510 including a plate 512 comprising a shaped profile, plate 512s herein, can provide benefits over “standard” CMUT components (e.g. current, commercially available CMUT components that include non-shaped plates and electrodes, such as shown in Fig. 4A), as described herein. For example, a shaped plate 512s can provide an enhanced electric field (e.g. an enhancement of at least 2%, 5%, or 10%), and / or increased electromechanical coupling efficiency (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%). Additionally, shaped plate 512s can provide improvement of both transmit and receive sensitivity, such as at least a 50%, 75%, and / or 100% increase in sensitivity with a decrease in DC voltage (e.g. an approximately 39% decrease in DC voltage). Additionally, shaped plate 512s can enable an increased transient maximum output pressure, such as at least a 1.1 times increase (e.g. at least a 10% improvement) with a 44% lower AC voltage. Shaped plate 512s can enable a decreased driving voltage (e.g. a decrease of at least 2%, 5%, 10%, 25%, and / or 50% for either or both bias voltage (DC) and excitation voltage (AC)), such as 39% lower DC voltage and 44% lower AC voltage (e.g. without a decrease in performance of CMUT 510).

[0139]

[0143] In some embodiments, CMUT 510 comprises one or more CMUT transducers configured for immersion applications and operates at one, two, or more of the following parameters: an operating frequency between lOKHz and 100MHz; a major axis (e.g. a diameter) of 10pm to 50mm; a plate thickness from 0.1 m to 100pm; and / or a gap height of lOnm to 5mm.

[0140]

[0144] In some embodiments, the shaped portions of plate 512 comprise a thickness of no more than 20% of the thickness of plate 512 (e.g. the thickness of the center portion of plate 512). Alternatively or additionally, the shaped portions of plate 512 can comprise a minimum thickness (e.g. a minimum thickness at the edge of the shaped portion) of at least 15% of the gap height or 5% of the effective gap height of CMUT 510.

[0141]

[0145] Fig. 5A shows a CMUT 510 comprising a CMUT configured to operate in a collapsed mode (e.g. a “collapsed mode CMUT”), and including a shaped plate comprising a stepped profile. CMUT 510 of Fig. 5A comprises a plate 512s with a stepped profile comprising steps 5123 which includes 2 steps, ring-shaped steps 5123a and 5123b as shown. In some embodiments, one or more of steps 5123 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a plate 512s with 3, 4, or more steps.

[0142]

[0146] Fig. 5B shows a CMUT 510 comprising a collapsed mode CMUT with a shaped plate comprising a sloped profile.

[0143]

[0147] Fig. 5C shows a CMUT 510 comprising a collapsed mode CMUT with a shaped plate comprising a curved profile.

[0144]

[0148] Fig. 5D shows a CMUT 510 comprising a collapsed mode CMUT with a shaped plate comprising a curved profile, where the edge of the plate contacts the edge of the bottom electrode (e.g. the edge of plate 512 contacts insulating layer 514 that is positioned on bottom electrode 511).

[0145]

[0149] CMUT 510 comprising a shaped plate 512s configured in a collapsed mode can provide benefits over a standard CMUT component (e.g. as shown in Fig. 4A) configured in a collapsed mode. For example, this shaped plate 512s configuration can provide an enhanced electric field (e.g. an enhancement increase of at least 2%, 5%, 10%, 25%, and / or 50%), it can enable increased transmit and receive sensitivities (e.g. an increase in sensitivity of either or both of at least 2%, 5%, or 10%), and it can enable lower operating voltages (e.g. a decrease in operating voltages of at least 2%, 5%, 10%, 25%, and / or 50%).

[0146]

[0150] Referring additionally to Figs. 6A-6I, various charts and graphs of CMUT output and other performance characteristics are illustrated, consistent with the present inventive concepts. Applicant has performed analyses of various shaped plate CMUT component configurations as described herein. The results of these analyses are shown in the figures and are described hereinbelow.

[0147]

[0151] Analyses performed by the applicant has shown a CMUT 510 component can include a shaped plate 512s, such as to significantly enhance the electric field and / or electromechanical coupling efficiency of CMUT 510 (e.g. an improvement of either or both of at least 2%, 5%, 10%, 25%, and / or 50%), and thus improve either or both of the transmit and receive sensitivities (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%, in either or both sensitivities, while keeping a wide bandwidth, such as a bandwidth between 50% and 150%). The shaped plate (e.g. plate 512s described herein), and the fabrication methods thereof, of the present inventive concepts, can be used for CMUTs operating in conventional mode (e.g. non-collapsed mode), collapsed mode, or both. Standard CMUTs comprise plates and electrodes that are flat, which limits the electric field when the plate is biased by a DC voltage, because the deflected plate 512 cannot move in parallel with the bottom electrode 511. The advantages of having a shaped plate 512s include but are not limited to: significantly enhanced electric field (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%); increased electromechanical coupling efficiency (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%); significantly improved both transmit and receive sensitivities (e.g. an increase of either or both of at least 2%, 5%, or 10%); and / or decreased driving voltage (e.g. a decrease of at least 2%, 5%, 10%, 25%, and / or 50%).

[0148]

[0152] Various examples of CMUT 510 comprising a shaped plate 512s for improving electromechanical coupling efficiency and thus increasing both transmit and receive sensitivities are shown in Figs. 4B-5D. In some embodiments, shaped plate 512s comprises “multiple profile step” structures, stepped portion 5123, which can face down toward a flat substrate 511 (as shown and described in reference to Figs. 4B, 5A, 8A, 10A, 22A, 24A, 26A, 28A, and otherwise herein). The shaped plate 512s can be made of a conductive material, such that the electric potential can be applied to stepped portion 5123 of shaped plate 512s (e.g. to the lower surface of portion 5123). In some embodiments, the material of plate 512s comprises an insulating material. In these embodiments, stepped portion 5123 can comprise conductive materials, such that the electric potential can be applied to the lower surface of stepped portion 5123. In some embodiments, shaped plate 512s comprises sloping structures, sloped portion 5124, which can face down to the flat substrate 511 (e.g. as shown and described in reference to Figs. 4C, 5B, 8B, 10B, 22B, 24B, 26B, 28B, and otherwise herein). Sloped portion 5124 can comprise a thickness that is no more than 50%, 60%, or 70% of the thickness of shaped plate 512s. Sloped portion 5124 can comprise a thickness that is at least 2%, 5% or 10% of the gap height of cavity 513. Sloped portion 5124 can comprise one, two or more of various similar and / or dissimilar materials, such as silicon. Sloped portion 5124 can comprise the same or a different material than shaped plate 512s. The shaped plate 512s can be made of a conductive material, such that the electric potential can be applied to sloped portion 5124 of shaped plate 512s (e.g. to the lower surface of sloped portion 5124). In some embodiments, shaped plate 512s comprises an insulating material. In these embodiments, sloped portion 5124 can comprise conductive materials, such that the electric potential can be applied to the lower surface of sloped portion 5124.

[0149]

[0153] In some embodiments, plate 512 comprises one or more curved structures, curved portion 5125, which can face down to the flat substrate 51 l(e.g. as shown and described in reference to Figs. 4D-E, 5C-D, 8C-D, 10C-D, 22C-D, 24C-D, 26C-D, 28C-D). Curved portion 5125 can comprise a thickness that is no more than 50%, 60%, or 70% of the thickness of shaped plate 512s. Curved portion 5125 can comprise a thickness that is at least 2%, 5% or 10% of the gap height of cavity 513. Curved portion 5125 can comprise one, two or more of various similar and / or dissimilar materials, such as silicon. Curved portion 5125 can comprise the same or a different material than shaped plate 512s. The shaped plate 512s can be made of a conductive material, such that the electric potential can be applied to curved portion 5125 of shaped plate 512s (e.g. to the lower surface of curved portion 5125). In some embodiments, plate 512 comprises an insulating material. In these embodiments, curved portion 5125 can comprise conductive materials, such that the electric potential can be applied to the lower surface of curved portion 5125. The profile of curved portion 5125 can be derived from (e.g. be set similar to) the shape of a deflected flat plate that is being driven with a large DC bias or large AC excitation signal. This provides a large improvement in performance (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50% in one or more performance parameters) without mechanically limiting the displacement of the center of the plate. The profile can approximate this shape, for example an approximation with horizontal steps, to reduce the fabrication complexity.

[0150]

[0154] In some embodiments, shaped plate 512s is constructed and arranged to be in contact with the substrate at the edge of CMUT 510, for example at contacting area 5126, as shown in Fig. 4E. In these embodiments, the curvature of curved portion 5125 can be constructed and arranged (e.g. optimized) to improve receive sensitivity (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%) by increasing driving voltage beyond the pull-in voltage. For example, the contacting area 5126 increases as more voltage is applied and the plate 512 deflection increases, and the lateral dimension of plate 512 becomes smaller, making plate 512 stiffer and preventing collapse. This allows higher voltages to be applied to CMUT 510 without reaching collapse.

[0155] Similar shaped plate 512s configurations can also be used in collapsed mode CMUTs, for example as shown in Figs. 5A-5D. Compared with the traditional flat substrate configurations (e.g. shown in Fig. 4A), the most active region associated with a strong electrical field can be increased up to 50%, 75%, and / or 100% using these configurations, thus resulting in strongly enhanced electromechanical coupling efficiency (e.g. an efficiency increase of at least 2%, 5%, 10%, 25%, and / or 50%), as described herein. For example, Figs. 5A-5D show CMUT 510 in collapsed mode with similar configurations to the CMUTs 510 of Figs. 4B-4E, respectively.

[0151]

[0156] Applicant has performed simulations (e.g. finite model analysis of various CMUT component configurations described herein). Fig. 6A shows a simulation of the deformation of a flat plate, where the plate is biased with a 90% pull-in voltage. Fig. 6B shows a simulation of the deformation of a plate comprising two “profile steps”, where the plate is biased with a 90% pull-in voltage. Fig. 6C shows a simulation of the deformation of a plate comprising a sloped portion, where the plate is biased with a 90% pull-in voltage. Fig. 6D shows a simulation of the deformation of a plate comprising a curved portion, where the plate is biased with a 90% pull-in voltage.

[0152]

[0157] Applicant designed and simulated the performance of CMUTs comprising various shaped plate configurations (e.g. of shaped plate 512s as described herein), when operating in conventional mode. In the simulation, the following parameters were used: an operating frequency of 7.5MHz; a 1.5pm thick plate 512; a plate 512 radius of 21pm; and a gap height of 0.25pm (e.g. to obtain a reasonable driving voltage, such as a driving voltage of less than 200V, such as less than 150V). Fig. 6E shows the pull-in voltages from different shaped plate 512s configurations compared with a standard CMUT component. As shown, in the comparison the pull-in voltage decreases by up to 38.8%. Figs. 6F and 6G show the enhanced electric field and the improved electromechanical coupling efficiency (e.g. an increase of either or both of at least 2%, 5%, 10%, 25%, and / or 50%), respectively. Fig. 6H shows the transmit (a) and receive (b) sensitivities biased at 90% of the pull-in voltage. Both the transmit and receive sensitivities can be increased by at least 50% (e.g. by approximately 93%) while driving with at least a 10% lower DC bias (e.g. a 38.8% lower DC bias). The maximum transient output pressure is similarly compared and shown in Fig. 61. The shaped plate 512s can generate more than 1.1 times the sound pressure, while being driven with 38.8% lower DC and 43.8% lower AC voltages. The shaped plate 512s also can suppress high order harmonics.

[0158] Referring now to Figs. 7A-10D, various cross-sectional views of piston-based CMUT components comprising shaped plates and / or shaped bottom electrodes are illustrated, consistent with the present inventive concepts. CMUTs 510 shown can comprise similar components to CMUT 510 described in reference to Fig. 1 and / or otherwise herein. In some embodiments, a CMUT 510 of Figs. 7A-10D or a CMUT 510 otherwise described herein, can comprise a solid piston as described herein in reference to Figs. 47A-B, or a non-solid piston as described herein in reference to Figs. 48A-B.

[0153]

[0159] Fig. 7A shows a CMUT 510 comprising a piston-based CMUT (e.g. a CMUT including a piston) configured to operate in conventional mode (a “piston-based conventional mode CMUT” herein) and including a flat plate and a flat bottom electrode.

[0154]

[0160] Fig. 7B shows a CMUT 510 comprising a piston-based conventional mode CMUT with a flat plate and shaped bottom electrode comprising a stepped profile. CMUT 510 of Fig. 7B comprises a substrate 511s with a stepped profile comprising steps 5113 which includes 2 steps, ring-shaped steps 5113a and 5113b as shown. In some embodiments, one or more of steps 5113 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a substrate 511s with 3, 4, or more steps. In some embodiments, insulating layer 514 covers the horizontal surfaces and / or the vertical surfaces of one, two, or more stepped portions 5113, although only the horizontal surfaces are shown covered in Fig. 7B.

[0155]

[0161] Fig. 7C shows a CMUT 510 comprising a piston-based conventional mode CMUT with a flat plate and a shaped bottom electrode comprising a sloped profile.

[0156]

[0162] Fig. 7D shows a CMUT 510 comprising a piston-based conventional mode CMUT with a flat plate and a shaped bottom electrode comprising a curved profile.

[0157]

[0163] Fig. 7E shows a CMUT 510 comprising a piston-based conventional mode CMUT with a flat plate and a shaped bottom electrode comprising a curved profile where the edge of the bottom electrode contacts the edge of the plate (e.g. insulating layer 514 contacts the edge of plate 512).

[0158]

[0164] Fig. 8A shows a CMUT 510 comprising a piston-based conventional mode CMUT with a shaped plate comprising a stepped profile. CMUT 510 of Fig. 8A comprises a plate 512s with a stepped profile comprising steps 5123 which includes 2 steps, ring-shaped steps 5123a and 5123b as shown. In some embodiments, one or more of steps 5123 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a plate 512s with 3, 4, or more steps.

[0159]

[0165] Fig. 8B shows a CMUT 510 comprising a piston-based conventional mode CMUT with a shaped plate comprising a sloped profile.

[0160]

[0166] Fig. 8C shows a CMUT 510 comprising a piston-based conventional mode CMUT with a shaped plate comprising a curved profile.

[0161]

[0167] Fig. 8D shows a CMUT 510 comprising a piston-based conventional mode CMUT with a shaped plate comprising a curved profile, where the edge of the plate contacts the edge of the bottom electrode (e.g. the edge of plate 512 contacts insulating layer 514 that is positioned on bottom electrode 511).

[0162]

[0168] A CMUT 510 comprising a shaped bottom electrode 511s, and / or a shaped plate 512s (e.g. a piston-based CMUT as described in reference to Figs. 7B-8D), when operating in conventional mode, can provide benefits over standard CMUT components (e.g. a standard CMUT including a piston as shown in Fig. 7A) when operating in conventional mode, as described herein. For example, these benefits include but are not limited to: a wider operational bandwidth; higher transmit and / or receive sensitivity; suppression of harmonics (e.g. enabling suppression of harmonics); enhanced electric field (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%); increased electromechanical coupling efficiency (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%); increased transient maximum output pressure (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%); and / or decreased driving voltage (e.g. a decrease of at least 2%, 5%, 10%, 25%, and / or 50%, for either or both of biased voltage (DC) and excitation voltage (AC)).

[0163]

[0169] In some embodiments, piston 518 comprises a thickness of at least 50% of the thickness of plate 512, and / or a thickness of no more than five times the thickness of plate 512. In some embodiments, piston 518 comprises a diameter between 20% and 80% of the major axis (e.g. diameter) of CMUT 510. In some embodiments, the shaped portions of electrode 511 and / or plate 512 can comprise a minimum thickness (e.g. a minimum thickness at the edge of the shaped portion) of at least 15% of the gap height or 5% of the effective gap height of CMUT 510.

[0164]

[0170] Fig. 9A shows a CMUT 510 comprising a piston-based CMUT configured to operate in collapsed mode (a “piston-based collapsed mode CMUT” herein), and including a flat plate and flat bottom electrode.

[0171] Fig. 9B shows a CMUT 510 comprising a piston-based collapsed mode CMUT with a flat plate and shaped bottom electrode comprising a stepped profile. CMUT 510 of Fig. 9B comprises a substrate 511s with a stepped profile comprising steps 5113 which includes 2 steps, ring-shaped steps 5113a and 5113b as shown. In some embodiments, one or more of steps 5113 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a substrate 511s with 3, 4, or more steps. In some embodiments, an insulating layer 514 covers the horizontal surfaces and / or the vertical surfaces of one, two, or more stepped portions 5113, although only the horizontal surfaces are shown covered in Fig. 9B.

[0165]

[0172] Fig. 9C shows a CMUT 510 comprising a piston-based collapsed mode CMUT with a flat plate and shaped bottom electrode comprising a sloped profile.

[0166]

[0173] Fig. 9D shows a CMUT 510 comprising a piston-based collapsed mode CMUT with a flat plate and shaped bottom electrode comprising a curved profile.

[0167]

[0174] Fig. 9E shows a CMUT 510 comprising a piston-based collapsed mode CMUT with a flat plate and shaped bottom electrode comprising a curved profile, where the edge of the bottom electrode contacts the edge of the plate (e.g. insulating layer 514 contacts the edge of plate 512).

[0168]

[0175] Fig. 10A shows a CMUT 510 comprising a piston-based collapsed mode CMUT with a shaped plate comprising a stepped profile. CMUT 510 of Fig. 10A comprises a plate 512s with a stepped profile comprising steps 5123 which includes 2 steps, ring-shaped steps 5123a and 5123b as shown. In some embodiments, one or more of steps 5123 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a plate 512s with 3, 4, or more steps.

[0169]

[0176] Fig. 10B shows a CMUT 510 comprising a piston-based collapsed mode CMUT with a shaped plate comprising a sloped profile.

[0170]

[0177] Fig. 10C shows a CMUT 510 comprising of a piston-based collapsed mode CMUT with a shaped plate comprising a curved profile.

[0171]

[0178] Fig. 10D shows a CMUT 510 comprising a piston-based collapsed mode CMUT with a shaped plate comprising a curved profile, where the edge of the plate contacts the edge of the bottom electrode (e.g. the edge of plate 512 contacts insulating layer 514 that is positioned on bottom electrode 511).

[0179] A CMUT 510 comprising a shaped bottom electrode 511s and / or a shaped plate 512s (e.g. a piston-based CMUT as described in reference to Figs. 9B-10D), when operating in collapsed mode, can provide benefits over standard CMUT components (e.g. a standard CMUT including a piston as shown in Fig. 9A) when operating in collapsed mode, as described herein. For example, these benefits include but are not limited to: a wider operational bandwidth; higher transmit and / or receive sensitivities; suppression of harmonics (e.g. enabling suppression of harmonics); enhanced electric field (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%); increased electromechanical coupling efficiency (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%); increased transient maximum output pressure (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%); and / or decreased driving voltage (e.g. a decrease of at least 2%, 5%, 10%, 25%, and / or 50% for either or both of biased voltage (DC) and excitation voltage (AC)).

[0172]

[0180] Referring now to Figs. 11A-20, various charts and graphs of CMUT output and other performance characteristics are illustrated, consistent with the present inventive concepts. Applicant has performed analyses of the various shaped plate CMUT component configurations described herein. The results of these analyses are shown and are described hereinbelow.

[0173]

[0181] Analyses performed by the applicant have shown a CMUT component of the present inventive concepts can include a piston (e.g. a piston mounted to plate 512, referred to herein as a “piston-plate”) and shaped electrodes (e.g. shaped bottom electrode 511s and / or shaped plate 512s) that significantly improves either or both transmit and receive sensitivities (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50% in either or both sensitivities), and significantly increases output sound pressure (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50% while keeping wide bandwidth with lower driving voltage). The pistonbased CMUT component configuration, and the fabrication methods thereof, of the present inventive concepts can be used for CMUTs operating in either or both conventional and collapsed modes. Standard flat plate and flat electrode piston-based CMUT configurations limit the electromechanical transformer ratio when the plate is biased by a DC voltage because the deflected plate cannot move in parallel with the bottom flat electrode. The advantages of having a piston and shaped electrodes (e.g. bottom electrode 511s and / or plate 512s) include but are not limited to: significantly improved both of transmit and receive sensitivities (e.g. an increase in transmit and / or receive sensitivity of at least 2%, 5%, 10%, 25%, and / or 50%); wide operational bandwidth (e.g. an increase in bandwidth of at least 2%, 5%, 10%, 25%, and / or 50%); suppression of harmonics (e.g. enabling suppression of harmonics of at least 2%, 5%, 10%, 25%, and / or 50%); decreased driving voltage (e.g. a decrease of at least 2%, 5%, 10%, 25%, and / or 50%); and / or improved electromechanical transformer ratio (e.g. an improvement of at least 2%, 5%, 10%, 25%, and / or 50%).

[0174]

[0182] Various examples of a CMUT 510 comprising a piston and shaped electrodes (e.g. bottom electrode 511 and / or plate 512) for improving both transmit and receive sensitivities are shown in Figs. 7B-10D. A piston-based CMUT can comprise a piston-plate, including a mass, piston 518, positioned on plate 512, for example as shown in Fig. 7A. In some embodiments, bottom electrode 511 comprises an electrode 511s comprising a multipleprofile step structure, stepped portion 5113, as shown and described in reference to Fig. 1, Figs. 7B, 9B, 2 IB, 23B, 25B, 27B, and otherwise herein. Alternatively or additionally, shaped bottom electrode 511s can comprise a sloping structure, sloped portion 5114, as shown and described in reference to Fig. 1, Figs. 7C, 9C, 21C, 23C, 25C, 27C, and otherwise herein. Sloped portion 5114 can comprise one, two, or more similar and / or dissimilar materials, such as silicon. In some embodiments, sloped portion 5114 comprises a similar material as substrate 511. Sloped portion 5114 can comprise a maximum thickness such that at maximum deflection, slope 5114 is proximate but not quite touching plate 512. Sloped portion 5114 can comprise a width that is at least 10%, or 20% of the length of the major axis of cavity 513. Sloped portion 5114 can comprise a maximum height that is at least 30%, 20%, or 10% of the gap height of cavity 513. In some embodiments, shaped bottom electrode 511s comprises a curved structure, curved portion 5115, as shown and described in reference to Fig. 1, Figs. 7D-E, 9D-E, 21D-E, 25D-E, 27D-E, and otherwise herein. The profile of curved portion 5115 can be derived from (e.g. be set similar to) the shape of a deflected flat plate that is being driven with a large DC bias or large AC excitation signal. Curved portion 5115 can comprise a curvature that approximates the curvature of the deflection profile of plate 512. Curved portion 5115 can comprise a height that is at least 2%, 5%, or 10% of the gap height of cavity 513.

[0175]

[0183] In some embodiments, bottom electrode 511 (e.g. electrode 51 Is) is constructed and arranged in contact with plate 512 at the edge of CMUT 510, for example at contacting area 5116, as shown in Figs. 7E, 9E, 2 IE, 23E, and 25E. The area associated with contacting area 5116 is dependent on the magnitude of the voltage applied to CMUT 510. The curvature of curved portion 5115 can be constructed and arranged (e.g. optimized) to improve receive sensitivity (e.g. an increase in sensitivity of at least 2%, 5%, 10%, 25%, and / or 50%) by increasing driving voltage beyond the pull-in voltage. For example, during deflection of plate 512, plate 512 gradually makes contact with curved portion 5115 such that the deflectable portion of plate 512 gradually shrinks, increasing the spring constant of plate 512, thus increasing the pull-in voltage.

[0176]

[0184] In some embodiments, a CMUT 510 comprises a piston-based CMUT with a shaped plate 512s. CMUT 510 can include a shaped plate 512s comprising stepped portion 5123 as shown in Fig. 8A. In some embodiments, CMUT 510 includes a shaped plate 512s comprising sloped portion 5124 as shown in Fig. 8B. In some embodiments, CMUT 510 includes a shaped plate 512s comprising curved portion 5125 as shown in Fig. 8C. The profile of curved portion 5125 can be derived from (e.g. be set similar to) the shape of a deflected flat plate that is being driven with a large DC bias or large AC excitation signal. In some embodiments, shaped plate 512s comprising curved portion 5125 can be in contact with bottom electrode 511 at contacting area 5126, as shown in Figs. 4E, 5D, 8D, 10D, 22D, 24D, 26D, 27E, and 28D. The curvature of curved portion 5125 can be constructed and arranged (e.g. optimized) to improve receive sensitivity (e.g. an increase in sensitivity of at least 2%, 5%, 10%, 25%, and / or 50%) by increasing driving voltage beyond the pull-in voltage, such as is described herein. The area associated with contacting area 5126 is dependent on the magnitude of the voltage applied to CMUT 510.

[0177]

[0185] CMUT 510 configurations of the present inventive concepts comprising a piston and shaped electrodes can be operated in collapsed mode, for example as shown in Figs. 9A- 10D. Figs. 9A-10D show a CMUT 510 in collapsed mode with similar configurations to those of Figs. 7B-8D, respectively.

[0178]

[0186] In some embodiments, shaped electrodes 511s comprise a conductive material. Piston 518 (e.g. a piston mounted to a plate 512) can comprise either a conductive material or insulation material. Compared with the traditional flat plate and flat electrode component configurations (e.g. shown in Fig. 7A), the most active region with the strongest electrical field can be increased up to 50%, 75%, and / or 100% using the configurations shown in Figs. 7B-10D, thus resulting in strongly enhanced electromechanical coupling efficiency (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%), as described herein.

[0179]

[0187] Applicant designed and simulated the performance of piston-based CMUTs comprising various shaped electrode configurations, operating in conventional mode. In the simulation, the following parameters were used: an operating frequency of 7.5MHz; a 1.5pm thick plate 512; a plate 512 radius of 21pm; and a gap height of 0.25pm (e.g. to obtain a reasonable driving voltage, such as a driving voltage of less than 200V peak to peak). The piston width was set (e.g. optimized) at half of the plate radius, which gave the best sensitivity without sacrificing the bandwidth. In some embodiments, piston 518 comprises one or more dimensions as described in reference to Fig. 1 and / or otherwise herein. The resonance frequency increases to 10 MHz resulting from the increased spring constant of the piston-plate and the pull-in voltage can increase approximately 22% (e.g. an increase of at least 5% and / or 10%). Figs. 11 A-l ID show the transmit and receive sensitivities of various CMUT component configurations biased at 90% of the pull-in voltage. Fig. 11 A compares the transmit sensitivity of CMUTs simulated with varying bottom electrodes 511. Fig. 1 IB compares the transmit sensitivity of CMUTs simulated with varying plates 512. Fig. 11C compares the receive sensitivity of CMUTs simulated with varying bottom electrodes 511. Fig. 1 ID compares the receive sensitivity of CMUTs simulated with varying plates 512. Both the transmit and receive sensitivities can be increased by at least 50%, 75%, 100%, 125%, and / or 150% (e.g. as described below). Comparisons of the maximum transient output pressure of CMUT component configurations with varying electrodes 511 (a) and varying plates 512 (b) are shown in Fig. 12. Simulation has shown that shaped plate 512s and shaped electrode 511s component configurations can generate more than 2.2 times sound pressure while being driven with the same driving voltage. Fig. 13 shows a comparison of the electromechanical transformer ratio to DC bias voltage for various component configurations described herein. The DC bias voltage is set to 90% of the pull-in voltage. A conventional flat CMUT design without a piston has the lowest electromechanical transformer ratio and DC bias. By adding a piston, the plate is stiffened significantly thus increasing the pull-in voltage to be the highest. However, with adding shaped electrodes, the DC is significantly lowered but the electromechanical transformer ratio is improved significantly (e.g. an improvement of at least 2%, 5%, 10%, 25%, and / or 50%). The curved electrode configuration has the best transformer ratio with lowest DC bias, followed by the sloping electrode, then the two-step electrode. The shaped plate configurations have a stiffer plate than the sub electrodes, thus having higher DCs.

[0180]

[0188] Fig. 14A shows a simulation of the deformation of the flat plate of a collapsed mode CMUT, where the plate is biased with a 100% pull-in voltage. Fig. 14B shows a magnified view of the simulation of Fig. 14A. Fig. 15A shows a simulation of the deformation of the flat piston-plate of a collapsed mode CMUT, where the plate is biased with a 100% pull-in voltage. Fig. 15B shows a magnified view of the simulation of Fig. 15 A. Fig. 16A shows a simulation of the deformation of the flat piston-plate of a collapsed mode CMUT comprising an electrode 511 with a sloped profile. Fig. 16B shows a magnified view of the simulation of Fig. 16A.

[0181]

[0189] Figs. 17A and 17B show graphs comparing the transmit and receive sensitivities, respectively, of the conventional CMUT of Fig. 14A, the piston-based CMUT of Fig. 15 A, and the piston-based CMUT of Fig. 16A including an electrode 511 with a sloped profile.

[0182]

[0190] Figs. 18A-18C show simulations of the CMUTs of Figs. 14A, 15A, and 16A, respectively, indicating the maximum vibration position of each design relative to the balance position.

[0183]

[0191] Fig. 19 shows a graph comparing the transient output sound pressure of the CMUTs of Figs. 14A, 15A, and 16A. Fig. 20 shows a table indicating percentage increases and decreases in key properties of these CMUT designs. As shown, the resonant frequency of the piston-based CMUT of Fig. 15A is lower than the CMUT of Fig. 14A, however the transmit and receive sensitivity, as well as the maximum transient output pressure are all increased. The piston-based CMUT of Fig. 16A including electrode 511 with a sloped profile shows further improvements in these metrics, as well as a decrease in pull-in voltage (e.g. a decrease in pull-in voltage of at least 2%, 5%, 10%, 25%, and / or 50%). The transmit and receive sensitivity of the configuration of CMUT 510 of Figs. 14A, 15A, and 16A is improved by more than 35%, with approximately 50% of excitation voltage, as shown.

[0184]

[0192] Referring now to Figs. 21A-28D, various cross-sectional views of CMUT components configured for use in airborne applications and comprising shaped plates and / or shaped bottom electrodes are illustrated, consistent with the present inventive concepts. CMUTs 510 shown can comprise similar components to CMUT 510 described in reference to Fig. 1 and otherwise herein, such as components 511, 512, 513, 514, 515, 516, 517, and 518 shown in the figures.

[0185]

[0193] Figs. 21B through 21E illustrate a CMUT 510 comprising a vent 516 and a shaped substrate 511s. Figs. 22A-D illustrate a CMUT 510 comprising a vent 516 and a shaped plate 512s. Figs. 23B-E illustrate a CMUT 510 comprising a trench 517 (e.g. four ring-shaped fluidic channels in substrate 511 and through dielectric 514, as shown), and a shaped substrate 511s. Figs. 24A-D illustrate a CMUT 510 comprising a trench 517 (e.g. four ringshaped fluidic channels positioned in substrate 511 and through dielectric 514, as shown), and a shaped plate 512s. Figs. 25B-E illustrate a CMUT 510 comprising a vent 516, a piston 518, and a shaped substrate 511s. Figs. 26A-D illustrate a CMUT 510 comprising a vent 516, a piston 518, and a shaped plate 512s. Figs. 27B-E illustrate a CMUT 510 comprising a vent 516, a trench 517 (e.g. four ring-shaped fluidic channels shown positioned in substrate 511 and through dielectric 514, as shown), and a shaped substrate 511s. Figs. 28A-D illustrate a CMUT 510 comprising a vent 516, a trench 517 (e.g. four ring-shaped fluidic channels positioned in substrate 511 and through dielectric 514, as shown), and a shaped plate 512s.

[0186]

[0194] Fig. 21 A shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a “vent through via” (e.g. a hole passing through bottom electrode 511 as shown), a flat plate, and flat bottom electrode.

[0187]

[0195] Fig. 21B shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including vent through via, a flat plate, and a shaped bottom electrode comprising a stepped profile (e.g. including one or more “profile steps”). CMUT 510 of Fig. 2 IB comprises a substrate 511s with a stepped profile comprising steps 5113 which includes 2 steps, ring-shaped steps 5113a and 5113b as shown. In some embodiments, one or more of steps 5113 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a substrate 511s with 3, 4, or more steps. In some embodiments, insulating layer 514 covers the horizontal surfaces and / or the vertical surfaces of one, two, or more stepped portions 5113, although only the horizontal surfaces are shown covered in Fig. 21B.

[0188]

[0196] Fig. 21C shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, a flat plate, and a shaped bottom electrode comprising a sloped profile.

[0189]

[0197] Fig. 21D shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, a flat plate, and a shaped bottom electrode comprising a curved profile.

[0190]

[0198] Fig. 21E shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, a flat plate, and a shaped bottom electrode comprising a curved profile, where the edge of the bottom electrode contacts the edge of the plate (e.g. insulating layer 514 contacts the edge of plate 512).

[0191]

[0199] Fig. 22A shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via and a shaped plate comprising a stepped profile. CMUT 510 of Fig. 22A comprises a plate 512s with a stepped profile comprising steps 5123 which includes 2 steps, ring-shaped steps 5123a and 5123b as shown. In some embodiments, one or more of steps 5123 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a plate 512s with 3, 4, or more steps.

[0192]

[0200] Fig. 22B shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via and a shaped plate comprising a sloped profile.

[0193]

[0201] Fig. 22C shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via and a shaped plate comprising a curved profile.

[0194]

[0202] Fig. 22D shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via and a shaped plate comprising a curved profile, where the edge of the plate contacts the edge of the bottom electrode (e.g. the edge of plate 512 contacts insulating layer 514 that is positioned on bottom electrode 511).

[0195]

[0203] Fig. 23 A shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a flat bottom electrode, consistent with the present inventive concepts.

[0196]

[0204] Fig. 23B shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a shaped bottom electrode comprising a stepped profile. CMUT 510 of Fig. 23B comprises a substrate 511s with a stepped profile comprising steps 5113 which includes 2 steps, ring-shaped steps 5113a and 5113b as shown. In some embodiments, one or more of steps 5113 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a substrate 511s with 3, 4, or more steps. In some embodiments, insulating layer 514 covers the horizontal surfaces and / or the vertical surfaces of one, two, or more stepped portions 5113, although only the horizontal surfaces are shown covered in Fig. 23B.

[0197]

[0205] Fig. 23C shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a shaped bottom electrode comprising a sloped profile.

[0198]

[0206] Fig. 23D shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a shaped bottom electrode comprising a curved profile.

[0207] Fig. 23E shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a shaped bottom electrode comprising a curved profile, where the edge of the bottom electrode contacts the edge of the plate (e.g. insulating layer 514 contacts the edge of plate 512).

[0199]

[0208] Fig. 24A shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, fluidic channels, and a shaped plate comprising a stepped profile. CMUT 510 of Fig. 24A comprises a plate 512s with a stepped profile comprising steps 5123 which includes 2 steps, ring-shaped steps 5123a and 5123b as shown. In some embodiments, one or more of steps 5123 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a plate 512s with 3, 4, or more steps.

[0200]

[0209] Fig. 24B shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, fluidic channels, and a shaped plate comprising a sloped profile.

[0201]

[0210] Fig. 24C shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, fluidic channels, and a shaped plate comprising a curved profile.

[0202]

[0211] Fig. 24D shows a CMUT 510 comprising an airborne-enabled conventional mode CMUT including a vent through via, fluidic channels, and a shaped plate comprising a curved profile, where the edge of the plate contacts the edge of the bottom electrode (e.g. the edge of plate 512 contacts insulating layer 514 that is positioned on bottom electrode 511).

[0203]

[0212] Fig. 25A shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, a flat plate, and flat bottom electrode.

[0204]

[0213] Fig. 25B shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, a flat plate, and a shaped bottom electrode comprising a stepped profile. CMUT 510 of Fig. 25B comprises a substrate 511s with a stepped profile comprising steps 5113 which includes 2 steps, ring-shaped steps 5113a and 5113b as shown. In some embodiments, one or more of steps 5113 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a substrate 511s with 3, 4, or more steps. In some embodiments, insulating layer 514 covers the horizontal surfaces and / or the vertical surfaces of one, two, or more stepped portions 5113, although only the horizontal surfaces are shown covered in Fig. 25B.

[0205]

[0214] Fig. 25C shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, a flat plate, and a shaped bottom electrode comprising a sloped profile.

[0206]

[0215] Fig. 25D shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, a flat plate, and a shaped bottom electrode comprising a curved profile.

[0207]

[0216] Fig. 25E shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, a flat plate, and a shaped bottom electrode comprising a curved profile, where the edge of the bottom electrode contacts the edge of the plate (e.g. insulating layer 514 contacts the edge of plate 512).

[0208]

[0217] Fig. 26A shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via and a shaped plate comprising a stepped profile. CMUT 510 of Fig. 26A comprises a plate 512s with a stepped profile comprising steps 5123 which includes 2 steps, ring-shaped steps 5123a and 5123b as shown. In some embodiments, one or more of steps 5123 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a plate 512s with 3, 4, or more steps.

[0209]

[0218] Fig. 26B shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via and a shaped plate comprising a sloped profile.

[0210]

[0219] Fig. 26C shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via and a shaped plate comprising a curved profile.

[0211]

[0220] Fig. 26D shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via and a shaped plate comprising a curved profile, where the edge of the plate contacts the edge of the bottom electrode (e.g. the edge of plate 512 contacts insulating layer 514 that is positioned on bottom electrode 511).

[0212]

[0221] Fig. 27A shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a flat bottom electrode, consistent with the present inventive concepts.

[0222] Fig. 27B shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a shaped bottom electrode comprising a stepped profile. CMUT 510 of Fig. 27B comprises a substrate 511s with a stepped profile comprising steps 5113 which includes 2 steps, ringshaped steps 5113a and 5113b as shown. In some embodiments, one or more of steps 5113 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a substrate 511s with 3, 4, or more steps. In some embodiments, insulating layer 514 covers the horizontal surfaces and / or the vertical surfaces of one, two, or more stepped portions 5113, although only the horizontal surfaces are shown covered in Fig. 27B.

[0213]

[0223] Fig. 27C shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a shaped bottom electrode comprising a sloped profile.

[0214]

[0224] Fig. 27D shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a shaped bottom electrode comprising a curved profile.

[0215]

[0225] Fig. 27E shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, fluidic channels, a flat plate, and a shaped bottom electrode comprising a curved profile, where the edge of the bottom electrode contacts the edge of the plate (e.g. insulating layer 514 contacts the edge of plate 512).

[0216]

[0226] Fig. 28A shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, fluidic channels, and a shaped plate comprising a stepped profile. CMUT 510 of Fig. 28A comprises a plate 512s with a stepped profile comprising steps 5123 which includes 2 steps, ring-shaped steps 5123a and 5123b as shown. In some embodiments, one or more of steps 5123 comprise a different geometry, such as an oval, rectangular, triangular, and / or other shape (e.g. a shape that is similar to the shape of cavity 513). In some embodiments, a CMUT 510 comprises a plate 512s with 3, 4, or more steps.

[0217]

[0227] Fig. 28B shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, fluidic channels, and a shaped plate comprising a sloped profile.

[0228] Fig. 28C shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, fluidic channels, and a shaped plate comprising a curved profile.

[0218]

[0229] Fig. 28D shows a CMUT 510 comprising an airborne-enabled, piston-based conventional mode CMUT including a vent through via, fluidic channels, and a shaped plate comprising a curved profile, where the edge of the plate contacts the edge of the bottom electrode (e.g. the edge of plate 512 contacts insulating layer 514 that is positioned on bottom electrode 511).

[0219]

[0230] The bandwidth of a vacuum-based CMUT (e.g. a vacuum-based CMUT such as is shown in Fig. 4A), when operating in air (e.g. used in an airborne application), is limited by the resistance from the air medium. In some embodiments, to expand the operational bandwidth, squeeze film damping is introduced by venting the vacuum cavity. In some embodiments, trench 517 comprising one or more fluidic trenches or other pathways can be included to significantly expand the bandwidth, while increasing the sensitivity and lowering the driving voltage. In some embodiments, trench 517 combined with shaped electrodes (e.g. electrode 511 and / or 512) is included, which further improves the sensitivity (e.g. a sensitivity improvement of at least 2%, 5%, 10%, 25%, and / or 50%) and further reduces the driving voltage (e.g. a reduction in voltage of at least 2%, 5%, 10%, 25%, and / or 50%). Advantages of having both shaped electrodes (e.g. shaped electrodes 511s and / or shaped plate 512s) and trench 517 include but are not limited to: large operational bandwidth, such as between 2% and 200%; ease of control of the bandwidth by tuning the trench 517 height; very low driving voltage, for example as low as 50V, such as at most 10V or 5V; high transmit and receive sensitivities; and / or simplified packaging and housing (e.g. by using a PCB). Advantages of also having a piston-based CMUT (e.g. including one or more pistons 518) also include increased output sound pressure (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%).

[0220]

[0231] Referring now to Figs. 29A-29D, top views of a portion of CMUT components including fluidic trenches in various patterns are illustrated, consistent with the present inventive concepts. In Fig. 29A, CMUT 510 comprises a trench 517 with ring-shaped fluidic trenches as shown. In Fig. 29B, CMUT 510 comprises a trench 517a with trenches arranged to surround an array of micropillars, micropillars 5171 as shown. Micropillars 5171 can comprise a major axis (e.g. a diameter) that is no more than 5%, 10%, or 20% of the major axis (e.g. diameter) of cavity 513. In Fig. 29C, CMUT 510 comprises a trench 517b with trenches arranged in a fan pattern as shown. In Fig. 29D, CMUT 510 comprises a trench 517b including a hybrid set of trenches, including trenches 517a surrounding an array of micropillars 5171 positioned near the center of CMUT 510, and fan shaped trenches 517b positioned in the periphery of CMUT 510, each as shown. Gaseous squeeze film is introduced when the cavity is vented by the through via (e.g. vent 516 described herein) and controlled by the fluidic trenches. The fluidic trenches of trench 517 tune the stiffening and damping effects of the squeeze film to control the bandwidth, in which the stiffening effect acts as a spring and the damping effect represents a damper. The illustrated patterns and / or combinations of these patterns can effectively tune the stiffening and damping effects of the squeeze film while lowering the pull-in voltage by enlarging the area of electrodes on the substrate. Because the displacement of plate 512 varies from zero at its edge to a maximum at its center, different regions of plate 512 contribute differently to the output pressure and damping of CMUT 510. Micropillars 5171 can comprise pillars that are smaller near the center of CMUT 510, and the relative trench area can be larger near this center (e.g. where the plate 512 displacement is larger, and more trench area is needed to counter the stiffening effect of the squeeze film). Micropillars 5171 can be larger near the edge of CMUT 510 where plate 512 displacement is smaller, so less trench area is needed and more area can be devoted to the electrode on the micropillars 5171.

[0221]

[0232] Referring now to Figs. 30A-30Y, various charts and graphs of CMUT output and other performance characteristics are illustrated, consistent with the present inventive concepts. Applicant has performed analyses of the various airborne CMUT component configurations described herein. The results of these analyses are shown and are described hereinbelow.

[0222]

[0233] Analyses performed by the applicant have shown an airborne CMUT component configuration can include shaped electrodes and / or fluidic trenches to significantly widen the operational bandwidth of airborne CMUTs and lower the driving voltage, as described hereinabove, while improving transmit and receive sensitivities. The bandwidth of vacuumbased CMUTs is limited by the small resistance from the air medium. In some embodiments, a CMUT (e.g. CMUT 510 described herein) comprises squeeze film damping and fluidic trenches (e.g. trench 517) configured to allow the exchange between sensitivity and bandwidth by design. Advantages of having shaped electrodes and fluidic trenches are described herein.

[0223]

[0234] Various examples of airborne CMUT 5++10 comprising shaped electrodes and / or fluidic trenches for improving both transmit and receive sensitivities are shown in Figs. 21 A- 28D. In some embodiments, a CMUT 510 includes a vent, vent 516, comprising one or more vias, such as one or more vias that pass through bottom electrode 511 between cavity 513 and the medium surrounding CMUT 510. In some embodiments, a via can be located proximate the center of CMUT 510 and / or one or more vias can be located proximate the edge of CMUT 510. The position and distribution of the one or more vias can be configured to optimize performance.

[0224]

[0235] An airborne-enabled CMUT can comprise vent 516 that extends through a flat bottom electrode 511, for example as shown in Fig. 21 A. In some embodiments, bottom electrode 511 comprises electrode 511s comprising a multiple-profile step structure (e.g. a two profile step structure), stepped portion 5113, and vent 516, each as shown in Fig. 21B. In some embodiments, shaped bottom electrode 511s comprises sloped portion 5114 and vent 516, as shown in Fig. 21C. A shaped bottom electrode 511s can comprise curved portion 5115 and vent 516, as shown in Fig. 2 ID. The profile of curved portion 5115 can be derived from (e.g. be set similar to) the deflected shape of a flat plate that is being driven with a large DC bias or large AC excitation signal.

[0225]

[0236] In some embodiments, a shaped bottom electrode 511s comprising curved portion 5115 and vent 516 is in contact with plate 512 at the edge of CMUT 510, for example at contacting area 5116, as shown in Fig. 2 IE. The curvature of curved portion 5115 can be constructed and arranged (e.g. optimized) to improve receive sensitivity (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%) by increasing driving voltage beyond the pull-in voltage. For example, during deflection of plate 512, plate 512 gradually makes contact with curved portion 5115, such that plate 512 gradually shrinks and the spring constant of plate 512 increases, thus increasing the pull-in voltage. In some embodiments, plate 512 comprises stepped portion 5123 and bottom electrode 511 comprises vent 516, as shown in Fig. 22A. Plate 512 can comprise sloped portion 5124 and bottom electrode 511 can comprise vent 516 as shown in Fig. 22B. In some embodiments, plate 512 comprises curved portion 5125 and bottom electrode 511 comprises vent 516, as shown in Fig. 22C. The profile of curved portion 5125 can be derived from (e.g. be set similar to) the deflected shape of a flat plate that is being driven with a large DC bias or large AC excitation signal. In some embodiments, plate 512 comprising curved portion 5125 can be in contact with insulating layer 514 on bottom electrode 511 at contacting area 5126, as shown in Fig. 22D, in which the curvature of curved portion 5125 can be constructed and arranged (e.g. optimized) to improve receive sensitivity (e.g. a sensitivity increase of at least 2%, 5%, 10%, 25%, and / or 50%) by increasing driving voltage beyond the pull-in voltage, such as is described herein. In some embodiments, bottom electrode 511 can include trench 517 (e.g. created with an etching process), where the trenches of trench 517 are configured to tune the squeeze film damping. CMUT 510 configurations including a trench 517 are shown in Figs. 23A-24D. The configurations shown in Figs. 23 A-24D can be similar to the configurations shown in Figs. 21A-22D, respectively, and can comprise similarly shaped electrodes, as described herein. CMUT 510 comprising piston-based CMUTs each including a piston 518 are shown in Figs. 25A-28D. The configurations shown in Figs. 25A-28D can be similar to the configurations shown in Figs. 21 A-Fig. 24D, respectively, and can comprise similarly shaped electrodes, vents, and / or fluidic trenches, as described herein.

[0226]

[0237] Applicant designed and simulated the performance of airborne CMUTs comprising various configurations, as described herein. In the stimulation, the following parameters were used: an operating frequency of 100 kHz; a 50pm thick plate 512; a plate 512 radius of 1500pm; and a gap height as small as 1pm. Simulations showed that with the shaped electrodes (e.g. shaped electrode 511s and / or shaped plate 512s), the pull-in voltage is decreased by around 70%. With the inclusion of trench 517, the pull-in voltage remains low. The pressure caused by the squeeze film damping on the substrate is reduced by 50 times, which makes the squeeze film damping dominate the dynamic behavior of a CMUT 510. However, the bandwidth can be widened up to at least 30% based on the trench 517 heights of the associated CMUT 510. The transmit and / or receive sensitivities are also improved (e.g. a sensitivity increase for either or both of at least 2%, 5%, 10%, 25%, and / or 50%) by the gap height being arranged in the sub micrometers range (e.g. less than 1pm). Simulations also showed that the bandwidth can be easily widened up to 30% based on the trench 517 heights of the associated CMUT 510, for example trench heights greater than 1pm and / or less than 100pm. In configurations with smaller gap heights, bandwidth can be over 150%. Simulations performed by applicant have shown the various CMUT 510 configurations described herein enabled the driving voltage to be lowered down to 10V, which is not practical to achieve in standard configurations. For example, the pull-in voltage of the flat configuration CMUT was measured at 32.8V, while a stepped profile arrangement achieved a 40% decrease (19.7V) in pull-in voltage, a sloped arrangement achieved a 59% decrease (13.4V) in pull-in voltage, and a curved arrangement achieved a 67% decrease (10.8V) in pull-in voltage.

[0227]

[0238] Fig. 30A shows the shape of a deflected flat plate biased by 90% of the pull-in voltage.

[0228]

[0239] Fig. 30B shows squeeze film pressure on the substrate for the standard flat electrode, vented CMUT without fluidic trenches.

[0229]

[0240] Fig. 30C shows a front view of a trench 517 comprising fluidic trenches for a CMUT 510 comprising a standard flat electrode CMUT.

[0230]

[0241] Fig. 30D shows a cross-sectional view of fluidic trenches for a standard flat electrode CMUT.

[0231]

[0242] Fig. 30E shows a graph of squeeze film pressure on the substrate of a standard flat electrode, vented CMUT with ring-shaped fluidic trenches. The pull-in voltage of the associated configuration was measured at 34.34V. For CMUTs 510 comprising ring-shaped fluidic trenches to tune the squeeze film, the pressure on the substrate is lowered to more than 50 times less than that of a similar design without fluidic trenches. By optimizing the distribution of the fluidic trenches, the pressure on the substrate becomes uniform, which enlarges the area of electrodes, thus increasing the effective capacitance and lowering the pull-in voltage.

[0232]

[0243] Fig. 30F shows the shape of a deflected two profile step plate, biased by 90% of pull-in voltage.

[0233]

[0244] Fig. 30G shows a graph of the squeeze film pressure on the substrate of a two profile step electrode, vented CMUT without fluidic trenches.

[0234]

[0245] Fig. 30H shows a front view of a trench 517 comprising fluidic trenches for a CMUT 510 comprising a two profile step electrode CMUT.

[0235]

[0246] Fig. 301 shows a cross-sectional view of fluidic trenches for a two profile step electrode CMUT.

[0236]

[0247] Fig. 30J shows a graph of squeeze film pressure on the substrate of a two profile step electrode, vented CMUT with fluidic trenches. The pull-in voltage of the associated configuration was measured at 22.85V, which is 33% lower than that of standard flat electrode design. As described above, for CMUTs 510 comprising ring-shaped fluidic trenches to tune the squeeze film, the pressure on the substrate is lowered nearly 50 times less than that of a similar design without fluidic trenches. The distribution of the fluidic trenches can be optimized to make the pressure on the substrate uniform, thus enlarging the area of electrodes and increasing the effective capacitance.

[0237]

[0248] Fig. 3 OK shows the shape of a deflected plate with sloped electrodes, biased by 90% of pull-in voltage.

[0238]

[0249] Fig. 30L shows a graph of the squeeze film pressure on the substrate of a sloped electrode, vented CMUT without fluidic trenches.

[0239]

[0250] Fig. 30M shows a front view of a trench 517 comprising fluidic trenches for a CMUT 510 comprising a sloped electrode CMUT.

[0240]

[0251] Fig. 30N shows a cross-sectional view of fluidic trenches for a sloped electrode CMUT.

[0241]

[0252] Fig. 300 shows a graph of squeeze film pressure on the substrate of a sloped electrode, vented CMUT with fluidic trenches. The pull-in voltage of the associated configuration was measured at 17.03 V, which is 50% lower than that of standard flat electrode design. By adding and optimizing the ring-shaped fluidic trenches to tune the squeeze film, the pressure on the substrate has been lowered more than 65 times less than that of a similar design without fluidic trenches.

[0242]

[0253] Fig. 30P shows the shape of a deflected plate with curved electrodes, biased by 90% of pull-in voltage.

[0243]

[0254] Fig. 30Q shows a graph of the squeeze film pressure on the substrate of a curved electrode, vented CMUT without fluidic trenches.

[0244]

[0255] Fig. 30R shows a front view of a trench 517 comprising fluidic trenches for a CMUT 510 comprising a curved electrode CMUT.

[0245]

[0256] Fig. 30S shows a cross-sectional view of fluidic trenches for a curved electrode CMUT.

[0246]

[0257] Fig. 30T shows a graph of squeeze film pressure on the substrate of a curved electrode, vented CMUT with fluidic trenches. The pull-in voltage of the associated configuration is 14.49V, which is 56% lower than that of standard flat electrode design. By adding and optimizing the ring-shaped fluidic trenches to tune the squeeze film, the pressure on the substrate has been lowered more than 60 times less than that of a similar design without fluidic trenches.

[0247]

[0258] Fig. 30U compares the transmit sensitivity of various electrode shapes of vented CMUTs.

[0259] Fig. 30V compares the receive sensitivity of various electrode shapes of vented CMUTs.

[0248]

[0260] Fig. 30W compares the transmit sensitivity of various electrode shapes of vented CMUTs with fluidic trenches.

[0249]

[0261] Fig. 3 OX compares the receive sensitivity of various electrode shapes of vented CMUTs with fluidic trenches.

[0250]

[0262] Fig. 30Y compares the transmit sensitivity and bandwidth of CMUTs with varying fluidic trench height, where the DC bias is 90% of the pull-in voltage. The bandwidth has been widened by introducing squeeze film and controlled by optimizing the fluidic trenches to tune the damping and stiffening effects of the squeeze film. The bandwidth can be tuned in a large range by adjusting the trench height, which simplifies the designs, optimizations, and fabrication of wide bandwidth airborne CMUTs 510. In some embodiments, trench 517 of the present inventive concepts comprises one or more trenches with a height (e.g. a depth) of at least 1pm, or 2pm and / or a height of no more than 15pm, 20pm, 30pm, or 40pm.

[0251]

[0263] Referring now to Fig. 31, a cross-sectional view of an embodiment of a CMUT with a shaped dielectric is illustrated, consistent with the present inventive concepts. CMUT 510 of Fig. 31 can be of similar construction and arrangement to CMUT 510 described in reference to Fig. 1 and otherwise herein. CMUT 510 can comprise bottom electrode 511, onto which dielectric layer 514 and support 515 are positioned. As shown in Fig. 31, support 515 and dielectric layer 514 can comprise one or more similar materials, such as silicon dioxide. Plate 512 is positioned on top of support 515, such that cavity 513 is formed between dielectric layer 514 and plate 512. Plate 512 can comprise a multi-layer construction, as shown, such as a construction comprising a first conductive layer 5121a that comprises a conductive material (e.g. doped silicon), and a second conductive layer 5121b that comprises another conductive material (e.g. aluminum). Alternatively, plate 512 can comprise a single layer construction (e.g. a single layer of doped silicon). Dielectric layer 514 can comprise a non-flat geometry (e.g. a contoured geometry as described herein), such as a geometry where the edges of dielectric layer 514 are thicker (e.g. closer to plate 512) than the center. The geometry of dielectric layer 514 can be selected to optimize the capacitance of CMUT 510 (e.g. while avoiding obstruction of the plate motion).

[0252]

[0264] The capacitance of a parallel plate capacitor is represented by:

[0253] C = 8rS() A / d where A is the plate area, d is the plate separation, sris the relative permittivity of the dielectric layer 514, and so is the vacuum permittivity. For a capacitor with a vacuum layer of thickness do, a dielectric layer 514 of thickness dins and relative permittivity srbetween the plates, we can define an effective gap height as: deff—do + dins / Er such that the capacitance is:

[0254] C = SoA / deff.

[0255]

[0265] Referring additionally to Fig. 31A, a schematic representing the capacitance of a CMUT is illustrated, consistent with the present inventive concepts. CMUT 510 of Fig. 31 A comprises bottom electrode 511 and plate 512, separated by shaped dielectric layer 514s and cavity 513. CMUT 510 can be modeled as a series of multiple parallel plate capacitors, as shown in Fig. 31 A. In the case of a flat bottom electrode 511, flat dielectric layer 514 (not shown), and flat plate 512, do + dins is constant across the cavity region in this model of CMUT 510 when the plate is not deflected. In some embodiments, the capacitance C for a segment of CMUT 510 (e.g. an edge segment) can be increased (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%) by decreasing the effective gap height deff. For example, by increasing the thickness of shaped dielectric layer 514s in a segment of CMUT 510, dins increases and do decreases, and with an sr>1 (e.g. sr= 3.8 for silicon dioxide), the effective gap height deff decreases.

[0256]

[0266] Referring additionally to Figs. 31B and 31C, cross-sectional views of various CMUT components comprising shaped dielectric layers are illustrated, consistent with the present inventive concepts. Fig. 3 IB shows a CMUT 510 comprising a stepped profile dielectric layer 514s (e.g. a dielectric layer 514s comprising one or more profile steps). Fig. 31C shows a CMUT 510 comprising a curved dielectric layer 514s. In some embodiments, the shape of curved dielectric layer 514s approximates the profile of plate 512 when plate 512 is fully deflected.

[0257]

[0267] CMUT 510 of Figs. 31A-31C, and other CMUTs 510 as described herein, can include a shaped plate 512s, while including a non-shaped (e.g. flat) bottom electrode 511. Advantages of this configuration include but are not limited to: simplified fabrication process (e.g. by eliminating the need to etch into the bottom electrode 511 to form a contoured or other non-flat shape, or by eliminating the need to add a curved support layer for the electrode 511 to be positioned on); and / or fabrication of all or a portion of CMUT 510 directly on top of integrated circuits (e.g. where it would not be possible to etch into electrode 511). Avoidance of a shaped electrode for electrode 511 avoids the limitations imposed regarding how close the bottom electrode 511 can be to the plate 512 near the edge of CMUT

[0258] 510 (e.g. because there must be a thick enough dielectric layer 514 between electrode 511 and plate 512) to prevent dielectric breakdown.

[0259]

[0268] Referring now to Fig. 32, a cross-sectional view of a CMUT comprising a multilayer dielectric is illustrated, consistent with the present inventive concepts. CMUT 510 of Fig. 32 comprises dielectric layer 514s which comprises a first portion 5141 and a second portion 5142. First portion 5141 can comprise a thickness that is determined such that the maximum electric field experienced by the dielectric during operation is a particular fraction of the dielectric strength of the dielectric, such as a fraction of at least 15%, 22%, or 30% and / or a fraction of no more than 40%, 50%, 60%, 70%, 77% or 85% of the dielectric strength of the dielectric layer. First portion 5141 can comprise one, two, or more of various materials, such as similar and / or dissimilar materials, such as: silicon oxide and / or silicon nitride. Second portion 5142 can comprise a thickness determined such that the comers of portion 5142 do not contact plate 512 when plate 512 is maximally deflected. Second portion 5142 can comprise one, two, or more of various materials, such as similar and / or dissimilar materials, such as: silicon nitride; hafnium oxide; zirconium silicate; hafnium silicate; and / or zirconium dioxide. First portion 5141 can comprise a first material comprising a first k value and a first dielectric strength. First portion 5141 can be positioned between bottom electrode

[0260] 511 and plate 512. Second portion 5142 can comprise a second material comprising a second k value, higher than the first k value of first portion 5141, such as a k value of more than 3.8, and a second dielectric strength. Second portion 5142 can be positioned proximate to the edges of plate 512, as shown. In some embodiments, the second material of second portion 5142 comprises a dielectric material with a high k value, such as a k value of more than 3.8, such as a dielectric material selected from the group consisting of: hafnium oxide; zirconium silicate; hafnium silicate; zirconium dioxide; and combinations of these. The first material of first portion 5141 can comprise a relatively lower k value dielectric material, such as a dielectric material selected from the group consisting of: silicon nitride; silicon oxide; and combinations of these. In some embodiments, dielectric layer 514s comprises a single material comprising a dielectric material with a high k value, such as a k value of more than 3.8. In some embodiments, one or more portions of layer 514s can be deposited (e.g. deposited onto bottom electrode 511 in a CMUT manufacturing process) using atomic layer deposition. Portions of CMUT 510 comprising insulative layer second portion 5142 can comprise a greater capacitance C (e.g. a capacitance that is at least 2%, 5%, 10%, 25%, and / or 50% greater), as a greater srvalue lowers the effective gap height deir.

[0261]

[0269] CMUT 510 of Fig. 32, and other CMUTs 510 described herein, can include a multi-layer dielectric layer 514, such as when a first layer comprises a high k value dielectric layer which is positioned on top of a second layer comprising silicon dioxide. Such arrangements can provide numerous advantages. For example, a material with higher dielectric strength but lower relative permittivity can be used as a bottom layer to prevent breakdown, while a material with higher relative permittivity but lower dielectric strength can be used as a top layer to provide increases in capacitance (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%) at the edge of the CMUT 510.

[0262]

[0270] Referring now to Fig. 33, a set of steps of a method of manufacturing a CMUT with a stepped profile dielectric layer is illustrated, consistent with the present inventive concepts. In Step A, oxide is delivered onto a silicon wafer (bottom electrode 511), for example via low pressure chemical vapor deposition (LPCVD). In Step B, the oxide layer deposited in Step A is patterned as shown. In Step C, an additional layer of oxide is delivered, which is again etched as shown in Step D. In Step E, another layer of oxide is delivered. The oxide layer geometry resulting from Step A through Step E forms a stepped profile dielectric layer 514s (e.g. a dielectric layer 514 comprising one or more profile steps), as well as support 515. In Step F, a SOI wafer (“silicon on insulator” wafer) is bonded to support 515, with the device layer forming plate 512. In some embodiments, one or more additional depositing profile steps and / or etching profile steps can be repeated to form one or more “profile steps” and / or other desired geometric features in dielectric layer 514.

[0263]

[0271] Referring now to Fig. 34, a set of steps of a method of manufacturing a CMUT with a stepped profile bottom electrode and a stepped profile dielectric layer is illustrated, consistent with the present inventive concepts. In Step A, oxide is delivered onto a silicon wafer (bottom electrode 511), for example via LPCVD. In Step B, the oxide layer deposited in Step A is patterned as shown. In Step C, an additional layer of oxide is delivered, which is again etched in Step D. In Step E, a thermal oxidation process is performed, oxidizing a portion of the silicon wafer to increase the thickness of the oxide layer while forming the stepped profile of the silicon layer shown. In Step F, a SOI wafer is bonded to support 515, and the handle and buried oxide layers are removed, forming plate 512. In some embodiments, one or more additional depositing steps (e.g. thermal oxidizing steps) and / or etching steps can be repeated to form one or more profile steps and / or other desired geometric features in dielectric layer 514. Alternatively or additionally, one or more etchingbased processes can be employed to modify the profile of one or more components of CMUT 510.

[0264]

[0272] Referring now to Figs. 35A-35D, cross-sectional views of CMUT configurations to be analyzed and graphs of transmit and receive sensitivity of the illustrated CMUT configurations are illustrated, consistent with the present inventive concepts. Applicant has performed finite element analysis of various CMUT configurations. A standard CMUT component (shown in Fig. 35 A) was analyzed and compared to a CMUT component comprising a shaped dielectric layer 514s (shown in Fig. 35B). The CMUT configurations are both radially symmetric (e.g. the CMUTs are circular). The CMUTs are the same in all aspects with the exception of the presence of additional shaped dielectric material in the shaped dielectric layer 514s arrangement. The analyzed CMUTs each comprise a plate, cavity, dielectric layer, and bottom electrode, as shown. The plate 512 of each CMUT 510 comprises three layers (listed from bottom to top): a 1.1 pm thick layer of highly doped silicon; a 250 nm thick layer of aluminum; and a 100 nm thick layer of silicon nitride. The gap in the center of each cavity 513 has a height of 275 nm. The dielectric layer 514 comprises silicon dioxide with a thickness in the center of the CMUT of 150 nm. The shaped dielectric CMUT (shown in Fig. 35B) additionally has two profile steps of dielectric on top of the base 150 nm layer (as shown). The first profile step starts at a radius of 9 pm and is 75 nm high. The second profile step starts at a radius of 15 pm and is 175 nm high. The top plate of each CMUT forms the top electrode (e.g. plate 512) and the highly doped silicon substrate forms the bottom electrode (e.g. electrode 511).

[0265]

[0273] Both of the above described CMUT 510 configurations have the same plate 512 dimensions and therefore the same resonance frequency. These CMUT 510 configurations are configured to operate at 5 MHz in water. The shaped dielectric layer 514s comprises a stepped profile to provide space for the same maximum possible plate 512 displacement as the standard component configuration, without the plate 512 contacting the dielectric layer 514. The standard CMUT configuration has a pull-in voltage of 100.4 V, while the associated shaped dielectric layer 514s configuration has a pull-in voltage of 83.0 V. This 17% reduction in pull-in voltage is advantageous because it reduces the voltage required to operate the CMUT, and it reduces the risk of dielectric breakdown.

[0266]

[0274] In Fig. 35C, the graph illustrates a comparison of the transmit sensitivity (the pressure output per applied volt) of the two CMUT configurations of Figs. 35 A and 35B. In both cases, a DC bias voltage equal to 80% of the pull-in voltage is applied. The shaped dielectric layer 514s arrangement has 25% greater maximum transmit sensitivity than the standard, flat dielectric layer 514 arrangement.

[0267]

[0275] In Fig. 35D, the graph illustrates a comparison of the receive sensitivity (the output current per incident pressure) of the two CMUT configurations of Figs. 35 A and 35B. In both cases, a DC bias voltage equal to 80% of the pull-in voltage is applied. The shaped dielectric layer 514s arrangement has 25% greater maximum receive sensitivity than the standard dielectric layer 514 configuration. In a typical use (e.g. pulse-echo imaging), the improvement illustrated in Figs. 35C and 35D shows a 56% improvement in the two-way sensitivity in comparing the CMUT configuration of Fig. 35B to that of Fig. 35 A.

[0268]

[0276] Applicant has discovered via computer simulation, that CMUT 510 configurations including a shaped dielectric layer 514s (as described herein) provide a strong “catching effect” on the plate when the plate displacement becomes large, or the device is operated in collapsed mode. In other words, when the plate 512 is pulled close to the dielectric layer 514 (e.g. a dielectric layer 514s comprising a shape that approximates the deflected shape of the plate 512), the force on the plate 512 is greater than if the dielectric layer 514 were flat as in a standard CMUT configuration. This discovery by applicant is advantageous for numerous reasons, such as are described immediately hereinbelow.

[0269]

[0277] For example, when operated in collapsed mode, devices can be used with a low (e.g. very low) snapback voltage. As a result, collapsed mode operation with very low DC bias voltages can be performed. For example, snapback voltage can be less than 30%, 40%, 50%, or 60% of the pull-in voltage.

[0270]

[0278] In another example, electrically tunable frequency of operation using strong spring softening can be employed.

[0271]

[0279] In yet another example, CMUT 510 can be configured as a two-state pre-charged component. The pre-charged CMUT 510 can include a built-in bias voltage, which is produced by trapping electrostatic charge at a location between the top and bottom electrode. With strong hysteresis from the catching effect, the snap-back voltage is lower, and the same DC bias voltage can be used in both conventional and collapsed mode operation. The CMUT 510 can be alternated between the two states by applying a voltage temporarily. The CMUT 510 has a different center frequency in collapsed and conventional mode, so this technique allows the same device to operate at two different frequencies. This could be useful, for example, to switch between a higher frequency, shorter range, higher resolution mode and a lower frequency, longer range, lower resolution mode in airborne ultrasound applications.

[0272]

[0280] In yet another example, a combination of a drive signal including half-wave excitation and / or unipolar pulses and a CMUT 510 with a shaped dielectric layer 514s can be employed. For example, a drive signal can comprise a high-wave excitation arrangement as described in United States Patent Application Number US20220152651A1. The catching effect reduces the maximum displacement as a fraction of the gap height that the plate can sustain under conventional sinusoidal or square wave AC excitation. The half-wave excitation technique might allow increased use of the gap. For example, with half-wave excitation, more force can be applied on the plate 512 before it reaches its peak amplitude, at which time the force can be rapidly reduced to reduce the catching effect.

[0273]

[0281] In yet another example, various dielectric layer 514s profiles can be included to optimize sensitivity versus pressure. Depending on the need for transmit and receive sensitivity versus a maximum pressure, a shaped dielectric layer 514s whose profile approximates (e.g. matches) the plate 512 deflection profile may not be optimal. Some degree of mismatch can be beneficial to reduce the catching effect. In modeling performed by applicant, with a dielectric layer 514s with a high k value, such as a k value of more than 3.8, and in a ring geometry, varying the inner radius of the ring varies the optimized performance between pressure (e.g. maximum pressure) and sensitivity. Rings of dielectric material can be positioned at different locations to tune the plate 512 displacement profile. The force on plate 512 is greater in regions where the dielectric ring is present, and so the force profile on plate 512 can be engineered to tune the plate displacement profile.

[0274]

[0282] In yet another example, a constraint on relative permittivity of the dielectric layer 514 can be 3.8. As sr is increased, an increase in sensitivity occurs (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%). As sr is increased further, there is little additional gain in sensitivity, but the catching effect strength increases (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50%). An appropriate range of sr can be used to improve sensitivity (e.g. a sensitivity increase of at least 2%, 5%, 10%, 25%, and / or 50%) without too much catching effect. Useful improvements to transmit and / or receive sensitivity can be realized with common dielectric materials with sr in the range of 3 to 6, such as silicon oxide and silicon nitride. Alternatively, dielectrics with sr greater than 6 can be used in parts of the insulating layer while lower dielectric constant materials form the remainder of the insulating layer.

[0275]

[0283] In yet another example, a CMUT 510 can be configured to receive without also transmitting, such as when used in photoacoustic and / or thermoacoustic devices (e.g. one or more CMUTs 510 are integrated into a device 100 configured to perform a photoacoustic and / or a thermoacoustic application). In these embodiments, maximizing the output pressure is not a design goal, so CMUT 510 features can be optimized (e.g. aggressively optimized) for high sensitivity. High sensitivity can be achieved with a shaped dielectric layer 514s with a high k value, such as a k value of more than 3.8. In these embodiments, gap heights can be very low, such as less than lOOnm, while still having a fairly thick dielectric layer 514, such as at least lOOnm. Also in these embodiments, CMUT 510 can be configured for low bias voltage operation (e.g. at most 20V, at most 15 V, or at most 10V), while still achieving high receive sensitivity.

[0276]

[0284] In yet another example, a CMUT 510 can be configured to be used in airborne ultrasound applications, such as are described herein. These applications could include ultrasonic flow metering of gasses, gesture sensing, obstacle sensing for cars and drones, and / or ultrasonic sensing of compressed gas leaks.

[0277]

[0285] Referring now to Fig. 36, a set of steps of a method of manufacturing a CMUT comprising a shaped bottom electrode is illustrated, consistent with the present inventive concepts. In Step A, a silicon wafer is shaped using local oxidation, such as is described herein. In Step B, support 515 is formed using local oxidation. In Step C, support 515 is etched, such as to define the edge of CMUT 510, and to create the shaped structure of dielectric layer 514. In Step D, the dielectric layer 514 is formed, for example via thermal oxidation. After Step D, CMUT 510 can be completed using one or more bonding techniques, such as fusion bonding.

[0278]

[0286] CMUT 510 can comprise a structure with a shaped bottom electrode 511s and a shaped dielectric layer 514s. In some embodiments, CMUT 510 comprises a thick support 515, such as a support 515 with a thickness greater than the thickness of insulating layer 514 plus the maximum gap height of CMUT 510 (e.g. the gap height at the center of CMUT 510). The increased thickness of support 515 can reduce parasitic capacitance of CMUT 510. The structure of CMUT 510 can be configured to reduce parasitic capacitance, while achieving a desired transmit and receive sensitivity. As shown, an elevated profile step of silicon material can be positioned around the edge of CMUT 510 (e.g. instead of in the middle of CMUT 510). This positioning creates a shaped bottom electrode 511s, and a support 515 (e.g. a thickened oxide support). In some embodiments, for example embodiments including the shaped electrode 511s and / or shaped dielectric layer 514s embodiments as described herein, the support 515 thickness is coupled to the gap height (e.g. the support 515 thickness equals the gap height plus the dielectric layer 514 thickness). The method of Fig. 36 allows for a support 515 with an increased thickness, such as a thickness greater than 500nm, and / or a thickness of no more than 2pm. This increased thickness can reduce the parasitic capacitance of the support area (e.g. a decrease in parasitic capacitance of at least 2%, 5%, 10%, 25%, and / or 50%), and / or reduce the risk of dielectric breakdown. Parasitic capacitance degrades the receive sensitivity of CMUT 510 by providing a parallel impedance to circuit ground for the receive current. For the same reason, the increased thickness of support 515 can also increase the power requirements when operating in transmit mode. The area of support 515 can make a substantial contribution to parasitic capacitance, for example when support 515 is relatively thin. The method of Fig. 36 allows for very fine control of the gap height, and allows manufacture of CMUTs 510 with a small gap height, such as a gap height of less than lOOnm, for example for low-voltage operation of less than 100 V.

[0279]

[0287] Referring now to Fig. 37, a set of steps of a method of forming a sloping silicon layer is illustrated, consistent with the present inventive concepts. CMUT transducers, such as CMUT 510 described herein, can be fabricated using various microfabrication processes, such as those described herein. The steps shown in Fig. 37 illustrate a method of fabricating a sloped silicon layer using a LOCOS (Local Oxidation of Silicon) process and a sloped silicon oxide mask. Step A illustrates a sloping silicon oxide mask that has been applied to an SOI wafer, for example using LPCVD. After a thermal oxidation process, where the oxidation pattern correlates to the thickness of the silicon oxide mask, the silicon oxide is removed, and the remaining SOI wafer comprises a sloped profile, as shown in Step B. This sloped wafer can be incorporated into the manufacturing of a CMUT 510, for example as the bottom electrode 511 and / or the plate 512, as described herein.

[0288] Referring now to Fig. 38, a set of steps of a method of forming a shaped silicon layer is illustrated, consistent with the present inventive concepts. The steps shown in Fig. 38 illustrate a method of fabricating a shaped silicon layer using a LOCOS process and a patterned oxide mask. Step A illustrates a patterned silicon oxide mask that has been applied to an SOI wafer. After a thermal oxidation process, where the oxidation pattern correlates to the thickness of the silicon oxide mask, the silicon oxide is removed and the remaining SOI wafer comprises a shaped profile, as shown in Step B. This shaped wafer can be incorporated into the manufacturing of a CMUT 510, for example as the bottom electrode 511 and / or the plate 512, as described herein.

[0280]

[0289] Referring now to Fig. 39, a set of steps of a method of fabricating a CMUT with a shaped plate is illustrated, consistent with the present inventive concepts. The steps shown in Fig. 39 illustrate a method of fabricating a CMUT, such as CMUT 510 described herein, using a sacrificial layer in the process. Step A illustrates a shaped (e.g. sloped as shown) sacrificial layer that has been deposited onto a silicon wafer and patterned as shown. In Step B, a metal layer has been applied, such as via an evaporation and / or a sputtering process. In Step C, the top of the metal layer has been flattened, such as via chemical-mechanical polishing (CMP). In Step D, the sacrificial layer and the metal layer have been patterned to reveal a portion of the wafer (e.g. an “anchor” region). In Step E, a dielectric material is deposited onto the assembly, where a portion of the deposited dielectric material is anchored to the wafer in the anchor region, and the dielectric material extends across the top of the metal layer. In Step F, the sacrificial layer is removed, releasing plate 512, comprising insulative layer 5122 and conductive layer 5121, from bottom electrode 511. Support 515 extends from the anchor region to the sides of plate 512.

[0281]

[0290] Referring now to Fig. 40, a set of steps of a method of fabricating a CMUT with a shaped bottom electrode is illustrated, consistent with the present inventive concepts. The steps shown in Fig. 40 illustrate a method of fabricating a CMUT, such as CMUT 510 described herein, using a multiple profile step oxide passivation layer. In Step A, a layer of silicon oxide (an “oxide mask”) has been applied to a silicon wafer, such as via thermal oxidation or LPCVD. In some embodiments, the thickness of the oxide mask is determined based on the desired profile step height resulting from the thermal oxidation of Step D. In Step B, photoresist has been applied, such as via lithography, and the silicon oxide layer has been etched where the photoresist is not present, such as via reactive-ion etching (RIE). The thickness of the etched oxide mask can be configured to control the height of the features to be created in the wafer. In Step C, additional photoresist has been applied, and the silicon oxide layer has been etched again. In Step D, the assembly has undergone thermal oxidation, where the oxide mask slowed the oxidation of the silicon wafer based on the height of the mask. In Step E, photoresist has been applied, and the silicon oxide layer has been etched, such as via buffered oxide etching (BOE). In Step F, a final thermal oxidation can be performed to form an insulating layer (e.g. dielectric layer 514) over the stepped profile silicon wafer. Step F results in a stepped profile bottom electrode 51 Is of CMUT 510, with dielectric layer 514 and support 515. A similar process can be used to fabricate a stepped profile plate 512s, as described herein.

[0282]

[0291] Referring now to Fig. 41, a set of steps of a method of fabricating a CMUT with a shaped bottom electrode is illustrated, consistent with the present inventive concepts. The steps shown in Fig. 41 illustrate a method of fabricating a CMUT, such as CMUT 510 described herein, using selective oxidation. In Step A, a silicon wafer has been patterned as described in reference to Fig. 40 herein. The wafer comprises multiple profile steps, and a layer of silicon oxide is positioned on the wafer, as shown. In Step B, a layer of silicon nitride has been applied, such as via LPCVD. In Step C, photoresist has been applied, and the silicon oxide and the silicon nitride layer have been etched, as shown. In Step D, the assembly has undergone thermal oxidation, such that the stepped profile of the silicon wafer now comprises a sloped profile, where each profile step gradually transitions, as shown. In some embodiments, the transition length (e.g. the slope) can be precisely controlled by controlling the thickness of the oxide passivation layer and / or the oxidation time. In Step E, the nitride layer has been removed, lithography was applied, and the unmasked oxide layer was removed, such as via BOE. In Step F, a final thermal oxidation can be performed to form an insulating layer (e.g. dielectric layer 514) over the sloped silicon wafer. Step F results in a sloped bottom electrode 51 Is of CMUT 510, with dielectric layer 514 and support 515. A similar process can be used to fabricate a sloped plate 512s, described herein.

[0283]

[0292] Referring now to Fig. 42, a set of steps of a method of fabricating CMUTs with shaped plates is illustrated, consistent with the present inventive concepts. The steps shown in Fig. 42 illustrate a method of fabricating two CMUT cells, such as CMUT 510 described herein, each comprising a shaped plate. In Step A, the fabrication starts with an SOI wafer. In Step B, two recesses (one per CMUT) have been created in the SOI wafer, as shown, for example via thermal oxidation and etching. In Step C, thermal oxidation is performed to create an oxide layer, which is then etched to form the profile shown. Step C shows a simple plate 512s shape, comprising a single level change (e.g. a single profile step), however various shapes can be achieved, such as those described herein. In Step D, a silicon wafer is thermally oxidized to create a layer of silicon oxide, and the shaped SOI wafer is flipped and aligned with the silicon wafer. In Step E, the two wafers are bonded together, such as via fusion bonding. In Step F, the handle layer and buried oxide layer of the SOI wafer are removed, such as via grinding and etching. In Step G, openings are etched through the SOI wafer to the silicon of the silicon wafer. In Step H, aluminum is deposited and patterned, such as to form an array of two CMUTs, CMUT 510a and 510b, shown. CMUTs 510a and 510b each comprise a shaped plate 512s, as shown. In some embodiments, additional steps can be performed, for example an (added) passivation step, a metal stacking (e.g. on bonding pads) step, and / or other micro-fabrication steps, such as those described herein.

[0284]

[0293] Referring now to Fig. 43, a set of steps of a method of fabricating top plates for a CMUT is illustrated, consistent with the present inventive concepts. The steps shown in Fig. 43 illustrate a method of fabricating two shaped plates, such as for two CMUT cells, such as two CMUTs 510 described herein, each plate comprising a multiple profile step profile. In Step A, the fabrication starts with an SOI wafer. In Step B, a layer of silicon oxide, and a layer of silicon nitride are deposited onto the silicon layer of the SOI wafer, for example via thermal oxidation and LPCVD, respectively. The oxide and nitride layers can be patterned as shown. These layers can comprise a mask for thermal oxidation. In Step C, thermal oxidation is performed, consuming unmasked silicon of the SOI wafer. In Step D, the oxide formed via the thermal oxidation is removed. In Step E, the oxide and nitride layers are again patterned, as shown. In Step F, another thermal oxidation is performed. In Step G, the oxide formed via the thermal oxidation is removed. In Step H, the oxide and nitride layers are removed. In Step I, thermal oxidation is performed to create an oxide layer, which is then etched to form the assemblies shown, comprising two plates 512s.

[0285]

[0294] In some embodiments, Steps A-I of Fig. 43 replace Steps A-C of Fig. 42. The process illustrated in Fig. 43 shows the formation of two profile steps in the contour of plate 512s, however steps of the process can be repeated to form more profile steps in the contour of plate 512s. In some embodiments, the contour of the profile steps created is smoother than the sharp profile steps shown in Fig. 43.

[0286]

[0295] Referring now to Fig. 44, a set of steps of a method of fabricating top plates for a CMUT is illustrated, consistent with the present inventive concepts. The steps shown in Fig. 44 illustrate a method of fabricating two shaped plates, such as for two CMUTs, such as two CMUTs 510 described herein, where each plate comprises a shape achieved via greyscale lithography. In Step A, the fabrication starts with an SOI wafer. In Step B, a layer of photoresist is applied and is exposed using greyscale lithography. In Step C, the silicon is etched, where the depth of the etch depends on the pattern of the greyscale lithography. In Step D, thermal oxidation is performed, to create the profile shown, including a shaped plate 512s.

[0287]

[0296] Referring now to Figs. 45A-45D, sectional schematic views of various CMUT designs, and graphs of CMUT performance are illustrated, consistent with the present inventive concepts. Fig. 45A shows a schematic of a CMUT 510, comprising a standard CMUT with a bottom electrode 511 comprising a flat geometry, and a plate 512 comprising a flat geometry. The sets of dashed lines illustrated indicate corresponding deflected shapes of plate 512 when associated bias voltages are applied to CMUT 510. The conventional shape shown represents the shape of plate 512 when a bias voltage below the collapse voltage of CMUT 510 is applied. The collapse shape shown represents the shape of plate 512 when a bias voltage at or with a range above the collapse voltage of CMUT 510 is applied. The deep collapse shape shown represents the shape of plate 512 when a bias significantly above the collapse voltage is applied, for example at least 300% above the collapse voltage, such as at least 400% above the collapse voltage. Fig. 45B shows a graph of the resonant frequency of CMUT 510 relative to the bias voltage. The varying states of CMUT 510 are shown as the bias voltage increases.

[0288]

[0297] In some embodiments, CMUT 510 can comprise a bottom electrode 511s with a non-flat geometry, as shown in Fig. 45C, and / or a plate 512s with a contoured (e.g. non-flat) geometry, not shown but described herein. The contoured (e.g. non-flat) shape of bottom electrode 511s (or plate 512s) can be configured to allow CMUT 510 to operate in more than one collapsed state each requiring a lower bias voltage than would be required to reach a “deep collapse” state of a similar standard CMUT. For example, bottom electrode 511s can comprise a stepped profile, such as is described herein, and as shown in Fig. 45C. Alternatively or additionally, bottom electrode 511s can comprise a curved, or other shaped profile, as described herein. In some embodiments, CMUT 510 comprises an insulator layer positioned on the bottom of plate 512 and / or on the top of bottom electrode 511s. The dashed lines of Fig. 45C indicate the deflected shape of plate 512 when a bias voltage is applied to CMUT 510. The conventional shape shown represents the shape of plate 512 when a bias voltage below the collapse voltage of CMUT 510 is applied. The first collapse shape shown represents the shape of plate 512 when a bias voltage at the first collapse voltage but below the second collapse voltage of CMUT 510 is applied. The second collapse shape shown represents the shape of plate 512 when a bias voltage above the second collapse voltage of CMUT 510 is applied. Fig. 45D shows a graph of the resonant frequency of CMUT 510 relative to the bias voltage. The varying states of CMUT 510 are shown as the bias voltage increases.

[0289]

[0298] The transition between the different collapsed modes can result in a “jump” in frequency and electric field, which is caused by a sudden change in the portion of the plate 512 that is allowed to move.

[0290]

[0299] By “discretizing” the collapse operation, CMUT 510 of Fig. 45C can achieve higher operating frequencies and electric fields while using lower driving voltages. In some embodiments, system 10 can be configured to allow variation of optimal frequency ranges used during operation (e.g. a bias voltage varied to vary the optimal frequency based on the application of use).

[0291]

[0300] System 10 can be configured to switch between the conventional, collapsed, and deep collapsed states described hereinabove (e.g. to allow a wide range of frequencies of operation in a single device). In some embodiments, CMUT 510 comprises a thick insulator layer (e.g. dielectric layer 514 not shown but as described herein), such as to accommodate the high voltages applied in the deep collapsed state.

[0292]

[0301] Referring now to Figs. 46A-46N, various examples of the geometry of a component before and after an oxidation process to be used in the fabrication of CMUTs are illustrated, consistent with the present inventive concepts. The illustrated examples are based on local oxidation of silicon, in which a thick oxide layer is used as a passivation layer to control the oxidation of the silicon. The transition length and the curvature of the oxidized silicon can be controlled by changing the thickness of the oxide layer. In some embodiments, combining these methods with a nitride barrier layer and / or a multiple profile step silicon substrate, 3D silicon structures comprising various geometry (e.g. various height) multiple profile steps, sloping rates, and / or curvature can be fabricated. The illustrated fabrication methods provide extremely precise control of the 3D dimensions and the profile of the silicon structures (e.g. micro-structures and / or nano-structures), and unprecedented uniformity across the whole wafer and among wafers, which guarantee the fabrication of the large-scale CMUT arrays that exhibit improved performance (e.g. an increase of at least 2%, 5%, 10%, 25%, and / or 50% in one or more performance parameters).

[0293]

[0302] The oxidation of silicon can be nonlinear, such that thinner oxide layers (e.g. masking and / or passivation layers) consume more silicon than thicker layers during the oxidation process. As such, silicon structures comprising multiple profile steps and / or curved profiles can be fabricated using a multiple profile step oxide layer comprising varying thicknesses. During the oxidation process, a transition region is formed between the portions of the oxide layer with varying thickness.

[0294]

[0303] Fig. 46A shows a silicon substrate with a 2pm oxide mask pre-oxidation, and the resultant structure after an oxidation process, where the silicon substrate comprises a stepped profile including a transition region between the profile steps, as shown.

[0295]

[0304] Fig. 46B shows a silicon substrate with a patterned oxide mask pre-oxidation, and the resultant structure after an oxidation process, wherein the silicon substrate comprises a multiple profile step profile including transition regions between the profile steps, as shown.

[0296]

[0305] Fig. 46C shows a silicon substrate with a patterned oxide mask pre-oxidation, and the resultant structure after an oxidation process, wherein the silicon substrate comprises a multiple profile step profile including transition regions between the profile steps, as shown. The profile steps shown in Fig. 46C are shorter (e.g. closer together) than the profile steps shown in Fig. 46B, resulting in a more “sloping profile” (also referred to as “sloped profile”).

[0297]

[0306] Fig. 46D shows a silicon substrate with a patterned oxide mask pre-oxidation, and the resultant structure after an oxidation process. The oxide mask comprises discrete sections, that result in “island” style multiple profile step silicon structures, as shown.

[0298]

[0307] In some embodiments, a nitride layer is used to mask a region of the silicon substrate from unwanted oxidation during the oxidation process. A thick oxide layer can be used to control the transition region of the oxidation, in which the transition length is related to the thickness of the oxide layer. During the manufacturing process, the thickness of the oxide layer can be selected to control the curvature of silicon structures to be fabricated using the techniques described herein. For example, Figs. 46E-46G show examples of transition differences achievable by varying the oxide layer from 1pm to 3 pm.

[0299]

[0308] Fig. 46E shows a silicon substrate with a 1pm oxide layer and a nitride layer masking the oxide layer pre-oxidation, and the resultant structure after an oxidation process.

[0300]

[0309] Fig. 46F shows a similar structure pre-oxidation and post-oxidation, with a 2pm oxide layer.

[0301]

[0310] Fig. 46G also shows a similar structure pre-oxidation and post-oxidation, with a 3 pm oxide layer.

[0302]

[0311] As shown in Figs. 46E-46G, a thicker oxide layer results in a shorter transition in the silicon substrate in the post-oxidation structure.

[0303]

[0312] In some embodiments, multiple oxidation steps can be performed to fabricate a multiple profile step silicon substrate, as shown in Fig. 46H.

[0304]

[0313] Fig. 46H shows a silicon substrate and an oxide layer partially masked by a nitride layer. After a first oxidation, a first profile step has been formed in the silicon substrate. An additional nitride mask is applied to the oxide layer prior to a second oxidation. After the second oxidation, the silicon substrate has formed a second profile step, as shown. In some embodiments, the design of the post-oxidation silicon structure can comprise a curved structure (e.g. comprising a smooth profile) by limiting the overlap of the nitride mask in the pre-oxidation steps, preventing flat regions from being created in the profiled area of the silicon substrate during oxidation.

[0305]

[0314] In some embodiments, a nitride layer can be used in conjunction with a thick, multiple profile step oxide layer to form a curved and / or quasi-sloping structure. A nitride layer and thick oxide layer can be selected to determine the transition length. The thickness of the oxide layer can be limited, for example by cost, such as to 3 pm or less. The use of a nitride layer in the manufacturing process can extend the transition length within the postoxidation silicon, for example as shown in Figs. 46I-46L.

[0306]

[0315] Fig. 461 shows a silicon substrate with a 2pm oxide layer partially masked with a nitride layer pre-oxidation, and the resultant structure after an oxidation process, wherein the silicon has a two-step profile with a sloping transition, as shown.

[0307]

[0316] Fig. 46J shows a silicon substrate with a 2pm oxide layer that has been partially etched and partially masked with a nitride layer pre-oxidation, and the resultant structure after an oxidation process, wherein the silicon has a two-step profile with a sloping transition, as shown. The various etching of the oxide layer pre-oxidation can affect the sloping rate of the silicon structure.

[0308]

[0317] Fig. 46K shows a silicon substrate with a multiple profile step oxide layer partially masked by a nitride layer pre-oxidation, and the resultant structure after an oxidation process, where the silicon comprises a multiple profile step structure with sloping transitions between the profile steps.

[0309]

[0318] Fig. 46L shows a silicon substrate with a multiple profile step oxide layer partially masked by a nitride layer pre-oxidation, and the resultant structure after an oxidation process, where the silicon comprises a sloping transition from a first thickness to a second thickness. The characteristics of the sloping transition are defined by the characteristics of the oxide and nitride layers pre-oxidation, as described herein.

[0310]

[0319] In some embodiments, combining patterned nitride layers and multiple profile step oxide layers on a multiple profile step silicon substrate can enable the manufacture of curved and / or sloping silicon structures (e.g. nano-structures and / or micro-structures) with varying properties. The shape of the nitride and / or oxide layers can be adjusted to control the curvature and / or slope of the resultant silicon structures, for example as shown in Figs. 46M- 46N.

[0311]

[0320] Fig. 46M shows a multiple profile step silicon substrate with patterned oxide and nitride layers pre-oxidation, and the resultant structure after an oxidation process, wherein the silicon substrate comprises a sloped profile.

[0312]

[0321] Fig. 46N shows a multiple profile step silicon substrate with patterned oxide and nitride layers pre-oxidation, and the resultant structure after an oxidation process, wherein the silicon substrate comprises a varied profile (e.g. a wavy profile).

[0313]

[0322] Referring now to Figs. 47A-B, top and side views, respectively, of a CMUT plate including a solid piston are illustrated, respectively, consistent with the present inventive concepts. Additionally, Figs. 48A-B, top and side views, respectively, of a CMUT plate including a non-solid piston are illustrated, respectively, consistent with the present inventive concepts. As described here, a piston-based CMUT can include a plate 512 with a mass, piston 518 positioned thereon. In some embodiments, piston 518 comprises a relatively solid structure, for example as shown in Figs. 47A and 47B. Alternatively piston 518 can comprise a lattice structure, including one or more hollow portions, for example, reliefs 5181 shown in Figs. 48A and 48B. Piston 518 can comprise one or more reliefs 5181 that extend vertically through the height of plate 512 (as shown in Fig. 48 A), that extend laterally through the thickness of piston 518 (as shown in Fig. 48B), or in both directions. Reliefs 5181 can extend laterally in the x-direction, the y-direction, or both, creating a grid pattern of reliefs 5181 internal to piston 518. A piston 518 comprising both vertical and lateral reliefs can comprise a three-dimensional lattice pattern. Piston 518 comprising reliefs 5181 can provide increased stiffness to plate 518, with less mass than an equivalently sized, solid piston 518.

[0314]

[0323] Referring now to Fig. 49, a series of steps of a method of manufacturing a CMUT with a shaped profile is illustrated, consistent with the present inventive concepts. Silicon can be shaped using a thermal oxidation process, for example as described herein. The speed of oxidation of silicon can be increased using a doping process, for example an ion implantation process, a diffusion doping process, or both. Various doping processes can be performed quickly and are well controlled. Additionally, a soft mask, such as a photoresist, can be used as a doping mask. A diffusion process can be used to redistribute dopants in the silicon, which can cause the doping profile to smooth sharp edges or corners.

[0315]

[0324] The process shown involves multiple ion implantation steps. At each step, various doses and ion beam energy can be used to acquire a desired dopant profile in the silicon substrate. As shown in Step A, a mask is applied to the silicon substrate, such as bottom electrode 511 of CMUT 510 described herein. The mask can include a photoresist mask or other mask that does not damage the top surface of the silicon substrate. In some embodiments, a hard mask, such as LPCVD oxide can be used. In Step B, an ion implantation process is performed on the silicon substrate, creating a doped area beneath the open portions of the mask. In Step C, the mask is removed, and a second mask is applied, revealing a different portion of the silicon substrate. An additional ion implantation process is performed, such that additional portions of the silicon substrate become doped. In Step D, a thermal diffusion process is performed, smoothing the gradient of the doping profile. In Step E, thermal oxidation is performed. The highly doped areas of the silicon substrate oxidize faster than the undoped areas, such that the oxidation process creates a shaped profile in the silicon substrate following the doped profile. In Step F, the oxide is removed, and in Step G, an insulation layer can be applied to the silicon substrate, as shown.

[0325] Referring additionally now to Fig. 50, another series of steps of a method of manufacturing a CMUT with a shaped profile is illustrated, consistent with the present inventive concepts. The process shown involves a single ion implantation step. By modulating the opening area of a doping mask, the volume and concentration of the dopant can be adjusted. Thermal diffusion can be used to convert a discrete doping pattern into a continuous doping profile. In Step A, a doping mask is applied to the silicon substrate. In Step B, the mask is patterned, with the density of the open areas varying across the surface of the substrate as shown. In Step C, an ion implantation process is performed on the silicon substrate, creating discrete doped portions of the substrate. In Step D, a thermal diffusion process is performed, smoothing the discrete doped portions into a continuous doping profile. In Step E, thermal oxidation is performed. The highly doped areas of the silicon substrate oxidize faster than the undoped areas, such that the oxidation process creates a shaped profile in the silicon substrate following the doped profile. In Step F, the oxide is removed, and in Step G, an insulation layer can be applied to the silicon substrate, as shown.

[0316]

[0326] In reference to components (e.g. parts or assemblies) of the present inventive concepts, when describing a performance or other metric of the component that is enabled by a particular feature of the component and that is expressed in terms of percentage increase and / or decrease, it should be understood that the associated increase and / or decrease relates to a comparison of the component including that feature to a component that does not include that feature but is otherwise similar (e.g. similar in size, materials of construction, and the like). For example, in describing a CMUT comprising a contoured plate that achieves at least a 10% increase in output pressure, this minimum increase describes a comparison to a similar CMUT (e.g. similar in size, material, geometry, etc.) without a similarly contoured plate.

[0317]

[0327] Referring now to Figs. 51A and 51B, a set of steps of a method of fabricating a CMUT with a shaped dielectric is illustrated, consistent with the present inventive concepts. The steps shown in Figs. 51A,B illustrate a method of fabricating a CMUT, such as CMUT 510 described herein. The described method can be used to fabricate a CMUT comprising a shaped dielectric layer (e.g. shaped dielectric layer 514s described herein). In some embodiments, for example as shown in Figs. 51 A and 5 IB, the described method can produce CMUT 510 and can further produce a shaped bottom electrode (e.g. shaped electrode 511s described herein). Alternatively, CMUT 510 can comprise a non-contoured (e.g. flat) bottom electrode (e.g. electrode 511 also described herein). The cross-sectional images shown in Figs. 51A-B are sections through the center of a circular CMUT (e.g. a CMUT comprising a circular cavity, cavity 513 described herein), such that profiles shown represent circular “rings” about the center axis of the CMUT. In other embodiments, the CMUT cell can comprise a non-circular geometry, such as hexagon, square, or other non-circular geometry. In some embodiments, such as to enhance the transmit and receive sensitivity performance, the contours formed by the steps of the shaped dielectric cavity, as described herein, can be formed to approximate (e.g. match) the equal -displacement contours of the deflected plate (e.g. plate 512 described herein). For example, for a circular cell, this approximation can be accomplished with circular contours. For other cell geometries it is more complex. For example, for square cells, the contours should transition from squares (e.g. squares with rounded corners) near the edge of the plate to circles near the center. In some embodiments, contours that are not optimized can still produce a significant beneficial effect, for example square contours with a square CMUT cell. One advantage of circular cells compared to other geometries is the simplicity of matching the contours of the shaped dielectric steps to the equal-displacement contours of the deflected plate.

[0318]

[0328] The process shown in Figs. 51A-B relies on thermal oxidation of silicon. During a thermal oxidation process, oxidation occurs on the surface of the silicon (e.g. on the surface of the silicon wafer, described herebelow). Initially, the rate of oxidation is limited by the rate of the chemical reaction at the silicon surface, and the oxide layer thickness increases linearly with time. However, as the oxide layer grows, it acts as a barrier that the oxidizing agent must diffuse through. The thicker the oxide layer becomes (e.g. the longer the oxide process continues), the slower oxidation becomes. In this regime, the oxide thickness increases with the square root of time. If a thermal oxidation is performed on a wafer that has patterned oxide on it (e.g. oxide that has been created in a previous oxidation process), areas without oxide will gain oxide thickness more quickly than areas with existing oxide.

[0319]

[0329] During an oxidation process, silicon is consumed to form the oxide. The new oxide layer is thicker (about 2.2 times thicker) than the silicon it consumes. A first portion of the oxide layer occupies the volume previously occupied by the consumed silicon, while a second portion extends above the surface of the consumed silicon.

[0320]

[0330] In some embodiments, the oxidation times and temperatures required to produce desired step heights of a shaped component can be determined using the Deal-Grove model of oxidation, and / or other models of thermal oxidation, such as the Massoud model. The full 2D and / or 3D structure of the CMUT to be produced in the processes described herein can be predicted using finite element analysis.

[0321]

[0331] In Step A, a first silicon wafer is shown, having undergone a thermal oxidation to form an oxide layer, which has subsequently been masked with a first masking layer comprising a photoresist (e.g. a photoresist applied with a lithography process). The oxide mask was then etched, using a timed etching process, forming the shaped oxide layer comprising a single step profile, as shown (e.g. a first “ring” of oxide raised relative to the central portion of the oxide layer). Timed oxide etching requires precise uniformity and etch rate control since there is not an “etch stop layer”, or a layer above which all existing oxide is to be etched (e.g. a layer of silicon which would not be etched, once the oxide was fully removed). In some embodiments, this timed oxide etching is performed in two steps, where the oxide is first partially etched, for example to approximately 70% of the target etching depth. The depth of the etch can then be measured, and the actual etching rate can be calculated. The calculated rate can be used to determine the time required to etch the remaining oxide to the desired target depth. The etch depth can be measured optically, such as via a spectroscopic reflectometer (e.g. when the timed etching is performed in a closed loop manner). In some embodiments, one or more “test structures” can be etched simultaneously for the CMUT being fabricated, and the test structures can be actively measured to monitor the progress of a timed etching process.

[0322]

[0332] Applicant fabricated an array of CMUTs, array 5010F, as an example manufacturing method of an array 5010. For this fabricated array 5010F, the oxide layer of Step A was 266nm thick, and the etch removed 85nm of oxide, leaving 181nm of oxide in the center portion of the CMUT. Array 5010F comprised multiple CMUTs each comprising a square cell, as described herein.

[0323]

[0333] In Step B, a second masking layer has been applied (e.g. a photoresist layer applied with a lithography process), and a second timed oxide etch has been performed, forming the two-step profile in the oxide layer, as shown.

[0324]

[0334] For the fabricated array 5010F, the etch in Step B removed 70nm of oxide, leaving 11 Inm of oxide in the center portion of the CMUT.

[0325]

[0335] In Step C, a third masking layer has been applied, and a third oxide etch has been performed, forming the three-step profile in the oxide layer, as shown. In some embodiments, the third oxide etch removes all unmasked oxide (e.g. in the center of the silicon wafer), as shown, and as such does not require a timed oxide etch, since the first silicon wafer acts as an etch stop layer.

[0326]

[0336] For fabricated array 5010F, the etch in Step C removed the remaining 11 Inm of oxide in the center of the CMUT.

[0327]

[0337] In Step D, the masking layer applied in Step C has been removed, and a thermal oxidation process has been performed, increasing the thickness of the oxide layer across the silicon wafer, while maintaining the multi-step profile shown. In some embodiments, the thermal oxidation process performed in Step D comprises a dry thermal oxidation process.

[0328]

[0338] For fabricated array 5010F, the thermal oxidation process of Step D increased the thickness of the oxide layer to 214nm in the center of the CMUT, and the outer portion of the oxide layer increased to 353nm.

[0329]

[0339] As shown in Figs. 51 A and 5 IB, dielectric layer 514s comprises levels, formed in the processes described in Steps A-D, as shown and described. More or less layers can be fabricated using similar processes by adding and / or removing masking and etching steps.

[0330]

[0340] In Step E, a fourth masking layer has been applied, the fourth masking layer comprising photoresist patterned with open rings on the various levels of the oxide layer. For example, each ring of photoresist covers a portion of a respective step of the oxide, without masking the transition between the steps, as shown. A fourth oxide etch has been performed (a “ring etch”, refining the transitions between the steps in the oxide layer). During the various oxidation processes described herein, the convex corners of the steps can form an upward “oxide bulge”. This bulge can be caused by an increased rate of oxidation due to shorter diffusion distance for the oxidate agents through the adjacent thinner oxide. In some embodiments, the ring etch can remove the oxide bulge, which can reduce the likelihood of high electric fields caused by the bulging oxide. Additionally or alternatively, this ring etch can remove oxide bulge which can occur along the edges of the cavity of the CMUT (e.g. along the comers of support 515), which can negatively impact the wafer bonding process described herebelow in reference to Step F by making the bonding surface non-flat. In some embodiments, Step E is performed before Step D, such that the ring etch is performed before the final thermal oxidation. Swapping of Steps D and E can decrease the risk of contamination of the oxide and the interior of the CMUT cells, by performing Step F immediately following the final oxidation of Step D. Additionally, this order of operation avoids creating a region of thinner oxide around the outer edge of the central oxide step. This thin region may be more susceptible to dielectric breakdown because the insulator oxide layer is thinner than the remainder of the CMUT cell.

[0331]

[0341] In some embodiments, the shaped dielectric steps may additionally function as mechanical “stops” to prevent the center of the plate (e.g. plate 512, describe herein) from contacting the bottom of the CMUT cell. This can reduce the risk of stiction by decreasing the contact area between the plate and the insulator oxide if the plate collapses. Additionally or alternatively, this can reduce the risk of dielectric breakdown of the insulator layer since it prevents the plate from making contact with the thinnest portion of the oxide, in the center of the CMUT. The ring etch of the dielectric steps, described hereabove, is helpful in realizing this since it creates corners with a well-defined height and distance from the center of the cell.

[0332]

[0342] For fabricated array 5010F, after Step E, the outer ring of the 4thmasking layer was 3 pm wide, and the inner two rings were 2pm wide. The etch depth was approximately 25nm.

[0333]

[0343] In Step F, a second silicon wafer has been bonded to the device formed in Steps A-E, as shown. In some embodiments, the second silicon wafer comprises a handle layer and a “buried oxide” (“BOX”) layer that are present during the bonding process, and that has been removed in Step F after the bonding process. In some embodiments, an insulative layer (not shown) can be added to the second silicon wafer, prior to the bonding process. Second silicon wafer can be positioned relative to the device of Steps A-E such that the insulator is facing toward the interior of the CMUT cell formed in Step F. In some embodiments, this insulating layer can comprise a thermal oxide layer of at least lOnm and / or no more than lOOnm, such as between lOnm and lOOnm.

[0334]

[0344] Steps A-F show an array 5010 comprising a single CMUT cell, although multiple cells can be formed simultaneously across the silicon waver, for example in a grid or other pattern, using these example manufacturing methods. In some embodiments, the multiple cells are formed in a pattern which forms an array of CMUT cells. Alternatively or additionally, a set of cells formed simultaneously across as a single silicon wafer may be separated into groups of one or more individual CMUTs. Steps G-K show a single CMUT cell, and the edge of an adjacent CMUT cell of an array of formed CMUT cells (the “array” herein), as well as the space between the two. In Step G, a fifth masking layer has been applied, the fifth masking layer comprising photoresist applied to the second silicon wafer across the array, for example the applied photoresist covers each CMUT cell formed in Steps A-F, leaving the ground contacting portions unmasked. An etching process has been performed, etching the second silicon wafer, the oxide layer, and into the first silicon wafer, as shown. This etching process creates openings to the first silicon wafer, for example such that ground pads can be applied.

[0335]

[0345] In Step H, the photoresist has been removed, and a layer of metal (e.g. aluminum) has been deposited across the array, covering each CMUT and the exposed portion of the first silicon wafer positioned between each CMUT. In some embodiments, the metal layer comprises multiple layers of different types of metal. For example, a layer of titanium can be included between the silicon wafer and the aluminum, such as to minimize “spiking”. Spiking is a phenomenon where silicon diffuses into an adjacent aluminum layer, creating voids. Aluminum fills the voids, creating “spikes” of aluminum extending into the silicon layer. In some embodiments, the metal layer comprising aluminum contains up to 2% silicon to minimize spiking, and / or up to 2% copper to minimize electromigration.

[0336]

[0346] For the fabricated array 5010F, the metal layer comprised a 15nm layer of titanium positioned on the silicon wafer, and 400nm of aluminum comprising 2% silicon.

[0337]

[0347] In Step I, a sixth masking layer has been applied, the sixth masking layer comprising photoresist applied across the metal layer, leaving exposed portions, which have been etched (e.g. via aluminum etching), as shown. This etching defines the top plate of the CMUT, bonding pads for the CMUT, and the electrical connections between the CMUT elements and the bonding pads. Steps G-I are agnostic to the interior structure of the CMUT cell, and in various embodiments may be performed in a variety of different ways and / or in a modified order. For example, in some embodiments, Steps G-I may be changed to first mask and etch the 2nd silicon wafer; then to mask and etch the opening to the 1st silicon wafer; and lastly to deposit, mask and etch the metal layer.

[0338]

[0348] In Step J, the photoresist has been removed, and a passivation layer has been applied. In some embodiments, the passivation layer is deposited using a process such as plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other deposition method. This passivation layer protects the CMUT devices and prevents surface conduction. The passivation layer can include a material selected from the group consisting of silicon oxide; silicon nitride; silicon oxynitride; aluminum oxide; and combinations of these.

[0339]

[0349] For the fabricated array 5010F, the passivation layers comprised lOOnm of silicon oxide deposited using PECVD.

[0350] In Step K, a seventh masking layer has been applied, the seventh masking layer comprising photoresist applied across the passivation layer, leaving exposed portions, which have been etched (e.g. via a passivation layer etch), as shown. Removing these portions of the passivation layer exposes bonding pads which can provide electrical attachment to the CMUT.

[0340]

[0351] Referring now to Fig. 52, a set of steps of a method of fabricating a CMUT with a shaped bottom electrode is illustrated, consistent with the present inventive concepts. Steps A-F of Fig. 52 are an alternate embodiment to Steps A-F of Fig. 51 A. In Step A, a first silicon wafer is shown, having undergone a thermal oxidation to form an oxide layer, which has subsequently been masked with a photoresist (e.g. photoresist patterned with a lithography process), and an oxide etch, forming the stepped layer of oxide, as shown.

[0341]

[0352] In Step B, a second thermal oxidation has been performed, creating the stepped profile of oxide on the first silicon wafer, as shown.

[0342]

[0353] In Step C, a second masked etching process has been performed, as described herein, forming the two-step profile of oxide, as shown.

[0343]

[0354] In Step D, a third thermal oxidation has been performed, creating the profile of oxide on the first silicon wafer, as shown.

[0344]

[0355] In Step E, a third masked etching process has been performed, as described herein, forming the three-step profile of oxide, as shown.

[0345]

[0356] In Step F, a fourth masked etching process has been performed, wherein the mask and etching process comprise a ring etch, such as described in reference to Step E of Fig. 51A.

[0346]

[0357] In Step G, a fourth thermal oxidation has been performed, as described herein, forming the three-step profile including a ring etch, as shown.

[0347]

[0358] In Step H, a second silicon wafer is bonded to the shaped oxide layer formed in Steps A-G, as shown. In some embodiments, the second silicon wafer comprises an oxide layer during the bonding process (e.g. a “bottom oxide” layer, or “BOX” layer) that has been removed in Step H after the bonding process. Following Step H, Steps G-K of Fig. 5 IB can be performed, as described herein. Fig. 52 illustrates the fabrication of a CMUT comprising a three-step shaped dielectric 514. As described herein, in some embodiments, fewer and / or greater numbers of steps may be fabricated by removing and / or adding one or more oxidation and / or etching steps.

[0359] The above-described methods of fabrication should be understood to be performed in numerous temporal orders of the steps that are described. For example, etching and oxidation steps can be performed in any order. In some embodiments, the bottom of plate 512 can include an oxide layer.

[0348]

[0360] Referring now to Figs. 53A-54B, various top and side views of CMUT arrays are illustrated, consistent with the present inventive concepts. Figs. 53 A and 54A show a CMUT array 5010 comprising rows of four CMUT cells 510 each. Figs. 53B and 54B show a CMUT array 5010 comprising rows of three CMUT cells 510 each. Arrays 5010 and components thereof can be of similar construction and arrangement to array 5010 described in reference to Fig. 1 and otherwise herein. Each array 5010 can comprise multiple CMUTs 510a and / or 510b, where CMUTs 510a and 510b comprise varying characteristics, as described herebelow.

[0349]

[0361] CMUT arrays (e.g. one or more arrays 5010) can exhibit acoustic coupling between cells (e.g. CMUT cells 510), such as through guided dispersive modes in the medium at the surface of the CMUT array. This coupling can create an acoustic mutual impedance between the cells, which can cause the cells to behave much differently than a single-cell model might predict (e.g. different than a prediction from a computer model used to design and / or test a CMUT array). The mutual acoustic impedance between cells can make the cells of an array have significantly different displacements, even when the cells are driven with the same voltage, for example as shown in Figs. 53 A and 53B. Typically the plate (e.g. plate 512 described herein) is constructed and arrange to prevent striking (e.g. significantly contacting) the bottom of the cell during operation, and the output pressure is determined by the average displacement of the cells. As such, uneven displacement between cells (e.g. CMUTs 510) limits the maximum output pressure of the array. In applications in which high output pressure is required or at least desired, uneven displacement is avoided.

[0350]

[0362] The nature of the acoustic coupling between cells depends on many variables such as the frequency of operation, the medium properties, and the inclusion of an acoustic lens and / or coating in the array. Acoustic coupling can occur between two or more arrays 5010 (e.g. when a device comprises two or more CMUT arrays 5010, each comprising one, two, or more CMUT cells). Acoustic coupling can also occur within a single CMUT array 5010, when the array comprises multiple CMUT cells 510 (e.g. where the coupling occurs between two or more of the multiple CMUT cells 510). The acoustic coupling behavior between arrays 5010 can further depend on the relative phases at which the arrays 5010 are driven. Modeling, such as finite element analysis (FEA), can be done for each proposed design of the cells 510 and / or arrays 5010 and operation parameters of the design, such as to properly understand the acoustic coupling behavior.

[0351]

[0363] In some embodiments, the non-uniform plate displacement caused by acoustic mutual impedance can be partially counteracted by using CMUT cells with different sensitivities within the same array. For example, a commonly seen displacement pattern is for the outer cells in a 3 or 4 cell wide element (e.g. CMUTs 510a shown) to have larger displacement than the inner cells (e.g. CMUTs 510b shown). In some embodiments, inner cells 510b can be made with higher sensitivity than the outer cells 510a to counteract this larger displacement of the outer cells, for example as shown in Figs. 54A and 54B. This sensitivity differentiation of the cells can result in increased maximum output pressure.

[0352]

[0364] The sensitivity of a CMUT cell can be changed by changing the gap height, changing the insulator layer thickness (e.g. the thickness of dielectric layer 514, not shown but described herein), or by changing both. However, this modification can add significant complexity to the fabrication process because the gap height and layer thicknesses are set by deposition and etching steps, which are usually performed over an entire wafer at once (e.g. for an entire array 5010 and / or for multiple arrays 5010 that are fabricated simultaneously). Using different gap heights and layer thicknesses within the same array would typically require separate lithography and etches for each variation.

[0353]

[0365] In some embodiments, the sensitivity of a single CMUT 510 can be modified by altering the profile of a shaped dielectric layer 514s, shaped bottom electrode 511s, or shaped top electrode 512s each described herein. The profile of these shaped components can be used to increase the sensitivity of a CMUT cell 510. These modified profiles can also be used to achieve non-uniform sensitivity across an element by implementing different magnitudes of the profile differences in different cells 510. This differentiation is advantageous because the sensitivity can be varied between cells (e.g. between neighboring CMUTs 510 within an array 5010) using the lithography pattern alone (e.g. avoiding added complexity in fabrication).

[0354]

[0366] In selecting the sensitivity profile of a CMUT 510, modeling (e.g. FEA modeling) can be done over the range of operating conditions to determine a cell sensitivity pattern that will give an overall beneficial effect. For example, modeling can be done with different driving signal phases between neighboring CMUTs 510 (e.g. CMUTs 510a and 510b shown) to find the displacement pattern of the cells under different focusing conditions.

[0367] In some embodiments, similar principles of element sensitivity profiling can also be applied for other purposes, such as apodization of an array 5010 in the elevation dimension, such as to reduce sidelobes.

[0355]

[0368] Another arrangement for counteracting non-uniformity due to acoustic mutual impedance between CMUT cells 510 is to divide the array elements into individually addressed sub-elements that are only one or two cells wide. In some embodiments, sub elements can be driven with different voltage amplitudes to counteract displacement nonuniformity.

[0356]

[0369] Referring now to Figs. 55A and 55B, sectional views of embodiments of CMUTs including micropillars are illustrated, consistent with the present inventive concepts. Figs. 55A and 55B each show a CMUT 510 with shaped plate 512s, configured to operate in a conventional mode and collapsed mode, respectively, as described herein. CMUT 510 and components thereof can be of similar construction and arrangement to CMUT 510 described in reference to Fig. 1 and otherwise herein. CMUT 510 of Figs. 55A and 55B can include shaped plate 512s including curved portion 5125, support 515, bottom electrode 511, and cavity 513, each as described herein. Dielectric layer 514 can be located on the top surface of bottom electrode 511, electrically isolating shaped plate 512s from bottom electrode 511. In some embodiments, plate 512 can comprise a flat plate, or bottom electrode 511 can comprise a shaped bottom electrode, and combinations of these, as described herein. In some embodiments, as shown, the edges of shaped plate 512s can contact dielectric layer 514 at contacting area 5126, as shown.

[0357]

[0370] In some embodiments, one or more surfaces of CMUT 510 includes a surface modification, such as one or more micropillars, for example micropillars 5171 shown. Dielectric layer 514 and / or shaped plate 512s can comprise an array of one or more micropillars or other surface modifications. A surface modification of dielectric layer 514 and / or shaped plate 512s (as shown) can reduce stiction between the two surfaces.

[0358]

[0371] Referring now to Fig. 56, a top view of a CMUT array is illustrated, consistent with the present inventive concepts. Array 5010 and components thereof can be of similar construction and arrangement to array 5010 described in reference to Fig. 1 and otherwise herein. Array 5010 can comprise one or more CMUTs 510, as described herein, such as CMUTs 510 shown. Array 5010 can comprise a silicon top layer which comprises plate 512 of each CMUT 510. The silicon top layer can extend from array 5010, as shown, forming a bonding pad for connecting a wire or other electrical conduit to array 5010. In some embodiments, the silicon top layer does not include any sharp corners, for example when the silicon top plate comprises rounded and / or otherwise non-sharp comers, as shown. Rounded comers can be configured to reduce electrical fields present at the comers of the silicon top plate and / or can prevent or reduce the likelihood of the formation of cracks in the silicon top plate.

[0359]

[0372] The above-described embodiments should be understood to serve only as illustrative examples; further embodiments are envisaged. Any feature described herein in relation to any one embodiment may be used alone, or in combination with other features described, and may also be used in combination with one or more features of any other of the embodiments, or any combination of any other of the embodiments. Furthermore, equivalents and modifications not described above may also be employed without departing from the scope of the inventive concepts, which is defined in the accompanying claims.

Claims

WHAT IS CLAIMED IS:

1. A process of fabricating a CMUT, comprising:(a) applying a thermal silicon oxide layer to a first silicon wafer;(b) performing a patterned etch of the silicon oxide layer; and(c) repeating step (b) one or more times to create a silicon oxide structure on the first silicon wafer, wherein the silicon oxide structure includes one or more steps.

2. The process according to one or more claims herein, further comprising:(d) performing a thermal oxide application after the steps are formed.

3. A process of fabricating a CMUT, comprising:(a) applying a thermal silicon oxide layer to a first silicon wafer;(b) performing a patterned etch of the oxide layer;(c) repeating steps (a) and (b) to form a silicon oxide structure on the first silicon wafer, wherein the silicon oxide structure includes one or more steps; and(d) performing a thermal oxide application after the steps are formed, wherein the etchings of the repeated steps (b) results in an exposed portion of the first silicon wafer.

4. The process according to one or more claims herein, wherein the silicon oxide structure that includes steps comprises a dielectric layer of the CMUT.

5. The process according to one or more claims herein, wherein the one or more steps comprise one or more comers, and wherein the process further comprises:(e) removing oxide bulge formed during step (a) from one or more of the one or more comers.

6. The process according to claim 5, wherein step (e) is performed with a patterned etch.

7. The process according to claim 5, wherein step (e) is performed prior to step (d).

8. The process according to claim 5, wherein step (e) is performed after step (d).

9. The process according to claim 5, wherein the silicon oxide structure further comprises one or more supports each comprising one or more comers.

10. The process according to claim 9, wherein step (e) includes removing oxide bulge formed during step (a) from one or more of the corners of the one or more supports.

11. The process according to one or more claims herein, further comprising:(f) attaching a second silicon wafer to the silicon oxide structure to form a CMUT cell with an interior cavity.

12. The process according to claim 11, further comprising applying an oxide layer to the second silicon wafer prior to step (f).

13. The process according to claim 12, wherein the oxide layer on the second silicon wafer comprises a thickness of at least lOnm and / or no more than lOOnm.

14. The process according to claim 12, wherein the oxide layer is positioned on the second silicon wafer toward the interior of the cavity of the CMUT.

15. The process according to claim 11, wherein the shape of the silicon oxide structure approximates the shape of the second silicon wafer when deflected in use.

16. The process according to one or more claims herein, wherein the first silicon wafer comprises one or more corners, wherein at least one corner comprises a non-sharp geometry.

17. A device comprising a sensor that includes one or more CMUTs of any one or more of claims 1 through 16.

18. The device according to claim 17, wherein the device comprises a medical device.

19. The device according to claim 17, wherein the sensor comprises two or more sensors in a redundant arrangement.

20. The device according to claim 17, wherein the sensor comprises a first set of the one or more CMUTs and a second set of the one or more CMUTs, and wherein the first set and the second set are configured in a redundant arrangement.

21. The device according to claim 17, wherein the sensor comprises two or more CMUT arrays, wherein each CMUT array comprises at least one of the one or more CMUTs.

22. The device according to claim 21, wherein the two or more CMUT arrays comprises a first CMUT array in a first configuration and a second CMUT array in a second configuration different than the first configuration.

23. The device according to claim 22, wherein the first array includes a first CMUT with a first configuration, and the second array includes a second CMUT with a second configuration different than the first configuration.

24. The device according to claim 23, wherein the first CMUT comprises a first bottom electrode configuration and a first plate configuration, wherein the second CMUT comprise a second bottom electrode configuration and a second plate configuration, and wherein the first plate configuration is different than the second plate configuration and / or the first bottom electrode configuration is different than the second bottom electrode configuration.

25. The device according to claim 23, wherein the first array and the second array comprise different geometric arrangement of CMUTs, different types of CMUTs, and / or different quantity of CMUTs.

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