Control of a multi-stage ADC

Abstract

Control circuitry for an analog-to-digital converter (ADC) is disclosed, wherein the ADC is configured to output a digital representation of an ADC input. The ADC comprises a first stage for providing a first digital output based on a first stage input signal and a second stage for providing a second digital output based on a second stage input signal, wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation. The first stage is a successive approximation register (SAR) ADC stage, which comprises a feedback digital-to-analog converter (DAC) configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal. The control circuitry is configured to determine a gain mismatch between first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal. The control circuitry is also configured to control the first stage processing to counteract the determined gain mismatch. A corresponding ADC is also disclosed, as well as an integrated circuit, an electronic apparatus, and a control method.

Description

[0001] CONTROL OF A MULTI-STAGE ADC

[0002] TECHNICAL FIELD

[0003] The present disclosure relates generally to the field of analog-to-digital conversion. More particularly, it relates to control of a multi-stage analog-to-digital converter (ADC).

[0004] BACKGROUND

[0005] Multi-stage ADCs are well known and typically demonstrate benefits related to power efficiency and conversion rate. For example, a two-stage ADC architecture is described in Tripathi and Murmann, "A 160 MS / s, 11.1 mW, Single-Channel Pipelined SAR ADC with 68.3 dB SNDR," Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, pp. 1-4.

[0006] The first stage of that two-stage ADC architecture employs a fast asynchronous SAR loop around a first digital-to-analog converter (DAC1). The first stage also employs a second digital-to-analog converter (DAC2), the low-noise residue of which is passed to the second stage via a residue amplifier. Thereby, the noise-limited path of the two-stage ADC is separated from the highspeed path.

[0007] A problem with ADC path separation (e.g., by use of first and second DACs) is that any processing mismatch between the separated paths typically propagates through the subsequent stage(s), and may lead to reduced accuracy and / or erroneous results (e.g., saturation in subsequent stage(s)).

[0008] Therefore, there is a need for approaches to handle (e.g., avoid or mitigate) impairments due to processing mismatch between separated paths in a multi-stage ADC.

[0009] SUMMARY

[0010] It should be emphasized that the term "comprises / comprising" (replaceable by "includes / including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0011] Generally, when an arrangement is referred to herein, it is to be understood as a physical product; e.g., an apparatus. The physical product may comprise one or more parts, such as controlling circuitry in the form of one or more controllers, one or more processors, or the like.

[0012] It is an object of some embodiments to solve or mitigate, alleviate, or eliminate at least some of the above or other disadvantages.

[0013] A first aspect is control circuitry for an analog-to-digital converter (ADC) configured to output a digital representation of an ADC input. The ADC comprises a first stage for providing a first digital output based on a first stage input signal and a second stage for providing a second digital output based on a second stage input signal, wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation. The first stage is a successive approximation register (SAR) ADC stage, which comprises a feedback digital-to-analog converter (DAC) configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal. The control circuitry is configured to determine a gain mismatch between first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal, and control the first stage processing to counteract the determined gain mismatch.

[0014] In some embodiments, the control circuitry is configured to determine the gain mismatch by determining a metric of correlation for elements of the first and second digital outputs.

[0015] In some embodiments, the metric of correlation comprises a covariance between the first digital value part and the second digital value part.

[0016] In some embodiments, the metric of correlation comprises a slope of an affine function representing a statistical count of values of the second digital value part for each of a plurality of values of the first digital value part. In some embodiments, the affine function represents the statistical count of values via least squares fitting.

[0017] In some embodiments, the plurality of values of the first digital value part comprises a first group of values of the first digital value part and a second group of values of the first digital value part, and wherein the slope of the affine function comprises a normalized difference between average value of the second digital value part for the first group of the first digital value part and average value of the second digital value part for the second group of the first digital value part.

[0018] In some embodiments, the control circuitry is configured to determine the gain mismatch by determining a metric of difference between residual signals associated with first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal.

[0019] In some embodiments, the control circuitry is configured to determine the gain mismatch by filtering the metric of difference.

[0020] In some embodiments, the control circuitry is configured to determine the gain mismatch by scaling the difference between residual signals by a most significant bit of the first digital output.

[0021] In some embodiments, the control circuitry is configured to control the first stage processing to counteract the determined gain mismatch by adjusting a gain for the first stage processing for provision of the first digital output.

[0022] In some embodiments, the control circuitry is configured to control the first stage processing to counteract the determined gain mismatch by controlling a variable gain amplifier that is configured to provide a variably amplified version of the first stage input signal to the feedback DAC.

[0023] In some embodiments, the control circuitry is configured to control the first stage processing to counteract the determined gain mismatch by controlling a variable range of the feedback DAC.

[0024] In some embodiments, the control circuitry is configured to control the first stage processing to counteract the determined gain mismatch by controlling a variable capacitance associated with an output of the feedback DAC. A second aspect is an analog-to-digital converter (ADC) configured to output a digital representation of an ADC input. The ADC comprises a first stage for providing a first digital output based on a first stage input signal and a second stage for providing a second digital output based on a second stage input signal, wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation. The first stage is a successive approximation register (SAR) ADC stage, which comprises a feedback digital-to-analog converter (DAC) configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal. The ADC also comprises the controlling circuitry of the first aspect.

[0025] In some embodiments, the feedback DAC is smaller than the feedforward DAC.

[0026] In some embodiments, the first stage further comprises a feedback DAC amplifier that is configured to provide the first stage input signal - correspondingly amplified - to the feedback DAC and / or a feedforward DAC amplifier that is configured to provide the first stage input signal - correspondingly amplified - to the feedforward DAC.

[0027] In some embodiments, the feedback DAC amplifier and / or the feedforward DAC amplifier is / are configured to amplify the first stage input signal in correspondence with a difference in range between the feedback DAC and the feedforward DAC.

[0028] A third aspect is an integrated circuit comprising the controlling circuitry of the first aspect, and / or the ADC of the second aspect.

[0029] A fourth aspect is an electronic apparatus comprising the controlling circuitry of the first aspect, and / or the ADC of the second aspect, and / or the integrated circuit of the third aspect.

[0030] In some embodiments, the electronic apparatus is a signal receiver.

[0031] In some embodiments, the electronic apparatus is a communication apparatus.

[0032] In some embodiments, the communication apparatus is a wireless communication device for a cellular communications system. In some embodiments, the communication apparatus is a base station for a cellular communications system.

[0033] A fifth aspect is a method for controlling an analog-to-digital converter (ADC) configured to output a digital representation of an ADC input. The ADC comprises a first stage for providing a first digital output based on a first stage input signal and a second stage for providing a second digital output based on a second stage input signal, wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation. The first stage is a successive approximation register (SAR) ADC stage, which comprises a feedback digital-to- analog converter (DAC) configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal. The method comprises determining a gain mismatch between first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal, and controlling the first stage processing to counteract the determined gain mismatch.

[0034] In some embodiments, any of the above aspects may additionally have features identical with or corresponding to any of the various features as explained above for any of the other aspects.

[0035] An advantage of some embodiments is that approaches are provided for handling (e.g., avoiding or mitigating) impairments due to processing mismatch between separated paths in a multistage ADC.

[0036] An advantage of some embodiments is that gain mismatch between the separated paths is reduced compared to other approaches; or is completely eliminated.

[0037] An advantage of some embodiments is that the ADC accuracy is increased compared to other approaches.

[0038] An advantage of some embodiments is that the probability of saturation is reduced compared to other approaches.

[0039] An advantage of some embodiments is that the residue amplifier and / or the subsequent (second) stage can have a smaller signal range compared to other approaches (since a smaller residue typically requires less redundancy processing). Thereby, a more power efficient ADC is enabled.

[0040] An advantage of some embodiments is that a power efficient ADC is provided.

[0041] An advantage of some embodiments is that an ADC is provided which is capable of operation at one or more of: relatively high conversion rate, relatively large bandwidth, and relatively high signal frequency.

[0042] An advantage of some embodiments is that an indicator of the gain mismatch (sign; and possibly magnitude) can be robustly determined.

[0043] An advantage of some embodiments is that gain variations (e.g., due to manufacturing imperfections, PVT (process, voltage, temperature) variations, etc.) may be effectively combatted.

[0044] An advantage of some embodiments is that the gain mismatch counteraction functions without any spectral requirements on the input signal, as long as the signal level is sufficiently high (e.g., compared to the ADC range and / or amplitude distribution).

[0045] BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Further objects, features and advantages will appear from the following detailed description of embodiments, with reference being made to the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the example embodiments.

[0047] Figure 1A is schematic drawing illustrating an example multi-stage ADC according to some embodiments;

[0048] Figure IB is a schematic drawing illustrating an example SAR ADC stage according to some embodiments;

[0049] Figure 2 is a schematic drawing illustrating an example arrangement for control of a multi-stage ADC according to some embodiments;

[0050] Figure 3 is a flowchart illustrating example method steps according to some embodiments;

[0051] Figure 4 is a plot illustrating example gain mismatch results according to some embodiments; Figure 5 is a histogram illustrating example gain mismatch results according to some embodiments;

[0052] Figure 6 is a collection of schematic drawings illustrating example gain mismatch processing according to some embodiments;

[0053] Figure 7A is a schematic drawing illustrating example gain mismatch counteraction according to some embodiments;

[0054] Figure 7B is a schematic drawing illustrating example gain mismatch counteraction according to some embodiments;

[0055] Figure 7C is a schematic drawing illustrating example gain mismatch counteraction according to some embodiments;

[0056] Figure 8 is a collection of plots illustrating example gain mismatch counteraction results according to some embodiments; and

[0057] Figure 9 is a schematic block diagram illustrating an example apparatus according to some embodiments.

[0058] DETAILED DESCRIPTION

[0059] As already mentioned above, it should be emphasized that the term "comprises / comprising" (replaceable by "includes / including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0060] Embodiments of the present disclosure will be described and exemplified more fully hereinafter with reference to the accompanying drawings. The solutions disclosed herein can, however, be realized in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0061] In the following, approaches will be described and exemplified for controlling a multi-stage ADC (a.k.a. a pipeline ADC) with path separation in at least one of the ADC stages. The multi-stage ADC control is for handling impairments due to processing mismatch between the separated paths. According to some embodiments, such impairments may be mitigated, or completely avoided.

[0062] Figure 1A schematically illustrates an example multi-stage ADC 100 according to some embodiments. The ADC 100 comprises a plurality of (two or more) ADC stages, each of which is illustrated as a successive approximation register (SAR) ADC; SARI 110, SAR2 120, SAR3 130.

[0063] The ADC 100 is configured to output a digital representation u0Ut199 of an ADC input 101. The first stage 110 provides a first digital output d±118 based on a first stage input signal vinl101, the second stage 120 provides a second digital output d2128 based on a second stage input signal vin2102, and so on. The first digital output d±118 corresponds to a first digital value part 171 for the digital representation 199, the second digital output d2128 corresponds to a second digital value part 172 for the digital representation 199, and so on. The digital representation 199 is provided by combining the digital value parts as illustrated by 190 (e.g., adding the digital value parts, as properly scaled).

[0064] As illustrated by 111, the first stage 110 determines a difference 117 between the first stage input signal vinl101 and a digital-to-analog converter (DAC) result vdl119. A comparator (CMP) 112 is used to sequentially make decisions based on the difference 117. The decisions are represented in a register (REG) 113, which is configured to provide the first digital output dr118. The output 118 of the register 113 is also used as DAC input, and the DAC result 119 is provided by application of DAC weights to the output 118 of the register 113, as illustrated by the weighting (Wl) 114.

[0065] Generally, it should be understood that using the output 118 of the register 113 as DAC input may involve some further processing (not shown); e.g., depending on the DAC implementation and / or the nature (e.g., alphabet size and / or meaning of different element values) of the elements of the digital output 118. For example, to control various switches in the DAC, the elements (e.g., bits) of the digital output 118 may need to be translated to corresponding switch control signals (compare with 718' of Figure 7C). For example, an element of the digital output 118 may be translated to switch control signals c, d, d_n. The first digital value part u±171 for the digital representation 199 is provided by application of digital weights w±to the first digital output d±118, as illustrated by the weighting (EW1) 115. The digital weights are ideally representing the DAC weights exactly (possibly with a scaling factor; More generally, the digital weights may be seen as estimates of the DAC weights wt. In practice typically differs (at least slightly) from a1w1; e.g., due to mismatches introduced in manufacturing.

[0066] The difference 117 is denoted as the residue vrlof the first stage 110, and is provided as the second stage input signal vln2102 after amplification by A in a residue amplifier 116. Generally, the terms residue and residual signal will be used interchangeably herein.

[0067] As illustrated by 121, the second stage 120 determines a difference 127 between the second stage input signal vln2102 and a digital-to-analog converter (DAC) result vd2129. A comparator (CMP) 122 is used to sequentially make decisions based on the difference 127. The decisions are represented in a register (REG) 123, which is configured to provide the second digital output d2128. The output 128 of the register 123 is also used as DAC input, and the DAC result 129 is provided by application of DAC weights w2to the output 128 of the register 123, as illustrated by the weighting (W2) 124.

[0068] The second digital value part u2172 for the digital representation 199 is provided by application of digital weights w2to the second digital output d2128, as illustrated by the weighting (EW2) 125. Thereafter, the second digital value part u2172 is scaled by an amplification inverse 1 / ^4 before combining to provide the digital representation 199, as illustrated by the scaling (SC) 125'. The digital weights w2are ideally representing the DAC weights w2exactly (possibly with a scaling factor; i.e., w2= cr2w2. More generally, the digital weights w2may be seen as estimates of the DAC weights w2. The amplification inverse 1 / ^4 is ideally represents an inverse of the amplification A exactly. More generally, the amplification inverse 1 / ^4 may be seen as the inverse of an estimate of the amplification A.

[0069] The difference 127 is denoted as the residue vr2of the second stage 120, and may be provided as a third stage input signal after amplification in a residue amplifier 126. The amplification in residue amplifier 126 may be equal to the amplification by A in the residue amplifier 116, or may differ therefrom. To exemplify further, for an input sample vinl101 the first stage (SARI) 110 sequentially takes decisions using the comparator 112, and each decision is added to the register 113, which already comprises the result of previous decisions for the input sample. The output 118 of the register 113 dr= [d1 / 0, d1#1, ... drives a DAC that generates a signal 119 that converges towards the input voltage of the sample (within a certain level of accuracy defined by the number Nblof decision cycles and the DAC weights 114 = [w1 0, w1 1(... w1 Wfei i]). The difference 117 between the input signal 101 and the DAC signal 119 is referred to as the residue vrland is fed to the comparator 112 for the subsequent decision.

[0070] The first stage 110 outputs a decision vector d1, wherein each element dl kmay be represented in any suitable way; depending on the function of the comparator 112. For example, a binary comparator 112 may detect the sign of the residue 117 and each decision element may be ternary {1,0, —1], where the values may represent positive sign, default value when no decision has been made, and negative sign, respectively. The first digital value part u±may be formed as

[0071] When the Nblcycles have been completed, the residue vrlis amplified in the residue amplifier 116 with gain A. The amplified residue 102 serves as input sample vln2to the subsequent stage (SAR2) 120, which continues the conversion by performing Nb2further decision cycles on the input sample vln2using DAC weights 124 w2= [w2 0, w2 1, ... w2jvb], and may provide the second digital value part u2. To account forthe residue amplification, u2is scaled by 1 / / 1 before being combined with ultto yield the ADC output u0Ut= u±+ u j .

[0072] Even though each stage of the multi-stage ADC 100 is a SAR ADC, it should be noted that the approaches described herein are not limited to such multi-stage ADCs. Rather, the approaches described herein are applicable for any multi-stage ADC (which has at least two ADC stages) wherein at least one ADC stage (the "first stage") with one or more subsequent ADC stage(s) is a SAR ADC. The "second stage" may, or may not, be a SAR ADC.

[0073] For simplicity, the description herein focuses on the example where the ADC stage that occurs first in the signal flow of the multi-stage ADC (e.g., the stage 110) is a SAR ADC with path separation (i.e., the example when the "first stage" is the ADC stage that occurs first in the signal flow of the multi-stage ADC). However, it should be noted that the "first stage" may be any ADC stage of a multi-stage ADC (e.g., the stage 120), except the ADC stage that occurs last in the signal flow of the multi-stage ADC. Typically, the "second stage" is the ADC stage of the multistage ADC that is directly subsequent to the "first stage".

[0074] Figure IB schematically illustrates an example successive approximation register (SAR) ADC stage according to some embodiments. The illustration refers to the first stage (SARI) 110 of Figure 1A, but is should be understood that the principles illustrated by Figure IB may be applied for any be any suitable ADC stage of a multi-stage ADC.

[0075] Similarly to what has been described in connection with Figure 1A, it is illustrated by 111 that the ADC stage 110 determines a difference 117 between the stage input signal vln101 and a digital-to-analog converter (DAC) result vSdl119. A comparator (CMP) 112 is used to sequentially make decisions based on the difference 117. The decisions are represented in a register (REG) 113, which is configured to provide a digital output d±118. The output 118 of the register 113 is also used as DAC input, and the DAC result 119 is provided by application of DAC weights wsito the output 118 of the register 113, as illustrated by the weighting (Wls) 114.

[0076] The application of digital weights to the digital output d±118 is also illustrated by the weighting (EW1) 115'.

[0077] The DAC 141 comprising the weighting (Wls) 114 may be denoted as a feedback digital-to- analog converter configured to provide a feedback analog representation (the DAC result 119) of the digital output dr118 for convergence (during SAR execution) of the digital output dr118.

[0078] The difference 117 that is provided to the comparator 112 may be denoted as a feedback DAC residue vSrl. In contrast to the illustration of Figure 1A, the feedback DAC residue vSrl117 is not provided as input signal for the subsequent stage. Instead, another DAC 142 is used for this purpose.

[0079] As illustrated by 148, the DAC 142 determines a difference 147 between the stage input signal vin101 and a DAC result vLdl149. The DAC result vLdl149 is provided by application of DAC weights wL1to the DAC input, as illustrated by the weighting (W1L) 144. The DAC input 160 corresponds to the output 118 of the register 113; possibly after processing by some suitable logic (LOG) 143. For example, the logic 143 may initially output a default state to the LDAC 142, and may later (e.g., after a predefined number of decision cycles) forward the output 118 to the LDAC 142.

[0080] Alternatively or additionally, the logic 143 may comprise a detect-and-skip (DAS) logic layer between the SDAC 141 and the LDAC 142, which is used to minimize the switching of the LDAC (e.g., by effectively implementing a ternary switching scheme to reduce the impact of most significant bit, MSB, mismatch errors when input signals are small).

[0081] Yet alternatively or additionally, the logic 143 may comprise mapping circuitry with dynamic element matching (DEM) circuitry, wherein the DEM circuitry is configured to apply time-varying element permutation on elements of the first digital output 118, or on elements of a digital representation derived from the first digital output 118 (e.g., thermometer codewords). For example, the mapping circuitry may be configured to provide the output of the DEM circuitry as the DAC input 160, either directly, or after further processing by the mapping circuitry.

[0082] The digital weights w±used in EW1 115' typically represent the weights wL1of the LDAC 142. For example, the digital weights used in EW1 115' may be the ideal - or expected - values of the weights used in WIL 144. The term "ideal values" may refer to the perspective of the elements in the digital output 118.The DAC 142 comprising the weighting (WIL) 144 may be denoted as a feedforward digital-to-analog converter configured to provide a feedforward analog representation (the DAC result vLdl149) of the digital output d±118 for generation of the input signal for a subsequent stage. To this end, the difference 147 may be denoted as a feedforward residue vLrl, and may be provided as input signal for a subsequent stage after amplification in a residue amplifier 116.

[0083] The use of two different DACs 141, 142 enables path separation, in that the determination of residue vLrl147 for propagation between stages (which is typically noise sensitive) is separated from the determination of residue vSrl117 for convergence of the digital output d±118 (which is typically time critical).

[0084] It is typically beneficial to let the feedback DAC 141 be a relatively small DAC (SDAC; e.g., to enable high-speed operation) and to let the feedforward DAC 142 be a relatively large DAC (LDAC; e.g., to enable high accuracy). For example, the feedback DAC 141 may be smaller than the feedforward DAC 142. The terms "small DAC" and "large DAC" may refer to the physical sizes of the DACs and / or to the capacitance values of the DACs. For example, if the DACs are capacitive DACs, the large DAC would typically have larger capacitors than the small DAC; which typically leads to that large DAC has a larger physical size than the small DAC.

[0085] The SDAC-LDAC technique has several potential benefits. For example, a fast, less accurate, lower power DAC (the SDAC) can be used for output decisions without adversely affecting linearity and noise of subsequent ADC stage(s). Alternatively or additionally, any errors introduced by the SDAC leads only to an increase in the residues. Yet alternatively or additionally, since there is no comparator loading the LDAC path, there is no comparator kick- back affecting the integrity of the feedforward residue. Yet alternatively or additionally, the signal levels in SDAC and the LDAC can be decoupled such that, for example, the SDAC can operate with higher signal levels than the LDAC to lower the impact from comparator offset, kickback, and noise while introducing moderate errors due to non-linear distortion (e.g., in 145). Yet alternatively or additionally, a logic layer (compare with 143 of Figure IB) may be introduced when propagating d±from the SDAC to the LDAC.

[0086] A potential benefit of the logic layer is that a function may be introduced that gates the first digital output (compare with 118 of Figure IB) to the LDAC until a certain number of decisions has been made via the SDAC, so as to minimize the switching activity of the LDAC over time.

[0087] Using dynamic element matching (DEM) approaches in relation to the logic layer enables handling (e.g., reduction and / or mitigation) of non-linear behavior of the ADC. Since the DEM is not applied within the feedback DAC loop, the conversion speed of the ADC is not negatively affected. Furthermore, the circuit layout design is more flexible than if the DEM was applied within the feedback DAC loop, e.g., enabling avoidance of parasitic load (and, hence, increased delay) in the decision loop.

[0088] The LDAC and / or the SDAC may be implemented as a C-DAC that allows it to double as a sample and hold capacitance as well as a DAC with an output being a superposition of the input sample and the DAC output effectively leading to a subtraction. The illustration of Figure IB can be seen as a functional representation, which is not necessarily an accurate circuit representation. Furthermore, it should be recognized that while the DACs operate based on the decisions by SAR, the inner workings of the DACs may involve other control signals (e.g., switch control signals as mentioned above) and / or clock signals; depending on the actual implementation of the DAC.

[0089] Also illustrated in Figure IB are optional amplifiers 145, 146. None, either, or both, of the optional amplifiers 145, 146 may be present according to various embodiments. The amplifiers 145, 146 may be seen as representing / modelling gain differences in the respective SDAC and LDAC paths. Alternatively or additionally, at least one of the amplifiers 145, 146 may represent an actual amplifier or buffer (e.g., differentiating signal levels between the SDAC and LDAC signal paths). Yet alternatively or additionally, at least one of the amplifiers 145, 146 may represent an effective gain when a signal is sampled onto the respective DAC.

[0090] The amplifier 145 is configured to provide the stage input signal 101 - correspondingly amplified by gs- to the feedback DAC 141 (e.g., to improve the signal-to-noise ratio for the feedback DAC 141), and may be denoted as a feedback DAC amplifier. The amplifier 146 is configured to provide the stage input signal 101 - correspondingly amplified by gL- to the feedforward DAC 142, and may be denoted as a feedforward DAC amplifier.

[0091] Typically, linearity requirements may be less strict for the feedback DAC amplifier 145 than for the feedforward DAC amplifier 146.

[0092] Generally, the amplification gs, gLof the optional amplifiers 145, 146 may be any suitable amplification.

[0093] For example, the feedback DAC amplifier 145 and / or the feedforward DAC amplifier 146 may be configured to amplify the stage input signal 101 in correspondence with a difference in range between the feedback DAC 141 and the feedforward DAC 142. If the full-scale ranges of the SDAC and the LDAC are RFS Sand RFS,L(respectively), the amplifications may, for example, be related as gL / gs= RFS,L / RFS,s-

[0094] Alternatively or additionally, the feedback DAC amplifier 145 (regardless of whether or not a feedforward DAC amplifier 146 is applied) may be configured to enable the feedback DAC 141 to operate with a full-scale range which is larger than (e.g., 1.5 times) that of the feedforward DAC 142; i.e., gs> gL.

[0095] It should be noted that the number of weights in the SDAC 141 and the LDAC 142 (i.e., the number of elements in wsiand wL1) may be the same, or may be different. For example, the weight for the least significant bit, LSB, may be omitted in the SDAC 141 (since a LSB switch is typically not needed in the SDAC 141 when the residue 117 is not used for a subsequent ADC stage).

[0096] Typically, SDAC-LDAC SAR ADCs suffer from very high sensitivity to gain mismatch between the paths (e.g., due to mismatches introduced in manufacturing, PVT (process, voltage, temperature) variations, etc.). This problem may be further exacerbated if the paths are implemented differently (e.g., when one branch includes an amplifier while the other does not, when different sampling and / or switching schemes are used, etc.). The gain mismatch may rapidly lead to saturation of subsequent stages. Thus, it may be beneficial if such gain mismatch could be mitigated or avoided.

[0097] Assuming that wTL1= awsTl(e.g., with a = RFS,L / RFS,S)a r|d that there are no error sources beyond the quantization, the SDAC residue 117 becomes vSrl= gsvin— = qsand the

[0098] LDAC residue 147 becomes qs) = vln(gL— ag ) + aqswhen all SAR decision cycles have been completed, where qsrepresents the quantization error (negated). Hence, if there is a gain mismatch (i.e., if gL— ags#= 0) the input signal vinwill leak into the second stage as part of the residue 147.

[0099] For simplicity, it is assumed that a = gs= 1, that gL= 1 + A, and that the ADC stage 110 is an Nblbit SAR. The residue 147 is ideally bound by | qs| < RFS / 2Nb +1, where RFSrepresents the full-scale range. A full-swing input signal will then leak into the residue 147 with a swing of A[— Rps / , RFS / 2], which has the same magnitude as the quantization error when RFS / 2Nbl+1= A ■ RFS / 2, i.e., when A= 1 / 2W^.

[0100] For example, with Nbl= 5, the gain error due to gain mismatch A becomes 3% of the gain gL. To accommodate for such leakage (on top of the quantization error), the residual amplifier 116 needs 6dB larger range and the second ADC stage needs one more bit of resolution (and one more decision cycle).

[0101] In practice, some additional range is provided when an ADC is designed (e.g., to accommodate noise, settling errors, etc.). It is typically desirable that signal leakage consumes as little as possible of this additional range budget. For example, the gain mismatch should preferably be in the order of 1% in some scenarios. It may generally be cumbersome to maintain such small gain mismatches over PVT imperfections based on ADC design; particularly if the SDAC path and LDAC path are based on different sampling schemes and / or different DAC switching schemes, and / or if one (or both) of the paths includes an amplifier.

[0102] Generally, a representation of a determined gain mismatch is denoted by 6 herein (possibly with a suitable subscript), where sign(8) represents (e.g., is an estimation of) the sign of the gain mismatch and |8| is an indication of the magnitude of the gain mismatch. For example, the determined gain mismatch 6 may have a monotonic (e.g., linear) relationship with the actual gain mismatch; at least over some range that includes zero gain mismatch.

[0103] According to some embodiments, a metric is calculated based on the digital outputs (e.g., 171, 172) of the first and second ADC stages, wherein the metric indicates sign (and typically magnitude) of the difference in gain between the two paths. The metric may be used to counteract the gain mismatch by manipulating the signal processing in any, or both, of the paths. Thus, the digital output u±may serve as reference for the leakage into the second stage (even though possibly with limited accuracy, at least limited by quantization errors), which may be related to the digital output u2to yield an indicator of the gain mismatch. These embodiments will be further exemplified in connection with Figures 4, 5, 7A, 7B, and 7C.

[0104] According to some embodiments, the SDAC residue 117 is used as reference and is compared with the LDAC residue 147. A feedback loop may be applied to counteract the gain mismatch (e.g., by manipulating the gain of the SDAC path) such that, on average, the LDAC residue 147 matched the SDAC residue 117. These embodiments will be further exemplified in connection with Figures 6, 7A, 7B, and 7C.

[0105] Figure 2 schematically illustrates an example arrangement according to some embodiments for control of a multi-stage ADC 210. For example, the multi-stage ADC 210 may correspond to the multi-stage ADC 100 of Figure 1A, wherein at least a first stage 110 is a SAR ADC stage as illustrated by Figure IB. The ADC 210 is configured to output a digital representation 293 (compare with 199 of Figure 1A) of an ADC input 291 (compare with 101 of Figure 1A).

[0106] The ADC 210 comprises a first stage 211 (compare with 110 of Figures 1A and IB) for providing a first digital output 281 (compare with 118 of Figures 1A and IB) based on a first stage input signal 291 (compare with 101 of Figures 1A and IB) and a second stage 213 (compare with 120 of Figure 1A) for providing a second digital output 282 (compare with 128 of Figure 1A) based on a second stage input signal 292 (compare with 102 of Figure 1A). The second stage input signal 292 comprises a feedforward residue 283 (compare with 147 of Figure IB) of the first stage 211, as amplified by residue amplifier 212 (compare with 116 of Figures 1A and IB).

[0107] The first digital output 281 corresponds to a first digital value part (compare with 171 of Figure 1A) for the digital representation and the second digital output 282 corresponds to a second digital value part (compare with 172 of Figure 1A) for the digital representation. As illustrated by processing circuitry 215 (PROC; compare with 115, 125, 125' of Figure 1A), the first and second digital outputs 281, 282 are suitably processed to provide the digital representation 293 of the ADC input.

[0108] The first stage 211 (ADC stage 1) is a successive approximation register, SAR, ADC stage. The second stage may, or may not, be a SAR ADC stage. As illustrated by 213 (ADC stage(s) 2...N; N>1), there may be one or more ADC stages which are subsequent to the first stage. The principles described herein for the "first stage" may be applied to any SAR ADC stage except the last (Nth) ADC stage.

[0109] The first stage 211 comprises a feedback DAC (SDAC; compare with 141 of Figure IB) configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC (LDAC; compare with 142 of Figure IB) configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal.

[0110] The arrangement of Figure 2 also comprises control circuitry (CNTR) 200. The control circuitry may be implemented as part of the ADC 210, or as separate circuitry.

[0111] The control circuitry is configured to determine a gain mismatch between first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal. To this end, the control circuitry 200 comprises a gain mismatch determiner (GMD; e.g., gain mismatch determination circuitry) 201, which is configured to determine the gain mismatch 298.

[0112] In some embodiments, the gain mismatch is determined by determining a metric of correlation for elements of the first and second digital outputs d1, d2(compare with 118, 128 or Figure 1A). The metric of correlation may involve all elements of the first and second digital outputs, or only some of the elements of the first and second digital outputs (with at least one element of first digital output and at least one element of second digital output). For example, the metric of correlation for elements of the first and second digital outputs d1, d2may be determined based on the first and second digital value parts ultu2(compare with 171, 172 or Figure 1A); which may be provided to the control circuitry 200 as illustrated by 294, 295.

[0113] In some embodiments, the gain mismatch is determined by determining a metric of difference between residual signals vSrl, vLrlassociated with first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal (compare with 117, 147 or Figure IB); which may be provided to the control circuitry 200 as illustrated by 296, 297.

[0114] The control circuitry is also configured to control the first stage processing to counteract the determined gain mismatch 298. To this end, the control circuitry 200 comprises a gain mismatch counteractor (GMC; e.g., gain mismatch counteraction circuitry) 202, which is configured to control the first stage processing, as illustrated by 299.

[0115] For example, the control of the first stage processing may be implemented by using the metric of correlation or the metric of difference (as applicable) directly as gain compensation; possibly after proper scaling. With y representing gain compensation, an example expression for updating the gain compensation is y[n + 1] = y[n] + / z ■ 8, where p represents a proper scaling factor and 6 is the metric of correlation.

[0116] Alternatively, the control of the first stage processing may be implemented by using the sign of the metric of correlation or the metric of difference (as applicable) to adjust the gain compensation by fixed step increment / decrement.

[0117] Figure 3 illustrates an example method 300 for controlling a multi-stage ADC (e.g., the ADC 210 of Figure 2, and / or the multi-stage ADC 100 of Figure 1A, wherein at least a first stage 110 is a SAR ADC stage as illustrated by Figure IB).

[0118] The method 300 comprises determining a gain mismatch between first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal, as illustrated by step 320, and controlling the first stage processing to counteract the determined gain mismatch, as illustrated by step 330. The gain mismatch determination of step 320 and / or the first stage processing control may be performed in accordance with any approach as described herein.

[0119] Typically, the method 300 is triggered by initialization of gain control, as illustrated by optional step 310. For example, the triggering may be performed periodically, and / or responsive to detecting an operator control signal or deteriorating ADC performance.

[0120] In some embodiments, the gain mismatch counteraction of step 330 may be evaluated, as illustrated by optional step 340. When the evaluation indicates that the gain mismatch counteraction is adequate (Y-path out of step 340), the method 300 may be considered complete, as illustrated by 350. When the evaluation indicates that the gain mismatch counteraction is not adequate (N-path out of step 340), steps 320 and 330 may be repeated. When, the method 300 is considered complete, as illustrated by 350, the latest gain mismatch counteraction may be applied henceforth (e.g., until there is an indication that it is no longer adequate, and / or until some specific time period has lapsed).

[0121] Any suitable condition for the gain mismatch counteraction may be applied in step 340. For example, the gain mismatch counteraction may be considered as adequate when the magnitude of the metric of correlation (or the metric of difference) is less than a threshold value. The threshold value may, for example, correspond to a certain level of gain mismatch (after correction) which the ADC has been designed to handle.

[0122] It should be noted that at least some portions of the method 300 may be performed offline (e.g., while the multi-stage ADC is not performing real-time analog-to-digital conversion) and / or by circuitry not comprised in the control circuitry or the ADC (e.g., remote circuitry). For example, the gain mismatch determination (step 320) may be performed by circuitry not comprised in the control circuitry or the ADC based on statistics (e.g., of ultu2and / or vSrl, vLrl) collected from the multi-stage ADC. The circuitry not comprised in the control circuitry or the ADC may, for example, be a custom digital circuit or accelerator (e.g., a field-programmable gate array, FPGA), or a multi-purpose processor (e.g., a computer).

[0123] As already mentioned, the gain mismatch between first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal may be determined by determining a metric of correlation for elements of the first and second digital outputs d1, d2(e.g., by using the first and second digital value parts iq, it2). This approach will now be further exemplified with reference to Figures 4 and 5.

[0124] According to some embodiments, the metric of correlation 8Ccomprises a covariance between the first digital value part and the second digital value part, i.e., 8C= — where £"[•] denotes the expected value, and a desired value (no leakage) is 8C= 0. The sign of the covariance indicates the sign of the gain mismatch, and the magnitude of the covariance corresponds (at least to some extent) to the magnitude of the gain mismatch. Thus, the covariance may be used as a metric to guide a gain mismatch correction algorithm. It should be noted that the covariance calculation may be implemented with comparatively low complexity.

[0125] More generally, the metric of correlation 8Cmay be determined as 8C= cov(itA, itB), where uArepresents a value based on elements dA, uBrepresents a value based on elements dB, and where dAand dBare subsets of the elements {dltd2}. The sets dAand dBare different, and may be disjunct or partially overlapping. Further, dAU dBmay be equal to {dltd2], or may be a subset thereof which comprises at least one element from each of d±and d2. For example, the most significant bits of drand d2may be used for determination of the metric of correlation.

[0126] Even more generally, the metric of correlation 8Cmay be determined based on the expression 8C= corr(A(dA),B(dB)), whereA(-) andB(-) are any suitable functions and corr(-) is any suitable correlation measure (e.g., cov(-))-

[0127] Figure 4 illustrates an example of 8C= covCi^, it2) as a function of gs(assuming gL= 1 and no other gain mismatch) for a two-tone input with added direct current (DC) offset and white noise. The horizontal axis shows gsand the vertical axis shows 8C.

[0128] The results for a relatively high input signal level are represented by 401, the results for a medium input signal level are represented by 402, and the results for a relatively low input signal level are represented by 403. It can be concluded that the covariance is zero (see 404) when the gain mismatch is zero, i.e., when gs= 1 (see 405). It can also be noted that the covariance behaves linearly around the desired value of gs= 1.

[0129] Even if the second stage saturates (which is manifested as compressed covariance values) when the gain mismatch is large for the relatively high input power 401, the sign of the covariance is still useful as an indicator of the gain mismatch.

[0130] According to some embodiments, the metric of correlation 8Ccomprises a slope of an affine function representing a statistical count of values of the second digital value part for each of a plurality of values of the first digital value part.

[0131] Figure 5 illustrates an example of an affine function 500 which represents the statistical count of values of the second digital value part u2for each of a plurality of values of the first digital value part u±via line fitting (e.g., least squares fitting) to a histogram Hfu^, wherein each histogram bar represents the mean of the u2for a particular value of u±.

[0132] The leakage [3gdue to gain mismatch ( / 3g= 1 — ags / gL} manifests itself as the slope of an affine function fitted to the histogram; where a positive slope means that (3g> 0, a negative slope means that (3g< 0, and the magnitude of the slope is an indication of the magnitude of the gain mismatch.

[0133] The example of Figure 5, relates to a single-tone input (assuming gsst 1, gL= 1, and no other gain mismatch). The horizontal axis represents different values of u±and the vertical axis shows the corresponding mean values of u2.

[0134] The histogram Hfu^ may be used directly, or only some of the histogram bars (i.e., only some of the values of u±) may be selected to form a pruned histogram H (itlp) that is used for slope determination, where ulprepresents the values of u±that correspond to the selected histogram bars. Any suitable selection criteria may be applied for the pruning. For example, a histogram bar may be selected if the corresponding mean value of u2is non-zero and is nonbiased.

[0135] In some embodiments, one or more of the bar(s) 501 representing the lowest value(s) of with non-zero bar(s) and / or one or more of the bar(s) 502 representing the highest value(s) of urwith non-zero bar(s) may be removed before line fitting. This may be beneficial because the corresponding statistics may not be consistent with the average behavior in general (e.g., when the probability density function of the signal is well confined; such as for a single-tone input). Then, the edges of the probability density function may not align with the coarse quantization grid, which leads to a bias in the mean value of the outermost bars of the histogram. For most modulated signals, the probability density function of the signal does not have such well confined edges, and no histogram bar removal is needed.

[0136] In some embodiments, the gain mismatch detection based on the histogram approach may be conditioned on the number of non-zero histogram bars exceeds a threshold value (e.g., not using the gain mismatch detection based on the histogram approach when the number of nonzero histogram bars are fewer than the threshold value). This has the benefit of avoiding use of gain mismatch detections that have low accuracy. When the number of non-zero bins are relatively few, the input signal is typically relatively small so that there is typically no saturation issues, and gain mismatch counteraction is not crucial.

[0137] In some embodiments, the plurality of values of the first digital value part comprises first and second (typically disjoint and / or equally large) groups of values. For example, the plurality of values of the first digital value part may be divided into a group of relatively low values ul°wand a group of relatively high values u^iah(e.g., by partitioning the plurality of values of the first digital value part u±between two adjacent values of ut). Then, the metric of correlation 8Cmay be determined as ^it2(it^I,9ft) — it2(it^0W)^ / ^it2(it^I'9ft) + it2(it^ow) wherein it2(iI5ft) represents the mean value of u2forthe group of relatively high values and it2 represents the mean value of u2for the group of relatively low values. Put differently, the slope of the affine function may be seen as comprising a normalized difference between average value of the second digital value part for the first group of the first digital value part and average value of the second digital value part for the second group of the first digital value part.

[0138] In the histogram context, this approach may be exemplified as dividing the histogram in two parts; an "higher" part corresponding to the values of u±which are higher than a dividing threshold and a "lower" part corresponding to the values of which are lower than the dividing threshold. Assuming that a pruned histogram H(ulp) is used, the lower part may be denoted by H (ulp low) and the higher part by H(ulp hi). The normalized difference between the mean values of each respective part can be used as a metric of correlation, and may be calculated as

[0139] Figure 6 schematically illustrates some example gain mismatch processing, wherein the gain mismatch is determined by determining a metric of difference between residual signals vSrland vLrl, associated with first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal, respectively.

[0140] In some situations, the approaches of Figure 6 requires that the SDAC residual signal vSrlis correct and can be used as reference. For example, a gain error in the SDAC path (e.g., due to a change of the DAC range) typically only changes the magnitude of the residue vSrl. Since the same DAC voltage reference (compare with 705, 706, 707 of Figures 7A-C) is used when taking decisions in the comparator as when generating the residue vSrl, the signal leakage effect experienced for the LDAC residual signal vLrlis not present for the SDAC residual signal vSrl. Thus, the SDAC residual signal vSrlis typically within its expected bounds.

[0141] For example, the gain mismatch may be determined by filtering the metric of difference. The filtering may be any suitable filtering. For example, the filtering may implement the function ~ vLrl)c for sample n, where gc(n) may be used as a control signal, c represents a filter coefficient, and a suitable initiation value is used (e.g., ^c(0) = 1).

[0142] The coefficient may have any suitable value. In some scenarios, the coefficient may be c = gintd1 0, where gintis an integrator gain determining accuracy and speed of convergence, and d1 0= ±1 is the most significant bit of d±(i.e., typically, representing the sign of the current sample).

[0143] Part (a) of Figure 6 schematically illustrates these principles as implemented by a controller (CNTR) 600. The controller 600 is configured to receive the residual signals vLrland vSrlas inputs at 696 and 697, respectively (compare with 296, 297). The difference 602 between the residual signals is determined, as illustrated by 601, and scaled by the coefficient 605, as illustrated by 606. The controller 600 is also configured to receive d1 0as input at 698, and the coefficient 605 is determined by multiplying d1 0by gint604, as illustrated by 603. The scaled difference 607 between the residual signals is filtered according to gc(n) = gc(n — 1) + (vLrl~ vLrl)c, as illustrated by 610, and the filter output 611 may be used as a control signal 699 for gain mismatch mitigation (compare with 299 of Figure 2).

[0144] Part (b) of Figure 6 schematically illustrates a controller (CNTR) 620, wherein an analog filter (AFILT) 629 is configured to implement gc(n) = gc(n — 1) + (vLrl— vLrl)gintd1 0completely in the analog domain. For example, a discrete-time integration can be implemented in analog domain using switched capacitor circuits of different types. In this particular approach, the weight for the LSB can typically not be omitted in the SDAC (since the analog residues 696, 697 from the LDAC and the SDAC are used directly and should preferably be comparable in terms of how they are generated). Part (c) of Figure 6 schematically illustrates a controller (CNTR) 640, wherein respective ADCs 641, 642 are configured to convert the residual signals vLrland vSrlto the digital domain, and a digital filter (DFILT) 649 is configured to implement gc(n) = gc(n — 1) + (vLrl— vLrl)gintd1 0completely in the digital domain. Thus, the integration is performed in the digital domain, as well as the difference determination.

[0145] Part (d) of Figure 6 schematically illustrates a controller (CNTR) 660, the difference 662 between the residual signals vLrland vSrlis determined in the analog domain, as illustrated by 661, and an ADC 663 is configured to convert the difference to the digital domain and provide the result to a digital filter (DFILT) 669 for provision of gc(n) = gc(n — 1) + (vLrl— vLrl)gintd1 0. Thus, the integration is performed in the digital domain, while the difference determination is performed in the analog domain. In this case, the ADC 663 may be implemented as a single bit ADC (comparator) or an ADC with relatively few bits; at least when the filter sufficiently averages any noise (e.g., long time integration).

[0146] Thereby, any of the controllers 600, 620, 640, 660 may be seen as acting in a feedback loop of the first stage; for driving the residual signal vLrltowards the residual signal vSrlby amplifying the difference (vLrl— vLrl) by gintto create an error signal 699, using d1 0to flip the sign of the error signal as needed (depending on input signal polarity) for the loop to converge.

[0147] In some scenarios, any of the controllers 600, 620, 640, 660 (and / or a variable gain amplifier used for manipulation of gs) may have an offset that affects the feedback loop. An offset in the variable gain amplifier will typically manifest itself only as an offset in vLrl(since the offset is treated as an input signal, it does not manifest itself in vSrl). Thus, an offset in the variable gain amplifier can typically be detected during start-up with vln= 0. This operation also addresses any offset of the controllers. When the offset is found, it may be subtracted from vLrland the gain calibration can proceed with any input signal. For example, the offset may be subtracted from any of the signals 696 and 602 in part (a) of Figure 6, from the signal 696 in part (b) of Figure 6, from the signal 696 or from the output of the ADC 641 in part (c) of Figure 6, and from any of the signals 696 and 662 in part (d) of Figure 6.

[0148] One or more of the principles described in connection with any of Figures 4, 5, and 6 may be implemented by the control circuitry 200 of Figure 2. Alternatively or additionally, One or more of the principles described in connection with any of Figures 4, 5, and 6 may be used in step 320 of Figure 3.

[0149] Generally, gain mismatch counteraction may be accomplished by application of a gain correction parameter ysapplied to the SDAC path and / or a gain correction parameter yLapplied to the LDAC path (where in increased value of a gain correction parameter may represent an increased gain of the corresponding path). The gain correction parameter(s) may be based on a determined metric of correlation for elements of the first and second digital outputs and / or based on a determined metric of difference between residual signals for provision of the first digital output and for generation of the second stage input signal.

[0150] According to some embodiments, gain mismatch counteraction commences by initialization of the gain correction parameter to a suitable start value (compare with step 310 of Figure 3). For example, the start value of the gain correction parameter may be yinit= 0. Then, the gain mismatch 6 is determined (compare with step 320 of Figure 3), for example by determining an indication of the gain mismatch sign and, optionally, an indication of the gain mismatch magnitude.

[0151] The gain correction parameter is updated based on the determination which leads to gain mismatch counteraction control (compare with step 330 of Figure 3). The update may be performed in any suitable way. For example, the update may be based only on the determined gain mismatch sign; e.g., y: = y + / z ■ sign(<5) where / z is a constant which controls gain change rate and resilience to errors of the gain mismatch determination. Alternatively, the update may be based on the determined gain mismatch sign and magnitude; e.g., y: = y + / z ■ 8. Then, the gain mismatch 6 is determined again (compare with the loopback to step 320 from step 340 in Figure 3), and the gain correction parameter is updated accordingly.

[0152] Figures 7A, 7B, and 7C schematically illustrate some example implementations of gain mismatch counteraction according to some embodiments. The gain mismatch counteraction is applied by controlling processing of a SAR ADC stage 710, 720, 730 (the "first stage"; compare with 110 of Figure IB and 211 of Figure 2), via a control signal 799 (compare with 299 of Figure 2).

[0153] The SAR ADC stage 710, 720, 730 comprises a feedback DAC in the form of an SDAC 711 (compare with 141 of Figure IB), a feedforward DAC in the form of an LDAC 712 (compare with 142 of Figure IB), and a processing block (C / R / L) 713. The processing block 713 typically comprises a comparator (compare with 112 of Figure IB), a register (compare with 113 of Figure IB), and - possibly - additional logic (compare with 143 of Figure IB).

[0154] Furthermore, the SAR ADC stage 710, 720, 730 is configured to receive a first stage input signal 701 (compare with 101 of Figure IB) and to provide a residual signal 727 (compare with 147 of Figure IB and 283 of Figure 2) to a residue amplifier 716 (compare with 116 of Figure IB and 212 of Figure 2).

[0155] The SDAC 711 is configured to determine a feedback residual signal 717 (compare with 117 of Figure IB) based on the first stage input signal 701 and an input 718' derived from a first digital output 718 (compare with 118 of Figure IB) of the processing block 713.

[0156] The LDAC 712 is configured to determine the feedforward residual signal 727 (compare with 147 of Figure IB) based on the first stage input signal 701 and a variant 728 (compare with 160 of Figure IB) of the first digital output of the processing block 713.

[0157] The SDAC 711 is controllable via reference signal inputs vrefS_p 705, vrefS_cm 706, and vrefS_m 707, and the LDAC 712 is controllable via reference signal inputs vrefL_p 702, vrefL_cm 703, and vrefL_m 704. The full-scale range of the SDAC 711 is defined by vrefS_p 705 and vrefS_m 707 and the full-scale range of the LDAC 712 is defined by vrefL_p 702 and vrefL_m 704. The reference signal inputs vrefS_cm 706 and vrefL_cm 703 are common-mode voltages; typically selected - respectively - as the mean value of vrefS_p 705 and vrefS_m 707, and as the mean value of vrefL_p 702 and vrefL_m 704. In some DAC implementations, the reference signal inputs 706, 703 are omitted. Generally, the first stage processing may be controlled to counteract the determined gain mismatch by adjusting a gain for the first stage processing for provision of the first digital output (e.g., adjusting an SDAC path gain) and / or by adjusting a gain for the first stage processing for provision of the feedforward residue (e.g., adjusting an LDAC path gain). It should be noted that adjustment of the LDAC path gain typically leads to a change of the overall gain of the first stage (which may need to be accounted for; e.g., if the multi-stage ADC is used as a constituent ADC of a time-interleaved ADC). For simplicity, the examples herein will focus on adjusting the SDAC path gain.

[0158] In the example illustrated in Figure 7A, the first stage processing is controlled to counteract the determined gain mismatch by using the control signal 799 to control a variable gain amplifier 715 that is configured to provide a variably amplified version of the first stage input signal 701 to the feedback DAC 711. The variable gain amplifier 715 may represent an actual amplifier or buffer. For example, the variable gain amplifier 715 may correspond to the amplifier 145 of Figure IB.

[0159] In the example illustrated in Figure 7B, the first stage processing is controlled to counteract the determined gain mismatch by controlling a variable range of the feedback DAC 711. This may be achieved, for example, by adjusting the reference signal inputs vrefS_p 705 and / or vrefS_m 707. To this end, the reference signal inputs vrefS_p 705, and vrefS_m 707 are controllable independently of the corresponding reference signal inputs vrefL_p 702, and vrefL_m 704.

[0160] Adjustment circuitry 725 may be applied for providing the reference signals 705, 706, 707 (or at least one of 705 and 707) based on the control signal 799.

[0161] Generally, the digital output value Doutof an ADC may relate to the analog input value Ainof the ADC as Dout= Ain / RFS, where RFSrepresents the full-scale range and may correspond to the difference between vref_p and vref_m. Thus, adjusting one or more of the reference signal inputs 705 and 707 typically leads to a change in full-scale range, which corresponds to a gain change.

[0162] In the example illustrated in Figure 7C, the first stage processing is controlled to counteract the determined gain mismatch by using the control signal 799 to control a variable capacitance Cg 750 associated with an output of the feedback DAC 711 (which is exemplified in Figure 7C as a capacitive DAC with binary weighted capacitors C, 2C, 4C, ... , 2Nbl~1C).

[0163] In the example of Figure 7C, the input signal 701 is top-plate sampled on the comparator input node 717 with no attenuation from 750 (although there may be a slight increase in loss due to longer settling time caused by 750). The full-scale range RFSof the feedback DAC 711 is affected by Cg, which may be expressed by RFS= C(2Wfel— l) / (C(2Wfel— 1) + C5). Thus, adjusting variable capacitance Cg750 typically leads to a change in full-scale range, which corresponds to a gain change.

[0164] Generally, the variable capacitance 750 may be implemented as comprised in the feedback DAC 711, or may be implemented as a separate component at the output of feedback DAC 711. The variable capacitance 750 may, for example, be implemented as a bank of capacitors 751, 752, 753, 754 (e.g., having respective values Cu, 2CU, 4CU, ... , 2yCu) with respective switches 755, 756, 757, 758. Then, the control signal 799 may be configured to close one or more of the switches to provide a suitable value for the variable capacitance 750.

[0165] One or more of the principles described in connection with any of Figures 7A, 7B, and 7C may be implemented by the control circuitry 200 of Figure 2. Alternatively or additionally, One or more of the principles described in connection with any of Figures 7A, 7B, and 7C may be used in step 330 of Figure 3.

[0166] Figure 8 illustrates, for two different example input signals, example gain mismatch counteraction results that may be achieved by application of the approaches described herein.

[0167] The example illustrated in part (a) uses a ramp signal as input signal vin801 (compare, for example, with 291 of Figure 2), and conversion of the gain compensation gcis illustrated by 804. The corresponding feedforward residual signal vLrl(compare, for example, with 283 of Figure 2) is illustrated by 803, which may be compared to the feedforward residual signal 802 that would result if gain mismatch counteraction was not applied. It can be seen that the feedforward residual signal 803 remains relatively close to zero when counteraction is applied, while the feedforward residual signal 802 drifts due to the ramp signal when counteraction is not applied. The example illustrated in part (b) uses a sinusoidal signal as input signal vln811 (compare, for example, with 291 of Figure 2), and conversion of the gain compensation gcis illustrated by 814. The corresponding feedforward residual signal vLrl(compare, for example, with 283 of Figure 2) is illustrated by 813, which may be compared to the feedforward residual signal 812 that would result if gain mismatch counteraction was not applied. It can be seen that the feedforward residual signal 813 remains relatively close to zero when counteraction is applied, while the feedforward residual signal 812 is more prominently impacted by the sinusoidal signal when counteraction is not applied.

[0168] Figure 9 schematically illustrates an example electronic apparatus (APP) 900 according to some embodiments. For example, the apparatus 900 may be a communication apparatus (e.g., a wireless communication device for a cellular communications system, or a base station for a cellular communications system). Alternatively or additionally, the apparatus 900 may be a signal receiver.

[0169] The apparatus 900 comprises controlling circuitry (CC) 940 (compare with 200 of Figure 2) for a multi-stage ADC (compare with 210 of Figure 2), wherein the controlling circuitry 940 is configured to determine a gain mismatch between first stage processing for provision of a first digital output and first stage processing for generation of a second stage input signal, and control the first stage processing to counteract the determined gain mismatch.

[0170] In some embodiments, the apparatus 900 also comprises a multi-stage ADC, as illustrated by 930. The controlling circuitry 940 may be comprised in the ADC 930 as illustrated by Figure 9, or may be implemented separately from the ADC.

[0171] In some embodiments, the ADC 930 and / or the controlling circuitry 940 is / are implemented on an integrated circuit (IC) 920.

[0172] The described embodiments and their equivalents may be realized in hardware. The embodiments may be performed by general purpose circuitry. Examples of general purpose circuitry include digital signal processors (DSP), central processing units (CPU), co-processor units, field programmable gate arrays (FPGA) and other programmable hardware. Alternatively or additionally, the embodiments may be performed by specialized circuitry, such as application specific integrated circuits (ASIC) or application-specific circuitry within an integrated circuit. The general purpose circuitry and / or the specialized circuitry may, for example, be associated with or comprised in an electronic apparatus such as a communication apparatus.

[0173] Embodiments may appear within an electronic apparatus (such as a communication apparatus) comprising arrangements, circuitry, and / or logic according to any of the embodiments described herein. Alternatively or additionally, an electronic apparatus (such as a communication apparatus) may be configured to perform method steps according to any of the embodiments described herein.

[0174] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used.

[0175] Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims.

[0176] For example, the method embodiments described herein discloses example methods through steps being performed in a certain order. However, it is recognized that these sequences of events may take place in another order without departing from the scope of the claims. Furthermore, some method steps may be performed in parallel even though they have been described as being performed in sequence. Thus, the steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step.

[0177] In the same manner, it should be noted that in the description of embodiments, the partition of functional blocks into particular units is by no means intended as limiting. Contrarily, these partitions are merely examples. Functional blocks described herein as one unit may be split into two or more units. Furthermore, functional blocks described herein as being implemented as two or more units may be merged into fewer (e.g. a single) unit.

[0178] Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever suitable. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa. Hence, it should be understood that the details of the described embodiments are merely examples brought forward for illustrative purposes, and that all variations that fall within the scope of the claims are intended to be embraced therein.

Claims

CLAIMS1. Control circuitry (200, 940) for an analog-to-digital converter, ADC, (100, 210, 930) configured to output a digital representation (199, 293) of an ADC input (101, 291), wherein the ADC comprises a first stage (110, 211) for providing a first digital output (118, 281) based on a first stage input signal (101, 291) and a second stage (120, 213) for providing a second digital output (128, 282) based on a second stage input signal (102), wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation, wherein the first stage is a successive approximation register, SAR, ADC stage, which comprises a feedback digital-to-analog converter, DAC, (141) configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC (142) configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal, and wherein the control circuitry is configured to: determine a gain mismatch between first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal, and control the first stage processing to counteract the determined gain mismatch.

2. The control circuitry of claim 1, wherein the control circuitry is configured to determine the gain mismatch by determining a metric of correlation for elements of the first and second digital outputs.

3. The control circuitry of claim 2, wherein the metric of correlation comprises a covariance between the first digital value part and the second digital value part.

4. The control circuitry of claim 2, wherein the metric of correlation comprises a slope of an affine function (500) representing a statistical count of values of the second digital value part for each of a plurality of values of the first digital value part.

5. The control circuitry of claim 4, wherein the affine function represents the statistical count of values via least squares fitting.

6. The control circuitry of claim 4, wherein the plurality of values of the first digital value part comprises a first group of values of the first digital value part and a second group of values of the first digital value part, and wherein the slope of the affine function comprises a normalized difference between average value of the second digital value part for the first group of the first digital value part and average value of the second digital value part for the second group of the first digital value part.

7. The control circuitry of claim 1, wherein the control circuitry is configured to determine the gain mismatch by determining a metric of difference between residual signals (696, 697) associated with first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal.

8. The control circuitry of claim 7, wherein the control circuitry is configured to determine the gain mismatch by filtering the metric of difference.

9. The control circuitry of any of claims 7 through 8, wherein the control circuitry is configured to determine the gain mismatch by scaling the difference between residual signals by a most significant bit (698) of the first digital output.

10. The control circuitry of any of claims 1 through 9, wherein the control circuitry is configured to control the first stage processing to counteract the determined gain mismatch by adjusting a gain for the first stage processing for provision of the first digital output.

11. The control circuitry of claim 10, wherein the control circuitry is configured to control the first stage processing to counteract the determined gain mismatch by controlling a variable gain amplifier (715) that is configured to provide a variably amplified version of the first stage input signal to the feedback DAC.

12. The control circuitry of claim 10, wherein the control circuitry is configured to control the first stage processing to counteract the determined gain mismatch by controlling (725) a variable range of the feedback DAC.

13. The control circuitry of claim 10, wherein the control circuitry is configured to control the first stage processing to counteract the determined gain mismatch by controlling a variable capacitance (750) associated with an output of the feedback DAC.

14. An analog-to-digital converter, ADC, (210, 930) configured to output a digital representation of an ADC input, the ADC comprising: a first stage for providing a first digital output based on a first stage input signal and a second stage for providing a second digital output based on a second stage input signal, wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation, wherein the first stage is a successive approximation register, SAR, ADC stage, which comprises a feedback digital-to-analog converter, DAC, configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal; and the controlling circuitry (200, 940) of any of claims 1 through 14.

15. The ADC of claim 14, wherein the feedback DAC is smaller than the feedforward DAC.

16. The ADC of any of claims 14 through 15, wherein the first stage further comprises a feedbackDAC amplifier (145) that is configured to provide the first stage input signal - correspondingly amplified - to the feedback DAC and / or a feedforward DAC amplifier (146) that is configured to provide the first stage input signal - correspondingly amplified - to the feedforward DAC.

17. The ADC of claim 16, wherein the feedback DAC amplifier and / or the feedforward DAC amplifier is / are configured to amplify the first stage input signal in correspondence with a difference in range between the feedback DAC and the feedforward DAC.

18. An integrated circuit (920) comprising the controlling circuitry (200, 940) of any of claims 1 through 13, and / or the ADC (210, 930) of any of claims 14 through 17.

19. An electronic apparatus (900) comprising the controlling circuitry (200, 940) of any of claims1 through 13, and / or the ADC (210, 930) of any of claims 14 through 17, and / or the integrated circuit (920) of claim 18.

20. The electronic apparatus of claim 19, wherein the electronic apparatus is a signal receiver.

21. The electronic apparatus of claim 19, wherein the electronic apparatus is a communication apparatus.

22. The electronic apparatus of claim 21, wherein the communication apparatus is a wireless communication device for a cellular communications system.

23. The electronic apparatus of claim 21, wherein the communication apparatus is a base station for a cellular communications system.

24. A method for controlling an analog-to-digital converter, ADC, configured to output a digital representation of an ADC input, wherein the ADC comprises a first stage for providing a first digital output based on a first stage input signal and a second stage for providing a second digital output based on a second stage input signal, wherein the first digital output corresponds to a first digital value part for the digital representation and the second digital output corresponds to a second digital value part for the digital representation, and wherein the first stage is a successive approximation register, SAR, ADC stage, which comprises a feedback digital-to-analog converter, DAC, configured to provide a feedback analog representation of the first digital output for convergence of the first digital output, and a feedforward DAC configured to provide a feedforward analog representation of the first digital output for generation of the second stage input signal, the method comprising: determining (320) a gain mismatch between first stage processing for provision of the first digital output and first stage processing for generation of the second stage input signal; and controlling (330) the first stage processing to counteract the determined gain mismatch.

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