Criticality determinations for elementary subparts of circuit designs

Abstract

Systems and methods are presented for criticality determinations for elementary subparts of a circuit design. Determination of criticality values (220) for elementary subparts (e.g., registers) in a logic-level circuit design (210) may be based on an input flop factor, an input combinational logic factor, and an output flop factor. The input flop factor may be based on a number of other registers in the logic-level circuit design (210) that affect to an input signal to a given register, the input combinational logic factor may be based on a number of logic gates that affect the input signal, and the output flop factor may be based on a number of other registers in the logic-level circuit design (210) with input signals that are affected by an output signal of the given register. Determined criticality values (220) may be used to set physical designs of corresponding elementary subparts.

Description

CRITICALITY DETERMINATIONS FOR ELEMENTARY SUBPARTS OF CIRCUIT DESIGNSBACKGROUND

[0001] Electronic circuits, such as integrated circuits, are used in nearly every facet of modem society, from automobiles to microwaves to personal computers and more. Design of circuits may involve many steps, known as a "design flow." The particular steps of a design flow are often dependent upon the type of circuit being designed, its complexity, the design team, and the circuit fabricator or foundry that will manufacture the circuit. Electronic design automation (EDA) applications support the design and verification of circuits prior to fabrication. EDA applications may implement various procedures, e.g., functions, tools, or features to analyze, test, or verify a circuit design at various stages of the design flow.BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Certain examples are described in the following detailed description and in reference to the drawings.

[0003] Figure 1 shows an example of a computing system that supports criticality determinations for elementary subparts of circuit designs.

[0004] Figure 2 shows an example analysis by a criticality determination engine to determine criticality values for registers of a logic-level circuit design.

[0005] Figure 3 shows an example of logic that a system may implement to support criticality determinations for elementary subparts of circuit designs.

[0006] Figure 4 shows an example of a computing system that supports criticality determinations for elementary subparts of circuit designs.DETAILED DESCRIPTION

[0007] With advances in modern technology, circuits have become an increasingly prevalent and integral part of modem society. Safety-critical embedded circuit systems and software-intensive systems are some examples of how circuits are employed in modem day contexts, from automobile anti-lock braking systems, to healthcare monitoring systems, to malware detection circuits, and near-countless other applications. Circuits, including embedded circuit systems, have become increasing complex in both size and functionality. The development and use of circuit systems that have the potential to endanger human lives or cause significant damage are often governed by strict safety standards. Identification of elementary subparts (e.g., registers) of a circuit design that are particularly impactful to the proper operation of circuits, including safety critical circuits that affect human life, is increasingly important, and doing so can increasingly ensure functional safety and reliability under varying operating conditions.

[0008] As used herein, an elementary subpart may refer to internal registers, latches, or related logic of a circuit design. In some examples, elementary subparts may be defined according to International Standard for Organization (ISO) 26262, part 11 , which provides guidance that a semiconductor component can be divided into parts. In such guidance, the whole semiconductor hierarchy can be specified as a component, a next level down in the hierarchy specified as a part (e.g., a CPU), the following levels of the hierarchy (e.g., a CPU register bank) as subparts, and elementary subparts of the hierarchy specified as to include registers, latches, and any other suitable logic at a consistent or similar complexity level in the logical design of the component.

[0009] For a given logical element of a circuit, multiple physical designs are possible to implement the same logical element. For example, implementing a particular register with an implementation that has increased number of transistors can provide increased drive strength, stability, and noise immunity. However, such implementations can consume greater chip area and have increased power requirements, and it would be impractical to uniformlyimplement every register of a circuit design with such an implementation. Thus, identification of which particular registers to implement with increased stability (though also with increased area or power consumption) is an important task for circuit design process. While ensuring proper functionality and design of safety critical circuits is imperative, individual evaluation of elementary subparts of a circuit design for impact on circuit functionality can be tedious, time-consuming, and overwhelming. With even simple circuits including thousands of registers, oftentimes more, manual inspection of logical circuit designs is not feasible nor practically possible with the human mind for even the most basic of circuit designs in modem applications and systems.

[0010] The disclosure herein may provide systems, methods, devices, and logic for criticality determinations for elementary subparts of circuit designs. The criticality determination technology of the present disclosure may support evaluation and analyses of circuit designs at a logical level, to identify elementary subparts for which faults or malfunction would impact operation of the circuit design to a greater degree that other subparts of the circuit design. As described herein, criticality determinations may be based on multiple factors, which can be computed through evaluation of a circuit design and how elementary subparts interact with one another. Such factors for criticality determination may include an input flop factor, an input combinational logic factor, and an output flop factor, as described in greater detail here. Through such factors, the impact and interconnection of an elementary subpart may be quantified, which may support the determination of important or critical registers within a circuit design.

[0011] Moreover, various diagnostic coverage determinations can be performed based on criticality analyses performed for circuit designs, which may allow circuit designers to protect especially-important registers or other elementary subparts through physical designs and implementations with increased fault-resistance and resiliency. Accordingly, the present disclosure may support identification of critical registers within a circuit design, and may do so flexibly and adaptably for specific characteristics and requirements of an embedded system. Through such determinations, designers can focus onimproving the reliability and fault tolerance of identified critical elementary subparts to ensure the functional safety and satisfactory operation of the circuit system.

[0012] These and other criticality determination features and technical benefits according to the present disclosure are described in greater detail herein.

[0013] Figure 1 shows an example of a computing system 100 that supports criticality determinations for elementary subparts of circuit designs. The computing system 100 may take the form of a single or multiple computing devices such as application servers, compute nodes, desktop or laptop computers, smart phones or other mobile devices, tablet devices, embedded controllers, and more. In some implementations, the computing system 100 hosts, instantiates, executes, supports, or implements an EDA application or EDA system that supports circuit design and analysis, and may accordingly provide or implement any of the criticality determination technology described herein.

[0014] As an example implementation to support any combination of the criticality determination features described herein, the computing system 100 shown in Figure 1 includes a criticality determination engine 110 and a physical design engine 112. The computing system 102 may implement the engines 110 and 112 (including components thereof) in various ways, for example as hardware and programming. The programming for the engines 110 and 112 may take the form of processor-executable instructions stored on a non-transitory machine-readable storage medium and the hardware for the engines 110 and 112 may include a processor to execute those instructions. A processor may take the form of single processor or multiprocessor systems, and in some examples, the computing system 100 implements multiple engines using the same computing system features or hardware components (e.g., a common processor or a common storage medium).

[0015] In operation, the criticality determination engine 110 may access a logic-level circuit design and determine criticality values for elementarysubparts in the logic-level circuit design, e.g., individual registers in the logiclevel circuit design. The criticality determination engine 110 may determine a criticality value for a given elementary subpart of the logic-level circuit design based on multiple factors, including an input flop factor, an input combinational logic factor, and an output flop factor. For a given elementary subpart, the input flop factor may be determined based on a number of other elementary subparts in the logic-level circuit design that affect to an input signal to the given elementary subpart, the input combinational logic factor may be determined based on a number of logic gates that affect the input signal to the given elementary subpart, and the output flop factor may be determined based on a number of other elementary subparts in the logic-level circuit design with input signals that are affected by an output signal of the given elementary subpart.

[0016] In operation, the physical design engine 112 may set (e.g., select or specify) a physical-level design for the given elementary subpart in the logiclevel circuit design based on the criticality value determined for the given elementary subpart. For example, the physical design engine 112 may set a physical implementation with increased fault tolerance, reliability, or resiliency for a particular register or other elementary subpart deemed as critical, e.g., with a criticality value that exceeds a predetermined threshold.

[0017] These and other features of the criticality determination technology of the present disclosure are described in greater detail next. The criticality determination technology described herein may be used to perform criticality determinations for any type of elementary subpart of a circuit design. Many of the examples described herein are provided using registers as an example type of elementary subpart for which the criticality determination technology of the present disclosure can be applied. However, criticality determinations can be performed for any suitable elementary subpart or discrete circuit part of a circuit design. For any example described herein using the term elementary subpart, such a description contemplates a register as the elementary subpart. Any example described herein using the term registercan likewise be consistently applied for elementary subparts or other circuit elements of any other type.

[0018] Figure 2 shows an example analysis by the criticality determination engine 110 to determine criticality values for registers of a logic-level circuit design. In the example of Figure 2, the criticality determination engine 110 accesses a circuit design shown in Figure 2 as the logic-level circuit design 210. The criticality determination engine 110 may access circuit designs in any suitable way, for example by loading from or accessing a memory, database, or any other data store at which a circuit design is stored.

[0019] The criticality determination engine 110 may access logic-level circuit designs for criticality determinations of elementary subparts, and a logic-level circuit design may refer to any circuit design that represents circuit elements at a logic level (as opposed to a physical layout or physical circuit design). As such, the logic-level circuit design 210 accessed by the criticality determination engine 110 may take the form of a gate-level circuit design, a register-transfer level (RTL) design (e.g., a synthesizable RTL design), or any other suitable format at which circuit elements are represented at a logical level.

[0020] The criticality determination engine 110 may analyze the logic-level circuit design 210 to identify any elementary subparts deemed as critical. Measures of criticality may be quantified by the criticality determination engine 110 in the analysis of the logic-level circuit design 210, for example as criticality values. In the example of Figure 2, the criticality determination engine 110 determines the criticality values 220 for registers (or any other suitable elementary subparts) of the logic-level circuit design 210, and the criticality values 220 may assess the degree to which a particular register (or failure thereof) impacts the logic-level circuit design 210. The greater the impact, the greater the criticality of the register, and the criticality determination engine 110 may determine a criticality value for the register to reflect such an impact in the circuit design. Quantification of criticality values for registers of a circuit design may allow the criticality determination engine 110 to assess which particular registers of the logic-level design 210 arestronger candidates for physical designs of increased reliability, noise immunity, and resiliency.

[0021] To assess criticality, the criticality determination engine 110 may determine criticality values that account for various factors by which elementary subparts impact circuit functionality, including both downstream and upstream in the signal propagation flow of circuit logic. As a continuing example provided herein, the criticality determination engine 110 may account for at least three (3) factors when assessing criticality of a given elementary subpart in a logic-level circuit design. These factors include an input flop factor, an input combinational logic factor, and an output flop factor. The criticality determination engine 110 may quantify each of these factors numerically through analysis of logic-level circuit designs, and each of these factors are described in turn.

[0022] In some implementations, the criticality determination engine 110 may bound determinations of criticality values (including contributing factors) to circuit subsections that surround a given elementary subpart. The criticality determination engine 110 may determine or select a circuit subsection that bounds the criticality value determination for a given elementary subpart. As such, the criticality determination engine 110 need not consider, process, or analyze the entire circuit design when computing a criticality value for the given elementary subpart. Doing so could be resource and time-consuming, and could overly account for circuit logic that may be distant from a given elementary subpart (whether distant by clock cycles in the propagation signal flow of a circuit design, by physical distance, by a number of intervening gates or other elementary subparts, or the like).

[0023] As a continuing example, the criticality determination engine 110 may limit determination of a criticality value for a given elementary subpart to a subsection of a circuit design comprised of subpart-to-subpart paths for the given elementary subpart (e.g., register-to-register paths from a given register for which a criticality value is being computed). As used herein, path distance from a given elementary subpart to a different elementary subpart (or other circuit location) may be counted or measured through a number of elementarysubparts in the path (including the endpoint elementary subpart). As such, the path distance between two directly linked registers would have a path distance of 1 (counting the endpoint register).

[0024] For a given elementary subpart, the criticality determination engine 110 may compute a criticality value (including underlying factor values) by considering only a portion of the circuit design that are within one elementary subpart from the given elementary subpart, e.g., within a path distance of 1 from the given elementary subpart. Such path distances may be counted and considered downstream or upstream in the signal propagation flow of the circuit design. As an example, the criticality determination engine 110 may determine the register-to-register paths that fan out from a given register for which a criticality value is being computed, and determine values for the input flop factor, the input combinational logic factor, and the output flop factor from the determined circuit subsection within a path distance of 1 (e.g., within a register-to-register distance) from the given register. Such circuit subsections may include any intervening combinational logic in the subpart-to-subpart paths. Various examples are presented herein to further illustrate these subsection features.

[0025] A continuing example is presented herein with circuit subsections for criticality value determinations limited to a path distance of 1. However, any suitable, predetermined, or configurable path distance value is contemplated herein from determination of criticality values and any underlying factor value. In some implementations, the criticality determination may weight different circuit subsections different in determining the criticality value for a given elementary subpart. For example, elementary subparts within a path distance of 1 from the given elementary subpart may be weighted with a first weight (e.g., 0.9) and elementary subparts with a path distance of 2 from the given elementary subpart may be weighted with a second weight (e.g., 0.1 ) in the criticality value determinations. Any suitable weighting scheme can be applied by the criticality determination engine 110 and is thus contemplated herein.

[0026] Turning to the various factors that the criticality determination engine 110 may account for, the input flop factor may account for the impact of otherelementary subparts that contribute to, impact, or otherwise affect (directly or indirectly) an input signal of a given elementary subpart. In that regard, the criticality determination engine 110 may determine the input flop factor as a function of (or otherwise based on) a number of other elementary subparts in the logic-level circuit design that affect to an input signal to the given elementary subpart. Impact or effect of other elementary subparts may refer to any signal generated (e.g., output) by another elementary subpart upon which the input signal of the given elementary subpart depends. Examples may thus include a direct output of another elementary subpart as the input for a given elementary subpart, outputs of elementary subparts that are inputs to combinational logic from which the input signal of the given elementary subpart depends, or combinations of both.

[0027] To illustrate input flop factor determinations, various circuit sections of the logic-level circuit design 210 are shown in Figure 2 as circuit sections211 and 212. In circuit section 211 of the logic-level circuit design 210, registers (implemented as flip-flops) are illustrated as registers A, B, C, D, and E as well as combinational logic in the circuit section 211. In circuit section212 of the logic-level circuit design 210, registers (implemented as flip flops) are illustrated as registers F, G, H, I, J, and K as well as combinational logic in the circuit section 212.

[0028] The criticality determination engine 110 may determine input flop factor values for each of the registers of the circuit sections 211 and 212. As seen in Figure 2, the output signal of register A may directly drive the input signal to registers B, C, and D. As such and under a configuration by the criticality determination engine 110 that presumes or sets fault contribution of each element of the logic-level circuit design 210 as contributing ‘x’ faults, then the criticality determination engine 110 may determine an input flop factor value for each of registers B, C, and D as ‘x’. This may be the case as only a single elementary subpart impacts the input signals of registers B, C, and D respectively.

[0029] For register E in Figure 2, the criticality determination engine 110 may determine an input flop factor value of ‘3x’, as three (3) elementary subpartsimpact the input signal of register E (in this case, register B, C and D). This may be the case in this specific example since the criticality determination engine 110 may limit computation of the input flop factor to elementary subparts within a subpart-to-subpart path distance of 1 from register E. In this case, registers B, C, and D are within a single register-to-register path distance from register E. Register A is a path distance of 2 from register E, and thus not considered from determination of the input flop factor for register E for implementations in which the criticality determination engine 110 limits criticality value determinations to within a path distance of 1 from a given elementary subpart.

[0030] In a consistent manner, the criticality determination engine 110 may determine input flop factor values for the registers depicted in circuit section 212. In this example, the criticality determination engine 110 may determine a respective input flop factor value of ‘x’ for registers G, H, I, and J and an input flop factor value of ‘2x’ for register K. In these examples, the criticality determination engine 11 determines the input flop factor as equal to a number of faults contributed by other elementary subparts to an input signal of a given elementary subpart, and this example is used with the criticality determination engine 110 configured to recognize that each element of a circuit design contributes a consistent ‘x’ number of faults. Any suitable function can be implemented or applied by the criticality determination engine 110 for input flop factor, other factor, and criticality value determinations.

[0031] Turning to a next factor, the input combinational logic factor may account for the impact of combinational logic that contributes to, impacts, or otherwise affects (directly or indirectly) an input signal of a given elementary subpart. Combinational logic may refer to basic logic gates, inverters, nonmemory logic elements, and the like. Any intervening logic or circuit elements between registers (or other elementary subparts) may be considered combinational logic by the criticality determination engine 110 in determination of input combinational logic factor values. As combinational logic may be used to affect or process signals between registers (or other elementary subparts),and the criticality determination engine 110 may quantify the effect of such combinational logic on a given elementary subpart.

[0032] The criticality determination engine 110 may determine the input combination logic factor as a function of (or otherwise based on) a number of logic gates that affect the input signal to the given elementary subpart. Impact or effect of logic gates may refer to any signal generated (e.g., output) by combinational logic upon which the input signal of a given elementary subpart depends. Examples may thus include a direct output of a logic gate as the input for a given elementary subpart, outputs of logic gates or combination logic that are inputs to combinational logic from which the input signal of the given elementary subpart depends, or combinations thereof. In some sense, the input combinational logic factor may consider a cone of logic that feeds into the input signal of a given elementary subpart, and each logic element in the cone may be accounted for in determination of the input combinational logic factor.

[0033] Example computations of the input combinational logic factor values for various registers of the logic-level circuit design 210 are provided through the example circuit sections 211 and 212 of Figure 2. As with prior examples, a configuration can be made by the criticality determination engine 110 that specifies, assumes, or otherwise sets (for purposes of criticality value determinations) that each element of the logic-level circuit design 210 contributes ‘x’ faults. In the example of Figure 2, the criticality determination engine 110 may determine an input combinational logic factor value for each of registers B, C, and D as ‘0’ as no combinational logic elements impact the input signals of registers B, C, and D respectively. For register E in Figure 2, the criticality determination engine 110 may determine an input combinational logic factor value of ‘4x’, as four (4) total logic elements impact the input signal of register E, the three (3) AND gates and the inverter.

[0034] In a consistent manner, the criticality determination engine 110 may determine input combinational logic factor values for the registers depicted in circuit section 212 of Figure 2 . In this example, the criticality determination engine 110 may determine a respective input combinational logic factor valueof ‘0’ for registers H, I, and J and an input combinational logic factor value of ‘x’ for register G (based on the one (1 ) inverter impacting the input signal of register G) as well as for register K (based on the one (1 ) AND gate impacting the input signal of register K).

[0035] As yet another example factor, the output flop factor may account for the impact of an output signal of an elementary subpart to the extent the output signal contributes to, impacts, or otherwise affects (directly or indirectly) an input signal of other downstream elementary subparts. In some sense, the output flop factor may be a complement to the input flop factor, instead measuring downstream impact whereas the input flop factor may measure the upstream impact to a given elementary subpart. The criticality determination engine 110 may determine the output flop factor for a given elementary subpart as a function of (or otherwise based on) a number of other elementary subparts in the logic-level circuit design with input signals that are affected by an output signal of the given elementary subpart. Impact or effect may refer to any input signal of other elementary subparts of a circuit design that the output signal of a given elementary subpart impacts, affects, or drives.

[0036] Example computations of the output flop factor values for various registers of the logic-level circuit design 210 are provided through the example circuit sections 211 and 212 of Figure 2. As with prior examples, the criticality determination engine 110 is configured to presume each element of the logiclevel circuit design 210 contributes ‘x’ faults. Accordingly, the criticality determination engine 110 may determine an output flop factor value for each of registers B, C, and D as ‘x’ as the output signals of registers B, C, and D respectively impact the input signal of register E. For register A in Figure 2, the criticality determination engine 110 may determine an output flop factor value of ‘3x’, as three (3) total registers are impacted by the output signal of register A (namely registers B, C, and D).

[0037] In a consistent manner, the criticality determination engine 110 may determine output flop factor values for the registers depicted in circuit section 212 of Figure 2 . In this example, the criticality determination engine 110 may determine a respective output flop logic factor value of ‘x’ for registers F andI, as the output signals of registers F and I affect the input signals of registers G and K respectively. Also in this example, the criticality determination engine 110 may determine an output flop factor value of ‘4x’ for register G, as the output signal of register G affects the input signals of four elementary subparts (in this case, registers H, I, J, and K).

[0038] Note that the criticality determination engine 110 may quantify the output flop factor based on the output of a given elementary subpart affecting various types of signals, including input signals to registers, latches, any state element, or any other elementary subpart. As another example, output flop factor determinations may account for an effect on system output signals. For example, if the output signal of register H drives an AND gate, and the AND gate drives a system output signal for the logic-level circuit design 210, the criticality determination engine 110 may determine an output flop factor value of ‘x’ for register H as the output signal of register H impacts a system output signal. A similar determination can be made for the output flop factor values of registers J and K respectively.

[0039] In any of the ways described herein, the criticality determination engine 110 may compute an input flop factor value, an input combinational logic factor value, and an output flop factor value for individual elementary subparts of a circuit design. Each of the different factors may quantify impact that a given elementary subpart has in a circuit design, and the criticality determination engine 110 may perform such factor value determinations in a selected subsection of an overall circuit design (e.g., within a path distance of 1 from an elementary subpart) to improve efficiency and accuracy. Then, the criticality determination engine 110 may determine a criticality value as a function of the determined factor values. In some implementations, the criticality determination engine 110 may determine a criticality value for a given elementary subpart as the sum of the determined factor values. The sum may be a weighted sum, and the criticality determination engine 110 may apply configurable weights to any of the computed factor values.

[0040] For the example in Figure 2, the criticality determination engines 110 may compute the following factor values and criticality values for registers ofthe circuit sections 211 and 212 of the logic-level circuit design 210. In the example tables below, the input signals of registers A and F may each be driven by a single register without intervening combinational logic (not shown in these circuit portions 211 and 212) and the output signals of registers E, H, J, and K may each directly drive a single register (not shown in these circuit portions 211 and 212).Table 1 : Criticality Factor and Value Determinations for Circuit Section 211Table 2: Criticality Factor and Value Determinations for Circuit Section 212In the examples above, the criticality determination engine 110 may determine criticality values 220 for registers of logic-level circuit design 210 as a sum of the determined input flop factor, input combinational logic factor, and output flop factor values. The greater the determined criticality value, the greater the quantified impact on the operation of the circuit design. As such, the criticality determination engine 110 may identify critical registers or other elementary subparts within a circuit design through the criticality determination technology described herein.

[0041] Note that in the examples above, the criticality determination engine 110 may assign a consistent value of ‘x’ faults attributable to each discreteelement of the logic-level circuit design 210. In such examples, registers, logic gates, and other circuit elements of the logic-level circuit design 210 may be weighted identically in criticality value determinations in terms of fault contribution. Various additions or alternatives are possible in criticality value determinations for elementary subparts of circuit designs.

[0042] For example, instead of assigning an identical ‘x’ fault contribution value for each separate element of a logic-level circuit design, the criticality determination engine 110 may assign an individual fault contribution value for each element of the logic-level circuit design 210. As an example, the assigned individual value may be equal to or a function of the number of transistors that are used to implement the element in the circuit design. Thus, instead of consistent ‘x’ value, the criticality determination engine 110 may compute factor values and criticality values based on the number of transistors of circuit elements that each factor accounts for. Such an assignment may flexibly account for the complexity of circuit elements in weighing fault contributions for criticality determinations.

[0043] Thus, the criticality determination engine 110 may determine the input flop factor is based on a number of transistors to implement the other registers in the logic-level circuit design 210 that affect to an input signal to a given elementary subpar. Likewise, the criticality determination engine 110 may determine the input combinational logic factor based on a number of transistors to implement the logic gates that affect the input signal to the given elementary subpart as well as determine the output flop factor based on a number of transistors to implement the other elementary subparts in the logiclevel circuit design with input signals that are affected by the output signal of the given register.

[0044] To illustrate such a feature, the criticality determination engine 110 may determine an input combinational logic factor value for register E of the circuit section 211 as a function (e.g., sum) of four (4) transistor values, the number of transistors to implement the inverter as well as the number of transistors to implement each of the three (3) AND gates that affect the input signal of register E. As another example, the criticality determination engine110 may determine an output flop factor value for register F as the number of transistors to implement register G in circuit section 212.

[0045] In any of the ways described herein, the criticality determination engine 110 may determine criticality values 220 for a logic-level circuit design 210. Through such computations and determined criticality values, the criticality determination engine 110 or physical design engine 112 may practically use and apply the criticality values 220. Various example applications are described herein.

[0046] In some implementations, the criticality determination engine 110 may identify critical registers from determined criticality values 220, for example doing so based on safety critical thresholds. A safety critical threshold may be any predetermined or configurable value by which classification of elementary subparts or other circuit elements can be performed. For example, the criticality determination engine 110 may identify a given elementary subpart of the logic-level circuit design 210 as a safety critical register responsive to a determination that the criticality value determined for the given elementary subpart exceeds the safety criticality threshold. The criticality determination engine 110 may access or apply multiple safety criticality thresholds, which may vary in value and can delineate classification tiers for elementary subparts of a circuit design.

[0047] In some implementations, the physical design engine 112 may set (e.g., specify or assign) a physical-level design for the elementary subparts in the logic-level circuit design 210 based on determined criticality values 220. For registers (or other elementary subparts) with higher criticality values (e.g., that exceed the safety criticality threshold), the physical design engine 112 may specify, design, or assign a physical design such registers with increased resiliency, fault tolerance, increased immunity, or any other suitable register characteristics. For registers with lower criticality values, the physical design engine 112 may set a physical-level design for such registers with reduced area consumption and lesser power dissipation. Through such features, the criticality determination technology of the present disclosure may improvecircuit designs by improving the efficiency of area, power, and fault resistant allocations in circuit designs.

[0048] For any of the features described herein, the criticality determination engine 110 or physical design engine 112 may support manufacture of circuit designs that are developed, revised, designed, or otherwise processed using criticality determinations a described herein. Any suitable circuit manufacture technology is contemplated herein in order to physically manufacture circuits designed using the criticality determination technology of the present disclosure.

[0049] As yet another feature of the present disclosure, the criticality determination engine 110 may support fault coverage analyses for elementary subparts. In some implementations, the criticality determination engine 110 may perform a coverage analysis for any given elementary subpart of a circuit design, doing so based on the other registers in the logic-level circuit design 210 with input signals that are affected by an output signal of the given elementary subpart. A coverage value for the given elementary subpart may be computed by the criticality determination engine 110 based on a ratio between a number of faults covered by the given elementary subpart and a total number of faults for the elementary subparts in the logic-level circuit design 210. Through such coverage analyses, the criticality determination engine 110 may assess the degree of fault coverage that a particular elementary subpart (or a set of elementary subparts) supports.

[0050] For example, the criticality determination engine 110 may assess fault coverage for a set of elementary subparts implemented with a 99% fault coverage physical implementation, and compare the fault coverage for such an implementation with other designs in which other registers are implemented with the 99% coverage physical implementation or other designs in which the set of elementary subparts is implemented with a 97% fault coverage physical implementation (or any other alternative implementation). Fault coverage analyses by the criticality determination engine 110 may account for the effect of input signals, combinational logic, and output signals. Such considerations may be particularly efficient as the criticalitydetermination engine 110 has already assessed the impact of such factors in the computation of values for the input flow factor, input combinational logic factor, and output flop factor. Through any such analyses as described herein, the criticality determination engine 110 may support efficient and robust analyses of circuit designs, giving increased flexibility and capability for circuit designers to weigh resources, space, and design trade-offs in circuit designs, e.g., when under safety-critical requirements for design of safety-critical embedded circuit systems.

[0051] Figure 3 shows an example of logic 300 that a system may implement to support criticality determinations for elementary subparts of circuit designs. For example, the computing system 100 may implement the logic 300 as hardware, executable instructions stored on a machine-readable medium, or as a combination of both. The computing system 100 may implement the logic 300 via the criticality determination engine 110 and the physical design engine 112, through which the computing system 100 may perform or execute the logic 300 as a method to support criticality determinations for elementary subparts of circuit designs. The following description of the logic 300 is provided using the criticality determination engine 110 and physical design engine 112 as examples. However, various other implementation options by systems are possible.

[0052] In implementing the logic 300, the criticality determination engine 110 may access a logic-level circuit design (302) and determine criticality values for elementary subparts in the logic-level circuit design (304), e.g., individual registers in the logic-level circuit design. As described herein, the criticality determination engine 110 may determine a criticality value for a given elementary subpart of the logic-level circuit design based on multiple factors, including an input flop factor, an input combinational logic factor, and an output flop factor. For a given elementary subpart, the input flop factor may be determined based on a number of other elementary subparts in the logic-level circuit design that affect to an input signal to the given elementary subpart, the input combinational logic factor may be determined based on a number of logic gates that affect the input signal to the given elementary subpart, andthe output flop factor may be determined based on a number of other elementary subparts in the logic-level circuit design with input signals that are affected by an output signal of the given elementary subpart.

[0053] In implementing the logic 300, the physical design engine 112 may set (e.g., select or specify) a physical-level design for the given elementary subpart in the logic-level circuit design based on the criticality value determined for the given elementary subpart, doing so in any of the ways described herein.

[0054] The logic 300 shown in Figure 3 provides an illustrative example by which a computing system 102 may support, implement, or provide capabilities for criticality determinations for elementary subparts of a circuit design. Additional or alternative steps in the logic 300 are contemplated herein, including according to any of the criticality determination technology described herein with regards to the criticality determination engine 110, physical design engine 112, or combinations of both.

[0055] Figure 4 shows an example of a computing system 400 that supports criticality determinations for elementary subparts of circuit designs. The computing system 400 may include a processor 410, which may take the form of a single or multiple processors. The processor(s) 410 may include a central processing unit (CPU), microprocessor, or any hardware device suitable for executing instructions stored on a machine-readable medium. The computing system 400 may include a machine-readable medium 420. The machine- readable medium 420 may take the form of any non-transitory electronic, magnetic, optical, or other physical storage device that stores executable instructions, such as the criticality determination instructions 422 and the physical design instructions 424 shown in Figure 4. As such, the machine- readable medium 420 may be, for example, Random Access Memory (RAM) such as a dynamic RAM (DRAM), flash memory, spin-transfer torque memory, an Electrically-Erasable Programmable Read-Only Memory (EEPROM), a storage drive, an optical disk, and the like.

[0056] The computing system 400 may execute instructions stored on the machine-readable medium 420 through the processor 410. Executing theinstructions (e.g., the criticality determination instructions 422 and / or the physical design instructions 424) may cause the computing system 400 to perform any of the criticality determination features described herein, including according to any of the features of the criticality determination engine 110, physical design engine 112, or combinations of both.

[0057] For example, execution of the criticality determination instructions 422 by the processor 410 may cause the computing system 400 to access a logic-level circuit design and determine criticality values for elementary subparts in the logic-level circuit design, e.g., individual registers in the logiclevel circuit design. Determination of a criticality value for a given elementary subpart of the logic-level circuit design may be based on multiple factors, including an input flop factor, an input combinational logic factor, and an output flop factor. For a given elementary subpart, the input flop factor may be determined based on a number of other elementary subparts in the logic-level circuit design that affect to an input signal to the given elementary subpart, the input combinational logic factor may be determined based on a number of logic gates that affect the input signal to the given elementary subpart, and the output flop factor may be determined based on a number of other elementary subparts in the logic-level circuit design with input signals that are affected by an output signal of the given elementary subpart.

[0058] Execution of the physical design instructions 424 by the processor 410 may cause the computing system 400 to set (e.g., select or specify) a physical-level design for the given elementary subpart in the logic-level circuit design based on the criticality value determined for the given elementary subpart.

[0059] Any additional or alternative criticality determination features as described herein may be implemented via the criticality determination instructions 422, physical design instructions 424, or a combination of both.

[0060] The systems, methods, devices, and logic described above, including the criticality determination engine 110 and physical design engine 112, may be implemented in many different ways in many different combinations of hardware, logic, circuitry, and executable instructions stored on a machine-readable medium. For example, the criticality determination engine 110, physical design engine 112, or combinations thereof, may include circuitry in a controller, a microprocessor, or an application specific integrated circuit (ASIC), or may be implemented with discrete logic or components, or a combination of other types of analog or digital circuitry, combined on a single integrated circuit or distributed among multiple integrated circuits. A product, such as a computer program product, may include a storage medium and machine-readable instructions stored on the medium, which when executed in an endpoint, computer system, or other device, cause the device to perform operations according to any of the description above, including according to any features of the criticality determination engine 110, physical design engine 112, or combinations thereof.

[0061] The processing capability of the systems, devices, and engines described herein, including the criticality determination engine 110 and physical design engine 112, may be distributed among multiple system components, such as among multiple processors and memories, optionally including multiple distributed processing systems or cloud / network elements. Parameters, databases, and other data structures may be separately stored and managed, may be incorporated into a single memory or database, may be logically and physically organized in many different ways, and may be implemented in many ways, including data structures such as linked lists, hash tables, or implicit storage mechanisms. Programs may be parts (e.g., subroutines) of a single program, separate programs, distributed across several memories and processors, or implemented in many different ways, such as in a library (e.g., a shared library).

[0062] While various examples have been described above, many more implementations are possible.

Claims

CLAIMS1 . A method comprising: by a computing system (100): accessing (302) a logic-level circuit design (210); determining (304) criticality values (220) for registers in the logic-level circuit design (210), wherein the criticality value (220) for a given register of the logic-level circuit design (210) is determined based on an input flop factor, an input combinational logic factor, and an output flop factor, wherein, for the given register of the logic-level circuit design (210): the input flop factor is based on a number of other registers in the logic-level circuit design (210) that affect to an input signal to the given register; the input combinational logic factor is based on a number of logic gates that affect the input signal to the given register; and the output flop factor is based on a number of other registers in the logic-level circuit design (210) with input signals that are affected by an output signal of the given register; and setting (306) a physical-level design for the given register in the logiclevel circuit design (210) based on the criticality value (220) determined for the given register.

2. The method of claim 1 , wherein the output flop factor is further based on a number of latches with input signals that are affected by an output signal of the given register, a number of system output signals that are affected by the output signal of the given register, or a combination of both.

3. The method of claim 1 or 2, wherein, for the given register of the logic-level circuit design (210):the input flop factor is further based on a number of transistors to implement the other registers in the logic-level circuit design (210) that affect to an input signal to the given register, the input combinational logic factor is further based on a number of transistors to implement the logic gates that affect the input signal to the given register, the output flop factor is further based on a number of transistors to implement the other registers in the logic-level circuit design (210) with input signals that are affected by the output signal of the given register, or any combination thereof.

4. The method of any of claim 1-3, wherein, for the given register of the logic-level circuit design (210): the input flop factor, the input combinational logic factor, the output flop factor, or any combination thereof are limited to a subsection of the logic-level circuit design (210) comprised of register-to-register paths for the given register.

5. The method of any of claims 1-4, further comprising performing a coverage analysis for the given register based on the other registers in the logic-level circuit design (210) with input signals that are affected by an output signal of the given register.

6. The method of claim 5, wherein a coverage value for the given register is computed based on a ratio between a number of faults covered by the given register and a total number of faults for the registers in the logiclevel circuit design (210).

7. The method of any of claims 1-6, further comprising identifying the given register of the logic-level circuit design (210) as a safety critical register responsive to a determination that the criticality value (220) determined for the given register exceeds a safety criticality threshold.

8. A system comprising: a processor (410); and a non-transitory machine-readable medium (420) storing instructions (422, 424) that, when executed by the processor, cause a computing system (100, 400) to: access a logic-level circuit design (210); determine criticality values (220) for registers in the logic-level circuit design (210), wherein the criticality value (220) for a given register of the logic-level circuit design (210) is determined based on an input flop factor, an input combinational logic factor, and an output flop factor, wherein, for the given register of the logic-level circuit design (210): the input flop factor is based on a number of other registers in the logic-level circuit design (210) that affect to an input signal to the given register; the input combinational logic factor is based on a number of logic gates that affect the input signal to the given register; and the output flop factor is based on a number of other registers in the logic-level circuit design (210) with input signals that are affected by an output signal of the given register; and set a physical-level design for the given register in the logiclevel circuit design (210) based on the criticality value (220) determined for the given register.

9. The system of claim 8, wherein the output flop factor is further based on a number of latches with input signals that are affected by an output signal of the given register, a number of system output signals that are affected by the output signal of the given register, or a combination of both.

10. The system of claim 8 or 9, wherein, for the given register of the logiclevel circuit design (210): the input flop factor is further based on a number of transistors to implement the other registers in the logic-level circuit design (210) that affect to an input signal to the given register, the input combinational logic factor is further based on a number of transistors to implement the logic gates that affect the input signal to the given register, the output flop factor is further based on a number of transistors to implement the other registers in the logic-level circuit design (210) with input signals that are affected by the output signal of the given register, or any combination thereof.11 . The system of any of claim 8-10, wherein, for the given register of the logic-level circuit design (210): the input flop factor, the input combinational logic factor, the output flop factor, or any combination thereof are limited to a subsection of the logic-level circuit design (210) comprised of register-to-register paths for the given register.

12. The system of any of claims 8-11 , wherein the instructions (422, 424), when executed, further cause the computing system (100, 400) to perform a coverage analysis for the given register based on the other registers in the logic-level circuit design (210) with input signals that are affected by an output signal of the given register.

13. The system of claim 12, wherein a coverage value for the given register is computed based on a ratio between a number of faults covered by the given register and a total number of faults for the registers in the logiclevel circuit design (210).

14. The system of any of claims 8-13, wherein the instructions (422, 424), when executed, further cause the computing system (100, 400) to identify the given register of the logic-level circuit design (210) as a safety critical register responsive to a determination that the criticality value (220) determined for the given register exceeds a safety criticality threshold.

15. A non-transitory machine-readable medium (420) storing instructions (422, 424) that, when executed by a processor (410), cause a computing system (100, 400) to perform a method according to any of claims 1-7.

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