Through silicon vias

Abstract

Herein is provided an apparatus, comprising a silicon layer (100), and a spike (103) through the silicon layer (100) to provide an electric feedthrough (104) for a microelectromechanical systems, MEMS, resonator Herein is further provided a method of manufacturing said apparatus.

Description

[0001] THROUGH SILICON VIAS

[0002] TECHNICAL FIELD

[0003] The present disclosure generally relates to the field of semiconductors and semiconductor chips. The disclosure relates particularly, though not exclusively, to through silicon vias.

[0004] BACKGROUND

[0005] This section illustrates useful background information without admission of any technique described herein representative of the state of the art.

[0006] Typically, through silicon vias, TSVs are structures that reach through the cap wafer of a bonded resonator package. TSVs enable electrical contact from outside the package to a resonator device, which is typically inside the bonded package.

[0007] There are various manners to provide through silicon vias. Typically, metals are needed to enhance the electrical contact and to ensure the functionality of the packaged resonator. Providing reliable metal-silicon interface of the through silicon vias typically requires thermal annealing in significantly elevated temperatures.

[0008] The bonded resonator packages are typically sensitive to temperature and exposing them to elevated temperatures should typically be avoided. Exposing the packages to too high temperatures may endanger device performance and generate frequency shifts. These frequency shifts are typically not easily reduced, since the conventional means to reduce such shifts, e.g. ion-beam trimming, is not a viable option after the resonator has already been packaged.

[0009] SUMMARY

[0010] The appended claims define the scope of protection. Any examples and technical descriptions of apparatuses, products and / or methods in the description and / or drawings not covered by the claims are presented not as embodiments of the invention but as background art or examples useful for understanding the invention.

[0011] It is an object of certain embodiments of the present disclosure to provide a scheme to avoid post-packaging thermal treatments for resonators or at least to provide an alternative to existing technology. Accordingly, certain disclosed embodiments provide for an ingenious apparatus comprising a through silicon via, TSV, and an ingenious method for manufacturing said apparatus.

[0012] According to a first example aspect of the present disclosure there is provided an apparatus, comprising a silicon layer, and a spike through the silicon layer to provide an electric feedthrough for a microelectromechanical systems, MEMS, resonator.

[0013] In certain embodiments the spike is of metal. In certain embodiments, the spike is of metal, such as of aluminium, Al. In certain preferred embodiments, the spike is of aluminium, Al.

[0014] In certain embodiments, the silicon layer comprises a doped region. In certain embodiments, the silicon layer comprises a doped region, preferably a locally doped region. In certain preferred embodiments, the silicon layer comprises a locally doped region. In certain embodiments, the apparatus further comprises undoped silicon.

[0015] In certain embodiments, the doped region comprises p-type doping. In certain embodiments, the doped region comprises p-type doping, preferably p++ doping. In certain preferred embodiments, the doped region comprises p++ doping. In certain embodiments, the doping comprises boron doping. In certain embodiments, the doping comprises gallium doping.

[0016] In certain alternative embodiments, the doped region comprises n-type doping. In certain embodiments, the doped region comprises n-type doping, preferably n++ doping. In certain preferred embodiments, the doped region comprises n++ doping. In certain embodiments, the doping comprises phosphorous doping. In certain embodiments, the doping comprises arsenic doping.

[0017] In certain embodiments, the apparatus comprises a metal deposit on the silicon layer. In certain embodiments, the apparatus comprises a metal deposit, such as an aluminium deposit on the silicon layer. In certain preferred embodiments, the apparatus comprises an aluminium deposit on the silicon layer. In certain preferred embodiments, the metal deposit is on the doped region of the silicon layer.

[0018] In certain embodiments, the metal deposit, such as the aluminium deposit is configured to form the spike. In certain embodiments, the metal deposit, such as the aluminium deposit is configured to form the spike upon annealing. In certain embodiments, the metal deposit, such as the aluminium deposit is configured to form the spike upon annealing in elevated temperature. In certain embodiments, said elevated temperature comprises temperatures above 300 °C, preferably above 400 °C. In certain embodiments, the metal deposit, such as the aluminium deposit is configured to form the spike via diffusion. In certain embodiments, the metal deposit, such as the aluminium deposit, is configured to diffuse into the doped region of the silicon layer. In certain embodiments, the metal deposit, such as the aluminium deposit, is configured to diffuse through the doped region of the silicon layer. In certain embodiments, the metal deposit, such as the aluminium deposit, is configured to diffuse through the doped region of the silicon layer towards undoped silicon.

[0019] In certain embodiments, the apparatus comprises a first wafer and a second wafer bonded together to form a package. In certain embodiments, the first wafer is a cap wafer comprising the spike. In certain embodiments, the second wafer is a device wafer comprising the microelectromechanical systems, MEMS, resonator.

[0020] In certain alternative embodiments, the first wafer is a device wafer comprising a microelectromechanical systems, MEMS, resonator. In certain embodiments, the apparatus comprises the first wafer and the second wafer bonded together to form a dual resonator package.

[0021] In certain embodiments, the apparatus comprises the spike through the silicon layer to provide the electric feedthrough using through silicon via for a microelectromechanical systems, MEMS, resonator. In certain embodiments, the apparatus comprises an electric feedthrough using a through silicon via on an opposite side of the silicon layer in comparison to the doped region of the silicon layer to expose the spike. In certain embodiments, the through silicon via is a silicon-based through silicon via.

[0022] In certain embodiments, the apparatus further comprises metallization. In certain embodiments, the apparatus comprises metallization to provide electrical contact to the electric feedthrough to the MEMS resonator of the second wafer. In certain embodiments, the metallization is of gold.

[0023] In certain embodiments, the MEMS resonator is adapted to resonate in an in-plane resonance mode. In certain embodiments, the MEMS resonator is adapted to resonate in a length extensional resonance mode. In certain embodiments, the MEMS resonator is adapted to resonate in an in-plane length extensional resonance mode. In certain alternative embodiments, the MEMS resonator is adapted to resonate in an out of plane resonance mode.

[0024] In certain embodiments, the MEMS resonator is adapted to resonate in a Lamb wave resonance mode. In certain embodiments, the MEMS resonator is adapted to resonate in a contour resonance mode. In certain embodiments, the MEMS resonator is adapted to resonate in a flexural resonance mode. In certain embodiments, the MEMS resonator is a beam resonator. In certain embodiments, the MEMS resonator is a stacked beam resonator.

[0025] In certain embodiments, the apparatus comprises a hermetical seal for the MEMS resonator within the package.

[0026] According to a second example aspect of the invention there is provided a method for manufacturing the apparatus according to the first aspect, the method comprising depositing a metal, such as aluminium, on a silicon layer, and annealing the apparatus in elevated temperature to initiate a spiking effect to form a spike.

[0027] In certain embodiments, the method further comprises doping a region of the silicon layer, preferably locally doping a region of the silicon layer. In certain preferred embodiments, the method comprises locally doping the region of the silicon layer.

[0028] In certain embodiments, the method comprises doping the region of the silicon layer using p-type doping. In certain embodiments, the method comprises doping the region of the silicon layer using p-type doping, preferably p++ doping. In certain preferred embodiments, the method comprises doping the region of the silicon layer using p++ type doping. In certain embodiments, the method comprises doping using boron.

[0029] In certain embodiments, the method comprises depositing a metal, such as aluminium on the silicon layer. In certain preferred embodiments, the method comprises depositing aluminium on the silicon layer.

[0030] In certain embodiments, the method comprises forming the spike using the metal deposit, such as aluminium. In certain embodiments, the method comprises forming the spike using the metal deposit, such as aluminium, upon annealing. In certain embodiments, the method comprises forming the spike using the metal deposit, such as aluminium, upon annealing in elevated temperature. In certain embodiments, the method comprises forming the spike using the metal deposit, such as aluminium, upon annealing in elevated temperature by the spiking effect.

[0031] In certain embodiments, said annealing is performed prior to bonding. In certain embodiments, said annealing in elevated temperature comprises elevating the temperature to above 300 °C, preferably above 400 °C. In certain embodiments, said spiking effect is an Al-spiking effect.

[0032] In certain embodiments, the method comprises forming a spike through the doped region of the silicon layer towards undoped silicon. In certain embodiments, the method comprises forming the spike using the metal deposit, such as aluminium, via diffusion. In certain embodiments, the method comprises diffusing the metal deposit into the doped region of the silicon layer. In certain embodiments, the method comprises diffusing the metal deposit through the doped region of the silicon layer. In certain embodiments, the method comprises diffusing the metal deposit through the doped region of the silicon layer towards undoped silicon.

[0033] In certain embodiments, the method further comprises etching an opposite side of the silicon layer in comparison to the doped region of the silicon layer to expose the spike. In certain embodiments, the method further comprises etching an opposite side of the silicon layer in comparison to the doped region of the silicon layer to expose the spike to provide an electric feedthrough (using a TSV). In certain embodiments, said etching comprises deep reactive ion etching, DRIE. In certain embodiments, the method comprises exposing the spike from the opposite side of the silicon layer in comparison to the doped region of the silicon layer.

[0034] In certain embodiments, the method further comprises thinning the opposite side of the silicon layer in comparison to the doped region of the silicon layer prior to said etching.

[0035] In certain embodiments, the method comprises bonding a first wafer and a second wafer to form a package. In certain embodiments, the first wafer is a cap wafer comprising the spike. In certain embodiments, the second wafer is a device wafer comprising the microelectromechanical systems, MEMS, resonator.

[0036] In certain embodiments, the first cap wafer is a wafer substrate. In certain embodiments, the second wafer is a wafer substrate. In certain embodiments, the first wafer is a silicon wafer. In certain embodiments, the second wafer is a silicon wafer. In certain embodiments, the second wafer is a silicon on insulator, SOI, wafer.

[0037] In certain embodiments, the method comprises bonding the first wafer and the second wafer via thermocompression bonding. In certain embodiments, the method comprises bonding the first wafer and the second wafer via Au-Au thermocompression bonding. In certain embodiments, the method comprises bonding the first wafer and the second wafer via eutectic bonding, or flip chip bonding. In certain alternative embodiments, the method comprises bonding the first wafer and the second wafer via glass frit bonding, anodic bonding, or adhesive bonding.

[0038] In certain embodiments, the method comprises providing a through silicon via on a silicon body of the first wafer. In certain embodiments, the method comprises providing a silicon- based through silicon vias.

[0039] In certain embodiments, the method comprises providing a hermetical sealing for the MEMS resonator within the package.

[0040] In certain embodiments, the method further comprises providing metallization. In certain embodiments, the method further comprises providing metallization to provide electrical contact to the electric feedthrough. In certain embodiments, the method comprises providing metallization to provide electrical contact to the electric feedthrough, wherein the metallization is of gold. In certain embodiments, the method comprises providing the metallization on the opposite side of the silicon layer in comparison to the doped region of the silicon layer.

[0041] Different non-binding example aspects and embodiments have been illustrated in the foregoing. The embodiments in the foregoing are used merely to explain selected aspects or steps that may be utilized in different implementations. Some embodiments may be presented only with reference to certain example aspects. It should be appreciated that corresponding embodiments may apply to other example aspects as well. In particular, the embodiments described in the context of the first aspect are applicable to each further aspect. Any appropriate combinations of the embodiments may be formed.

[0042] BRIEF DESCRIPTION OF THE FIGURES

[0043] Some example embodiments will be described with reference to the accompanying figures, in which:

[0044] Fig. 1a schematically shows a step of manufacturing an apparatus according to an example embodiment;

[0045] Fig. 1 b schematically shows another step of manufacturing an apparatus according to an example embodiment;

[0046] Fig. 1 c schematically shows yet another step of manufacturing an apparatus according to an example embodiment; Fig. 1d schematically shows yet another step of manufacturing an apparatus according to an example embodiment;

[0047] Fig. 1e schematically shows yet another step of manufacturing an apparatus according to an example embodiment; and

[0048] Fig. 1f schematically shows yet another step of manufacturing an apparatus according to an example embodiment.

[0049] DETAILED DESCRIPTION

[0050] In the following description, like reference signs denote like elements or steps.

[0051] Fig. 1 a-1 f show steps of manufacturing an apparatus according to an example embodiment.

[0052] Fig. 1 a shows a step of manufacturing an apparatus according to an example embodiment. The apparatus comprises a silicon layer 100. In certain embodiments, the silicon layer 100 comprises a doped region 101. In certain preferred embodiments, the silicon layer 100 comprises a locally doped region 101. Locally doping the silicon wafer enables improving the conductivity of the doped region. In certain preferable embodiments, the doped region 101 comprises p++ doping.

[0053] Fig. 1 b shows another step of manufacturing an apparatus according to an example embodiment. In certain embodiments, the apparatus comprises a metal deposit, such as an aluminium deposit 102 on the silicon layer 100. In certain preferred embodiments, the metal deposit 102 is on the doped region 102 of the silicon layer.

[0054] Fig. 1 c shows yet another step of manufacturing an apparatus according to an example embodiment. In certain embodiments, the metal deposit, such as the aluminium deposit 102 is configured to form the spike 103 upon annealing in elevated temperature. In certain embodiments, said annealing is performed prior to bonding wafers together to form a package. In certain embodiments, said annealing in elevated temperature comprises elevating the temperature to above 300 °C, preferably above 400 °C.

[0055] As used herein, the term “package” refers to two wafers bonded together, one of which being the device wafer and the other being the cap wafer. Typically, a package comprises a resonator within.

[0056] In certain embodiments, the spike 103 is formed using the metal deposit, such as deposited aluminium 102 by a spiking effect. In certain embodiments, the spiking effect is an Al-spiking effect. In certain embodiments, the metal deposit, such as aluminium deposit 102 extends towards undoped silicon through the doped region 101 of the silicon layer 100. Diffusion drives the spiking effect.

[0057] As used herein, the term “spike” refers to an approximate form that the metal accepts as it diffuses through the doped region of the silicon layer. The term “spike” is not limited to any definite shape, or size. Furthermore, the term “spike” is not limited to one “spike” but may comprise a plurality of “spikes”, or even an undefinable form comprising several “spikes” merged with the adjacent “spikes”. Accordingly, by way of an example, a conventional feedthrough etched into (layer(s) of) the semiconductor apparatus should not be understood as “a spike”, as used herein. In certain embodiments, the spike of the present disclosure is a spike formed by a spiking effect. In certain embodiments, the spike is originated from a spiking effect. In certain embodiments, the spike is a spiking effect generated spike. In certain embodiments, the spike is a non-etched spike (configured to reach through relevant layer(s)). In certain embodiments, the spike is a spike formed by annealing (annealed spike, annealing spike).

[0058] The spiking effect is typically a harmful phenomenon that is avoided in semiconductor manufacturing. Herein the inventors have found that the typically harmful phenomenon of spiking effect can be used to provide an electric feedthrough (the spike) for the MEMS resonator. In certain embodiments, the spike is an intentionally formed spike (formed by spiking effect intentionally). In certain embodiments, the spike is configured to provide an electrical feedthrough (to the MEMS resonator, between two wafers of the package, to both wafers of the package). In certain embodiments, the spike is configured to provide an electrical feedthrough to the cap wafer and to the device water of the package.

[0059] Accordingly, the method for manufacturing the apparatus comprises depositing a metal, such as aluminium, on a silicon layer; and annealing the apparatus in elevated temperature to initiate the spiking effect to form the spike.

[0060] Fig. 1d shows yet another step of manufacturing an apparatus according to an example embodiment. In certain embodiments, the apparatus comprises a first wafer (silicon layer 100) and a second wafer 120 bonded together to form a package. In certain embodiments, the first wafer and the second wafer are bonded using bonding protrusion or protrusions 110. In certain embodiments, the bonding protrusion or protrusions 110 separate adjacent MEMS resonator devices from each other. In certain embodiments, the bonding protrusion 110 circulates the MEMS resonator device. In certain embodiments, the bonding protrusion or protrusions 110 are of gold.

[0061] In certain embodiments, a cavity (gap) 130 is formed within the bonded package. In certain embodiments, the cavity 130 is formed in between the first wafer and the second wafer. In certain embodiments, the cavity 130 is in vacuum. In certain embodiments, the apparatus comprises a hermetical seal for the MEMS resonator within the package.

[0062] In certain embodiments, the first wafer is a cap wafer comprising the spike 103. In certain embodiments, the first wafer further comprises the doped region 101. In certain embodiments, the second wafer 120 is a device wafer comprising the microelectromechanical systems, MEMS, resonator (not shown). In certain embodiments, the MEMS resonator is adapted to resonate in an in-plane length extensional resonance mode.

[0063] Fig. 1 e shows yet another step of manufacturing an apparatus according to an example embodiment. In certain embodiments, the apparatus comprises the electric feedthrough 104 using the through silicon via on an opposite side of the silicon layer 100 in comparison to the doped region 101 of the silicon layer.

[0064] In certain embodiments, the electric feedthrough 104 is provided using a through silicon via. In certain embodiments, the through silicon via is in a form of a hole to expose the spike 103. In certain embodiments, the through silicon via is formed by etching. In certain embodiments, the through silicon via is a silicon-based through silicon via.

[0065] In certain embodiments, the TSV is provided by etching the opposite side of the silicon layer 100 in comparison to the doped region 101 of the silicon layer to expose the spike 103 to provide the electric feedthrough 104. In certain embodiments, said etching comprises deep reactive ion etching, DRIE. In certain embodiments, the spike 103 formed of the metal deposit 102 is exposed at etching. Said exposing the spike 103 enables readily using the spike 103 as an electrical contact to provide electric feedthrough to the MEMS resonator of the second wafer.

[0066] In certain embodiments, the silicon layer 100 is thinned on the opposite side of the silicon layer 100 in comparison to the doped region 101 of the silicon layer prior to said etching. Accordingly, the apparatus comprises the silicon layer 100, and the spike 103 through the silicon layer 100 to provide an electric feedthrough 104 for the microelectromechanical systems, MEMS, resonator.

[0067] Fig. 1f shows yet another step of manufacturing an apparatus according to an example embodiment. Fig. 1f shows an example of utilizing the readily exposed spike 103 as electrical metal-metal contact interface. The readily exposed spike 103 enables providing electric feedthrough 104 to the MEMS resonator of the second wafer.

[0068] In certain embodiments, the apparatus comprises metallization 105 on the opposite side of the silicon layer 100 in comparison to the doped region 101 of the silicon layer to provide electrical contact to the electric feedthrough 104 to the MEMS resonator of the second wafer 120. In certain embodiments, the metallization 105 is of gold.

[0069] In certain embodiments, the electrical contact is provided to the metallization 105. In certain embodiments, the electrical contact is provided using the electric feedthrough 104 through the first wafer (silicon layer 100) to the second wafer 120. In certain embodiments, the electrical contact is provided using the through silicon via. In certain embodiments, the electric feedthrough 104 is configured to provide contact to the spike 103 (formed by a spiking effect).

[0070] In certain embodiments, the electrical contact is provided using the electric feedthrough 104 through the first wafer (silicon layer 100) to the spike 103. In certain embodiments, the electrical contact is provided using the through silicon via to reach the spike 103. In certain embodiments, the through silicon via is etched onto the top surface of the silicon layer 100 reaching the spike 103.

[0071] In certain embodiments, the electrical contact is provided using the spike 103 to the first wafer and the second wafer. In certain embodiments, the spike 103 is configured to provide an electrical feedthrough for the apparatus (for the MEMS resonator). In certain embodiments, electrical contact is provided via the spike 103 to (and from) outside of the packaging (of the MEMS resonator).

[0072] In certain embodiments, the metallization 105 is arranged on the opposite side of the silicon layer 100 than the spike 103 (and than the metal deposit 102). The spike eventually reaches (at least partly) through the silicon layer 100 due to the spiking effect, but the spike 103 formation starts from one side of the silicon layer 100 (wherein the metal deposit 102 is provided). In certain embodiments, the metal deposit 102 is arranged inside the packaging of the MEMS resonator.

[0073] In certain embodiments, the spike 103 formed by a spiking effect propagates (diffuses, extends) into the silicon layer 100 towards the outside of the packaging. In certain embodiments, the spike 103 formed by a spiking effect propagates (diffuses, extends) into the silicon layer 100 from the inside of the packaging and towards the outside of the packaging. In certain embodiments, the spike 103 formed by a spiking effect propagates into the silicon layer 100 towards the doped region 101. In certain embodiments, the spike 103 formed by a spiking effect propagates into the silicon layer 100 towards the metallization 105.

[0074] In certain embodiments, the metallization 105 is deposited on the outside of the packaging. In certain embodiments, the metallization 105 is deposited on the top surface of the silicon layer 100. In certain embodiments, the metallization 105 is configured to reach the spike 103. In certain embodiments, the apparatus comprises metallization 105 in contact with the spike 103 (to provide electrical feedthrough or electrical contact). In certain embodiments, the metallization 105 and the spike 103 are configured to provide an electrical metal-metal contact interface (to provide electrical contact for the MEMS resonator). In certain embodiments, the electrical contact is formed from the metal deposit 102 using the spike 103 to the metallization 105 on the opposing side of the silicon layer 100.

[0075] In certain embodiments, the apparatus further comprises a redistribution layer (not shown). In certain embodiments, the redistribution layer is deposited on the metal deposit 102 of the first wafer. In certain embodiments, the redistribution layer is of metal. In certain embodiments, the redistribution layer is deposited via metallization. In certain embodiments, the redistribution layer provides electrical contact in the first wafer from the electrical feedthrough 104 to the points where the first wafer is connected to the device wafer.

[0076] Without limiting the scope and the interpretation of the patent claims, certain technical effects of one or more of the example embodiments disclosed herein are listed in the following. A technical effect of the invention is providing reliable, low resistance electric feedthrough using through silicon vias without exceeding the thermal budget requirements for the product. Any thermal treatments needed are provided already before the bonding. The post-bonding thermal treatments are typically harmful to the resonators within the packaging. A further technical effect is providing packaged MEMS resonators without frequency shifts which typically originate from thermal treatments after bonding. A further technical effect is providing electric feedthroughs using TSVs for wafer level packaged (WLP) resonators.

[0077] A further technical effect is avoiding post-packaging thermal treatments. The method according to the second aspect enables that all thermal treatments needed to provide reliable electric feedthroughs using TSVs to be performed prior to bonding. A further technical effect is providing a method for providing TSVs that is compatible with other typical silicon processing steps of semiconductor manufacturing.

[0078] Various embodiments have been presented. It should be appreciated that in this document, words comprise, include, and contain are each used as open-ended expressions with no intended exclusivity.

[0079] The foregoing description has provided by way of non-limiting examples of particular implementations and embodiments a full and informative description of the best mode presently contemplated by the inventors for carrying out the invention. It is however clear to a person skilled in the art that the invention is not restricted to details of the embodiments presented in the foregoing, but that it can be implemented in other embodiments using equivalent means or in different combinations of embodiments without deviating from the characteristics of the invention.

[0080] Furthermore, some of the features of the afore-disclosed example embodiments may be used to advantage without the corresponding use of other features. As such, the foregoing description shall be considered as merely illustrative of the principles of the present invention, and not in limitation thereof. Hence, the scope of the invention is only restricted by the appended patent claims.

Claims

CLAIMS1. An apparatus, comprising a silicon layer (100); and a spike (103) through the silicon layer (100) to provide an electric feedthrough (104) for a microelectromechanical systems, MEMS, resonator.

2. The apparatus of claim 1 , wherein the spike (103) is of metal, such as of aluminium, Al.

3. The apparatus of claim 1 or 2, wherein the silicon layer (100) comprises a doped region (101 ), preferably a locally doped region.

4. The apparatus of claim 3, wherein the doped region (101 ) comprises p-type doping, preferably p++ doping.

5. The apparatus of any preceding claim, comprising a metal deposit (102), such as an aluminium deposit, on the silicon layer (100).

6. The apparatus of any preceding claim, comprising a first wafer and a second wafer (120) bonded together to form a package.

7. The apparatus of claim 6, wherein the first wafer is a cap wafer comprising the spike (103).

8. The apparatus of claim 6 or 7, wherein the second wafer (120) is a device wafer comprising the microelectromechanical systems, MEMS, resonator.

9. The apparatus of any claim 6-8, comprising metallization (105) to provide electrical contact to the electric feedthrough (104) to the MEMS resonator of the second wafer.

10. A method of manufacturing the apparatus of claim 1 , the method comprising: depositing a metal (102), such as aluminium, on a silicon layer (100); and annealing the apparatus in elevated temperature to initiate a spiking effect to form a spike (103).11 . The method of claim 10, further comprising doping a region (101 ) of the silicon layer (100), preferably locally doping a region (101) of the silicon layer (100).

12. The method of claim 11 , further comprising etching an opposite side of the silicon layer (100) in comparison to the doped region (101) of the silicon layer (100) to expose the spike (103).

13. The method of any claim 10-12, further comprising providing metallization (105) to provide electrical contact to an electric feedthrough (104).

14. The method of any claim 10-13, wherein said annealing is performed prior to bonding.

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