A method for manufacturing a MEMS infrared detector wafer

Abstract

The application discloses a preparation method of a MEMS infrared detector wafer and relates to the technical field of semiconductor wafer preparation. The preparation method comprises the following steps: depositing a seed layer on a readout circuit wafer; performing photolithography etching treatment on the seed layer by using a photolithography etching process to reserve the seed layer in the area where a solder ring is located; forming a polyimide layer on the top surface of the readout circuit wafer and the circumferential side of the seed layer, and obtaining a MEMS structure deposited on the surface of the readout circuit wafer through solidification treatment; exposing part of the seed layer and depositing to form a solder ring by using a photolithography etching process; exposing the pad structure of the readout circuit wafer by using a photolithography etching process, and obtaining a MEMS infrared detector wafer after sequentially performing electrical testing and adhesive removal treatment. The preparation method can avoid cavity pollution caused by the deposition of the seed layer on the organic sacrificial layer, reduce the manufacturing cost, improve the process efficiency, and prevent the test pads from being polluted and corroded in the processing process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor wafer fabrication technology, and specifically to a method for fabricating a MEMS (Micro-Electro-Mechanical Systems) infrared detector wafer. Background Technology

[0002] In the wafer-level packaging process of uncooled infrared detectors, it is typically necessary to form a MEMS infrared detection structure on the readout circuit wafer and build a solder ring structure for vacuum packaging on its surface. In existing technologies, the fabrication process of a MEMS infrared detector wafer generally includes: coating a first layer of polyimide on top of the readout circuit wafer and curing it at high temperature as a protective or sacrificial layer; then fabricating the infrared detector MEMS structure; subsequently, opening the test pads for electrical testing using photolithography and etching processes; then coating a second layer of polyimide and curing it, forming a solder ring trench in the polyimide layer using photolithography and etching to expose the substrate; forming a metal seed layer in this trench using physical vapor deposition, and forming a solder ring structure on the seed layer using photolithography and electroplating processes; finally, obtaining the MEMS infrared detector wafer by releasing the sacrificial layer.

[0003] However, the above-mentioned existing technical solutions have at least the following shortcomings: the test pads are opened at an early stage, making them susceptible to contamination, oxidation, or corrosion during subsequent wet processes, electroplating, and plasma treatment, affecting the reliability of subsequent electrical tests; the seed layer is formed by sputtering deposition on the surface of organic polyimide, and polyimide is prone to backsplashing or escaping during sputtering, thereby contaminating the deposition cavity and reducing the adhesion and uniformity of the seed layer; this process requires two polyimide coating and curing processes, which not only increases the complexity of the process and manufacturing costs, but also reduces production efficiency.

[0004] Therefore, there is an urgent need to provide a new method for fabricating MEMS infrared detector wafers, which can solve the problems of easy contamination of test pads, unclean seed layer deposition environment, complex process flow and high cost in the existing technology, while ensuring high-precision alignment of MEMS structure and solder ring and hermetic sealing performance. Summary of the Invention

[0005] One objective of this invention is to provide a method for fabricating MEMS infrared detector wafers, which solves the technical problems in the prior art, such as the test pads being easily contaminated and corroded due to early opening, the seed layer being easily contaminated and having insufficient adhesion due to deposition on organic layers such as polyimide, and the need for multiple polyimide processes resulting in complex processes, high costs and low efficiency.

[0006] Another objective of this invention is to further improve the compatibility between the MEMS structure, the solder ring, and the substrate, as well as the overall packaging reliability.

[0007] According to the purpose of this invention, a method for fabricating a MEMS infrared detector wafer is provided, comprising the following steps: A seed layer is deposited on a readout circuit wafer, the readout circuit wafer including a pad structure; The seed layer is photolithographically etched to preserve the seed layer in the area where the solder ring is located; A polyimide layer is formed on the top surface of the readout circuit wafer and on the periphery of the seed layer, and a MEMS structure deposited on the surface of the readout circuit wafer is obtained by curing. The photolithography etching process is used to expose a portion of the seed layer, and a solder ring is deposited on the exposed seed layer; The photolithography etching process is used to expose the pad structure of the readout circuit wafer, and after electrical testing and resist removal are performed in sequence, the MEMS infrared detector wafer is prepared.

[0008] Optionally, prior to the step of exposing a portion of the seed layer using the photolithography etching process and depositing a solder ring on the exposed seed layer, the method further includes: A first photoresist is coated on the polyimide layer and the surface of the MEMS structure.

[0009] Optionally, the step of exposing the pad structure of the readout circuit wafer using the photolithography etching process further includes: Remove the first photoresist; A second photoresist is coated on the polyimide layer, the solder ring, and the MEMS structure.

[0010] Optionally, the first photoresist and the second photoresist are any one of positive photoresist, negative photoresist or dry film photoresist.

[0011] Optionally, the curing temperature is any value between 300℃ and 400℃.

[0012] Optionally, the deposition process of the seed layer is any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, or electroplating thin layer deposition.

[0013] Optionally, the seed layer includes an adhesive layer and a conductive layer stacked from bottom to top.

[0014] Optionally, the adhesive layer is one or more of titanium, chromium, tantalum, tungsten, and titanium-tungsten alloy; The conductive layer is one or more of copper, nickel, gold, silver, or their alloys.

[0015] Optionally, the solder ring comprises one or more solder materials selected from tin, tin alloys, indium, indium alloys, gold-tin alloys, gold-germanium alloys, or combinations thereof.

[0016] Optionally, the solder ring is formed by one or more of the following methods: electroplating deposition, chemical plating deposition, physical vapor deposition, evaporation deposition, printing deposition, or preform mounting.

[0017] This invention achieves an overall improvement in the cleanliness, reliability, and manufacturing efficiency of MEMS infrared detector wafers by constructing a process sequence system that first forms a seed layer, then constructs the MEMS structure, subsequently forms a solder ring, and finally exposes the test pads. This avoids the backsplashing contamination problem caused by the deposition of the seed layer on the surface of the organic sacrificial layer, avoids contamination and corrosion caused by the exposure of the pad structure in the middle and front-end processes, reduces the number of times the polyimide sacrificial layer is used, reduces process complexity and cost, improves the electroplating quality of the solder ring and the stability of the package's hermeticity, and ultimately improves the consistency and yield of the overall wafer-level packaging.

[0018] Furthermore, by limiting the curing temperature of the polyimide layer to any value within the range of 300℃-400℃, this invention enables the polyimide material to achieve a dense and stable network structure while being fully imidized. This significantly improves the mechanical strength, heat resistance, and dimensional stability of the film, ensuring the structural reliability of the formed MEMS structure during subsequent processes and use. Simultaneously, this temperature range effectively removes residual solvents and internal stress, reducing the risk of film shrinkage, warping, and cracking, while also preventing excessively high temperatures from causing thermal damage or performance degradation to the readout circuit wafer and metal layer. Moreover, by adjusting the specific curing temperature within this range, the stress state and interface bonding quality can be flexibly optimized according to different device structural dimensions and material systems, thereby further improving the compatibility between the MEMS structure and the solder ring and substrate, and the overall packaging reliability.

[0019] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0020] The following sections will describe some specific embodiments of the invention in detail by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or portions. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic flowchart of a method for fabricating a MEMS infrared detector wafer according to an embodiment of the present invention; Figure 2This is a schematic structural diagram of a MEMS infrared detector wafer according to an embodiment of the present invention; Figure 3 This is a schematic structural diagram of a readout circuit wafer with a seed layer according to an embodiment of the present invention; Figure 4 This is a schematic structural diagram of a MEMS structure according to an embodiment of the present invention; Figure 5 This is a schematic structural diagram of a first photoresist according to an embodiment of the present invention; Figure 6 This is a schematic structural diagram of a solder ring according to an embodiment of the present invention; Figure 7 This is a schematic structural diagram of removing the first photoresist according to one embodiment of the present invention; Figure 8 This is a schematic structural diagram of a second photoresist according to an embodiment of the present invention; Figure 9 This is a schematic structural diagram showing the exposed pad structure according to an embodiment of the present invention.

[0021] Figure label: 100 - MEMS infrared detector wafer, 10 - readout circuit wafer, 11 - pad structure, 20 - seed layer, 21 - adhesive layer, 22 - conductive layer, 30 - polyimide layer, 40 - MEMS structure, 50 - solder ring, 60 - first photoresist, 70 - second photoresist. Detailed Implementation

[0022] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and are not intended to limit the scope of the invention.

[0023] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0024] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0025] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0026] Figure 1 This is a schematic flowchart of a method for fabricating a MEMS infrared detector wafer according to an embodiment of the present invention; Figure 2 This is a schematic structural diagram of a MEMS infrared detector wafer according to an embodiment of the present invention. Figure 3 This is a schematic structural diagram of a readout circuit wafer with a seed layer according to an embodiment of the present invention. Figure 4 This is a schematic structural diagram of a MEMS structure according to an embodiment of the present invention. Figure 5 This is a schematic structural diagram of a first photoresist according to an embodiment of the present invention. Figure 6 This is a schematic structural diagram of a solder ring according to an embodiment of the present invention. Figure 7 This is a schematic structural diagram of removing the first photoresist according to one embodiment of the present invention. Figure 8 This is a schematic structural diagram of a second photoresist according to an embodiment of the present invention. Figure 9 This is a schematic structural diagram showing the exposed pad structure according to an embodiment of the present invention.

[0027] like Figure 1 As shown, the present invention provides a MEMS infrared detector wafer 100 (refer to...). Figure 2 The preparation method of ) includes the following steps: Step S100: Deposit a seed layer 20 on a readout circuit wafer 10 (refer to...) Figure 2 The readout circuit wafer 10 includes a pad structure 11; Step S200: Perform photolithography etching on the seed layer 20 to preserve the seed layer 20 in the area where the solder ring 50 is located (refer to...). Figure 3 ); Step S300: A polyimide layer 30 is formed on the top surface of the readout circuit wafer 10 and around the seed layer 20 (see reference). Figure 3 The MEMS structure 40 deposited on the surface of the readout circuit wafer 10 was prepared by curing treatment (refer to...). Figure 4 and Figure 5 ); Step S400: Expose a portion of the seed layer 20 using photolithography etching, and deposit a solder ring 50 on the exposed seed layer 20 (refer to...). Figure 6 and Figure 7 ); Step S500: Expose the pad structure 11 of the readout circuit wafer 10 using photolithography etching process (refer to...) Figure 9 After performing electrical tests and resist removal in sequence, a MEMS infrared detector wafer 100 was prepared.

[0028] In this embodiment, the fabrication method of the MEMS infrared detector wafer 100 firstly involves depositing a seed layer 20 on the surface of a readout circuit wafer 10 with a pad structure 11, and then using a photolithography etching process to etch the seed layer 20 so that only the area where the solder ring 50 is located is retained. Next, a polyimide layer 30 is coated on the readout circuit wafer 10 and the seed layer 20. After curing, a preset pattern for depositing the MEMS structure 40 is formed in the polyimide layer 30 using an etching process, and then deposited using a deposition process. MEMS structure 40 is deposited on readout circuit wafer 10. Then, the polyimide layer 30 is etched using photolithography to expose the seed layer 20. Solder ring 50 is deposited on the surface of the exposed seed layer 20. Finally, a portion of the polyimide layer 30 corresponding to the pad structure 11 is etched away using photolithography to perform electrical testing on the readout circuit wafer 10 through the pad structure 11. After the electrical testing is completed, the polyimide layer 30 is removed to prepare MEMS infrared detector wafer 100.

[0029] In this embodiment, by constructing a process sequence system that first forms the seed layer 20, then the MEMS structure 40, subsequently the solder ring 50, and finally exposes the test pads, the overall cleanliness, reliability, and manufacturing efficiency of the MEMS infrared detector wafer 100 during the manufacturing process are improved. This avoids the backsplashing contamination problem caused by the deposition of the seed layer 20 on the surface of the organic sacrificial layer, avoids the contamination and corrosion of the pad structure 11 caused by exposure in the middle and front-end processes, and can also reduce the number of times the polyimide sacrificial layer is used, reduce process complexity and cost, improve the electroplating quality of the solder ring 50 and the stability of the packaging hermeticity, and ultimately improve the consistency and yield of the overall wafer-level packaging.

[0030] In step S100, a seed layer 20 is preferentially formed on the clean inorganic surface of the readout circuit wafer 10, allowing the seed layer 20 to be directly deposited on the organic-free substrate interface. This effectively avoids the backsplash contamination of the cavity that may occur during sputtering on the polyimide surface. Simultaneously, the seed layer 20 exhibits higher adhesion and film uniformity with the substrate, significantly improving the uniformity and stability of the subsequent solder ring 50 electroplating process. It also provides a stable and reliable conductive foundation for the subsequent construction of the MEMS structure 40 and the solder ring 50, thus constructing the basic conductive and adhesion platform required for the formation of the subsequent structure.

[0031] In step S200, by performing photolithographic etching pre-patterning processing on the seed layer 20, the seed layer 20 is retained only in the corresponding area of ​​the solder ring 50, thereby effectively avoiding the subsequent residual metal layer and the resulting short circuit risk. At the same time, it reduces the process complexity of subsequent etching and removal of excess seed layer 20, and improves the positioning accuracy of the subsequent electroplating process by pre-limiting the position of the solder ring 50, thereby achieving pre-limitation and precise structural control of the solder ring 50 area.

[0032] In step S300, a polyimide layer 30 is formed on the patterned seed layer 20 and a MEMS structure 40 is constructed. This prevents the seed layer 20 from being deposited on organic materials, thereby significantly reducing contamination and particle defects generated during sputtering. At the same time, the structure can be constructed by using the polyimide layer 30 as a sacrificial layer only once, reducing the number of processes, reducing manufacturing costs and improving process efficiency. Furthermore, the MEMS structure 40 and the solder ring 50 region are formed in the same reference system, thereby improving the alignment accuracy and overall consistency of the structure and achieving optimized integration of the structure construction and the material system.

[0033] In step S400, by exposing the seed layer 20 and depositing the solder ring 50 after the MEMS structure 40 is completed, the retained photoresist is used as a protective layer to effectively avoid damage to the MEMS structure 40 in the subsequent electroplating process. At the same time, electroplating on the clean and stable conductive seed layer 20 helps to improve the metal purity, density and hermetically sealed performance of the solder ring 50, and further improves the relative positional accuracy between the solder ring 50 and the MEMS structure 40, so as to achieve reliable collaborative construction of high-quality solder ring 50 and MEMS structure 40.

[0034] In step S500, by exposing the pads after the solder ring 50 is formed, the pads are kept in a closed and protected state during most of the processing, thereby effectively avoiding problems such as contamination, oxidation and corrosion, significantly improving the contact reliability during subsequent electrical testing, and reducing cleaning and rework processes, thus achieving clean protection of the test interface and improving overall reliability.

[0035] like Figure 6As shown, in a further embodiment, before the step of exposing a portion of the seed layer 20 using a photolithography etching process and depositing a solder ring 50 on the exposed seed layer 20, the method further includes: A first photoresist 60 is coated on the surface of the polyimide layer 30 and the MEMS structure 40.

[0036] In this embodiment, by pre-coating the polyimide layer 30 and the MEMS structure 40 with a first photoresist 60, the subsequent exposure of the seed layer 20 opening and the deposition of the solder ring 50 are established on a controlled photolithographic mask system, thereby enabling precise definition of the opening position, size, and boundary morphology of the solder ring 50. Simultaneously, the first photoresist 60 serves as an effective physical protective layer during subsequent etching and electroplating processes, shielding and isolating the MEMS structure 40 and the polyimide layer 30 to prevent contamination, corrosion, or mechanical damage from etching solutions, electroplating solutions, or metal deposition. Furthermore, the patterning control of the photoresist allows for selective deposition and improved boundary regularity in the solder ring 50 region, thereby enhancing the morphological quality, dimensional consistency, and reliability of subsequent hermetically sealed assembly of the solder ring 50.

[0037] like Figure 8 As shown, in a further embodiment, the step of exposing the pad structure 11 of the readout circuit wafer 10 using photolithography etching process includes: Remove 60g of the first photoresist; A second photoresist 70 is coated on the polyimide layer 30, the solder ring 50, and the MEMS structure 40.

[0038] In this embodiment, before exposing the pad structure 11 of the readout circuit wafer 10, the first photoresist 60 is removed, and then the second photoresist 70 is recoated onto the polyimide layer 30, solder ring 50, and MEMS structure 40. This allows the subsequent opening process of the pad structure 11 to be built on a completely new photolithographic mask system, avoiding the adverse effects of aging, residue, or morphological degradation of the first photoresist 60 after previous etching, electroplating, and other processes on the pattern accuracy. Simultaneously, the second photoresist 70 provides complete coverage and effective protection for the formed solder ring 50 and MEMS structure 40, preventing metal corrosion, structural contamination, or mechanical damage during the opening etching and cleaning process of the pad structure 11. Furthermore, by redefining the opening window of the pad structure 11, the alignment accuracy and boundary neatness of the exposed position and size of the pad structure 11 can be further improved, thereby enhancing the contact reliability of subsequent electrical tests and the overall device consistency and yield.

[0039] In a further embodiment, the first photoresist 60 and the second photoresist 70 are any one of positive photoresist, negative photoresist, or dry film photoresist. In this embodiment, by setting the first photoresist 60 and the second photoresist 70 as any one of positive photoresist, negative photoresist, or dry film photoresist, the process system of the present invention has stronger material adaptability and process flexibility. Specifically, positive photoresist is beneficial for achieving high resolution and fine aperture patterns, and is suitable for scenarios with high requirements for the dimensional accuracy of the solder ring 50 and the pad window. Negative photoresist has high structural stability and etching resistance, which is beneficial for providing more reliable protection during subsequent electroplating and etching processes. Dry film photoresist has the advantages of uniform thick film, good coverage, and suitability for large-area processing, which can improve process consistency and mass production yield. Through the optional configuration of the above-mentioned multiple types of photoresist, a suitable photolithography system can be flexibly selected according to different device structure dimensions, MEMS structure 40 morphology, and packaging requirements, thereby improving process stability, yield, and the reliability of the final device while ensuring pattern accuracy.

[0040] In a further embodiment, the curing temperature is any value within the range of 300℃-400℃. That is, the curing temperature of the polyimide layer 30 can be 300℃, 310℃, 320℃, 330℃, 340℃, 350℃, 360℃, 370℃, 380℃, 390℃, or 400℃, or any other value within the range of 300℃-400℃. In this embodiment, by limiting the curing temperature of the polyimide layer 30 to any value within the range of 300℃-400℃, the polyimide material can obtain a dense and stable network structure while being fully imidized. This significantly improves the mechanical strength, heat resistance, and dimensional stability of the film layer, ensuring the structural reliability of the formed MEMS structure 40 during subsequent processes and use. Simultaneously, this temperature range effectively removes residual solvents and internal stress, reducing the risk of film shrinkage, warping, and cracking, while also preventing excessively high temperatures from causing thermal damage or performance degradation to the readout circuit wafer 10 and the metal layer. Furthermore, by adjusting the specific curing temperature within this range, the stress state and interface bonding quality can be flexibly optimized according to different device structure dimensions and material systems, thereby further improving the matching between MEMS structure 40, solder ring 50, and substrate, as well as the overall packaging reliability.

[0041] In a further embodiment, the seed layer 20 is deposited using any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, or electroplating thin-layer deposition, giving the seed layer 20 preparation method of the present invention good process compatibility and adjustability. Specifically, physical vapor deposition can obtain a dense, uniform metal film with excellent adhesion, suitable for forming a high-quality initial conductive layer 22. Chemical vapor deposition is beneficial for achieving uniform coverage on complex morphological surfaces, improving step coverage capability. Atomic layer deposition can achieve atomic-level thickness control and excellent consistency, suitable for scenarios with high requirements for film uniformity and interface quality. Electroplating thin-layer deposition can quickly form a thicker conductive layer 22 on an existing conductive substrate, improving the conductivity efficiency of the subsequent electroplated solder ring 50. Through the optional configuration of the above-mentioned multiple deposition processes, a suitable seed layer 20 preparation method can be flexibly selected according to different structural sizes, surface morphologies, and conductivity requirements, thereby improving process stability, yield, and final device packaging reliability while ensuring adhesion and conductivity performance.

[0042] In a further embodiment, the seed layer 20 includes an adhesive layer 21 and a conductive layer 22 stacked from bottom to top, enabling the seed layer 20 to possess both excellent interfacial bonding ability and conductivity. The lower adhesive layer 21 enhances the bonding strength between the seed layer 20 and the surface of the readout circuit wafer 10, improving the adhesion and stability of the film layer and preventing peeling or delamination during subsequent photolithography, etching, and electroplating processes. The upper conductive layer 22 provides a continuous, low-resistance conductive path, which is beneficial for improving the current distribution uniformity and deposition efficiency of the subsequent solder ring 50 electroplating, thereby improving the density and morphological consistency of the solder ring 50. Through the synergistic arrangement of the above-mentioned dual-layer structure, the conductivity can be optimized while ensuring stable adhesion of the seed layer 20, thereby improving the formation quality of the solder ring 50 and the reliability and yield of the overall packaging structure.

[0043] In a further embodiment, the adhesive layer 21 is one or more of titanium, chromium, tantalum, tungsten, and titanium-tungsten alloys, and the conductive layer 22 is one or more of copper, nickel, gold, silver, or their alloys, thereby achieving a better match between the interfacial bonding and electrical performance of the seed layer 20. Specifically, the aforementioned adhesive layer 21 materials all possess strong interfacial activity and good adhesion to the silicon-based or insulating layer surface, which can significantly improve the bonding strength and peel resistance between the seed layer 20 and the readout circuit wafer 10. The selected conductive layer 22 material has low resistivity and good electrochemical stability, which is beneficial for forming a continuous and stable electroplated conductive path, thereby improving the uniformity, density, and interfacial reliability of the solder ring 50 electroplating.

[0044] In a further embodiment, the solder ring 50 comprises one or more solder materials selected from tin, tin alloys, indium, indium alloys, gold-tin alloys, gold-germanium alloys, or combinations thereof, enabling the solder ring 50 to have a good adjustable match between melting point range, wettability, and hermetic sealing performance. Tin and tin alloys have good wettability and mature electroplating processes, facilitating the formation of a continuous and dense solder structure. Indium and indium alloys have low melting points and good ductility, enabling reliable bonding at lower temperatures and reducing the thermal impact on the MEMS structure 40 and readout circuitry. Gold-tin alloys and gold-germanium alloys have high mechanical strength, excellent hermeticity, and long-term stability, making them suitable for infrared detector packaging scenarios with high requirements for sealing reliability. Through the flexible selection of these various solder materials, optimization can be performed according to different packaging temperature windows, device thermal budgets, and hermeticity requirements, thereby improving the density of the packaging interface, environmental stability, and the overall long-term reliability and yield of the device while ensuring the bonding strength of the solder ring 50.

[0045] In a further embodiment, the solder ring 50 is formed by one or more of the following methods: electroplating deposition, electroless plating deposition, physical vapor deposition, evaporation deposition, printing deposition, or preform mounting. This allows for greater flexibility and adaptability in the fabrication process of the solder ring 50. Specifically, electroplating or electroless plating can selectively deposit solder on the patterned seed layer 20 to obtain a solder ring 50 structure with uniform thickness, high density, and controllable morphology. Physical vapor deposition or evaporation deposition is suitable for forming high-purity, clean-interface thin-film solder layers, which is beneficial for improving interface bonding quality. Printing deposition or preform mounting simplifies process steps, reduces equipment requirements, and is suitable for the rapid formation of larger-sized or specific-thickness solder rings 50. By combining or selecting from the above-mentioned various deposition or forming methods, optimized matching can be performed according to different material systems, solder thickness requirements, and production line conditions. This ensures the dimensional accuracy and morphological consistency of the solder ring 50 while improving process stability, production efficiency, and packaging yield, further enhancing the hermeticity and long-term reliability of wafer-level packaged infrared detectors.

[0046] The technical solution of this application will be further described below with reference to specific embodiments.

[0047] Example 1 In the fabrication method of MEMS infrared detector wafer 100, a seed layer 20 is first deposited on the surface of a readout circuit wafer 10 with a pad structure 11. The seed layer 20 is then photolithographically etched to retain only the area where the solder ring 50 is located. Next, a polyimide layer 30 is coated on the readout circuit wafer 10 and the seed layer 20. After curing, a pre-defined pattern for depositing the MEMS structure 40 is formed in the polyimide layer 30 using an etching process. Finally, the MEMS structure 40 is deposited using a deposition process. The S-structure 40 is deposited on the readout circuit wafer 10. Then, the polyimide layer 30 is etched using a photolithography etching process to expose the seed layer 20. A solder ring 50 is deposited on the surface of the exposed seed layer 20. Finally, a portion of the polyimide layer 30 corresponding to the pad structure 11 is etched away using a photolithography etching process to perform electrical testing on the readout circuit wafer 10 through the pad structure 11. After the electrical testing is completed, the polyimide layer 30 is removed to prepare the MEMS infrared detector wafer 100.

[0048] Comparative Example 1 First, a readout circuit wafer 10 containing test pads and covered with a passivation layer is provided. A first layer of polyimide is coated on its surface and cured at a high temperature of 350°C to serve as a sacrificial layer for the subsequent construction of the MEMS structure 40. Subsequently, the MEMS structure 40 for an infrared detector is fabricated on this sacrificial layer, and the test pads are opened through photolithography and etching processes for electrical testing. Then, a second layer of polyimide is coated on the wafer surface and cured at a low temperature of 250°C. Solder rings are formed in this polyimide layer 30 through photolithography and etching. A deep trench 50 is formed to expose the substrate. A titanium layer and a copper layer are sequentially formed in the deep trench by PVD sputtering as a seed layer 20, wherein the titanium layer is used to enhance adhesion and the copper layer is used to reduce the resistance of the solder ring 50. The seed layer 20 in the solder ring 50 area is then exposed by photolithography while the remaining area is covered by photoresist. Copper metal is then electroplated to form the solder ring 50. Subsequently, the photoresist is removed and excess seed layer 20 is etched away. Finally, the polyimide sacrificial layer is released by plasma process to obtain a MEMS infrared detector wafer 100 for wafer-level packaging.

[0049] Example 1 adopts a technical solution of first seeding layer 20 and then MEMS structure 40, which avoids seeding layer 20 sputtering onto sacrificial layer, reduces contamination of sputtering cavity, and also reduces the use of one sacrificial layer, improving efficiency and saving cost. Test pad structure 11 is opened in the later stage of MEMS wafer fabrication, avoiding dirt and corrosion of test pad structure 11.

[0050] In contrast, Comparative Example 1 first opened the test pad structure 11. During the process, the pad structure 11 was prone to getting dirty and corroded. In addition, the seed layer 20 was sputtered onto the organic polyimide, which was prone to backsplashing and contaminating the cavity. Furthermore, the polyimide was used twice during the preparation process, resulting in high cost and low efficiency.

[0051] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0052] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a MEMS infrared detector wafer, characterized in that, Includes the following steps: A seed layer is deposited on a readout circuit wafer, the readout circuit wafer including a pad structure; The seed layer is photolithographically etched to preserve the seed layer in the area where the solder ring is located; A polyimide layer is formed on the top surface of the readout circuit wafer and on the periphery of the seed layer, and a MEMS structure deposited on the surface of the readout circuit wafer is obtained by curing. The photolithography etching process is used to expose a portion of the seed layer, and a solder ring is deposited on the exposed seed layer; The photolithography etching process is used to expose the pad structure of the readout circuit wafer, and after electrical testing and resist removal are performed in sequence, the MEMS infrared detector wafer is prepared.

2. The method for fabricating a MEMS infrared detector wafer according to claim 1, characterized in that, The method further includes, prior to the step of exposing a portion of the seed layer using the photolithography etching process and depositing a solder ring on the exposed seed layer: A first photoresist is coated on the polyimide layer and the surface of the MEMS structure.

3. The method for fabricating a MEMS infrared detector wafer according to claim 2, characterized in that, The process further includes, prior to the step of exposing the pad structure of the readout circuit wafer using the photolithography etching process: Remove the first photoresist; A second photoresist is coated on the polyimide layer, the solder ring, and the MEMS structure.

4. The method for fabricating a MEMS infrared detector wafer according to claim 3, characterized in that, The first photoresist and the second photoresist are any one of positive photoresist, negative photoresist or dry film photoresist.

5. The method for fabricating a MEMS infrared detector wafer according to claim 4, characterized in that, The curing temperature is any value between 300℃ and 400℃.

6. The method for fabricating a MEMS infrared detector wafer according to claim 5, characterized in that, The deposition process of the seed layer can be any one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, or electroplating thin layer deposition.

7. The method for fabricating a MEMS infrared detector wafer according to any one of claims 1-6, characterized in that, The seed layer includes an adhesive layer and a conductive layer stacked from bottom to top.

8. The method for fabricating a MEMS infrared detector wafer according to claim 7, characterized in that, The adhesive layer is one or more of titanium, chromium, tantalum, tungsten, and titanium-tungsten alloy; The conductive layer is one or more of copper, nickel, gold, silver, or their alloys.

9. The method for fabricating a MEMS infrared detector wafer according to claim 8, characterized in that, The solder ring comprises one or more solder materials selected from tin, tin alloy, indium, indium alloy, gold-tin alloy, gold-germanium alloy, or combinations thereof.

10. The method for fabricating a MEMS infrared detector wafer according to claim 8, characterized in that, The solder ring is formed by one or more of the following methods: electroplating deposition, chemical plating deposition, physical vapor deposition, evaporation deposition, printing deposition, or preform mounting.

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