Three-dimensional photomask transmission with kernel-based modeling

EP4751134A1Pending Publication Date: 2026-06-03SIEMENS INDUSTRY SOFTWARE INC
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Patent Information

Authority / Receiving Office
EP · EP
Patent Type
Applications
Current Assignee / Owner
SIEMENS INDUSTRY SOFTWARE INC
Filing Date
2023-08-28
Publication Date
2026-06-03

AI Technical Summary

Technical Problem

Existing model-based optical proximity correction techniques struggle to accurately simulate three-dimensional light transmission in the near-field of lithographic masks, especially when dealing with non-Manhattan or curvilinear shapes, leading to reduced accuracy in wafer image simulation and mask layout design modifications.

Method used

A computing system that simulates three-dimensional light transmission in the near-field of a lithographic mask using a compact mask model and edge grids, generating directional kernels based on through-the-lens target orders and edge grid orders to accurately model light diffraction.

Benefits of technology

The system achieves improved accuracy in simulating three-dimensional light transmission, enabling more precise optical proximity correction and mask layout design modifications, which enhances pattern fidelity and manufacturing accuracy.

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Abstract

This application discloses a computing system to simulate three-dimensional light transmission in a near-field of a lithographic mask using a thin mask approximation of the lithographic mask rasterized from a mask layout design describing the lithographic mask and using a compact mask model including a plurality of directional kernels representing light diffraction in the near-field of the lithographic mask. The computing system can generate a wafer image or resist contours based on the simulated three-dimensional light transmission in the near-field of the lithographic mask, and utilize an optical proximity correction (OPC) process to modify the mask layout design based on the wafer image or the resist contours. The lithographic mask corresponding to the mask layout design is configured for use in the manufacturing of an integrated circuit.
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