Automatic cell and macro placement in VLSI layout design

Abstract

Systems (101) and methods (300) for generation of a very-large-scale-integration floorplan (400). A method includes receiving (302) inputs (322, 324, 326) for automatic placements of macros in a floorplan (400). The method includes performing (304) an automatic macro placement process based on the received inputs (322, 324, 326). The method includes generating (308) the floorplan (400) according to the automatic macro placement process. The floorplan (400) can thereafter be used to generate a physical layout and a physical chip can thereafter be manufactured according to the generated physical layout.

Description

AUTOMATIC CELL AND MACRO PLACEMENT IN VLSI LAYOUT DESIGNTECHNICAL FIELD

[0001] The present disclosure is directed, in general, to the design of physical layouts for very-large-scale-integration (VLSI) integrated circuits (ICs), and in particular to improved methods for automatic placement of macros and standard cells on the VLSI physical layout design (or “floorplan”).BACKGROUND OF THE DISCLOSURE

[0002] Design and manufacture of integrated circuits has become increasingly complex. A modem integrated circuits can include millions of standard “cells,” each of which is comprised of transistor and interconnect structures to implement one or more logic functions, and many microcell arrays or “macros,” that are predesigned structures of multiple cells that implement specific functions, such as flip-flops, arithmetic logic unit (ALU) functions, registers, memory cells, or otherwise. A physical layout of a design includes the physical location of each of the cells and the macros on the IC chip, along with the interconnections between them (the “wires”). A physical chip can then be manufactured from the layout.

[0003] Traditionally, in the physical design stage of IC design flow, macros are placed manually in the floorplan by floorplan designers, which ty pically takes a few weeks to several months to generate a floorplan. Then designers must place standard cells and perform other steps of physical design flow to generate a physical layout that can be manufactured without errors or interference between the various components and interconnections and that can operate efficiently. There is need in the industry for systems that can automatically design or aid in designing a VLSI floorplan.SUMMARY OF THE DISCLOSURE

[0004] Various disclosed embodiments include systems and methods for generation of very-large-scale-integration floorplans. A method includes receiving inputs for automatic placements of macros in a floorplan. The method includes performing an automatic macro placement process based on the received inputs. The method includes generating the floorplan according to the automatic macro placement process. The floorplan can thereafter be used to generate a physical layout and a physical chip can thereafter be manufactured according to the generated physical layout.

[0005] In various embodiments, the automatic macro placement process is timing driven to place macros in a same hierarchical module near each other in the floorplan, and macros with a same library are grouped together. In various embodiments, the automatic macro placement process includes performing global macro placement of a plurality of macros in the floorplan, performing a legalization process for the global macro placement, building macro groups, each macro group having multiple ones of the plurality of macros, performing a global macro group placement of the macro groups, and performing a legalization process for the global macro group placement.

[0006] In various embodiments, the global macro placement is based on modeled repulsive nuclear field forces and attractive wire forces between the plurality of macros in the floorplan. In various embodiments, the global macro group placement is based on modeled repulsive nuclear field forces and attractive wire forces between the macro groups. In various embodiments, the legalization process for the global macro placement and / or the global macro group placement is an iterative simulation annealing-based legalization using modification techniques. In various embodiments, the legalization process for the global macro group placement includes performing a regroup process to form new macro groups.

[0007] In various embodiments, building macro groups includes assigning macro groups for each macro according to a floorplan bin, grouping together macros that have cells from a same standard cell library, and grouping together macros that are on a same logical hierarchical level

[0008] In various embodiments, building macro groups includes assigning macro groups for each macro according to an instance name-based hierarchy, groupingtogether macros that have cells from a same standard cell library, and grouping together macros according to physical proximity-based clusters.

[0009] Some embodiments further include placing a standard cell in the floorplan based on modeled repulsive nuclear field forces and attractive wire forces between the standard cell and the plurality of macros in the floorplan.

[0010] Other embodiments include a computer system having a processor and an accessible memory, configured to perform processes described herein. Other embodiments include non-transitory computer-readable media encoded with executable instructions that, when executed, cause one or more computer systems to perform processes as described herein.

[0011] The foregoing has outlined rather broadly the features and technical advantages of the present disclosure so that those skilled in the art may better understand the detailed description that follows. Additional features and advantages of the disclosure will be described hereinafter that form the subject of the claims. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure in its broadest form.

[0012] Before undertaking the DETAILED DESCRIPTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and / or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed,whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases. While some terms may include a wide variety of embodiments, the appended claims may expressly limit these terms to specific embodiments.BRIEF DESCRIPTION OF THE DRAWINGS

[0013] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which:

[0014] FIGS. 1 and 2 illustrate components of a computer system that may be used to implement various embodiments of the disclosed technology;

[0015] FIG. 3 illustrates a high-level view of a process for automatic generation of a floorplan, in accordance with disclosed embodiments;

[0016] FIG. 4 illustrates an example of a floorplan produced in accordance with disclosed embodiments;

[0017] FIG. 5A illustrates an example of a floorplan in accordance with disclosed embodiments;

[0018] FIG. 5B illustrates a more detailed view of the macros of a selected portion of a floorplan in accordance with disclosed embodiments;

[0019] FIG. 5C illustrates a more detailed view of the macros of a selected portion of a floorplan after manual repack in accordance with disclosed embodiments;

[0020] FIG. 6 illustrates a high-level of a process for automatic placement of macros in a floorplan in accordance with disclosed embodiments;

[0021] FIG. 7 illustrates a process for global placement of nodes in a floorplan in accordance with disclosed embodiments;

[0022] FIG. 8 illustrates a simulated annealing (SA) based legalization process in accordance with disclosed embodiments; and

[0023] FIGS. 9A and 9B illustrate processes for building a macro group in accordance with disclosed embodiments.DETAILED DESCRIPTION

[0024] FIGS. 1 through 9B, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged device. The numerous innovative teachings of the present application will be described with reference to exemplary non-limiting embodiments.

[0025] There are multiple goals in the design of a successful floorplan that may include thousands of cells both individually, as standard or custom cells, and as grouped into macros. One significant objective is manufacturability, which requires that the cells, macros, and wires are placed so that they can be successfully manufactured without mterfenng with each other in the manufacturing process. Another significant objective is operability, which includes ensuring that the cells, macros, and wires do not electrically or electromagnetically interfere with each other during operation. Another significant objective is efficiency, so that the manufactured chip can perform its function as quickly and efficiently as possible, which can include designing the interconnections to be as short as possible without sacrificing other objectives. The “quality of results” (QoR) for the floorplan is repeatedly evaluated during the legalization process to ensure proper and efficient operations.

[0026] Disclosed embodiments include systems and methods for automatic placement of macros and other cells in a floorplan. Various embodiments can include techniques for local refinement of the placement of individual cells or macros (“legalization”) to remove overlaps in structure, ensure proper connections between various components, and, if necessary, perform modifications such as translations or transformations of cell or macro shapes (e.g., sliding, shifting, flipping, or rotating the shapes). While the techniques described herein can be applied on both the cell and macro levels, various embodiments are particularly useful for automatic macro placement in a floorplan.

[0027] Disclosed embodiments, as described in more detail below, use a nuclear-force based modeling, timing driven global placement for individual nodes, including cells, macros, and macro groups. Disclosed embodiments can use simulation annealing based legalization for individual macros and macro groups.Illustrative Operating Environment

[0028] The execution of various processes described herein may be implemented using computer-executable software instructions executed by one or more programmable computing devices. Because these processes may be implemented using software instructions, the components and operation of a generic programmable computer system on which various embodiments of these processes may be employed will first be described. Further, because of the complexity of some electronic design and testing processes and the large size of many circuit designs, various electronic design and testing tools are configured to operate on a computing system capable of simultaneously running multiple processing threads. The components and operation of a computer system having a host or master computer and one or more remote or slave computers therefore will be described with reference to FIG. 1. This operating environment is only one example of a suitable operating environment, however, and is not intended to suggest any limitation as to the scope of use or functionality of any implementations of the invention.

[0029] In FIG. 1, the computer system 101 includes a master computer 103. In the illustrated example, the master computer 103 is a multi -processor computer that includes a plurality of input and output devices 105 and a memory 107. The input and output devices 105 may include any device for receiving input data from or providing output data to a user. The input devices may include, for example, a keyboard, microphone, scanner or pointing device for receiving input from a user. The output devices may then include a display monitor, speaker, printer or tactile feedback device. These devices and their connections are well known in the art, and thus will not be discussed at length here.

[0030] The memory 107 may similarly be implemented using any combination of computer readable media that can be accessed by the master computer 103. The computer readable media may include, for example, microcircuit memory devices such as read- rite memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable media may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, punched media, holographic storagedevices, or any other non-transitory storage medium that can be used to store desired information. As used herein, the term "non-transitory" refers to the ability to store information for subsequent retrieval at a desired time, as opposed to propagating electromagnetic signals.

[0031] As will be discussed in detail below, the master computer 103 runs a software application for performing one or more operations according to various examples of the invention. Accordingly, the memory 107 stores software instructions 109A that, when executed, will implement a software application for performing one or more operations. The memory 107 also stores data 109B to be used with the software application. In the illustrated embodiment, the data 109B contains process data that the software application uses to perform the operations, at least some of which may be parallel.

[0032] The master computer 103 also includes a plurality of processor units 111 and an interface device 113. The processor units 111 may be any type of processor device that can be programmed to execute the software instructions 109A, but will conventionally be a microprocessor device. For example, one or more of the processor units 111 may be a commercially generic programmable microprocessor, such as Intel® Pentium® or Xeon™ microprocessors, Advanced Micro Devices Athlon™ microprocessors or Motorola 68K / Coldfire® microprocessors. Alternately or additionally, one or more of the processor units 111 may be a custom-manufactured processor, such as a microprocessor designed to optimally perform specific types of mathematical operations. The interface device 113, the processor units 111, the memory 107 and the input / output devices 105 are connected together by a bus 115.

[0033] With some implementations of the invention, the master computer 103 may employ one or more processing units 111 having more than one processor core. Accordingly, FIG. 2 illustrates an example of a multi-core processor unit 111 that may be employed with various embodiments of the invention. As seen in this figure, the processor unit 111 includes a plurality of processor cores 201. Each processor core 201 includes a computing engine 203 and a memory cache 205. As known to those of ordinary skill in the art, a computing engine contains logic devices for performing various computing functions, such as fetching software instructions and then performing the actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, and comparing numbers, performinglogical operations such as AND, OR, NOR and XOR, and retrieving data. Each computing engine 203 may then use its corresponding memory cache 205 to quickly store and retrieve data and / or instructions for execution.

[0034] Each processor core 201 is connected to an interconnect 207. The particular construction of the interconnect 207 may vary depending upon the architecture of the processor unit 201. With some processor cores 201, such as the Cell microprocessor created by Sony Corporation, Toshiba Corporation and IBM Corporation, the interconnect 207 may be implemented as an interconnect bus. With other processor units 201, however, such as the Opteron™ and Athlon™ dual-core processors available from Advanced Micro Devices of Sunnyvale, Calif, the interconnect 207 may be implemented as a system request interface device. In any case, the processor cores 201 communicate through the interconnect 207 with an input / output interfaces 209 and a memory controller 211. The input / output interface 209 provides a communication interface between the processor unit 201 and the bus 115. Similarly, the memory controller 211 controls the exchange of information between the processor unit 201 and the system memory 107. With some implementations of the invention, the processor units 201 may include additional components, such as a high-level cache memory accessible shared by the processor cores 201.

[0035] While FIG. 2 shows one illustration of a processor unit 201 that may be employed by some embodiments of the invention, it should be appreciated that this illustration is representative only and is not intended to be limiting. It also should be appreciated that, with some implementations, a multi-core processor unit 111 can be used in lieu of multiple, separate processor units 111. For example, rather than employing six separate processor units 111, an alternate implementation of the computing system 101 may employ a single processor unit 111 having six cores, two multi-core processor units each having three cores, a multi-core processor unit 111 with four cores together with two separate single-core processor units 111, etc.

[0036] Returning now to FIG. 1, the interface device 113 allows the master computer 103 to communicate with the slave computers 117A, 117B, 117C . . . 117x through a communication interface. The communication interface may be any suitable type of interface including, for example, a conventional wired network connection or an optically transmissive wired network connection. The communication interface mayalso be a wireless connection, such as a wireless optical connection, a radio frequency connection, an infrared connection, or even an acoustic connection. The interface device 113 translates data and control signals from the master computer 103 and each of the slave computers 117 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP), the user datagram protocol (UDP), and the Internet protocol (IP). These and other conventional communication protocols are well known in the art, and thus will not be discussed here in more detail.

[0037] Each slave computer 117 may include a memory 119, a processor unit 121, an interface device 123, and, optionally, one more input / output devices 125 connected together by a system bus 127. As with the master computer 103, the optional input / output devices 125 for the slave computers 117 may include any conventional input or output devices, such as keyboards, pointing devices, microphones, display monitors, speakers, and printers. Similarly, the processor units 121 may be any type of conventional or custom-manufactured programmable processor device. For example, one or more of the processor units 121 may be commercially generic programmable microprocessors, such as Intel®. Pentium®, or Xeon™ microprocessors, Advanced Micro Devices Athlon™ microprocessors or Motorola 68K / Coldfire®. microprocessors. Alternately, one or more of the processor units 121 may be custom- manufactured processors, such as microprocessors designed to optimally perform specific types of mathematical operations. Still further, one or more of the processor units 121 may have more than one core, as described with reference to FIG. 2 above. The memory 119 then may be implemented using any combination of the computer readable media discussed above. Like the interface device 113, the interface devices 123 allow the slave computers 117 to communicate with the master computer 103 over the communication interface.

[0038] In the illustrated example, the master computer 103 is a multi-processor unit computer with multiple processor units 111, while each slave computer 117 has a single processor unit 121. It should be noted, however, that alternate implementations of the technology may employ a master computer having single processor unit 111. Further, one or more of the slave computers 117 may have multiple processor units 121, depending upon their intended use, as previously discussed. Also, while only a singleinterface device 113 or 123 is illustrated for both the master computer 103 and the slave computers, it should be noted that, with alternate embodiments of the invention, either the computer 103, one or more of the slave computers 117, or some combination of both may use two or more different interface devices 113 or 123 for communicating over multiple communication interfaces.

[0039] With various examples of the computer system 101, the master computer 103 may be connected to one or more external data storage devices. These external data storage devices may be implemented using any combination of non-transitory computer readable media that can be accessed by the master computer 103. The computer readable media may include, for example, microcircuit memory devices such as readwrite memory (RAM), read-only memory (ROM), electronically erasable and programmable read-only memory (EEPROM) or flash memory microcircuit devices, CD-ROM disks, digital video disks (DVD), or other optical storage devices. The computer readable media may also include magnetic cassettes, magnetic tapes, magnetic disks or other magnetic storage devices, punched media, holographic storage devices, or any other medium that can be used to store desired information. According to some implementations of the computer system 101, one or more of the slave computers 117 may alternately or additions be connected to one or more external non- transitory data storage devices. Typically, these external non-transitory data storage devices will include data storage devices that also are connected to the master computer 103, but they also may be different from any data storage devices accessible by the master computer 103.

[0040] It also should be appreciated that the description of the computer system 101 illustrated in FIG. 1 and FIG. 2 is provided as an example only, and it not intended to suggest any limitation as to the scope of use or functionality of various embodiments of the invention.

[0041] FIG. 3 illustrates a high-level view of a process 300 for automatic generation of an VLSI design layout / floorplan, including automatic placement of macros, that can be performed, for example, by a computer system such as computer system 101, referred to herein as simply the “system.”

[0042] At 302, the system receives inputs for automatic placements of macros in a floorplan. These inputs describe, among other things, the cells and / or macros to be placed in the floorplan. These inputs can include, for example, VLSI inputs 322 that describe information such as the cells and macros to be included in the floorplan, the interconnections between them, the hierarchical modules to which each of them belong, and macro libraries to which each macro is associated. VLSI inputs 322 can include a netlist describing some or all of this information. “Receiving,” as used herein, can include loading from storage, receiving from another device or process, receiving via an interaction with a user, and otherwise.

[0043] The inputs can include tuning parameters 324. Tuning parameters can include any parameters described herein and can include such parameters as maximum distances between cells / macros, minimum “gap” distances between cells / macros, timing requirements, wiring requirements, uniform density requirements, and other such parameters to be used by the automatic macro placement process.

[0044] The inputs can include large macro placement 326. For example, the system may receive a user selection of specific large macros to be “fixed” in place on the chip boundary and let the automatic macro placement process find best locations for smaller macros, such as in the middle of chip.

[0045] At 304, the system performs an automatic macro placement process as described herein, based on the received inputs. According to various embodiments, the system can perform timing-driven macro placement to place macros in same hierarchical module close together. The system can place some macros in middle of chip for best timing results. The system can group together macros with the same library to ensure proper alignment.

[0046] At 306, the system optionally performs a manual repack of some or all of the macros in the floorplan. This process can be performed in response to receiving a user selection of macros to be manually repacked, and the manual repack can then include performing an automatic macro placement process on just the selected macros. This process can more efficiently arrange the selected macros within the floorplan to eliminate bottlenecks.

[0047] At 308, the system generates a floorplan according to the automatic macro placement process and (if performed) the manual repack. The system can display, store, or transmit the floorplan as part of this step.

[0048] Designers can use the floorplan to run subsequent physical design steps (such as placement and routing) to generate the full physical layout. Thereafter, a physical chip can be manufactured according to the floorplan and layout.

[0049] FIG. 4 illustrates an example of a floorplan 400 produced in accordance with disclosed embodiments. Floorplan 400 includes a number of macros 402. Multiple macros 402 may be grouped into macro groups 404, as described herein. In this figure, for illustrative purposes, fill patterns used to identify macro groups. Note that individual macros 404 can be of different sizes, and multiple identical macros 404 may be used in the floor plan. The size and shape of each macro and macro group can be used in the automatic macro placement process, which can include translating or transforming a macro or macro group by rotating or flipping it. While this example of floorplan 400 does not include interconnections / wires between the various cells, macros, and chip connections, other floorplans can include this information.

[0050] FIG. 5A illustrates an example of a floorplan 500 in accordance with disclosed embodiments, including a selected portion 502, used to illustrate a manual repack 306. Floorplan 500 may represent a floorplan 500 after an automatic macro placement process is performed globally on the floorplan 500, where all macros are placed and legalized, but where a user considers the selected portion 502 is inefficiently or inelegantly laid out in the floorplan 500 and desires an automatic macro placement process to be performed locally on selected portion 502 subsequent to the global process. Consider that the macros in selected portion 502 are selected for manual repack.

[0051] FIG. 5B illustrates a more detailed view of the macros of selected portion 502 before manual repack.

[0052] The system can perform a local automatic macro placement process on just selected portion 502. FIG. 5C illustrates a more detailed view of the macros of selected portion 502 after manual repack using the local automatic macro placement process.Note that the selected macros are much more efficiently and elegantly placed with respect to each other.

[0053] FIG. 6 illustrates a high-level of a process 600 for automatic placement of macros in a VLSI design layout / floorplan that can be performed, for example, by a computer system such as computer system 101, referred to herein as simply the “system.” This process can be used, for example, as automatic macro placement 306 described with respect to FIG. 3. It is assumed here that the system has already received necessary data, such as VLSI inputs 322, tuning parameters 324, and large macro placements 326.

[0054] At 602, the system performs global placement of macros (excluding any manually -placed macros such as large macro placements 326).

[0055] A number of different approaches can be taken with regard to macro placements (and, below, macro group placements), and a number of tuning parameters can be used, as understood by those of skill in the art. For example, one approach is to first place larger macros on the borders or edges of the chip, then fill in the interior with smaller macros (and eventually other cells), accounting for required wiring, spacing, and other tuning considerations. Another approach is to first place larger macros in specific areas of the chip, then fill in the unused portions of the floorplan with smaller macros (and eventually other cells), accounting for required wiring, spacing, and other tuning considerations.

[0056] Either of those techniques can lead to issues with electromagnetic interference, crosstalk, and noise between the macros or nets of specific circuits that are placed too closely together. One approach to addressing such issues is to use the so-called “ePlace” technique, described, for example, in ePlace: Electrostatics-Based Placement Using Fast Fourier Transform and Nesterov's Method (Lu, el al., ACM Transactions on Design Automation of Electronic Systems, Vol. 20, No. 2, 2015), hereby incorporated by reference. The ePlace technique models every object as a positive charge and the density cost as the potential energy of the electrostatic system to aid in placement. This technique, however, can give less than ideal results by weighting large, distant VLSI objects such that they influence local placement more than necessary.

[0057] Disclosed embodiments improve on known techniques by using an “N-Place” global placement process for placing macros and standard cells in a VLSI floorplan.

[0058] FIG. 7 illustrates a process 700 for global placement of nodes in a VLSI floorplan in accordance with disclosed embodiments. A “node” refers to any VLSI object to be placed as described herein, whether a cell, a macro, or a macro group. In various embodiments, this global placement method can be used for placement of mixed macros and standard cells during floorplan creation, and can be used for placement of standard cells in the physical IC design stage.

[0059] At 702, the system models each of a plurality of nodes as a nuclear charge proportional to the area of the node on the floorplan.

[0060] At 704, the system models the repulsive potential of each of the plurality of nodes with respect to each other node. According to disclosed embodiments, this can be performed by modeling the repulsive potential using the anti-Yukawa potential (nuclear force) calculated by qr<p(r) = — ero r where (p is repulsive nuclear force, r is the radial distance between a pair of nodes, q is the attributed nuclear charge, e is Euler’s number, and rO is a selectable tuning parameter used to adjust the repulsive potential modeling range. An example of an acceptable value for rO is 0.5 (of chip width / height). Note that as r0-» co, this equation reduces to a calculation of electric potential.

[0061] At 706, the system determines the attractive wire force between each pair of nodes, as known to those of skill in the art.

[0062] At 708, the system determines the nuclear field (N-field) for each node according to the charge density of each node. To do so, the system can calculate a density grid for the floorplan and each node, then use a Fast Fourier Transform (FFT) of the charge density of each node to computer the N-field for each node.

[0063] At 710, the system places each of the nodes within the floorplan according to the nuclear field of each node and the attractive wire force between each pair of nodes.In placing each node, the system attempts to balance the attractive wire forces acting on each node with the repulsive N-field forces acting on each node. This process can include making an initial placement of some nodes as described herein (e.g., by placing large macros on chip borders or in specific regions), then placing each subsequent node according to the nuclear field of each node and the attractive wire force between the current node and those already placed. Further, after initial placement, the system may move each node as necessary to optimize placement for balancing the repulsive nuclear field force and the attractive wire force, including by using Nesterov’s Method, known to those of skill in the art.

[0064] Returning to the process of FIG. 6, at 604, the system performs a legalization process for the global macro placement. “Legalization,” in this context, refers to ensuring that the placement of all objects does not violate any design rules, such as overlap of objects, overrunning the chip edge, or others as known to those of skill in the art.

[0065] In various embodiments, the system can perform simulation annealing-based (SA) legalization. Simulated annealing is a probabilistic technique for approximating the global optimum of a given function. Specifically, it is a metaheuristic to approximate global optimization in a large search space for an optimization problem. For large numbers of local optima, SA can find the global optima.

[0066] FIG. 8 illustrates an SA legalization process 800 in accordance with disclosed embodiments.

[0067] At 802, the system performs SA iterations on the existing floorplan, including any nodes, including moving any nodes to address legalization requirements.

[0068] At 804, the sy stem performs a quality -of-result (QoR) analysis based on the SA iterations and current state of the floorplan. This can be performed, for example, every 1000 SA iterations. The QoR analysis can include, in addition to physical legalization requirements such as avoiding design rules, timing requirements, dead space, bottleneck, wiring issues, and others. The QoR analysis can include determining whether to perform a node modification as described below. The QoR analysis caninclude determining whether regrouping is required or advisable (when grouping has been performed).

[0069] At 806, the system can apply modification techniques. In this step, the system can perform post processing and determine what modification techniques are to be included, and can determine weighting, probabilities, or other tuning factors for those techniques as determined by the QoR analysis. These modification techniques can be used in the next SA operation (at 802). In this context, modification techniques do not refer to changing the structure of the node and its elements, but rather refers to performing certain modifications of the placement or arrangement of the node. The modification techniques can include, for example, sliding or shifting a node, flipping, inverting, or mirroring a node, swapping locations between two nodes, reshaping macro groups, and other such modifications.

[0070] In performing any modification technique, the system can apply a cost function to the macro distribution so that higher-level hierarchical constraints are honored.

[0071] At 808, the system can optionally rollback the state of the floorplan and related SA iterations. That is, the SA legalization process can continue with the current state, modifying it until legalization is complete, but if the QoR analysis results indicate that the QoR is actually worsening, the system can rollback to a previous state and attempt other node modifications. For example, in some case, the system could rollback to the state of the floorplan a certain number (such as 1000 or 2000) of SA iterations prior.

[0072] At 810, the system can perform a regroup process as described herein such as for step 610 below, when groups are being legalized. The system can determine whether to perform a regroup process based on the QoR analysis.

[0073] The process loops back to the SA iterations at 802 until the floorplan (or a selected portion of the floorplan) has been successfully legalized.

[0074] Returning to the process of FIG. 6, at 606 and 610, the system builds macro groups and globally places them within the floorplan. These two processes - building macro groups at 610 and global placement of macro groups at 606 - can be performed at the same time, so that the system places each macro group as it is built.

[0075] At 606, the system performs global placement of macro groups (excluding any manually-placed macros such as large macro placements 326). This can be performed as described above with respect to FIG. 7. Note that, since some macros may have been globally placed before grouping at step 602, those macros may be removed from their current placement when the macro groups are built, then re-placed as part of step 606.

[0076] At 610, the system builds macro groups, each group comprising a plurality of macros. In the simplest case, the system can simply build a macro group according to the logic hierarchy of each macro, so that each plurality of macros with the same logic hierarchy (such as according to a hierarchical netlist) is placed together in a macro group. However, various embodiments also can perform more complex macro grouping as described below, both of which can be considered timing-driven macro grouping to place macros in same hierarchical module together, and can be further ensure that macros with the same library cells are grouped together for proper alignment.

[0077] FIG. 9A illustrates a process 900 for building a macro group in accordance with disclosed embodiments.

[0078] At 902, the system assigns macro groups for each macro according to its “bin” on the floorplan. A floorplan (or selected portion of a floorplan) can be partitioned into grid areas referred to as “bins” or “buckets”. At 902, the system can initially assign all macros in a bin or in a group of bins to a single macro group.

[0079] At 904, from these initial groups, the system can build subgroups by grouping together any macros in a macro group that have cells from the same standard cell library.

[0080] At 906, from the subgroups, the system can build further subgroups by grouping together any macros in a macro subgroup that are on the same logical hierarchical level, then return the macro subgroups (as macro groups) to the calling process.

[0081] FIG. 9B illustrates another process 950 for building a macro group in accordance with disclosed embodiments.

[0082] At 952, the system initially assigns macro groups for each macro according to an instance name-based hierarchy, such as according to a hierarchical netlist.

[0083] At 954, from these initial groups, the system can build subgroups by grouping together any macros in a macro group that have cells from the same standard cell library.

[0084] At 956, from the subgroups, the system can build further subgroups by grouping together macro subgroups according to physical proximity-based clusters (using an algorithm such as Density-Based Spatial Clustering of Applications with Noise (DBSCAN)), then return the macro subgroups (as macro groups) to the calling process.

[0085] Returning to the process of FIG. 6, at 608, the system performs a legalization process for the global macro group placement. This can be performed for the macro groups as described above for the legalization of other floorplan nodes at 604. This legalization process can use the process of FIG. 8, including building new groups at 610 as necessary for the regroup process at 810.

[0086] Of course, those of skill in the art will recognize that, unless specifically indicated or required by the sequence of operations, certain steps in the processes described above may be omitted, performed concurrently or sequentially, or performed in a different order.

[0087] Those skilled in the art will recognize that, for simplicity and clarity, the full structure and operation of all data processing systems suitable for use with the present disclosure is not being depicted or described herein. Instead, only so much of a data processing system as is unique to the present disclosure or necessary for an understanding of the present disclosure is depicted and described. The remainder of the construction and operation of the computer systems disclosed herein may conform to any of the various current implementations and practices known in the art.

[0088] It is important to note that while the disclosure includes a description in the context of a fully functional system, those skilled in the art will appreciate that at least portions of the mechanism of the present disclosure are capable of being distributed in the form of instructions contained within a machine-usable, computer-usable, or computer-readable medium in any of a variety of forms, and that the present disclosure applies equally regardless of the particular type of instruction or signal bearing medium or storage medium utilized to actually carry out the distribution. Examples of machineusable / readable or computer usable / readable mediums include: nonvolatile, hard-coded type mediums such as read only memories (ROMs) or erasable, electrically programmable read only memories (EEPROMs), and user-recordable type mediums such as floppy disks, hard disk drives and compact disk read only memories (CD- ROMs) or digital versatile disks (DVDs).

[0089] Although an exemplary embodiment of the present disclosure has been described in detail, those skilled in the art will understand that various changes, substitutions, variations, and improvements disclosed herein may be made without departing from the spirit and scope of the disclosure in its broadest form.

[0090] None of the description in the present application should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope: the scope of patented subject matter is defined only by the allowed claims. Moreover, none of these claims are intended to invoke 35 USC §112(f) unless the exact words "means for" are followed by a participle. The use of terms such as (but not limited to) “mechanism,” “module,” “device,” “unit,” “component,” “element,” “member,” “apparatus,” “machine,” “system,” “processor,” or “controller,” within a claim is understood and intended to refer to structures known to those skilled in the relevant art, as further modified or enhanced by the features of the claims themselves, and is not intended to invoke 35 U.S.C. §112(f).

Claims

WHAT IS CLAIMED IS:

1. A method (300) for generation of a very -large-scale-integration floorplan (400), the method comprising: receiving (302) inputs (322, 324, 326) for automatic placements of macros in a floorplan (400): performing (304) an automatic macro placement process based on the received inputs (322, 324, 326); and generating (308) the floorplan (400) according to the automatic macro placement process, wherein the floorplan (400) can thereafter be used to generate a physical layout and a physical chip can thereafter be manufactured according to the generated physical layout.

2. The method of claim 1, wherein the automatic macro placement process (304) is timing driven to place macros (402) in a same hierarchical module near each other in the floorplan (400), and macros (402) with a same library are grouped together.

3. The method of claim 1 , wherein the automatic macro placement process (304) includes: performing (602) global macro placement of a plurality of macros (402) in the floorplan (400): performing (604) a legalization process for the global macro placement (602); building (610) macro groups (404), each macro group (404) having multiple ones of the plurality of macros (402); performing (606) a global macro group placement of the macro groups (404); and performing a legalization process (608) for the global macro group placement (606).

4. The method of claim 3, wherein the global macro placement (602) is based on modeled repulsive nuclear field forces and attractive wire forces between the plurality of macros (402) in the floorplan (400).

5. The method of claim 3, wherein the global macro group placement (606) is based on modeled repulsive nuclear field forces and attractive wire forces between the macro groups (404).

6. The method of claim 3, wherein the legalization process (604) for the global macro placement (602) is an iterative simulation annealing-based legalization using modification techniques.

7. The method of claim 3, wherein the legalization process (608) for the global macro group placement (606) is an iterative simulation annealing-based legalization using modification techniques.

8. The method of claim 3, wherein the legalization process (608) for the global macro group placement (606) includes performing a regroup process to form new macro groups (404).

9. The method of claim 3. wherein building (610) macro groups (404) includes: assigning macro groups (404) for each macro (402) according to a floorplan bin; grouping together macros (402) that have cells from a same standard cell library; and grouping together macros (402) that are on a same logical hierarchical level.

10. The method of claim 3. wherein building (610) macro groups (404) includes: assigning macro groups (404) for each macro (402) according to an instance name-based hierarchy; grouping together macros (402) that have cells from a same standard cell library; and grouping together macros (402) according to physical proximity based clusters.

11. The method of claim 3, further comprising placing a standard cell (710) in the floorplan (400) based on modeled repulsive nuclear field forces and attractive wire forces between the standard cell and the plurality of macros (402) in the floorplan (400).

12. A computer sy stem (101) compri sing : a processor (111); and an accessible memory (107), the computer system (101) particularly configured to perform a method as in any of claims 1-11.

13. A non-transitory computer-readable medium (107) encoded with executable instructions that, when executed, cause one or more computer systems (101) to perform a method as in any of claims 1-11.

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