Processing crossbar semiconductor device

Abstract

There is disclosed a processing crossbar semiconductor device for processing an input vector a weight tensor, to derive an output vector as processed version of the weight tensor, the weight tensor having a plurality of weights, the crossbar processing device being configured to process each input electric value of an array of input electric values representing the input vector, the processing crossbar semiconductor device comprising: a set of weighting elements (101) arranged according to element columns and elements rows, each weighting element corresponding to a weight of the weight tensor, wherein the set of weighting elements is partitioned among a plurality of blocks (102), the plurality of blocks (102) being arranged according to super columns (108) and super rows (106) in such a way that each super row includes a plurality of immediately subsequent element rows and each super column includes a plurality of immediately subsequent element columns; a plurality of block output buses, each being associated with, and connected to, a plurality of blocks in the respective super row without being connected to blocks associated with, and connected to other super row, each block output bus including a plurality of block output lines, wherein each block of the plurality of blocks is configured, when activated, to weight input electric values of the array of input electric values by corresponding weights of the weight tensor, to provide electric weighted values to the block output bus associated with the super row of which the block is part; and a plurality of analog accumulation elements, each electrically connected with a block output line, to thereby provide a respective electric accumulated weighted value from the electric weighted values obtained from the corresponding element columns of a plurality of activated blocks in the super row associated with the block output line, to derive an array of accumulated weighted output values which form the output vector.

Description

Processing crossbar semiconductor deviceThe present examples relate to a processing crossbar semiconductor device, e.g. for vector matrix multiplication (VMM) using analog in-memory computing. The ex- amples further relate to perform deep neural network processing.Analog in-memory computing using crossbar architectures is known to compute VMMs. The multiplication part of these VMM products may be computed by apply- ing an input activation voltage from an input matrix - either in analog using digital to analog converters, DACs, or in digital, e.g. selection bits, to a synapse circuit that results a proportional current or a charge, wherein the proportionality factor comes from the weight matrix. The accumulation part of the VMM computation happens inherently by the charge or current integration to a common node, namely a column in a crossbar. The integrated charge or current from a column is con- verted further to digital domain by employing analog to digital converters, ADCs. The existing solutions known to the authors, [1], [2], [3], employ a fixed number of synapses per crossbar column. This limits the configurability of weight vectors as- sociated to a neuron, and it leads to underutilization of the crossbar because of unused synapses. The limitation in configurability can also lead to complex map- ping scenarios. These disadvantages can become severe for longer columns, which can range from 128 as used in [4] to 2304 in [5].The present examples offer solutions to these problems e.g. by employing a con- figurable and scalable crossbar architecture, and other associated building block circuits such as a digitally configurable current source-based synapse cell, analog to digital converters, ADCs, Shift-Add circuit with built in offset and gain support, etc.Prior to delving into the details of the present examples, some information is pro- vided on how Vector Matrix Multiplications (VMMs) (e.g. as involved in a neuralnetwork) can be computed using a traditional in-memory computing architecture. Fig. 1 shows a fully connected layer of a neural network having inputs N of dimen- sion n and output neurons M of dimension m. This translates to VMMs given by the following matrix formula:Note that the neurons in Fig. 1 can be accompanied by a non-linear activation function, which is applied to the dot product results computed by the above equa- tion. Fig. 2 depicts a typical crossbar array according to the prior art for in-memory computing, showing R number of rows and C number of columns, where each el- ement represents a synapse weight W (the subscripts not being shown in Fig. 2, therefore W is used instead of W±1... Wln, etc.). The input activation lines, and the accumulation lines typically connect complete rows and columns of the crossbar respectively. To compute the M outputs of the fully connected layer, the inputs from the input matrix are applied to these activation lines, either in analog as voltages or in digital as select bits. The weights from the weight matrix are mapped on to the crossbar weight elements in the form of resistances or capacitances. Conse- quently, the accumulation lines generate currents or charges that are equivalent to the neuron pre-activation values. The activation functions that follow the accumu- lation results are not shown in Fig. 2. The bit lines and the word lines shown in Fig. 2 are used to configure the weights in the crossbar. Depending on whether the input matrix N and the output matrix M in equation (2) is longer or shorter than the number of rows R and the number of columns C of the crossbar respectively, the crossbar can map the fully connected layer in Fig. 1 partially or completely. Re- gardless of the size, the crossbar would have unused weights in the rows and col- umns, because the input lines and the accumulation lines physically connect the entire row or column.FiguresFig. 1 shows an example of fully connected layer which can be addressed to by the present examples.Fig. 2 shows an example of a crossbar according to the prior art.Fig. 3 shows an example according to the present disclosure.Fig. 4 shows the operation of the example of Fig. 2.Fig. 5, 6, 7, and 8 show optional features of possible components of the example of Fig. 3.According to an aspect there is provided a processing crossbar semiconductor device for processing at least one input vector by at least one weight tensor, to derive at least one output vector as processed version of the at least one weight tensor, the at least one weight tensor having a plurality of weights, the crossbar processing device a multiple input line including a plurality of single input lines, each single input line being configured to process each input electric value of an array of input electric values representing the at least one input vector, the pro- cessing crossbar semiconductor device comprising: a set of weighting elements arranged according to element columns and el- ements rows, each weighting element corresponding to a weight of the at least one weight tensor, wherein the set of weighting elements is partitioned among a plurality of blocks, the plurality of blocks being arranged according to super col- umns and super rows in such a way that each super row includes a plurality of immediately subsequent element rows and each super column includes a plural- ity of immediately subsequent element columns; a plurality of block output buses, each block output bus being associated with, and connected to, a plurality of blocks in the respective super row without being connected to blocks associated with, and connected to at least one othersuper row, each block output bus including a plurality of block output lines, wherein each block of the plurality of blocks is configured, when activated, to weight input electric values of the array of input electric values by corresponding weights of the at least one weight tensor, to provide electric weighted values to the block output bus associated with the super row of which the block is part; and a plurality of analog accumulation elements, each analog accumulation ele- ment being electrically connected with at least one block output line, to thereby provide a respective electric accumulated weighted value from the electric weighted values obtained from the corresponding element columns of a plurality of activated blocks in the at least one super row associated with the at least one block output line, to derive an array of accumulated weighted output values which form the at least one output vector.The processing crossbar semiconductor device may be so that each block of a super row is configured to activate a plurality of weighting elements simultane- ously, to thereby provide, to the respective block output lines and through the weighting elements, the electric weighted values simultaneously, so that each an- alog accumulation element that receives the electric weighted values from the same block output line has the accumulation value simultaneously.The processing crossbar semiconductor device may be so that each weighting el- ement is configured to provide a current analogically obtained by weighting the in- put electric values, so that the respective accumulation element provides at least one of an accumulated weighted current as the electric accumulated weighted value.The processing crossbar semiconductor device may be so that each weighting el- ement is configured to provide a charge and / or a voltage analogically obtained by weighting the input electric values, so that the respective accumulation elementprovides an accumulated weighted charge and / or an accumulated weighted volt- age as the electric accumulated weighted value.The processing crossbar semiconductor device may be so that at least one elec- tric input value encodes a binary value, so that a first electric level of the at least one electric input value corresponds to a first logical level of the binary value and a second electric level of the at least one electric input value corresponds to a second logical level of the binary value, each of the relating weighting elements being configured to process the electric input value according to a weight which is selected between more than two weight values.The processing crossbar semiconductor device may be so that at least one of the weighting elements is configured to select between a first current generator providing a first current and a second current generator providing a second cur- rent, wherein the weighting element is configured to selectabiy route each of the first current and the second current, independently of each other, to a respective conductor chosen between a first conductor of the respective block output line and a second conductor of the of the respective block output line, so that the re- spective block output line carries one selected of multiple selectable levels of the weighted output value.The processing crossbar semiconductor device may be so that at least one of the relating weighting elements is configured to select between at least one positive polarity, thereby generating a positive weight, and one negative polarity, thereby generating a negative weight, by awarding a larger electric level to a positive con- ductor or electrode of the analog accumulation element than to a negative con- ductor or electrode of the analog accumulation element in case of positive electric weighted value, and by awarding a larger electric level to the negative conductoror electrode than to the positive conductor or electrode in case of positive electric weighted value.The processing crossbar semiconductor device may be so that the plurality of an- alog accumulation elements are gathered in analog accumulation element buses, each of the analog accumulation element buses being connected with, and asso- ciated to, at least one block output bus, each analog accumulation element of each analog accumulation element bus being connected to at least one block out- put line of the associated at least one block output line, to accumulate weighted electric values from the same element columns of the blocks of at least one super row associated with the associated at least one block output bus.The processing crossbar semiconductor device may be so that at least one ana- log accumulation element bus is associated with, and connected to, at least a first block output bus associated with, and connected to, a first super row and a sec- ond block output bus associated with, and connected to, a second super row, so that each analog accumulation element of the analog accumulation element bus provides an electric accumulated weighted value accumulated from the electric weight values from both first blocks of the first super row and second blocks of the second super row.According to an aspect, the processing crossbar semiconductor device further comprises at least one analog to digital, ADC, converter to convert at least two electric accumulated weighted values from at least two analog accumulation ele- ments, respectively.The processing crossbar semiconductor device may convert at least one electric accumulated weighted value onto one single bit in accordance to the electric level of the electric accumulated weighted value.The processing crossbar semiconductor device may be configured to convert at least one electric accumulated weighted value onto a plurality of bits in accord- ance to the electric level of the electric accumulated weighted value, the weight level .The processing crossbar semiconductor device may be configured to convert multiple accumulated weight values, from different accumulation elements, onto a super string of bits, by converting at least one first electric accumulated weighted value onto at least one least significant bit or least significant string, and at least one second electric accumulated weighted value onto at least one most signifi- cant bit or most significant string.The processing crossbar semiconductor device may further comprise at least one digital accumulation element to accumulate different accumulated weighted val- ues, once converted in digital, from different analog accumulation elements or from different analog accumulation element buses.The processing crossbar semiconductor device may be configured so that a first block a first super row, which is associated with a first block output bus, contains a selectable multiple connection with a second block of a second super row, the second super row being associated with, and connected to, a second block out- put bus but being not associated with, and not connected to, the first block output bus, wherein the first block output bus is connected to, and associated with, a first analog accumulation element bus including a plurality of first analog accumulation elements and the second block output bus is connected to a second analog accu- mulation element bus including a plurality of second analog accumulation ele- ments, none the first analog accumulation elements being connected to any of the second analog accumulation elements, the selectable multiple connectionelectrical ly connecting, when selected, the first block with the block output bus, in such a way that the weighted electric values from the first block are provided to the second block output bus, and to the second analog accumulation element bus.The processing crossbar semiconductor device may be so that a plurality of blocks of at least one super column are electrically connected two by two through a plurality of selectable multiple connections, in such a way to selectably provide weighted values obtained at a first block of a first super row to a second block output bus which is not electrically connected to a first block output bus to which the first super row is connected.The processing crossbar semiconductor device may be configured to evaluate whether the input vector has more elements than the element rows of first blocks of a first super row, so that, in case of the input vector having more elements than the number of element rows in each first block of the first super row, to distribute electric input values between the element rows of the first blocks of the first super row and element rows of second blocks of at least one second super row, and to selectably provide electric weighted values from each of the first blocks of the first super column to at least one of the further blocks of the second super row, the second blocks thereby providing to the same block output bus, with which they are associated, both the weighted values from the first blocks and the weighted values from the further blocks.The processing crossbar semiconductor device may be so that the plurality of blocks includes a first subplurality of blocks and a second subplurality of blocks disjoint from the first subplurality of blocks, the plurality of block output buses in- cluding a first subplurality of block output buses uniquely connected to blocks of the first subplurality of blocks and a second subplurality of block output busesuniquely connected to blocks of the second subplurality of blocks, wherein the second subplurality of blocks is selectably activatable and deactivatable.The processing crossbar semiconductor device may be so that the plurality of an- alog accumulation elements includes at least a first subplurality of analog accu- mulation elements to accumulate electric weighted values from the first subplural- ity of blocks and a second subplurality of analog accumulation elements to accu- mulate electric weighted values from the second subplurality of blocks, the pro- cessing crossbar semiconductor device further comprising a plurality of further accumulation elements, each further accumulation element being configured to accumulate a weighed electric value obtained by accumulating both a first weighted electric value from a first analog accumulation element of the first sub- plurality of blocks and a second weighted electric value obtain from a second an- alog accumulation element of the second subplurality of blocks.The processing crossbar semiconductor device may be so that the further accu- mulation element is a digital accumulation elements.The processing crossbar semiconductor device may be configured to evaluate whether the output vector to be obtained has more elements than the number of element columns of the first subplurality of blocks, so as to activate, in case the output vector has more elements than the number of element columns of the first subplurality, a number of super columns of blocks of the second subplurality of blocks, so that the number of columns of the activated super columns of blocks at least matches the number of elements of the output vector.The processing crossbar semiconductor device may be so that the second sub- plurality of blocks are selectively activatable and deactivatable.The processing crossbar semiconductor device may be so that each analog ac- cumulation element is a resistor which receives the weighted electric values from the weighting elements of the same element row in multiple blocks of at least one super row, so that the respective electric accumulated weighted value becomes a sum of the weighted electric values.The processing crossbar semiconductor device may be so that the weighted elec- tric values are currents, and the electric accumulated weighted value is a current which is the sum of the currents from the block output lines.The processing crossbar semiconductor device may be so that each analog ac- cumulation element is a capacitor which receives the weighted electric values from the weighting elements of the same element row in multiple blocks of at least one super row, so that the respective electric accumulated weighted value becomes a sum of the weighted electric values which are charges or voltages.The processing crossbar semiconductor device may be configured to activate dif- ferent blocks independently of each other.The processing crossbar semiconductor device may be configured to activate simultaneously multiple blocks of the same super row, in such a way that weighting elements connected to the same block output line provide electric weighted values to the same block output line to thereby provide the electric weighted values.According to an aspect, the processing crossbar semiconductor device may be configured to receive the array of electric values as at least a first input vector and a second input vector independent from the first input vector, the first inputvector being inputted to a first super row of blocks and, simultaneously, the sec- ond input vector being provided to a second super row of blocks.The processing crossbar semiconductor device may be so that the weighting ele- ments of each block are configured to provide, in parallel, respective electric weighted values to respective block output lines, thereby preaccumulating the electric weighted values in the same output line.The crossbar processing device may be configured to implement a neural net- work according to a plurality of layers, including an input layer, an output layer, and optionally at least one hidden layer, wherein each transition from a layer to the immediately subsequent layer is performed by processing the analog input vector, wherein each weight of the at least one weight tensor represents a synap- sis, each analog input value is a neuron, and each output value is a neuron of the immediately subsequent layer.The processing crossbar semiconductor device may be so that the analog input vector is a kernel, or a portion of kernel, to be convolutionally applied to the at least one weight tensor.The processing crossbar semiconductor device may be configured to perform af- ter a first phase in which the weights of the at least one weight tensor are ob- tained by minimizing a cost function providing error metrics on a known dataset, an inference phase in which the weights of the weight tensor are established, and predictions are provided in response to input values.According to an aspect there is provided a method (e.g. using any of the device above or below) for at least one input vector by at least one weight tensor, to de- rive at least one output vector as processed version of the at least one weighttensor, the at least one weight tensor having a plurality of weights, the method in- cluding processing each input electric value of an array of input electric values representing the at least one input vector, the method using weighting elements arranged according to element columns and elements rows, each weighting ele- ment corresponding to a weight of the at least one weight tensor, wherein the set of weighting elements is partitioned among a plurality of blocks, the plurality of blocks being arranged according to super columns and super rows in such a way that each super row includes a plurality of immediately subsequent element rows and each super column includes a plurality of immediately subsequent element columns, the method further using a plurality of block output, each block output bus being associated with, and connected to, a plurality of blocks in the respec- tive super row without being connected to blocks associated with, and connected to at least one other super row, each block output bus including a plurality of block output lines, the method comprising: activating weighting input electric values of the array of input electric values by corresponding weights of the at least one weight tensor, to provide electric weighted values to the block output bus associated with the super row of which the block is part; and providing, through a plurality of analog accumulation elements, each ana- log accumulation element being electrically connected with at least one block out- put line, a respective electric accumulated weighted value from the electric weighted values obtained from the corresponding element columns of a plurality of activated blocks in the at least one super row associated with the at least one block output line; and deriving an array of accumulated weighted output values which form the at least one output vector.According to an aspect there is provided a non-transitory storage unit storing in- struction which, when executed by a processor, cause the processor to perform the above method.According to an aspect the crossbar processing device further comprises a con- troller to activate at least one among the following: at least one block, at least one super row, at least one super column, at least one element row, at least one bypassing connection, at least one subplurality and / or to associate weights to re- spective weight elements, input electric values to element rows, and / or output electric values to element columns of at least one block.ExamplesThe present examples solve, or at least alleviate, the problem described above by means of a field-configurable crossbar array architecture, see Fig. 3, which is equipped with architectural and circuit features described below.Before describing the present examples further, it is to be noted that the scope of the present examples is not limited to the specific parameter dimensions that are used in Fig. 3 to describe the present examples, e.g. number of element rows and a number of element columns, but includes all other possible dimensions.Fig. 3 shows an example of a processing crossbar semiconductor device 100 ac- cording to one of the present examples. The processing crossbar semiconductor device may perform a multiplication in analog domain between a matrix and a vec- tor. It is here noted, notwithstanding, that the concept of matrix can be generalized to tensor, i.e., having a number of dimensions which is generic (e.g., three dimen- sions). For example, the tensor could be the matrix of formula (1 ),but there could be a plurality of channel representing another matrix in a third di- mension, e.g. a first channel could be a second channel couldbe , and a p-th channel could be . The processing crossbar semiconductor device may therefore process at least one input vector, which may be analog or digital, but in general terms may be in the form an array of electric values through the plurality of weights of a weight tensor, thereby generating an output vector (either in digital form or in analog form). Just to give an example, there could be (in the example of Fig. 3) e.g., 16 input electric values, thereby forming an array of input electric values, which also represents an input vector.The input vector may be analog or digital (in case of being digital, it may be con- verted onto an analog value encoding the digital value). Therefore, the electric val- ues which represent the input vector may be either digital values, each which in principle can only be encoded in two logical states (e.g. a first logical state repre- sented by a first electric level, and a second logical state represented by a second electric value different from the first electric value) or strings of logical states, or analog values (e.g. ideally defined in a continuous interval of analog values). The input values may be provided in the form of voltages, charges, currents, and so on, either in digital form or in analog form. The processed values (e.g.,. weighted val- ues, accumulated weighted values, etc.) may be analog values (e.g. in the form of at least one of voltages, charges, currents, and so on), in case being converted form the digital domain. The output elements (e.g. elements of the output vector) may be either analog values (e.g. in the form of at least one of voltages, charges, currents, and so on), or digital values (e.g. after the processed values being con-verted from analog to digital values. It will be shown that weightings are here per- formed in analog domain, but accumulations are either performed in analog domain (e.g., by summation of several weighted electric values from multiple weightings in each accumulation element) or, in some examples, include a first, analog step (e.g., in which a summation of several weighted electric values from multiple weightings is performed at several, different analog accumulation elements), the first step being followed by a second step, in which, after a conversion of analog accumulated weighted values onto digital versions of the accumulated weighted values, digital versions of the accumulated weighted values provided by different analog accumulation elements are summed with each other in digital version. Therefore, while in some examples the input values and the output values are dig- ital, their processing in advantageously performed in analog domain, thereby sav- ing from power consumption and increasing processing rate.Hence, the input vector is to be processed (e.g., multiplied, weighted, scaled) by a weight tensor, with weights defined in different dimensions (in the case of the ma- trix, the dimensions will be two, the weight tensor being a weight matrix, while in the case of three dimensional tensors, dimensions will be three and the weight tensor will be a three dimensional tensor). In Fig. 3 each of the little rectangles 101 represents a weighting element, which corresponds to a weight to be applied to an input electric value, while the input vectors are or are part of kernels, such as the kernels K0_0 (301 ), K0_1 (302), K1_0 (303), K1_1 (304). Therefore, in the time instant depicted by Fig. 3, the input vectors are multiplied by the weights in the positions 301 , 302, 303, 304.As can be seen in Fig. 3, the matrix elements (tensor elements) are organized in a matrix style arrangement, with a matricial disposition along a plurality of element columns (identified as vertical in the figure) and a plurality of element rows (indi- cated horizontally in the drawing). It may be understood that each element row isassociated with (e.g. inputted by and / or processing) a particular input electric value (e.g., all the weighing elements in a specific element row are applied to the same electric input value) (e.g. the input may be a digital value, which may be converted onto an analog value e.g. by the weighting element 101 or upstream to the weighting element 101 ), while each element column (e.g. of a plurality of blocks of the same super column) may be associated with (e.g. may provide, may output) one particular output value (e.g. analog value). It will be understood, however, that in order to increase configurability, it is possible to selectably use multiple element columns (e.g. corresponding element columns in multiple blocks, the multiple blocks being in the same super row but in different super rows, see below) for the same output value or, selectably, use the different elements columns for different inputs. Moreover, it is possible to selectably use multiple element rows (e.g., cor- responding element rows in different blocks, the different blocks being in the same super column but in different super rows, see below) for the same electric input value, for example, or selectably use them for different electric input values. Fig. 6 shows examples of weighting elements for weighting electric input vectors con- trolled by the digital inputs djn, djno, djni, djna (which in this case control the provision of the supply voltage Vdd) As shown in Fig. 6, each weighting element (also called CS_AWE, see below) has a conventionally positive terminal voutjc and a conventionally negative terminal vout_n, which constitute a connection port with a relative block output line (OL-Ao, OL-Ai OL-A2, OL-A31, see below); in particular, vout_p may be connected to a conventionally positive terminal of the block output line, and vout_n may be connected to a conventionally negative ter- minal of the block output line). As shown in Fig. 6, at least one among deviations (e.g. bifurcations), choice of one single generator (e.g. current generator) among a first and a second generators, choice of the polarity (e.g. by selectively exchanging the highest electrical value between vout_p and vout_n) may permit to select one among multiple (in particular more than 2) weights of the weighting element, so as to advantageously process the weighting of the binary value according to a subbinary resolution. It is noted that it may be that all the weighting elements 101 of an element row of a block provide the electric weighted values to the same block output line simultaneously and in parallel, so that the block output line acts as a pre-accumulating output line which pre-accumulates multiple weighted values of the same element column of the same block.Fig. 3 shows a plurality of block output buses, here indicated with OL-A0-3, OL-A4- 7, OL-As-n, OL-A28-31. Each block output bus (which may be understood as a multiple output line, or a group of lines in parallel) may include a plurality of single output lines (e.g. in parallel connection with each other for each block output bus), not electrically connected with each other, and here called block output lines (each of the block output lines may have only one single voltage value at a given time instant, while the block output bus may represent an array of multiple voltage val- ues at the given time). The block output bus OL-A0-3 is shown to include the four output lines OL-Ao, OL-A1 OL-A2, OL-A3 (different numbers are also possible). Each of the block output lines OL-Ao, OL-A1 OL-A2, ... , OL-A31 may a dual channel (e.g. with only one first positive conductor, connected to vout_p and one negative con- ductor connected to vout_n), but different implementations are possible (e.g., each single output line could only have one single conductor, and a common analog ground could be used instead of the second conductor; however, it has been un- derstood that the use of two different conductors instead of a common analog ground is advantageous: primarily because the use to the common ground can lead to process dependent errors such as from PVT variations, and also can add asymmetric electric parasitic capacitances I resistances. Additionally, in the ab- sence of even a common analog ground, it is possible to define a polarity, providing a sign to the weight, thereby permitting to define negative weights). Examples of conductors (conventionally chosen as positive conductor) and (conventionally cho- sen as negative conductor) are not shown, but Fig. 6 shows a positive terminalvout_p of the weighting element and a negative terminal vout_n which are con- nected to the conventionally chosen as positive conductor and conventionally cho- sen as negative conductor, respectively. It will be shown that each output bus is connected to, and associated with, one particular groups of weighting elements (or more in particular of blocks of weighting elements which are in the same super row, see below), but is not connected to, and not associated with, other groups of weighting elements (or more in particular of blocks of weighting elements which are in different super rows, see below). Analogously, each of the block output bus OL-Ao, OL-Ai OL-A2, OL-A31 is meant at receiving analog weighted values only from some portions of element columns (i.e., each block output line receiving weighted values from corresponding weighting elements displaced in element col- umns of blocks of the same super row), but not from the totality of the weighting elements of any global element column. In general terms, each of the block output lines OL-Ao, OL-A1 OL-A2, OL-A3 is electrically disconnected from any other of the block output lines OL-Ao, OL-A1 OL-A2, OL-A3 of the same block output bus OL-Ao-3.Each block output bus OL-A0-3, OL-A4-7, OL-As-n, .... OL-A28-31 is in generally elec- trically disconnected from other block output buses, or at least from the some of them (e.g., the majority of them), or analogously each of the block output lines OL- Ao, OL-A1 OL-A2, OL-A3 of a generic block output bus OL-A0-3 is electrically discon- nected from block output lines buses of other block output buses, or at least from the some block output lines buses of other block output buses (e.g., the majority of the block output lines buses of other block output buses). For example, the block output bus OL-A0-3 is in general electrically separated from the OL-A4-7 and also from OL-As-n, OL-A12-15, OL-A20-23, OL-A24-27, OL-A28-31 (i.e. from the majority of other block output buses). As it will be shown later, there is an option according to which the block output bus OL-A0-3, despite not directly connected with the block output bus OL-A16-19 notwithstanding provides its weighted electric values to thesame analog accumulation elements (AL0-3) to which also OL-A16-19 provides its electric weighed values (and, in the same example it may be that OL-A4-7 and OL- A20-23 despite not directly connected to each other, are notwithstanding connected to the same analog accumulation elements AL4-7; OL-As-u and OL-A24-27 could pro- vide their weighted values to the same analog accumulation elements AL.8-11; and so on). However, apart from this, each block output bus may be electrically sepa- rated from the majority of other block output buses, and in particular it may be separated from the immediately closest block output bus close to it. Therefore, dif- ferent block output buses may be associated to (e.g.,. connected with) the same analog accumulation element bus, but not electrically connected with each other directly, but electrically connected with each other only through said same analog accumulation element bus. It has been noted that it is preferable that, by moving along one columnar direction, a regular interval between the groups of block output buses connected with each other is defined (e.g., so that the distance between two closest block output buses connected with each other is either constant): in the case of N block output buses (e.g. N=8 in Fig. 4) and with connections of couples of block output buses, we may have that the first block output bus (OL-A0-3) is con- nected with the (N / 2+1 )th(e.g. 5th) block output bus (OL-A16-19); the second block output bus (OL-A4-7) is connected with the (N / 2+2)th(e.g. 6th) block output bus (OL- A20-23); and the (N / 2)th(e.g. 4th) block output bus (OL-A12-15) is connected with the Nthoutput line (OL-A28-31). This arrangement can provide optimal tradeoff between configurability (which is to be maximized) and number of multiplexers (which is to be minimized), and also permits to minimize parasitic capacitances. In practice, an interval is defined so that different block output buses connected to the same ana- log accumulation element bus have a constant number of other block output buses (e.g., between OL-Ao s and OL-A16-19 there are three other block output buses; and between OL-A4-7 and OL-A20-23 there are three other block output buses, and so on). In practice, the block output buses may be displaced according to a periodicinterval for which between two block output buses connected to the same analog accumulation element bus there is a constant number of other block output buses.As can be seen, the block output buses OL-A0-3, OL-A4-7, OL-As-n, ... , OL-A28-31 may traverse the semiconductor processing device in parallel to the elongation of the element rows in the device, in some examples.As shown from Fig. 3, each block output bus OL-Ao, OL-A1 OL-A2, ... OL-A31 may be connected to one accumulation element bus ALo, AL1, AL2, ... AL31 (which is a single accumulation line). Multiple of these accumulation element buses ALo, AL1, AL2, ... AL31 (shown, for example, in Fig. 7) may be gathered together in accumu- lation element busses AL0-3, AL4-7, ALs-n, ... , AL28-31. For example, the accumula- tion element bus AL0-3 may include (gather) an array of analog accumulation ele- ments ALo, AL1, AL2, AL3, while the accumulation element bus AL4-7 may include an array of analog accumulation elements AL4, AL5, ALo, AL7, and so on. Each single accumulation element (e.g. ALo, AL1, AL2, AL3) may be electrically con- nected, in downstream, to at least one respective block output line (e.g. OL-Ao, OL- A1 OL-A2, OL-A3). In practice, at least one block output bus is connected to one single, respective accumulation element bus, and all the block output lines of each block output bus connected with a given accumulation element bus are connected to a respective analog accumulation element of the given accumulation element bus. While each block output bus is connected with one single accumulation bus, each accumulation bus can be connected with a plurality of block output buses. For example, the accumulation element ALo may be electrically connected to both the output line OL-Ao and the output line OL-A16. Since, as it may be mentioned, each output line is fed with analog electrical values coming from a group of weighting elements of the processing crossbar semiconductor device, the accumu- lation line (e.g., ALo) will be affected by an integral information of the weighted electric values (e.g. in accumulative form) obtained from those weighting elements.It may be understood that each analog accumulation element ALo, ALi, ... AL31 may comprise, for example, a resistor through which a current flows which is the sum of the currents outputted from the weighting elements to which the analog accumulation element is electrically connected (e.g. the current of the analog ac- cumulation element ALo may be the sum of the currents received from the single output line OL-Ao and, in some examples, under a suitable selection also form the single output line OL-A16-19, which are in turn received from weighting elements of corresponding columns of the blocks associated with the single output lines OL-Ao and OL-A16-19). In addition or in alternative, instead of currents the weighted electric values may be provided as voltages and / or charges generated by the different weighting elements. Each analog accumulation element ALo... AL31 may be capac- itor, and its charge may be the sum of the effects of the output of the different weighting elements to which it is electrically connected (in this case, it may be pref- erable to avoid the current generators in Fig. 6, for example).As shown by Fig. 3, the weighting elements 101 may be gathered in the blocks also called case and indicated globally with 104 (inf Fig. 3 there are shown partic- ular blocks 104-00, 104-01 , 104-10, 10411 ). For example, in Fig. 3 there are blocks 104 each with 16 rows and 4 columns (not all the 16 rows are shown for simplicity). Therefore, each block (CAE) can be a matrix 16x4 (of course, the different numbers of columns can be chosen for different matrixes). As can be seen in these exam- ples, the blocks are also arranged according to super rows 106 (elongated along the element rows, horizontal in Fig. 3) and super columns 108 (elongated along the element columns, vertical in Fig. 3). In particular, the super row are indicated from the top to the bottom with 106-0, 106-1 , 106-2, 106-3, 106-4, 106-5, 106-6, 106-7. The super columns 108 are indicated from left to right with 108-0, 108-1 , 108-2, 108-3, etc. For example, the block 104-00 on the top left is part of the top super row 106-0 (together with block 104-10 and all the blocks behind it) and the leftsuper column 108-0 (together with block 104-01 , and the blocks on its right). There- fore, each super row 104 includes a plurality of immediately subsequent element rows (e.g. the top super row 106-0 includes the top 16 elements rows of the device, and the second top super row 106-1 includes the 17thto 32ndelement rows of the device) and each super column includes a plurality of immediately subsequent el- ement columns (e.g. the left super column 104-0 includes the most left 16 elements columns of the device, and the second lest super column 104-1 includes the 17thto 32ndelement column of the device). For each block 104 of a determined super row 106, each element column is electrically connected to one block output line (e.g., the most left element column of each of the blocks 104-00, 104-01 , etc. of the same super row 106-0 is connected to the block output line OL-Ao; the second most left element column of each of the blocks 104-00, 104-01 , etc. of the same super row 106-0 is connected to the block output line OL-Ai; and so on). The con- nection of a given element column of a block with a respective block output line may imply that all the weighting elements of the given element column are con- nected to the respective block output line, thereby providing the weighted electric values to the respective block output line. Moreover, multiple corresponding ele- ment columns of different super columns but in the same super row are connected to the same block output line. Corresponding element columns in different blocks of the same super row may be electrically connected to the same block output line, to thereby provide weighted outputs to be accumulated by the corresponding ac- cumulation element ALo. It is to be noted that therefore, for each super row all the corresponding columns of all the blocks are electrically connected to the same ac- cumulation element. It may be understood that the blocks 104 in different super rows 106 are connected to different block output buses (and therefore different block output lines), which are in general electrical independent from the other block output buses (or at least the majority thereof). Apart from the correspondences such as the correspondence between OL-A0-3 and OL-A16-19 connected to the sameanalog accumulation elements ALo, ALi, Al_2, AL3 (or OLAw with OL-A20-23 con- nected to the same accumulation element buses AL0-3, AL4-7, etc.), blocks 104 of different super rows 106 route their weighted electric values to different analog accumulation elements. (It is maintained that the blocks of the super row connected to the block output bus OL-A16-19 can, in some examples, be accumulated together with the weighted values of the connection line OL-A0-3.). In general terms, each super row 106 is associated with one single block output bus (e.g. the top super row 106-0 being associated with and connected to the first block output bus OL-Ao- 3, the second top super row 106-1 being associated with and connected to the block output bus OL-A4-7 and so on).It is to be noted that the weighed values provided by the blocks 104 of a super row (e.g. 106-0) are in principle independent from weighed values provided by another super row (e.g. 106-1 ): this is other, for example, from the prior art of Fig. 2, where all the weighting elements of a column shall provide an output to the same accu- mulation line. Notably, different super rows (e.g., 106-0 and 106-1 ) may be simul- taneously used for processing different electric input values. Since the same elec- tric input value is provided to all the processing elements 101 of the same element row (which is therefore shared by all the blocks 104 of the same super row), it is possible to provide two different input vectors (independent from each other) to different super rows (e.g., 106-0 and 106-1 ), and simultaneously obtain different weighted accumulation values which to be outputted as output values independent of each other. For example, in Fig. 3 the kernels K_0_0 (301 in block 104-00) and K0_1 (302 in block 104-1 ), in the top super row 106-0, have the same electric input values with each other, while the kernels K_1__0 (303 in block 104-10) and K _1 _1 (304 in block 104-11 ) have another electric input value (being applied to different element rows in the second top super row 106-1 ) which share nothing with K__0_0 (301 ) and K0 1 (302). Notwithstanding, and advantageously, all the kernels K_0_0(301 ), K0_1 (302), K_1_0 (303), and K _1 _1 (304) can be processed simultane- ously. This would not be possible in Fig. 4 (representing the prior art), where ker- nels K_0_0 (401 ) and K_0_1 (402) cannot be simultaneously processed with K_1_0 (403) and K_1_1 (404) in the same column of 401 and 402, by virtue of the fact that it would not make sense to use the same vertical accumulation line for different kernels. With the present examples like in Fig. 3, by virtue of the fact that different super rows 106 of blocks 104 rout different weighted values to different accumulation element buses, it is advantageously possible to operate with multiple input vectors simultaneously.It shall be noted, that, in some examples, all the blocks 104 can be activated sim- ultaneously. More in general, multiple blocks 104 can be activated simultaneously. However, in some examples, even though different blocks 104 can be activated simultaneously, they can be activated in selectable independent way: it may be decided, for example, that some blocks 104 are not to be activated at all, thereby advantageously reducing the power consumption. Notwithstanding, when activated simultaneously, an increased speed is increased. In examples, the blocks 104 are activated independently of each other, thereby energizing only those block which are actually used to perform weightings, without energizing the non-activated block. In examples, it is possible to activate the weighting elements selectively, within each block 104, so as to reduce power consumption at the minimum. In other ex- amples, different weighting elements of the same block 104 are activated simulta- neously, even if they are not used for weighting.It is noted that the possibility of having several super rows (e.g. 106-0, 106-4) of blocks 104 to be connected to the same analog accumulation element bus (e.g. AL0-3) allows processing an input vector with a number of elements which is larger than the number of element rows in the blocks (for example, in Fig. 3 each block has 16 rows and each kernel K_0_0, KJ)_1 , K_1_0, K_1 1 , has 16 electric inputvalues). In the case in which a input vector has more than 16 electric input values (e.g., between 17 and 32), then it is possible to further activate, beside the top super row 106-0, also the second top super row 106-1 , which is associated with the block output bus OL-A16-19 which is electrically connected to the same analog element bus AL0-3: therefore, the 17thto 32ndinput value will be provided to that super row. Basically, it is possible to distribute exceeding input vector elements to further blocks of further super rows. Accordingly, the kernel will be partially pro- vided to the first super row (top super row in Fig. 3) and other remaining 16 electric input values will be provided to the super row connected to the output line OL-A16- 19 (and providing output weighted values to the same accumulation line AL0-3)It has been understood, moreover, that it is possible to further increase the config- urability of the processing crossbar semiconductor device 100. In particular, it has been understood that, instead of (or in addition to) relying on the connection be- tween different block output buses connected to the same analog accumulation element bus (e.g. OL-A0-3 and OL-A16-19 being connected to the same analog ac- cumulation element bus AL0-3), it is further possible to connect blocks of a super row to a block output bus associated with a different super row (e.g., to connect blocks 104-00, 104-01 , etc. of the top super row 106-0 to the block output bus OL- A4-7 associated with the second top super row 106-1 instead of the block output bus OL-A0-3 which is associated with the top super row 106-0). According to exam- ples, blocks of the same super column (e.g. ) can, in some examples, exchange weighted values with each other, thereby bypassing some block output buses(e.g. block 104-00 of the left super column 108-0 can transmit weighted values to block 104-10 of the same left super column 108-0, while it may be that simultaneously block 104-01 of the second left column 108-1 transmits weighted values to block 104-11 of the same second left column 108-0).An example is provided by comparing Fig. 3 with Fig. 5. In some cases it could be preferred to have a single kernel formed the by 301 and 303 (in this particular case, 301 and 303 are not different kernels, but two portions of the same kernel), or more in general an input vector is longer (in number of rows) than the number of rows of each block 104. In this case, it could be preferable to provide all the electric weighted values to the same analog accumulation elements, and not to different single analog accumulators. However, in Fig. 3, the blocks (104-00, 104-01 ) of a first super row (in this case the super row 106-0 at the top position) are connected to the first block output bus OL-A0-3 but not to the second block output bus OL-A4- 7, while the blocks (104-10, 104-11 ) of the second super row 106-1 are connected to the second block output bus OL-A4-7 but not to the first block output bus OL-Ao- 3. This would in principle cause the electric weighted values processed by the blocks 104-00 and 104-01 of the first super row 106-0 to flow to the analog accu- mulation bus OL-A0-3, and the electric weighted values processed by the blocks 104-10 and 104-11 of the second super row 106-2 to flow to the analog accumula- tion bus OL-A4-7, without therefore giving the possibility of accumulating all those values onto one single analog accumulation bus. However, it has been understood that it is possible to bypass one block output bus (e.g. OL-A0-3) to provide all the weighted values (coming from the blocks of both the first and second super col- umns) to one single analog output bus (e.g., OL-A4-7) to be therefore accumulated by one single analog accumulation bus (e.g. OL-A4-7). In this later case, it is also possible to use the first block output bus OL-A0-3 and the first analog accumulation bus OL-A0-3 for other processings (e.g. using some blocks of the same super col- umns which do not bypass the first block output bus OL-A0-3). In practice, it has been understood that it is possible to selectively bypass the block output bus OL- A0-3 by providing all the electric weighted values to the block output bus OL-A4-7. In examples, any of (e.g. all) the blocks of a same super column can be selectively connectable with each other (at least in the same subplurality, in the examples which have subpluralities A and B). In particular, a first block 104-00 of a first superrow 106-0 may provide weighted electric values to a first block (e.g. a correspond- ing block 104-10) of a second super row (106-1 ), which in some examples in turn can provide the same electric values (together its own electric weighted values) to the first block of a third super row 106-2, and so on, or route both the electric weighted values from the first block 104-00 and the electric weighted values pro- cessed by itself to its associated output line OL-A4-7. For example, the first block 104-00 of the first super row 106-0 may, instead of providing the weighted values processed by itself to the first block output bus OL-A0-3 (which is associated with the first super row 106-0), based on a selection, provide the value to a correspond- ing first block 104-10 of the second super row 106-0, which may (based on a se- lection) pass both the weighted values generated by the first block 104-00 of the first super row 106-0, and also further the weighted values generated by the first block 104-00 of the first super row 106-0 of its own, to the second output line OL- A4-7 associated with the second super row 106-1 . Accordingly, a pre-accumulated weighted value (taking into account the weighted values obtained from the first block of the first super row and the accumulated values obtained from the first block of the second super row) may be accumulated in the block output bus OL-A4-7. Meanwhile, it is possible that different blocks (e.g. other blocks of the first super row 106-0 which are not the blocks 104-00 and 104-01 ) process the electric input values to provide different electric weighted values to the first output line OL-A0-3, in case of such a selection. Accordingly, it is possible to achieve a better configu- rability and to configure the different values differently. Therefore:1 ) If the input vector has a number of elements which is larger than the number of element rows of the blocks (or equivalently the array of input electric val- ues has more input electric values than the number of element rows that each block of a super row has), it is possible to distribute the input electric values to more than one super rows, and meanwhile2) Directly mutually connecting blocks (in the same super column) from those super rows, thereby bypassing at least one block output bus, to thereby pro- vide all the weighted elements to the block output bus of one super row, and3) In case not all the super columns are used (e.g. in the same subplurality of blocks), it is possible to use at least one block to route weighted values to the block output bus which is bypassed by the other blocks.Let us consider Fig. 5, which shows a generic first block (here indicated with 104- 00, but which could be any other of Fig. 3) of a generic first super row (here indi- cated with 106-0) which is connected to a first block output bus (“Analog Bus”, OL- A0-3) associated with the first super row 106-0. The block (CAE) 104-00 is shown as being a 16x4 block. E.g., the first (left) column has weights w0_0, w1_0, , w15_0 (each weight for processing a respective electric input value), and normally provides the electric weighted values to a first, corresponding single electric output line (e.g., OL-Ao) of the associated first block output bus (OL-A0-3). The second (from left) column has weights w0_1 , w1__1 , ... , w15_1 (each weight for processing a respective electric input value), and normally provides the electric weighted val- ues to a second, corresponding single electric output line (e.g., OL-A1) of the as- sociated first block output bus (OL-A0-3). The last (right) column has weights w0_3, w1_3, , w15__3, and provides the weighted values to a second, corresponding single electric output line (e.g., OL-A3) of the associated first block output bus (OL- A0-3). (The behavior of the first block 104-00 is repeated by the other blocks of the same super row 106-0, and also the element columns of each block are meant to correspond, to thereby accumulate different electric weighted values and to provide different elements of the output vector). As shown in Fig. 5, however, the connec- tion between each element column of the block and the respective block output line traverses a selectable multiple connection (multiplexer) 519 (or more in general selectable multiple connection) which may e.g. deviate, under selection, theweighted values to the immediately adjacent block 104-10 of the same supercol- umn 108-0 (indicated with “Next CAE”). In Fig. 5 in particular there is shown that:1 ) The connection between each element column and the respective block out- put line is subjected to two switches (e.g. SwOa, SwOb, collectively indicated with 518), each of which may be selectably activated (closed) or deactivated (opened)2) In particular, one first switch (e.g. SwOb for the column w0_0, w1_0, ... , w15_0; Sw1 b for the column w0_1 , w1_1 , ... , w15__1 ; and so on) controls (e.g. independently) the connection with the respective block output line (e.g. OL-Ao) of the block output bus (e.g. OL-A0-3)3) Meanwhile, one second switch (e.g. SwOa for the column w0_0, w1_0, ... , w15_0; Sw1a for the column w0_1 , w1_1 , ... , w15_1 ; and so on) controls (e.g. independently) the connection with the respective immediately closed block of the same super column but in the immediately subsequent super row4) It is noted that, for each column (e.g. w0_0, w1_0, ... , w15_0) of the block, the first switch (e.g. SwOb) and the second switch (e.g. SwOa) may be acti- vated or deactivated simultaneously: a. if activated simultaneously, the weighted value will be provided to both the respective block output line (e.g. OL-Ao) of the block out- put bus (e.g. OL-A0-3) associated to the block and the immediately closed block of the same super column b. if deactivated simultaneously, no weighted value will be provided to the respective block output line (e.g. OL-Ao) of the block output bus (e.g. OL-A0-3) associated to the block and the immediately closed block of the same super column.5) Each second switch (e.g. SwOa) may be controlled independently from the other second switches (e.g. Sw1 a, Sw2a, etc.) of the same block (e.g. by a binary command written in a cell, like the SRMA cells), but in some examplesall the second switches of one single block are controlled by one single com- mand6) Each first switch (e.g. SwOb) may be controlled independently from the other first switches (e.g. Sw1 b, Sw2b, etc.) of the same block (e.g. by a binary command written in a cell, like the SRMA cells); in some examples, the bi- nary command is to be subjected to at least one external activation, e.g. performed through AND ports, (e.g., one column-wise activation controlled by a binary command S-Col Select, and one row-wise activation controlled by a binary command S-Row Select).7) In general terms, a multiplexer may be used (e.g. controlled by the AND gates) to selectively choose between a. providing the electric weighted values to the block output bus OL- AO-3 (indicated in Fig. 3 with 86) b. bypassing it (indicated in Fig. 3 with 85), thereby providing the electric weighted values to the adjacent block 104-10); or c. both providing the electric weighted values to the block output bus OL-Ao-s and providing the electric weighted values to the adjacent block 104-10)As can be seen in Fig. 3, the plurality of blocks may be partitioned into different subpluralities (e.g. different sections), e.g. a first subplurality of blocks may be in- dicated as being confined in Section A, while a second subplurality of blocks may be confined in Section B. There may be other sections which also contain other subpluralities. Each subplurality has its own super columns and may share super rows with other subpluralities (or, in comes cases, it may be that the super rows of the first subplurality are different from the super rows of the second subplurality). All the features of the second subplurality (Section B) may be the same of all those of the first subplurality (Section A), and are here therefore not repeated. It is noted, however, that the second subplurality (Section B) may be constituted of blockswhich, in some examples, are not even activated (e.g. in the cases in which the number of elements of the output vector are less than the total number of element columns in the first subplurality). Notwithstanding, in examples, the different sub- pluralities are activated. For example, the first super row in the part of the second subplurality, (Section B) may be subjected to the same input values to which the blocks of the first super row of the first subplurality (Section A) are subjected to. Notwithstanding, they are output to different output lines (OL-B0-3, which is not con- nected to OL-A0-3) and which also route to different accumulation lines (e.g., in the first super row in the second plurality, Section B) the weighted values are outed in the accumulation element bus AL28-31, which is different from the analog accumu- lation bus AL0-3, which receives the weighted values from the blocks of the first su- per row in the first subplurality (Section A). In other terms, it may be possible to accumulate the values accumulated by the two accumulation element buss AL0-3 and AL28-31 (of two different subpluralities) digitally, at a digital accumulator (S&A, see below).For the rest, the Section B can be identical to Section A, or may at least have features which are the same or similar (maybe not in combination) to those de- scribed for Section A. Of course, the second subplurality may be deactivated (e.g. by simultaneously deactivating all the blocks of the second subplurality), so as to avoid power consumption in case it is not needed. An example of using the second subplurality (Section B) is in the case in which the output value shall have a dimen- sion which has more elements than the element columns of the first subplurality. In the example of Fig. 3, if the output shall have more than 16 elements, the second subplurality shall be activated. For example, if the output shall have 17 to 20 output values, then only one super column of the second subplurality (Section B) will be activated, while the remaining super columns of the second subpluralities will not be activated, thereby saving power consumption.By virtue of the above, it may therefore be possible to have the reconfigurable pro- cessing device to permit at least of one (e.g. a combination) of the following selec- tions:1 ) a selection of the blocks to be activated (hence reducing power consumption in case some blocks are not used with respect of the prior art of Figs. 2 and 4);2) a selection of different input vectors to be processed simultaneously, by rout- ing their weighted values in different block output buses and in different an- alog accumulation buses (which is not possible in the prior art of Figs. 2 and 4, which does not allow different analog accumulation elements to be asso- ciated with the same columns);3) in case the length of the input vector being larger than the number of columns of a first generic block of a first super row and a first generic supercolumn onto which the input vector is inputted, to: either a. select a bypass from the first block to a second block of the same first super column and a second super row, so that the second block pro- vides both the weighted values from itself and the weighted values from the first block to a second block output bus associated with the second super row, e.g. the first block refraining from providing the weighted values from itself to the first block output bus associated with the first super row; or b. activate at least one second block from a second super row electrically connected to the same analog accumulation bus which receives the weighted values from the first super row of which the first block is part; or c. both;4) in case the length of the output vector is larger than the number of blocks in the same super row of the first subplurality (section A), to select the activa- tion of blocks of the second subplurality, to convey the weighted values to adifferent analog accumulation element buses, and subsequently sum the two accumulated values digitally.The above notwithstanding, in some examples it is also possible to select the mag- nitude of the weight according to a digital address (e.g., 3 bits), e.g. to select among a plurality of different levels of weight (e.g., seven levels, addressed by 3 bits).In general terms, while each electric input value is provided to a respective element row (line in the prior art) each element column is not bounded to one single output value (link in the prior art of Figs. 2 and 4): each different output values arrive from corresponding element columns of blocks in the same super row (or from corre- sponding element columns of blocks from different super tows, after bypass). Therefore, in principle one single super column is not reserved to one single output value.Fig. 6 shows an example 501 of how each weighting element 101 (AWE) may be carried out (different implementations are possible). Each weighting element may provide at least one of a current, a charge or a voltage obtained in analog domain by weighting an input electric value (which may encode a digital value), so as to provide a respective block output line OL-Ao with at least one weighted value, which is to be accumulated by the respective accumulation element ALo. The element 101 may provide at least one of an weighted current, a weighted charge. The weighting element 101 may be in parallel to all the weighting elements of the same element column of the same block, so as to provide in parallel and simultaneously the electric weighted values to the same respective block output line OL-Ao, to be pre-accumulated together with other electric weighted values from corresponding element columns of other blocks of the same super row. At least one electric input value may encode a binary value (e.g. indicated with djn in 501 and 502, or djno, djni, d_in2in 503 and 504), so that a first electric level of the at least one electricinput value corresponds to a first logical level (e.g. 1 ) of the binary value and a second electric level of the at least one electric input value corresponds to a second logical level (e.g. 0) of the binary value. This may be obtained, for example, by activating vs deactivating a switch controlled by the binary value (e.g. djn or djno, djni, d_in2) thereby imposing vs releasing at least one electric value (e.g. impos- ing Vdd, which may be a supply voltage, and / or by imposing a particular current or charge, vs releasing the electric voltage, e.g. by letting the electric value to float, or by imposing a different voltage or a different electric value). The weighting element 101 may, in the example of 501 , select between a first current generator 1101 providing a first current I and a second current generator 11012 providing a second current 12 (e.g. 12=2*1 or more in general 12^11 ). The weighting element 101 may selectably route each of the first current 11 and the second current I2, independently of each other, to a respective terminal (first, conventionally positive terminal vout_p vs second, conventionally negative terminal vout_n) connected to a respective con- ductor (first, conventionally positive conductor AL-P<0> of the block output line vs second, conventionally negative conductor AL-N<0> of the block output line, see Fig. 7). This effect may be achieved, for example, by coordinately activate vs de- activate, e.g. independently:1 ) a first switch d_wp<1> downstream to the first current generator and up- stream to the first terminal (and the positive conductor of the block output line)2) a second switch d_wn<1> downstream to the first current generator and upstream to the second terminal (and the negative conductor of the block output line)3) a third switch d_wp<0> downstream to the second current generator and upstream to the first terminal (and the positive conductor of the block out- put line)4) a fourth switch d_wn<0> downstream to the second current generator and upstream to the second terminal (and the negative conductor of the block output line).A table providing the various outputs is represented in a subsequent pars of the present description. It is notwithstanding clear that it possible, for example, to change the sign of the weight by changing the polarity. For example: if the current is caused to flow mainly in the first terminal vout_p (and in the positive conductor of the block output line) rather than in the second terminal voutjn (and in the negative conductor of the block output line), then the polarity will be positive, thereby being indicative of a positive weight; and if the current is caused to flow mainly in the second terminal vout_n (and in the negative conductor of the block output line) rather than in the first terminal vout_p (and in the positive conductor of the block output line), then the polarity will be negative, thereby being indicative of a negative weight.A description is now provided regarding an optional digital accumulation 600 of Fig. 7 (an embodiment of some elements being in Fig. 8). This because it is possible to reconvert the array electric analog accumulated values accumulated by the analog accumulation element buses AL0-3, AL28-31 onto digital values. It is to be noted, however, that, in particular in the cases, like that of 501 , in which each binary input (e.g. djn) is processed with weights having a resolution which is greater than 2 (i.e. the binary input may be processed according to a weight which is selected among more than 2 weight values), each digital output value from each processed input value may have, advantageously, a resolution of more than 1 bit (i.e. each digital output value may have a resolution of more than 1 bit, for example). For this reason, there may be used an analog to digital conversion which, for each analog accumulated value accumulated by a respective analog accumulation elementsALo, provides a digital output value encoded in more than 1 bit. Notably, each an- alog accumulation element ALo, ... , AL31 may have one accumulated weighted value which is one of a set of potential accumulated weighted values which has a cardinality of twice the number of input elements in the input vector multiplied by the number of weight levels that can be provided to each electric input value mul- tiplied by the number of weighting elements. For examples, the output of the ADC of Fig. 7 can be in nine bits for each analog accumulation element but (e.g. AL0-3). Shift registers e.g. in S&As (sample and adds) elements 702 may be used to gen- erate a super string of bits, in the case that different analog accumulation element carry different weighted accumulated values of different bits of input encoded val- ues.Neural networkSome examples regarding the application of the processing crossbar semiconduc- tor device 100 is now discussed for the application to a neural network. The cross- bar processing semiconductor device 100 may implement a neural network accord- ing to a plurality of layers, such as those shown in Fig. 1. The layers may include an input layer, an output layer, and e.g. at least one hidden layer (usually a se- quence of multiple hidden layers). For example, a given layer may be from N1 to Nn, and for the immediately subsequent layer M1 to Mm, each of N1 , N2, N3, ... , Nn, M1 , M2, M3, Mm is a neuron. Each transition from a layer (N1 , N2, N3, Nn) to the immediately subsequent layer (M1 , M2, M3, ... , Mm) may be performed with the techniques discussed in the present document. For example:1 ) The input vector is N1 , N2, N3, Nn (it could be represented by an array of digital values, e.g. forming an input digital string)2) The input vector may be converted into an array of input electric values which represent the input vector (each bit of the input digital string may be the binary value djn of Fig. 6, which generates an input electric value which may be, for example, Vdd)3) At each weighting element 101 , each electric value may be processed by weighting, e.g. by applying the current generator(s) 1101 and 110I2 and / or by opportunely activating vs deactivating the switches d_wp<1 >, d__wp<0>, d_wn<1 >, d_wn<0>, thereby providing a current value at the terminals vout_p and vout_n4) The weighted electric values are then routed to the block output lines and to the analog accumulation element buses5) The electric accumulated weighted values are subsequently digitized and, if necessary, composed together forming a super string6) In case, an activation function in the digital domain may be applied7) The digital activated output may be the output vector M1 ... Mm which con- stitutes the subsequent layer.Each weight of the at least one weight tensor represents a synapsis. Each analog input value is a neuron. Each output value is a neuron of the immediately subse- quent layer.The input vector may be, for example, a kernel.It is possible to perform after a first phase in which the weights of the at least one weight tensor are defined by minimizing a cost function providing error metrics on a known dataset (and evaluating the error metrics with respect to know values of the dataset). Subsequently, an inference phase may be performed in which the weights are established, and predictions are provided in response to input values. This may be performed for each layer.ControllerA controller (not shows) may be used to perform the processing and / or the selec- tions.In particular, the controller may control the operations of the weighting elements, activating vs deactivating the weighting elements and / or the blocks.The controller may be, for example, the same which defines the neural network, or may be a slave controller, which receives, forma neural network controller, a request for defining the neural structure of the neural network (e.g., how many layers, how many neurons for layers, which synapses, which weights, etc.). In any case, it is here discussed the hypothesis that the controller performs the op- erations of adapting the structure of the processing crossbar semiconductor de- vice 100 to the neural network to be used, imagining that the structure of the neu- ral network is either requested by an external entity or is pre-defined.The controller may receive information on the number of elements of the input vector, the number of elements of the output vector, and the values of the weights to be applied. The controller may evaluate at least one of:1 ) whether the number of elements of the input vector is greater than or equal to or lower than the number of element rows in one block of a super row, and:a. if it is ascertained that the number of elements of the input vector is lower than or equal to the number of element rows in the block, then the controller assigns each input value to a respective row of the block b. if the number of elements of the input vector is greater than the num- ber of element rows in the block, then the input values may be dis- tributed among: i. different super rows (and weighted values in different super rows may be bypassed to the same block output line, to reach the same analog accumulation element) and / or ii. different super rows which are connected to the same analog accumulation element bus (e.g. super rows 106-0 and 106-4, which route to the same accumulation elements in the accu- mulation element bus AL4-7) ) whether the number of elements of the output vector is greater than or equal to or lower than the total number of element columns in the first sub- plurality: a. If it is ascertained that the number of elements of the output vector is greater than the total number of element columns in the first subplu- rality, then some elements of the output vector are assigned to blocks of the first subplurality of blocks, and some other elements of the output vector are assigned to additional blocks in the second subplurality of blocks (e.g., in the same element rows) b. Otherwise, only one single subplurality of blocks may be activated) whether the number of elements of the output vector is greater than or equal to or lower than the total number of element columns in one block of one super column:a. if it is ascertained that the number of elements of the output vector is lower than or equal to the number of element columns in one block, then each output value is assigned to one single block or one single super column b. if it is ascertained that the number of elements of the output vector is greater than the number of element columns in one block of one su- per column, then each input value is assigned to multiple blocks of a same super row (and, in case, weighted values are bypassed to one single block output line, so that they are routed to the same analog accumulator element), or to blocks of different subpluralities in the but having the same element rows (i.e. having the same electric in- put values) 4) Once having assigned input values and output values to the blocks, but be- fore performing the processings, the super row, the super columns, etc. the controller may evaluate whether there is the possibility of insert a further in- put vector. This is evaluated by: a. checking whether there are left enough free element rows for the ele- ments of the input vector to be processed with the same weights of the first input vector and enough free element columns (if it is ascer- tained that there are enough, it is possible to proceed and also apply different input vectors in the same weight tensor, otherwise it is not performed) b. checking whether there are left enough free element rows for the ele- ments of the input vector to be processed with the same weights of the first input vector and enough free element columns and enough blocks to insert an additional weight tensor (if it is ascertained that there are enough, it is possible to proceed and also apply different input vectors using a different weight tensor to be simultaneously processed, otherwise it is not performed)i. subsequently, the assignments of the values to the blocks and element rows and element columns and super columns and super rows are performed as for the first input vector, but dis- carding the blocks and element rows and element columns and super columns and super rows are performed as for the first input vector which are already assigned to the first input vector.It is also to be noted that the controller may associate the weights of the tensor weight to the weighting elements 101 , e.g. in positions complying with the activated weighting elements and weighting blocks.Structural featuresThe layout of the device 100 may substantially follow Fig. 3. In particular, the weighting elements 101 may be placed according to that bidimensional array, e.g. one adjacent to the other one. Each block onto which the bidimensional array is partitioned may comprise a reduced bidimensional array, e.g. comprising only those weighting elements which are spatially enclosed in a closed boundary, for example. In examples, all the blocks of at least one super row and / or at least one super column have the same number of element rows and element columns. The bidimensional array may be obtained, for example, by opportunely doping a silicon substrate, thereby making the weighting elements and the connection. The bidi- mensional array may extend mostly planarly. The super rows may be geometrical parallel to each other and the super columns may be geometrical parallel to each other. The super rows may be geometrical perpendicular to the super columns. The block element output buses may be geometrical parallel to the super rows. The block element accumulation busses may be geometrical parallel to the super columns. The block element output buses may be geometrical perpendicular to the super columns. The bypasses obtained thought the multiple connections 519 maybe obtained in such a way that each block is connected to the immediately closest block(s) of the immediately closest super row(s), to thereby minimizing the length of the multiple connection 519. The blocks of the first sub plurality may be all within one single closed boundary excluding all the blocks of the second sub plurality, and / or the blocks of the second sub plurality may be all within another single closed boundary excluding all the blocks of the first sub plurality. The blocks and the weighting elements may be grouped in a position which is spaced from the ADCs 700. It has been understood that these solutions permit to reduce parasitic capac- itances.DiscussionThe complete crossbar array (CA) of Fig. 3 may be divided into two sections (sub- pluralities), Section A (first subplurality) and Section B (second subplurality), and each section is further divided into blocks (which smaller crossbar array elements or case). Each block (CAE) may include 4 columns and 16 rows (other numbers are possible) of e.g. analog synapses, which are termed as weighting elements or analog weight emulators (AWEs). Columns and rows of blocks (CAEs) are termed as Super-Columns and Super-Rows respectively. All blocks (CAEs) in a Super- Row of a section share a dual channel analog bus of e.g. width 8 (i.e. eight con- ductors) - a pair for each CAE column, spanning horizontally over all the Super- Columns in the section. These analog buses are termed as CAE Output Lines (block output buses) inFig. 3, and there may be as many such analog buses per section as there are Super-Rows, referred to as OL-A and OL-B for Section A (first subplurality) and Section B (second subplurality) respectively. Several of these OL- A and OL-B analog buses (block output buses), in their respective sections (sub- pluralities), are connected to another set of dual channel analog buses, termed in Fig. 3as Accumulation Line (accumulation element bus), and referred to as AL-A and AL-B for Section A (first subplurality) and Section B (second subplurality), re- spectively. In Fig. 3, there are 32 accumulation elements - 16 per section and e.g.each of width 2 (i.e. two conductors). There are as many as AL-A and AL-B per section as there are ADCs, and they span over all the Super-Rows in each section. The CA in Fig. 3 may comprise e.g. 32 shift and add digital blocks, as many as there are ADCs.Each blocks (CAE) may be equipped with special multiplexers that can be config- ured statically - e.g. prior to running inference, and / or dynamically - while running inference. These multiplexers enable the CAE (blocks) to forward their outputs to the next block (CAE) in the same Super-Column and / or to their Output Lines (e.g. AL-A0-3) as shown by the long and short arrows in Fig. 3. The outputs from the analog block output buses (e.g., OL-AO-3, 0L-A4-?,... ) can then be further forwarded to different analog Accumulation lines (e.g., AL-0-3, AL-AA-Z,... ), which finally gets digitized by the ADCs. Thus, using appropriate configurations of the multiplexers, multiple CAEs (blocks) can be configured to support convolution and fully con- nected kernels (or more in general input vectors) of varying dimensions (and also to achieve output vectors of multiple, variable dimensions), without sacrificing the utilization of the analog crossbar. Here, a convolution or fully connected kernel di- mension is defined as the number of weights associated to a neuron computation, For a 2 dimensional convolution layer filter of width 3, height 3, and 3 channels, the kernel dimension is 3 x 3 x 3 = 27, while the same for a fully connected shown in Fig. 1 , is n.Kernel mapping on crossbar: an exercise on configurability and utilizationTo explain advantages of the presented examples, let us consider again the exam- ple with four kernels, K0_0, KO 1 , K1_0, and K1__1 , each of length 16. Also, K0_0, and K0_1 form a pair which gets the same inputs, while K1_0, and K1 1 form an- other pair, which also gets same inputs but different from the former pair. Such an assumption is a valid model configuration, for instance a CNN layer with two filterswould get the same set of inputs, but the inputs would obviously be different for two different layers.Reference numerals 301 to 304 in Fig. 3and 401 to 404 in Fig. 4 (prior art) shows the mapping of the above 4 K*__* (where is a generic notation meaning “any number”) kernels on the configurable crossbar presented in these examples and the traditional in-memory computing crossbar of Fig. 2 respectively. If in Fig. 4 (prior art) reference numerals 403 and 404 are mapped on the same element column as that 401 and 402, their accumulation results cannot be computed simultaneously because they connect to the same accumulation lines. However, 303 and 304, while mapped below 301 and 302 in the same columns, can be computed simulta- neously because the accumulation outputs from 301 and 302 or 303 and 304 can be forwarded to different accumulation lines through the output lines. For example, accumulation outputs from 301 and 302 can be forwarded to accumulation lines A- 3 through output lines OL-Ao-3, while that from 303 and 304 can be forwarded to accumulation lines AL4-7 through OL-A4-7, simultaneously. The routing configuration of OLs and ALs are controlled by CAE multiplexers, configurations of which are set during compile time and runtime.MultiplexersFig. 5 shows the multiplexer circuit employed by each CAE (block), where a com- bination of the S-Col Select, the S-Row Select, and the signals from the SRAM cells may control the switch array. The accumulated output from each column of the CAE (block) is forwarded to the corresponding column of the next CAE (block) when first row of the SRAM cells contains the bit “1”, while the outputs are for- warded to the Output Lines when the S-Col Select, the S-Row Select are both high, and the second row of the SRAM cells contain the bit “1”. The switch array in Fig. 5 comprises 8 analog switches. Depending on the implementation of the AWEs(weighting elements) inside each CAE (block), the On-Off resistances and the par- asitic capacitances of these switches are the critical design specifications which must be met.The accumulated outputs from the CAE (block) are forwarded to next CAE (next block) when the kernel length is greater than the height (number of rows) of the CAE (block), which in Fig. 5 is 16. This being a neural network dependent param- eter is calculated at compile time and therefore is treated as a static signal. On the contrary, the S-Row and S-Col Select signals, which control the Output Line ac- cess, may be generated during runtime by means of instructions and therefore are configured dynamically. Driving the compile time signals by SRAM cells also sim- plifies the interface complexity of the CA (device) as they can be configured using an existing memory interface and reduces the energy consumption as they are located locally in the CAE (block).Multiply and accumulate or MAC using analog weight emu- lator or AWEMultiply and accumulate or MAC is a basic operation all vector matrix multiplica- tions or VMMs that involves a multiply operation on two operands followed by an accumulation operation that adds the outputs of two multiply operations. There are several different implementations of MAC operations employed by in-memory com- puting (IMC) engines, much of which employ SRAM-based IMCs that typically ac- cumulate charges and eNVM-based IMCs that accumulate currents [1], [3], [4], [5], [6], [7], [8], The present examples may employ current mode accumulation using current sources and 6-T CMOS SRAM cells.Fig. 6 shows the current source based analog weight emulator (CS-AWE, weighting element) implementation employed in the present examples for MAC computation, which multiplies a 1 -bit input and a signed weight with 3-bit or 7 levels.This will be referred to as a 1 bx3b MAC operation in this description. The example501 shows the detailed implementation of the CS-AWE (weighting element) while502 shows a compact representation of the CS-AWE (weighting element). The magnitude part of a synaptic weight is encoded into the two binary weighted current sources in the examples 501 and 502, while the sign part of the weight is effectively computed by subtracting vout__n from vout_p (thereby inverting the polarity). The switches controlled by d_wn<1:0> and d_wp<1:0> control the flow of current to either vout_n or vout_p depending on the sign of the weight. Table 1 shows the mapping between the 7 possible weight levels or values and the switch control signals d_wn<1:0> and d_wp<1:0>. The input bit, djn, is essentially used as a selection bit, which controls the switch that enables the CS-AWE (weighting ele- ment).Example 503 shows a circuit example of a neuron connected to three inputs, djno- 2, by synaptic weights Wo, Wi, W2. Example 504 shows an equivalent circuit of the neuron implementation of 503, along with the electrical parameters that equate the output voltage to the inputs and weights. In the example shown in 504, all the three inputs of 503 are high, which enables all the weights or the CS-AWEs (weighting elements). The weighted currents for the positive weights, Wo and W2 are directed to the vout_p terminal, while the weighted current for the negative weight W1 is directed to the voutji terminal, controlled by d_wn<1:0> and d__wp<1:0> according to Table 1 . The equivalent MAC output for the three multiply and accumulate oper- ations between the three inputs and weights is calculated in 504 and generalized in 505, where Input = 1 , SUM(Weights) = -2, and the Constant term is determined by the product of the unit current of the current sources and the accumulation re- sistor Race.Table 1Configurable activation and weight precision using Shift- Add circuitThe present examples may include circuits and apparatus that can be employed to configure the bit precession of neuron activations and weights, see Fig. 7. The neuron activations can be configured from unsigned 1 bit to 8 bits in steps of 1 bit, while the weights can be configured from signed 3 to 9 bits in steps of 2 bits. The general idea is to compute accumulations for 1 bit input and 3-bit signed weights separately by employing the unit MAC of 1 bit times 3 bit, described above, and subsequently combine all such accumulations for multiple input bits ranging from 1 bit to 8 bit and multiple weight bits ranging from 3 bit to 9 bit, either sequentially in multiple cycles or parallelly in a single cycle. All the accumulations corresponding to the same set of input and weights of higher precision than the unit MAC precision is performed by shifting and adding the digital accumulation result from each ADC.The 32 pair of AL-P (positive conductors) and AL-N (negative conductors) signals shown by 601 in Fig. 7 are the vertically traversing accumulation lines that carry the 1 bx3b MAC accumulation outputs of VMMs, which are digitized by the 32 ADCs and fed to the 32 shift-add blocks. For each bit of a higher precision input of a VMM,the digitized accumulation result from an ADC is left shifted by one and added to the previous output in a sequential manner, from most significant bit (MSB) to the least significant bit (LSB) of the input. For example, 8-bit VMM inputs take 8 accu- mulation cycles to compute the combined 8bx3b MAC accumulations, where the digitized accumulation results corresponding to MSB of the input encounter 7 left shifts. The left shifts (resulting in multiplications by 2) are shown by 603 in Fig. 7. Each ADC and shift-add block or S&A comprise a shift-add column shown by 602, which can facilitate the MAC accumulations of corresponding 3-bit weights. For VMMs with higher weight precision, multiple Shift-Add Column outputs, shown by 604, are left shifted by 2, shown by 605, and added to Shift-Add Column to its left. For example, 5-bit weight would require 2 Shift-Add Columns, and 9-bit weight would require 4 Shift-Add Columns. The final output is available at the left most column of the combination of columns.Fig. 8 shows detailed implementation of a shift-add circuit. The shift-add circuit supports sequential addition of digitized accumulation outputs corresponding to dif- ferent bits of a multi-bit input from the same AL and that corresponding to different bits of a multi-bit weight from different Als. It also supports multiplication of the accumulated result with configurable 8 bit gain 801 and addition of configurable off- set 802, a combination of which can be used to support Batch Normalization fea- ture used in deep neural networks.Some aspectsThe present examples may include a field configurable analog crossbar architec- ture for in-memory computing, described above, which provides functionality to map and compute VMM kernels of varying dimensions without sacrificing resource utilization and performance.The present examples are not limited to the specific parameter values, e.g. dimen- sions of crossbar, CAE (block), Super-Row, Super-Column, ADC, Shift-ADD etc., used to describe the solution above, but extends beyond to other feasible dimen- sions.Some of the present examples may include a multiplexer circuit implementation which can be configured statically, at compile time, and dynamically, during runtime, by means of memory and switches.The present examples are not limited to SRAM (Static Random Access Memory) memory and CMOS (Complementary Metal Oxide Semiconductor) switches, but extends to non-volatile memories like RRAM (Resistive Random Access Memory), FeFET (Ferro-electric Field Effect transistor), MRAM (Magnetoresistive Random Access Memory), etc.Some of the present examples provide an Analog Weight Emulator or AWE circuit which facilitates multi-bit signed Multiply and Accumulate or MAC computation.The present examples are not limited to SRAM memory and CMOS switches, but extends to non-volatile memories like RRAM, FeFET, MRAM, etc.The present examples are not limited to 3-bit signed weight and 1 bit input, but extends to other bit precisions.Some of the present examples provide a shift and add circuit that supports built in batch normalization functionality.The present examples are not limited to the specific precisions used above, but extends to other precisions.Further characterization of the figures:Fig. 1 A fully connected layer exampleFig. 2 An in-memory computing array exampleFig. 3 Configurable Crossbar Array architectureFig. 4 Traditional In-memory Crossbar Array architecture showing kernel mapping Fig. 5 CAE (block) multiplexerFig. 6 AWE implementation showing 3 MAC operationsFig. 7 Shift - Add columns for multibit input and weight configurationFig. 8 Reconfigurable shift and add block for multibit input and multibit weightReferences[1] H. Tsai et al, "Recent progress in analog memory-based accelerators for deep learning," J. Phys. D: Appl. Phys, 2018.[2] A. Reuther, P. Michaleas, M. Jones, V. Gadepally, S. Samsi and J. Kepner, "Al and ML Accelerator Survey and Trends," in 2022 IEEE High Performance Extreme Computing Conference (HPEC), Waltham, MA, USA, 2022.[3] N. R. Shanbhag and S. K. Roy, "Comprehending In-memory Computing Trends via Proper Benchmarking," in 2022 IEEE Custom Integrated Circuits Conference (CICC), 2022.[4] A. Shafiee, A. Nag, N. Muralimanohar et al., "ISAAC: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars," Proc. 43rd Int. Symp. Comput. Archit., pp. pp. 14-26, 2016.[5] N. Verma, H. Valavi and H. Jai, "Configurable in memory computing engine, platform, bit cells and layouts therefore". USA Patent US 2021 / 0271597 A1 , 02 Sep 2021.[6] H. Jia et al., "15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing," in 2021 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021.[7] J. -W. Su et al., "16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for Al Edge Chips," in 2021 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021.[8] M. -S. K. N. R. S. S. E. a. K. C. M. Kang, "An energy-efficient VLSI architec- ture for pattern recognition via deep embedding of computation in SRAM," in 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, Italy, 2014.[9] G. W. Burr et al,, "Experimental demonstration and tolerancing of a large- scale neural network (165000 synapses) using phase-change memory as the synaptic weight element," Proc. Int. Electron Devices Meeting, pp. pp. 29.5.1- 29.5.4, 2014.

[0010] M. A. Z. Wei Lu, "Field-programmable crossbar array for reconfigurable com- puting". US Patent US10346347B2, 2017.

Claims

Claims1 . A processing crossbar semiconductor device for processing at least one in- put vector by at least one weight tensor, to derive at least one output vector as processed version of the at least one weight tensor, the at least one weight tensor having a plurality of weights, the crossbar processing device being configured to process each input electric value of an array of input electric values representing the at least one input vector, the processing crossbar semiconductor device com- prising: a set of weighting elements (101 ) arranged according to element columns and elements rows, each weighting element (101 ) corresponding to a weight of the at least one weight tensor, wherein the set of weighting elements (101 ) is parti- tioned among a plurality of blocks (102), the plurality of blocks (102) being arranged according to super columns (108) and super rows (106) in such a way that each super row includes a plurality of immediately subsequent element rows and each super column includes a plurality of immediately subsequent element columns; a plurality of block output buses (OL-A0-3, OL-A4-7, OL-As-n, OL-A28-31), each block output bus (OL-A0-3, OL-A4-7, OL-As-n, ... , OL-A28-31) being associated with, and connected to, a plurality of blocks (104-00) in the respective super row (102-0) without being connected to blocks (104-10, 104-11 ) associated with, and connected to at least one other super row (102-1 ), each block output bus (OL-A0-3, OL-A4-7, OL-As-n, OL-A28-31) including a plurality of block output lines (OL-Ao , OL-A31), wherein each block (104) of the plurality of blocks is configured, when activated, to weight input electric values of the array of input electric values by corresponding weights of the at least one weight tensor, to provide electric weighted values to the block output bus associated with the super row (106-0) of which the block (104-00) is part; and a plurality of analog accumulation elements (ALOo, ... , AL31), each analog accumulation element (ALOo) being electrically connected with at least one block output line (OL-Ao), to thereby provide a respective electric accumulated weightedvalue from the electric weighted values obtained from the corresponding element columns of a plurality of activated blocks (104-00, 104-01 ) in the at least one super row (106-0) associated with the at least one block output line (OL-Ao), to derive an array of accumulated weighted output values which form the at least one output vector.

2. The processing crossbar semiconductor device of claim 1 , wherein each block (14-00) of a super row (106-0) is configured to activate a plurality of weighting elements (101 ) simultaneously, to thereby provide, to the respective block output lines and through the weighting elements (101), the electric weighted values sim- ultaneously, so that each analog accumulation element that receives the electric weighted values from the same block output line has the accumulation value sim- ultaneously.

3. The processing crossbar semiconductor device of any of the preceding claims, wherein each weighting element (101 ) is configured to provide a current analogically obtained by weighting the input electric values, so that the respective accumulation element provides at least one of an accumulated weighted current as the electric accumulated weighted value.

4. The processing crossbar semiconductor device of any of the preceding claims, wherein each weighting element (101 ) is configured to provide a charge and / or a voltage analogically obtained by weighting the input electric values, so that the respective accumulation element provides an accumulated weighted charge and / or an accumulated weighted voltage as the electric accumulated weighted value.

5. The processing crossbar semiconductor device of any of the preceding claims, wherein at least one electric input value encodes a binary value (djn, djno,djni, d_iri2), so that a first electric level of the at least one electric input value corresponds to a first logical level of the binary value and a second electric level of the at least one electric input value corresponds to a second logical level of the binary value, each of the relating weighting elements (101 ) being configured to process the electric input value according to a weight which is selected between more than two weight values.

6. The processing crossbar semiconductor device of claim 5, wherein at least one of the weighting elements (101 ) is configured to select between a first current generator (1101) providing a first current (I) and a second current generator (11012) providing a second current (12), wherein the weighting element (101 ) is configured to selectably route each of the first current and the second current, independently of each other, to a respective conductor chosen between a first conductor of the respective block output line and a second conductor of the of the respective block output line, so that the respective block output line carries one selected of multiple selectable levels of the weighted output value.

7. The processing crossbar semiconductor device of any of the preceding claims, wherein at least one of the relating weighting elements (101 ) is configured to select between at least one positive polarity, thereby generating a positive weight, and one negative polarity, thereby generating a negative weight, by award- ing a larger electric level to a positive conductor or electrode of the analog accu- mulation element than to a negative conductor or electrode of the analog accumu- lation element in case of positive electric weighted value, and by awarding a larger electric level to the negative conductor or electrode than to the positive conductor or electrode in case of positive electric weighted value.

8. The processing crossbar semiconductor device of any of the preceding claims, wherein the plurality of analog accumulation elements (ALo, ALi, AL2, AL3)are gathered in analog accumulation element buses (AL0-3, .... AL28-31), each of the analog accumulation element buses (AL0-3) being connected with, and associated to, at least one block output bus (OL-A0-3), each analog accumulation element (ALo) of each analog accumulation element bus (AL0-3) being connected to at least one block output line (OL-Ao) of the associated at least one block output line (OL-A0-3), to accumulate weighted electric values from the same element columns of the blocks (104-00, 104-01 ) of at least one super row (106-0) associated with the as- sociated at least one block output bus (OL-A0-3).

9. The processing crossbar semiconductor device of any of the preceding claims, wherein at least one analog accumulation element bus (ALo) is associated with, and connected to, at least a first block output bus (AL0-3) associated with, and connected to, a first super row (106-0) and a second block output bus (OL-A16-19) associated with, and connected to, a second super row (106-4), so that each ana- log accumulation element (ALo) of the analog accumulation element bus (AL0-3) provides an electric accumulated weighted value accumulated from the electric weight values from both first blocks (104-00, 104-01 ) of the first super row (106-0) and second blocks of the second super row (106-4).

10. The processing crossbar semiconductor device of any of the preceding claims, further comprising at least one analog to digital, ADC, converter to convert at least two electric accumulated weighted values from at least two analog accu- mulation elements, respectively.

11. The processing crossbar semiconductor device of claim 10, configured to convert at least one electric accumulated weighted value onto one single bit in ac- cordance to the electric level of the electric accumulated weighted value.

12. The processing crossbar semiconductor device of claim 10, configured to convert at least one electric accumulated weighted value onto a plurality of bits in accordance to the electric level of the electric accumulated weighted value, the weight level .

13. The processing crossbar semiconductor device of any of claims 10-12, con- figured to convert multiple accumulated weight values, from different accumulation elements, onto a super string of bits, by converting at least one first electric accu- mulated weighted value onto at least one least significant bit or least significant string, and at least one second electric accumulated weighted value onto at least one most significant bit or most significant string.

14. The processing crossbar semiconductor device of any of claims 10-14, fur- ther comprising at least one digital accumulation element to accumulate different accumulated weighted values, once converted in digital, from different analog ac- cumulation elements or from different analog accumulation element buses.

15. The processing crossbar semiconductor device of any of the preceding claims, configured so that a first block (104-00) a first super row (106-0), which is associated with a first block output bus (OL-A0-3), contains a selectable multiple connection with a second block (104-10) of a second super row (106-1 ), the second super row (106-1 ) being associated with, and connected to, a second block output bus (OL-A4-7) but being not associated with, and not connected to, the first block output bus (OL-A0-3), wherein the first block output bus (OL-A0-3) is connected to, and associated with, a first analog accumulation element bus (AL0-3) including a plurality of first analog accumulation elements (ALo, AL1, AL2, AL3) and the second block output bus (OL-A4-7) is connected to a second analog accumulation element bus (AL4-7) including a plurality of second analog accumulation elements (AL4, AL5, AL.6, AL7), none the first analog accumulation elements (ALo, AL1, AL2, AL3) beingconnected to any of the second analog accumulation elements (AL4, AL5, ALe, AL7), the selectable multiple connection electrically connecting, when selected, the first block (104-00) with the block output bus (OL-A4-7), in such a way that the weighted electric values from the first block (104-00) are provided to the second block output bus (OL-A4-7), and to the second analog accumulation element bus (AL0-3).

16. The processing crossbar semiconductor device of any of the preceding claims, wherein a plurality of blocks (104-00, 104-01 ) of at least one super column (108-0) are electrically connected two by two through a plurality of selectable mul- tiple connections, in such a way to selectably provide weighted values obtained at a first block (104-00) of a first super row (106-0) to a second block output bus (OL- A4-7) which is not electrically connected to a first block output bus to which the first super row is connected.

17. The processing crossbar semiconductor device of any of claims 15-16, con- figured to evaluate whether the input vector has more elements than the element rows of first blocks (104-00, 104-01 ) of a first super row (106-0), so that, in case of the input vector having more elements than the number of element rows in each first block (104-00, 104-01 ) of the first super row (106-0), to distribute electric input values between the element rows of the first blocks (104-00, 104-01 ) of the first super row (106-0) and element rows of second blocks (104-10, 104-11 ) of at least one second super row (106-1 ), and to selectably provide electric weighted values from each of the first blocks (104-00, 104-01 ) of the first super column (108-0) to at least one of the further blocks (104-10) of the second super row (106-1 ), the second blocks (104-10, 104-11 ) thereby providing to the same block output bus (OL-A47), with which they are associated, both the weighted values from the first blocks (104-00, 104-01 ) and the weighted values from the further blocks (104-10, 104-11 ).

18. The processing crossbar semiconductor device of any of the preceding claims, wherein the plurality of blocks (104) includes a first subplurality of blocks(A) and a second subplurality of blocks (B) disjoint from the first subplurality of blocks, the plurality of block output buses including a first subplurality of block output buses (OL-A0-3) uniquely connected to blocks (104-00, 104-01 ) of the first subplurality of blocks (A) and a second subplurality of block output buses (OL-Bo- 3, ... , OL-B28-31) uniquely connected to blocks of the second subplurality of blocks(B), wherein the second subplurality of blocks (B) is selectably activatable and de- activatable.

19. The processing crossbar semiconductor device of claim 18, wherein the plu- rality of analog accumulation elements includes at least a first subplurality of analog accumulation elements (AL0-3) to accumulate electric weighted values from the first subplurality of blocks (A) and a second subplurality of analog accumulation ele- ments (AL.28-3i)to accumulate electric weighted values from the second subplurality of blocks, the processing crossbar semiconductor device further comprising a plu- rality of further accumulation elements, each further accumulation element being configured to accumulate a weighed electric value obtained by accumulating both a first weighted electric value from a first analog accumulation element of the first subplurality of blocks and a second weighted electric value obtain from a second analog accumulation element of the second subplurality of blocks.

20. The processing crossbar semiconductor device of claim 19, wherein the further accumulation element is a digital accumulation elements.21 . The processing crossbar semiconductor device of any of claims 18-20, con- figured to evaluate whether the output vector to be obtained has more elements than the number of element columns of the first subplurality of blocks (A), so as to activate, in case the output vector has more elements than the number of elementcolumns of the first subplurality, a number of super columns of blocks of the second subplurality of blocks (B), so that the number of columns of the activated super columns of blocks at least matches the number of elements of the output vector.

22. The processing crossbar semiconductor device of any of claims 18-21 , wherein the second subplurality of blocks are selectively activatable and deactivat- able.

23. The processing crossbar semiconductor device of any of the preceding claims, wherein each analog accumulation element is a resistor which receives the weighted electric values from the weighting elements (101 ) of the same element row in multiple blocks of at least one super row, so that the respective electric ac- cumulated weighted value becomes a sum of the weighted electric values.

24. The processing crossbar semiconductor device of claim 23, wherein the weighted electric values are currents, and the electric accumulated weighted value is a current which is the sum of the currents from the block output lines.

25. The processing crossbar semiconductor device of any of the preceding claims, wherein each analog accumulation element is a capacitor which receives the weighted electric values from the weighting elements (101 ) of the same ele- ment row in multiple blocks of at least one super row, so that the respective electric accumulated weighted value becomes a sum of the weighted electric values which are charges or voltages.

26. The processing crossbar semiconductor device of any of the preceding claims, configured to activate different blocks independently of each other.6o27. The processing crossbar semiconductor device of any of the preceding claims, configured to activate simultaneously multiple blocks of the same super row, in such a way that weighting elements (101 ) connected to the same block output line provide electric weighted values to the same block output line to thereby provide the electric weighted values.

28. The processing crossbar semiconductor device of any of the preceding claims, configured to receive the array of electric values as at least a first input vector and a second input vector independent from the first input vector, the first input vector being inputted to a first super row of blocks and, simultaneously, the second input vector being provided to a second super row of blocks.

29. The processing crossbar semiconductor device of any of the preceding claims, wherein the weighting elements of each block are configured to provide, in parallel, respective electric weighted values to respective block output lines, thereby preaccumulating the electric weighted values in the same output line.

30. The crossbar processing device of any of the preceding claims configured to implement a neural network according to a plurality of layers, including an input layer, an output layer, and optionally at least one hidden layer, wherein each tran- sition from a layer to the immediately subsequent layer is performed by processing the analog input vector, wherein each weight of the at least one weight tensor rep- resents a synapsis, each analog input value is a neuron, and each output value is a neuron of the immediately subsequent layer.31 . The crossbar processing device of claim 30, wherein the analog input vector is a kernel, or a portion of kernel, to be convolutionally applied to the at least one weight tensor.

32. The crossbar processing device of any of claims 30-31 , configured to per- form after a first phase in which the weights of the at least one weight tensor are obtained by minimizing a cost function providing error metrics on a known dataset, an inference phase in which the weights of the weight tensor are established, and predictions are provided in response to input values.

33. A method for at least one input vector by at least one weight tensor, to derive at least one output vector as processed version of the at least one weight tensor, the at least one weight tensor having a plurality of weights, the method including processing each input electric value of an array of input electric values representing the at least one input vector, the method using weighting elements (101 ) arranged according to element columns and elements rows, each weighting element (101 ) corresponding to a weight of the at least one weight tensor, wherein the set of weighting elements (101 ) is partitioned among a plurality of blocks (102), the plu- rality of blocks (102) being arranged according to super columns (108) and super rows (106) in such a way that each super row includes a plurality of immediately subsequent element rows and each super column includes a plurality of immedi- ately subsequent element columns, the method further using a plurality of block output buses (OL-AO-3, OL-A4-7, OL-As-n, OL-A28-31), each block output bus (OL- A0-3, OL-A4-7, OL-As-n, OL-A28-31) being associated with, and connected to, a plurality of blocks (104-00) in the respective super row (102-0) without being con- nected to blocks (104-10, 104-11 ) associated with, and connected to at least one other super row (102-1 ), each block output bus (OL-A0-3, OL-A4-7, OL-As-n, OL- A28-31) including a plurality of block output lines (OL-Ao .... OL-A31), the method comprising: activating weighting input electric values of the array of input electric values by corresponding weights of the at least one weight tensor, to provide electric weighted values to the block output bus associated with the super row (106-0) of which the block (104-00) is part; andproviding, through a plurality of analog accumulation elements (ALOo, AL31), each analog accumulation element (ALOo) being electrically connected with at least one block output line (OL-Ao), a respective electric accumulated weighted value from the electric weighted values obtained from the corresponding element columns of a plurality of activated blocks (104-00, 104-01 ) in the at least one super row (106-0) associated with the at least one block output line (OL-Ao); and deriving an array of accumulated weighted output values which form the at least one output vector.

34. A non-transitory storage unit storing instruction which, when executed by a processor, cause the processor to perform the method of claim 33.

35. The crossbar processing device of any of claims 1-32, further comprising a controller to activate at least one among the following: at least one block, at least one super row, at least one super column, at least one element row, at least one bypassing connection, at least one subplurality and / or to associate weights to re- spective weight elements, input electric values to element rows, and / or output elec- tric values to element columns of at least one block.

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