Pixel circuit, driving method and display device

Abstract

A pixel circuit, a driving method and a display device are provided. The pixel circuit includes a driving circuit, a light emitting element, an energy storage circuit and a data writing-in circuit; the data writing-in circuit sequentially provides a display data voltage and a light emitting time control data voltage to the writing-in node under the control of a writing-in control signal; the writing-in node is the second node; or, the pixel circuit also includes a switch control circuit; the switch control circuit controls the connection between the driving circuit and the light emitting element under the control of a potential of the switch control terminal; the writing-in node includes a first writing-in node and a second writing-in node; the first writing-in node is the second node, and the second writing-in node is electrically connected to the switch control terminal. The present disclosure implement the control mode of combining driving current and light emitting time by sequentially writing a display data voltage and a light emitting time control data voltage, and improves the display effect.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technology, in particular to a pixel circuit, a driving method and a display device.BACKGROUND

[0002] Micro Light Emitting Diode (Micro LED) and Mini Light Emitting Diode (Mini LED) will be widely used in the future display field due to its high brightness and high reliability. As a self-light emitting device, the light emitting efficiency, brightness and color coordinates of LED will change with the current density at low current density. To achieve grayscale display, LED needs to be under high current density, that is, high current to achieve grayscale display. Traditional current control driving circuits cannot meet the requirements of grayscale display requirements of Micro LED and Mini LED.SUMMARY

[0003] In one aspect, the present disclosure provides in some embodiments a pixel circuit, including a driving circuit, a light emitting element, an energy storage circuit and a data writing-in circuit; a control terminal of the driving circuit is electrically connected to a first node, and the driving circuit is configured to generate a driving current to drive the light emitting element under the control of a potential of the first node; a first terminal of the energy storage circuit is electrically connected to the first node, a second terminal of the energy storage circuit is electrically connected to a second node, and the energy storage circuit is configured to store electrical energy; the data writing-in circuit is electrically connected to a writing-in control terminal and a writing-in node respectively, and is configured to sequentially provide a display data voltage and a light emitting time control data voltage to the writing-in node under the control of a writing-in control signal provided by the writing-in control terminal; the writing-in node is the second node; or, the pixel circuit also includes a switch control circuit; the switch control circuit is electrically connected to a switch control terminal, the driving circuit and the light emitting element, respectively, and is configured to control the connection between the driving circuit and the light emitting element under the control of a potential of the switch control terminal; the writing-in node includes a first writing-in node and a second writing-in node; the first writing-in node is the second node, and the second writing-in node is electrically connected to the switch control terminal.

[0004] Optionally, the writing-in node is the second node; the pixel circuit further comprises a first reset circuit and a second reset circuit; the first reset circuit is electrically connected to the reset control terminal, a reference voltage terminal and the second node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the second node under the control of a reset control signal provided by the reset control terminal during a reset time period set between a time period for writing the display data voltage and a time period for writing the light emitting time control data voltage; the second reset circuit is electrically connected to the reset control terminal, a first initial voltage terminal and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the reset control signal during the reset time period.

[0005] Optionally, the writing-in node is the second node; the writing-in control terminal includes a first control terminal and a second control terminal; the data line includes a first data line and a second data line; the display cycle of the pixel circuit includes a first writing-in time period and a second writing-in time period which are set successively; the data writing-in circuit is electrically connected to the first control terminal, the second control terminal, the first data line and the second data line respectively, and is configured to write the display data voltage provided by the second data line into the second node under the control of the second control signal provided by the second control terminal in the first writing-in time period, and to write the light emitting time control data voltage provided by the first data line into the second node under the control of the first control signal provided by the first control terminal in the second writing-in time period.

[0006] Optionally, the writing-in node is the second node; the pixel circuit further comprises a light emitting control circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to a third node; the light emitting control circuit is electrically connected to the light emitting control terminal, the third node and the first electrode of the light emitting element respectively, and is configured to control the connection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal; the second electrode of the light emitting element is electrically connected to the second voltage terminal; or, the first electrode of the light emitting element is electrically connected to the first voltage terminal; the light emitting control circuit is electrically connected to the light emitting control terminal, the second electrode of the light emitting element and the first terminal of the driving circuit respectively, and is configured to control the connection between the second electrode of the light emitting element and the first terminal of the driving circuit under the control of the light emitting control signal; the second terminal of the driving circuit is electrically connected to the second voltage terminal.

[0007] Optionally, the pixel circuit further comprises a switch control circuit; the writing-in node comprises a first writing-in node and a second writing-in node; the data writing-in circuit comprises a first writing-in sub-circuit and a second writing-in sub-circuit; the writing-in control terminal comprises a first control terminal and a scanning terminal; the first writing-in sub-circuit is electrically connected to the first control terminal, the first data line and the second writing-in node respectively, and is configured to write the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of the first control signal provided by the first control terminal; the second writing-in sub-circuit is electrically connected to the scanning terminal, the second data line and the first writing-in node respectively, and is configured to write the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal provided by the scanning terminal.

[0008] Optionally, the pixel circuit further comprises a light emitting control circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal; the second terminal of the driving circuit is electrically connected to the third node; the light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the switch control circuit respectively, and is configured to control the second terminal of the driving circuit to be connected to the switch control circuit under the control of the light emitting control signal provided by the light emitting control terminal; the first terminal of the switch control circuit is electrically connected to the second terminal of the driving circuit through the light emitting control circuit, the second terminal of the switch control circuit is electrically connected to the first electrode of the light emitting element, and the switch control circuit is configured to control the connection between the light emitting control circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; the second electrode of the light emitting element is electrically connected to the second voltage terminal.

[0009] Optionally, the pixel circuit further comprises a light emitting control circuit; the first electrode of the light emitting element is electrically connected to the first voltage terminal; the first terminal of the driving circuit is electrically connected to a third node; a first terminal of the switch control circuit is electrically connected to the second electrode of the light emitting element, a second terminal of the switch control circuit is electrically connected to the first terminal of the driving circuit through the light emitting control circuit, and the switch control circuit is configured to control the connection between the second electrode of the light emitting element and the light emitting control circuit under the control of the potential of the switch control terminal; the light emitting control circuit is electrically connected to the light emitting control terminal, the switch control circuit and the first terminal of the driving circuit respectively, and is configured to control the switch control circuit to be connected to the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; the second terminal of the driving circuit is electrically connected to the second voltage terminal.

[0010] Optionally, the pixel circuit further includes an initialization circuit and a voltage maintenance circuit; wherein the initialization circuit is electrically connected to the second control terminal, the second initial voltage terminal and the second writing-in node respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the second writing-in node under the control of the second control signal provided by the second control terminal; the voltage maintaining circuit is electrically connected to the switch control terminal and is configured to maintain a potential of the switch control terminal.

[0011] Optionally, the pixel circuit further includes a compensation control circuit and a voltage control circuit; wherein the compensation control circuit is electrically connected to the scanning terminal, the first node and the third node respectively, and is configured to control the connection between the first node and the third node under the control of the scanning signal provided by the scanning terminal; the voltage control circuit is electrically connected to the light emitting control terminal, the reference voltage terminal and the second node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the second node under the control of the light emitting control signal provided by the light emitting control terminal.

[0012] Optionally, the light emitting element is an inorganic light emitting diode, a width-to-length ratio of a transistor included in the light emitting control circuit is greater than 1, and a width-to-length ratio of a transistor included in the driving circuit is greater than 0.5.

[0013] Optionally, the light emitting element is an inorganic light emitting diode, a width-to-length ratio of a transistor included in the switch control circuit is greater than 1, and a width-to-length ratio of a transistor included in the driving circuit is greater than 0.5.

[0014] Optionally, the energy storage circuit comprises a storage capacitor; the light emitting element is an inorganic light emitting diode; a capacitance value of the storage capacitor is greater than 3 times a gate-source capacitance of the transistor in the driving circuit.

[0015] Optionally, the first reset circuit comprises a first transistor, and the second reset circuit comprises a second transistor; a gate electrode of the first transistor is electrically connected to the reset control terminal, a first electrode of the first transistor is electrically connected to the reference voltage terminal, and a second electrode of the first transistor is electrically connected to the second node; a gate electrode of the second transistor is electrically connected to the reset control terminal, a first electrode of the second transistor is electrically connected to the first initial voltage terminal, and a second electrode of the second transistor is electrically connected to the first node.

[0016] Optionally, the data writing-in circuit comprises a third transistor and a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the second node; a gate electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the second node.

[0017] Optionally, the data writing-in circuit comprises a third transistor; a gate electrode of the third transistor is electrically connected to the scanning terminal, a first electrode of the third transistor is electrically connected to the data line, and a second electrode of the third transistor is electrically connected to the second node; the data line is configured to provide display data voltage and light emitting time control data voltage in time division manner.

[0018] Optionally, the first writing-in sub-circuit comprises a third transistor, and the second writing-in sub-circuit comprises a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the second writing-in node; a gate electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the first writing-in node.

[0019] Optionally, the light emitting control circuit comprises a fifth transistor; and the driving circuit comprises a driving transistor; a second electrode of the driving transistor is electrically connected to the third node; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the fifth transistor is electrically connected to the first electrode of the light emitting element; a gate electrode of the driving transistor is electrically connected to the first node, and a first electrode of the driving transistor is electrically connected to the first voltage terminal; or, the first electrode of the light emitting element is electrically connected to the first voltage terminal, the gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the light emitting element, and the second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; the gate electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second voltage terminal.

[0020] Optionally, the compensation control circuit comprises a sixth transistor, and the voltage control circuit comprises a seventh transistor; a gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the first node, and a second electrode of the sixth transistor is electrically connected to the third node; a gate electrode of the seventh transistor is electrically connected to the light emitting control terminal, a first electrode of the seventh transistor is electrically connected to a reference voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second node.

[0021] Optionally, the light emission control circuit comprises a fifth transistor; the switch control circuit comprises an eighth transistor; and the driving circuit comprises a driving transistor; a gate electrode of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the first voltage terminal, and a second electrode of the driving transistor is electrically connected to the third node; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the third node, and a second electrode of the fifth transistor is electrically connected to a first electrode of the eighth transistor; a gate electrode of the eighth transistor is electrically connected to the switch control terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.

[0022] Optionally, the light emitting control circuit comprises a fifth transistor; the switch control circuit comprises an eighth transistor; and the driving circuit comprises a driving transistor; a gate electrode of the eighth transistor is electrically connected to the switch control terminal, a first electrode of the eighth transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the eighth transistor is electrically connected to a first electrode of the fifth transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, and a second electrode of the fifth transistor is electrically connected to a first electrode of the driving transistor; a gate electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the second voltage terminal.

[0023] Optionally, the initialization circuit comprises a ninth transistor, the energy storage circuit comprises a first capacitor; and the voltage maintenance circuit comprises a second capacitor; a gate electrode of the ninth transistor is electrically connected to the second control terminal, a first electrode of the ninth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the second writing-in node; a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the second node; a first terminal of the second capacitor is electrically connected to the switch control terminal, and a second terminal of the second capacitor is electrically connected to a DC voltage terminal.

[0024] In a second aspect, an embodiment of the present disclosure provides a driving method, applied to the pixel circuit, the driving method comprises: generating, by the driving circuit, the driving current for driving the light emitting element; providing, by the data writing-in circuit, under the control of the writing-in control signal provided by the writing-in control terminal, the display data voltage and the light emitting time control data voltage to the writing-in node successively.

[0025] Optionally, the writing-in node is the second node; the pixel circuit further comprises a first reset circuit and a second reset circuit; the display cycle of the pixel circuit comprises a first display phase and a second display phase which are arranged successively, the first display phase comprises a first reset time period, and the second display phase comprises a second reset time period; the driving method comprises: in the first reset time period and the second reset time period, writing, by the first reset circuit, the reference voltage into the second node under the control of the reset control signal, and writing, by the second reset circuit, the first initial voltage into the first node under the control of the reset control signal.

[0026] Optionally, the first display phase includes a first writing-in time period arranged after the first reset time period, and the second display period includes a second writing-in time period arranged after the second reset time period; the driving method comprises: in the first writing-in time period, providing, by the data writing-in circuit, a display data voltage to the second node under the control of a writing-in control signal; in the second writing-in period, providing, by the data writing-in circuit, the light emitting time control data voltage to the second node under the control of a writing-in control signal.

[0027] Optionally, the writing-in node is the second node; the pixel circuit further comprises a first reset circuit and a second reset circuit; the display cycle comprises a first display phase and A second display phases; A is an integer greater than 1, and a is a positive integer less than but equal to A; the first display stage is set before the A second display phases; the first display phase comprises a first reset time period and a first writing-in time period which are set in sequence, and an ath second display phase comprises an ath second reset time period and an ath second writing-in time period which are set in sequence; the driving method comprises: in the first reset time period and the ath second reset time period, writing, by the first reset circuit, the reference voltage into the second node under the control of the reset control signal, and writing, by the second reset circuit, the first initial voltage into the first node under the control of the reset control signal; in a first writing-in period, providing, by the data writing-in circuit, a display data voltage to the second node under the control of a writing-in control signal; in the ath second writing-in period, providing, by the data writing-in circuit, the ath light emitting time control data voltage to the second node under the control of the writing-in control signal.

[0028] Optionally, the first display phase includes a first writing-in time period, the second display period includes a second writing-in time period; the pixel circuit further includes a switch control circuit; the writing-in node includes a first writing-in node and a second writing-in node; the data writing-in circuit includes a first writing-in sub-circuit and a second writing-in sub-circuit; the driving method includes: in a first writing-in time period, writing, by the second writing-in sub-circuit, the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal; in the second writing-in time period, writing, by the first writing-in sub-circuit, the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of the first control signal provided by the first control terminal.

[0029] In a third aspect, an embodiment of the present disclosure provides a display device comprising the pixel circuit.BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 14 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 17 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 18 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 19 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 20 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 21 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 22 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 23 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 24 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 25 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 26 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 27 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 28 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 29 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 30 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 31 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 32 is a timing diagram of the pixel circuit shown in FIG. 31; FIG. 33A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in a first reset time period S11; FIG. 33B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in the first writing-in time period S12; FIG. 33C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in the first light emitting time period S13; FIG. 33D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in a second reset time period S21; FIG. 33E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in a second writing-in time period S22; FIG. 34A is a schematic diagram of simulation results of a high grayscale display of the pixel circuit shown in FIG. 31; FIG. 34B is a schematic diagram showing simulation results of low grayscale display of the pixel circuit shown in FIG. 31; FIG. 35 is a timing diagram of the pixel circuit shown in FIG. 31; FIG. 36 is a schematic diagram of the light emitting time of the pixel circuit shown in FIG. 31 when emitting light at a high grayscale and a low grayscale; FIG. 37 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 38 is a timing diagram of the pixel circuit shown in FIG. 37; FIG. 39 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 40 is a timing diagram of the pixel circuit shown in FIG. 39; FIG. 41A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in a first reset time period S11; FIG. 41B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in the first writing-in time period S12; FIG. 41C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in the first light emitting time period S13; FIG. 41D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in a second writing-in time period S22; FIG. 41E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in the second light emitting time period S23; FIG. 42A is a schematic diagram showing simulation results of a high grayscale display of the pixel circuit shown in FIG. 39; FIG. 42B is a schematic diagram showing simulation results of low grayscale display of the pixel circuit shown in FIG. 39; FIG. 43A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 43B is a first timing diagram of the pixel circuit shown in FIG. 43A of the present disclosure; FIG. 43C is a second timing diagram of the pixel circuit shown in FIG. 43A of the present disclosure; FIG. 44 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 45A is a first timing diagram of the pixel circuit shown in FIG. 44; FIG. 45B is a timing diagram of the pixel circuit shown in FIG. 44; FIG. 46 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 47A is a first timing diagram of the pixel circuit shown in FIG. 46 of the present disclosure; FIG. 47B is a second timing diagram of the pixel circuit shown in FIG. 46 of the present disclosure; FIG. 48A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 46 in a first reset time period S11; FIG. 48B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 46 in the first writing-in time period S12; FIG. 48C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 46 in the first light emitting time period S13; FIG. 48D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 46 in the second writing-in time period S22; FIG. 48E is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the second light emitting time period S23; FIG. 49 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 50A is a first timing diagram of the pixel circuit shown in FIG. 49; FIG. 50B is a second timing diagram of the pixel circuit shown in FIG. 49; FIG. 51 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 52 is a timing diagram of the pixel circuit shown in FIG. 51; FIG. 53A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 in the first writing-in time period S12 and the first light emitting time period S22; FIG. 53B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 in a second writing-in time period S21 and a second light emitting time period S22; FIG. 53C is a schematic diagram of the working state of the pixel circuit shown in FIG. 51 during a reset time period SC1; FIG. 53D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 during the compensation time period SC2; FIG. 53E is a schematic diagram of the working state of the pixel circuit shown in FIG. 51 during the extraction time period SC3; FIG. 54A is a schematic diagram showing simulation results of high grayscale display in a display phase of the pixel circuit shown in FIG. 51; FIG. 54B is a schematic diagram of simulation results of performing low grayscale display in the display phase of the pixel circuit shown in FIG. 51; FIG. 55 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 56 is a timing diagram of the pixel circuit shown in FIG. 55; FIG. 57 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 58 is a timing diagram of the pixel circuit shown in FIG. 57; FIG. 59 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 60 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 61 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 62 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 63 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 64 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 65 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 66 is a timing diagram of the pixel circuit shown in FIG. 65; FIG. 67A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 in a first reset time period; FIG. 67B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 during a first writing-in time period; FIG. 67C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 in the first light emitting time period; FIG. 67D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 in a second reset time period; FIG. 67E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 during a second writing-in time period; FIG. 67F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 in the second light emitting time period; FIG. 68A is a schematic diagram showing simulation results of a the pixel circuit shown in FIG. 66 when performing high grayscale display; FIG. 68B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 66 when performing low grayscale display; FIG. 69 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 70 is a timing diagram of the pixel circuit shown in FIG. 69; FIG. 71 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 72 is a timing diagram of the pixel circuit shown in FIG. 71; FIG. 73A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 71 when performing high grayscale display; FIG. 73B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 71 when performing low grayscale display; FIG. 74 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 75 is a timing diagram of the pixel circuit shown in FIG. 74; FIG. 76A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 in a first reset time period; FIG. 76B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 during a first writing-in time period; FIG. 76C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 in the first light emitting time period; FIG. 76D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 in a second reset time period; FIG. 76E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 during a second writing-in time period; FIG. 76F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 in the second light emitting time period; FIG. 77A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 74 when performing high grayscale display; FIG. 77B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 74 when performing low grayscale display; FIG. 78 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 79 is a timing diagram of the pixel circuit shown in FIG. 78; FIG. 80 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 81 is a timing diagram of the pixel circuit shown in FIG. 80; FIG. 82 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 83 is a timing diagram of the pixel circuit shown in FIG. 82; FIG. 84A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 83 when performing high grayscale display; FIG. 84B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 83 when performing low grayscale display; FIG. 85 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 86 is a first timing diagram of the pixel circuit shown in FIG. 85; FIG. 87 is a second timing diagram of the pixel circuit shown in FIG. 85; FIG. 88 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 89 is a first timing diagram of the pixel circuit shown in FIG. 88; FIG. 90 is a second timing diagram of the pixel circuit shown in FIG. 88; FIG. 91A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in a first reset time period S11; FIG. 91B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in the first writing-in time period S12; FIG. 91C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in the first light emitting time period S13; FIG. 91D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in the second writing-in time period S22; FIG. 91E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in the second light emitting time period S23; FIG. 92 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 93 is a first timing diagram of the pixel circuit shown in FIG. 92; FIG. 94 is a second timing diagram of the pixel circuit shown in FIG. 92; FIG. 95 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 96 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 97 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 98 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 99 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 100 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 101 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 102 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 103 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 104 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 105 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 106 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 107 is a timing diagram of the pixel circuit shown in FIG. 106; FIG. 108A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in a first reset time period; FIG. 108B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in the first writing-in time period; FIG. 108C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in the first light emitting time period; FIG. 108D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in a second reset time period; FIG. 108E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 during a second writing-in time period; FIG. 108F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in a second light emitting time period; FIG. 109A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 106 of the present disclosure when performing a low grayscale display; FIG. 109B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 106 of the present disclosure when performing a high grayscale display; FIG. 110 is a timing diagram of the pixel circuit shown in FIG. 106; FIG. 111 is a schematic diagram of the light emitting time of the pixel circuit shown in FIG. 106 when emitting light at a high grayscale and at a low grayscale; FIG. 112 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 113 is a timing diagram of the pixel circuit shown in FIG. 112; FIG. 114 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 115A is a timing diagram of the pixel circuit shown in FIG. 114; FIG. 115B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 114 when performing high grayscale display; FIG. 115C is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 114 when performing high grayscale display; FIG. 116 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 117 is a timing diagram of the pixel circuit shown in FIG. 116; FIG. 118 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 119 is a timing diagram of the pixel circuit shown in FIG. 118; FIG. 120A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 in a first reset time period; FIG. 120B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 in a first writing-in time period; FIG. 120C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 in the first light emitting time period; FIG. 120D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 during a second writing-in time period; FIG. 120E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 in the second light emitting time period; FIG. 121A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 118 when performing high grayscale display; FIG. 121B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 118 when performing low grayscale display; FIG. 122 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 123 is a timing diagram of the pixel circuit shown in FIG. 122; FIG. 124A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in a first reset time period S11; FIG. 124B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in the first writing-in time period S12; FIG. 124C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in the first light emitting time period S13; FIG. 124D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in the second writing-in time period S22; FIG. 124E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in the second light emitting time period S23; FIG. 125A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 122 when performing high grayscale display; FIG. 125B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 122 when performing low grayscale display; FIG. 126 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 127 is a timing diagram of the pixel circuit shown in FIG. 126; FIG. 128 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 129 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 130 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 131 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 132 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 133 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 134 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 135 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 136 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 137 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 138 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 139 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 140 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 141 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 142 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 143 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 144 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 145 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 146 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 147 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 148 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 149 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 150 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 151 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 152 is a timing diagram of the pixel circuit shown in FIG. 151; FIG. 153A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 in a first reset time period; FIG. 153B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 during a first compensation time period; FIG. 153C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 during a first writing-in time period; FIG. 153D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 in a second reset time period; FIG. 153E is a schematic diagram of the working state of the pixel circuit shown in FIG. 151 in the first light emitting time period; FIG. 153F is a schematic diagram of the working state of the pixel circuit shown in FIG. 151 in a third reset time period; FIG. 153G is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 during a second compensation time period; FIG. 153H is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 during a second writing-in time period; FIG. 153I is a schematic diagram of the working state of the pixel circuit shown in FIG. 151 in a fourth reset time period; FIG. 153J is a schematic diagram of the working state of the pixel circuit shown in FIG. 151 in the second light emitting time period; FIG. 154A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 151 of the present disclosure when performing high grayscale display; FIG. 154B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 151 of the present disclosure when performing low grayscale display; FIG. 155 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 156 is a timing diagram of the pixel circuit shown in FIG. 155; FIG. 157 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 158 is a timing diagram of the pixel circuit shown in FIG. 157; FIG. 159 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 160 is a timing diagram of the pixel circuit shown in FIG. 159; FIG. 161 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 162 is a timing diagram of the pixel circuit shown in FIG. 161; FIG. 163 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 164 is a timing diagram of the pixel circuit shown in FIG. 163; FIG. 165 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 166 is a timing diagram of the pixel circuit shown in FIG. 165; FIG. 167 is a timing diagram of the pixel circuit shown in FIG. 165; FIG. 168 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 169 is a first timing diagram of the pixel circuit shown in FIG. 168; FIG. 170 is a second timing diagram of the pixel circuit shown in FIG. 168; FIG. 171 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 172 is a timing diagram of the pixel circuit shown in FIG. 171; FIG. 173A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 in a first reset time period; FIG. 173B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 during a first compensation time period; FIG. 173C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 during a first writing-in time period; FIG. 173D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 in the first light emitting time period; FIG. 173E is a schematic diagram of the working state of the pixel circuit shown in FIG. 171 during a second reset time period; FIG. 173F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 during a second compensation time period; FIG. 173G is a schematic diagram of the working state of the pixel circuit shown in FIG. 171 during a second writing-in time period; FIG. 173H is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 in the second light emitting time period; FIG. 174A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 171 when performing high grayscale display; FIG. 174B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 171 when performing low grayscale display; FIG. 175 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 176 is a timing diagram of the pixel circuit shown in FIG. 175 of the present disclosure; FIG. 177 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 178 is a timing diagram of the pixel circuit shown in FIG. 177 of the present disclosure; FIG. 179 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 180 is a first timing diagram of the pixel circuit shown in FIG. 179 of the present disclosure; FIG. 181 is a second timing diagram of the pixel circuit shown in FIG. 179 of the present disclosure; FIG. 182 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 183 is a first timing diagram of the pixel circuit shown in FIG. 182 of the present disclosure; FIG. 184 is a second timing diagram of the pixel circuit shown in FIG. 182 of the present disclosure; FIG. 185 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 186 is a timing diagram of the pixel circuit shown in FIG. 185; FIG. 187A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 in a first reset time period; FIG. 187B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 during a first compensation time period; FIG. 187C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 in the first light emitting time period; FIG. 187D is a schematic diagram of the working state of the pixel circuit shown in FIG. 185 in a third reset time period; FIG. 187E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 during a second compensation time period; FIG. 187F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 in the second light emitting time period; FIG. 188A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 185 when performing high grayscale display; FIG. 188B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 185 when performing low grayscale display; FIG. 189 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 190 is a timing diagram of the pixel circuit shown in FIG. 189 of the present disclosure; FIG. 191 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 192 is a timing diagram of the pixel circuit shown in FIG. 191 of the present disclosure; FIG. 193 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 194 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 195 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 196 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 197 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 198 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 199 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 200 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 201 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 202 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 203 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 204 is a timing diagram of the pixel circuit shown in FIG. 203; FIG. 205A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 in a first writing-in time period; FIG. 205B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 in the first light emitting time period; FIG. 205C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 during a second writing-in time period; FIG. 205D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 in the second light emitting time period; FIG. 205E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 during a sensing reset time period; FIG. 205F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 during a compensation time period; FIG. 205G is a schematic diagram of the working state of the pixel circuit shown in FIG. 203 during an extraction time period; FIG. 206A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 203 when performing high grayscale display; FIG. 206B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 203 when performing low grayscale display; FIG. 207 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 208 is a timing diagram of the pixel circuit shown in FIG. 207; FIG. 209A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 in a first writing-in time period; FIG. 209B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 in the first light emitting time period; FIG. 209C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 during a second writing-in time period; FIG. 209D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 in the second light emitting time period; FIG. 209E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 during a sensing reset time period; FIG. 209F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 during a compensation time period; FIG. 209G is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 during an extraction time period; FIG. 210A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 207 when performing high grayscale display; FIG. 210B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 207 when performing low grayscale display; FIG. 211 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 212 is a timing diagram of the pixel circuit shown in FIG. 211; FIG. 213A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 211 when performing high grayscale display; FIG. 213B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 211 when performing low grayscale display; FIG. 214 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 215 is a timing diagram of the pixel circuit shown in FIG. 214; FIG. 216 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 217 is a timing diagram of the pixel circuit shown in FIG. 216; FIG. 218 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 219 is a timing diagram of the pixel circuit shown in FIG. 218; FIG. 220 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 221 is a timing diagram of the pixel circuit shown in FIG. 220; FIG. 222 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 223 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 224 is a timing diagram of the pixel circuit shown in FIG. 223; FIG. 225 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 226 is a timing diagram of the pixel circuit shown in FIG. 225; FIG. 227 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 228 is a timing diagram of the pixel circuit shown in FIG. 227; FIG. 229A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 during a first writing-in time period; FIG. 229B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 in the first light emitting time period; FIG. 229C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 during a second writing-in time period; FIG. 229D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 in the second light emitting time period; FIG. 229E is a schematic diagram of the working state of the pixel circuit shown in FIG. 227 during a sensing reset time period; FIG. 229F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 during a compensation time period; FIG. 229G is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 during an extraction time period; FIG. 230 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 231 is a circuit diagram of a pixel circuit described in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present disclosure.

[0032] The transistors used in all embodiments of the present disclosure may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiment of the present disclosure, in order to distinguish the two electrodes of the transistor except the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode.

[0033] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode. The pixel circuit described in the embodiment of the present disclosure includes a driving circuit, a switch control circuit, a light emitting element, a driving control circuit and a first reset circuit; a control terminal of the driving circuit is electrically connected to a first node, and is configured to generate a driving current to drive the light emitting element under the control of a potential of the first node; The driving circuit is electrically connected to the light emitting element or a first voltage terminal through the switch control circuit, and the switch control circuit is electrically connected to a switch control terminal, and the switch control circuit is configured to control the connection between the driving circuit and the light emitting element or the first voltage terminal under the control of a potential of the switch control terminal; The driving control circuit is electrically connected to a first control terminal and a first data line respectively, and is configured to write a light emitting time control data voltage provided by the first data line into the switch control terminal under the control of a first control signal provided by the first control terminal; The first reset circuit is configured to write a set voltage into a second node, a first electrode of the light emitting element or a second electrode of the light emitting element under the control of a set control signal provided by a set control terminal.

[0034] In at least one embodiment of the present disclosure, the pixel circuit may include a driving circuit, a switch control circuit, a light emitting element, a driving control circuit and a first reset circuit; the driving control circuit writes a light emitting time control data voltage into the switch control terminal under the control of a first control signal; the first reset circuit writes a set voltage into a second node, a first electrode of the light emitting element or a second electrode of the light emitting element under the control of a set control signal, so as to initialize the potential of the second node, the potential of the first electrode of the light emitting element or the potential of the second electrode of the light emitting element before the light emitting phase; At least one embodiment of the present disclosure writes a light emitting time control data voltage into a switch control terminal through the driving control circuit in a second data writing-in time period included in a second display phase arranged after the first display phase, so as to control the light emitting time of the light emitting element according to the light emitting time control data voltage during the light emitting time period included in the second display phase, so as to delay writing-in the light emitting time control data voltage into the pixel circuit, control the pixel circuit with a driving current + light emitting time, and improve the display effect of the light emitting element.

[0035] Optionally, the light emitting element is an inorganic light emitting diode, a width-to-length ratio of a transistor included in the switch control circuit is greater than 1, and a width-to-length ratio of a transistor included in the driving circuit is greater than 0.5.

[0036] In at least one embodiment of the present disclosure, the light emitting element may be an inorganic light emitting diode, for example, the light emitting element may be a micro light emitting diode or a mini light emitting diode.

[0037] In a specific implementation, when the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the driving transistor included in the driving circuit is greater than 0.5, and the width-to-length ratio of the transistor included in the switch control circuit is greater than 1.

[0038] Optionally, the light emitting element may also be an organic light emitting diode.

[0039] In at least one embodiment of the present disclosure, the width-to-length ratio of a transistor is a ratio of a channel width W to a channel length L of the transistor.

[0040] In at least one embodiment of the present disclosure, the set voltage may be a reference voltage, a first initial voltage, or a second initial voltage, but is not limited thereto.

[0041] Optionally, the set control terminal may be a reset control terminal, but is not limited thereto.

[0042] Optionally, the light emitting element may be an OLED (organic light emitting diode), a Mini LED (mini light emitting diode) or a Micro-LED (micro light emitting diode), but is not limited thereto.

[0043] Optionally, the first electrode of the light emitting element may be an anode, and the second electrode of the light emitting element may be a cathode. Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes an energy storage circuit; The first terminal of the energy storage circuit is electrically connected to the first node, the second terminal of the energy storage circuit is electrically connected to the second node, and the energy storage circuit is configured to store electrical energy; The first reset circuit is configured to write a set voltage into the second node under the control of the set control signal.

[0044] Optionally, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal, but is not limited thereto.

[0045] In at least one embodiment of the present disclosure, the energy storage circuit may include a storage capacitor; the light emitting element may be an inorganic light emitting diode; The capacitance value of the storage capacitor is greater than 3 times the gate-source capacitance of the transistor in the driving circuit. In a specific implementation, the capacitance value of the storage capacitor is set to be greater than 3 times the gate-source capacitance of the transistor in the driving circuit, so that when the source potential of the transistor in the driving circuit changes, the potential of the gate electrode of the transistor in the driving circuit can be maintained to ensure display accuracy.

[0046] In at least one embodiment of the present disclosure, the gate-source capacitance of the transistor in the driving circuit may be a parasitic capacitance between the gate electrode and the source electrode of the transistor in the driving circuit, which may be calculated based on the facing area of the gate electrode and the source electrode of the transistor in the driving circuit, and a dielectric constant, wherein the dielectric constant may be calculated based on the material and thickness of the insulating layer between the gate electrode and the source electrode of the transistor in the driving circuit. As shown in FIG. 1, the pixel circuit described in the embodiment of the present disclosure includes an energy storage circuit 10, a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13 and a first reset circuit 14; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving circuit 11 is electrically connected to the first electrode of the light emitting element E1 through the switch control circuit 12; The first terminal of the driving circuit 11 is electrically connected to the first voltage terminal V1; The switch control circuit 12 is electrically connected to the switch control terminal N4, the second terminal of the driving circuit 11 and the first electrode of the light emitting element E1 respectively. The switch control circuit is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the reference voltage terminal and the second node N2 respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the reset control signal provided by the first reset control terminal RST1;

[0047] The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, and the second terminal of the energy storage circuit 10 is electrically connected to the second node N2. The energy storage circuit 10 is configured to store electrical energy. As shown in FIG. 2, the pixel circuit described in the embodiment of the present disclosure includes a storage circuit 10, a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13 and a first reset circuit 14; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving circuit 11 is electrically connected to the second electrode of the light emitting element E1 through the switch control circuit 12; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The switch control circuit 12 is electrically connected to the switch control terminal N4, the first terminal of the driving circuit 11 and the second electrode of the light emitting element E1 respectively, and the switch control circuit 12 is configured to control the connection between the first terminal of the driving circuit 11 and the second electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the reference voltage terminal and the second node N2 respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the first reset control signal provided by the first reset control terminal RST1;

[0048] The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, and the second terminal of the energy storage circuit 10 is electrically connected to the second node N2. The energy storage circuit 10 is configured to store electrical energy. As shown in FIG. 3, the pixel circuit described in the embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13 and a first reset circuit 14; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving circuit 11 is electrically connected to the first voltage terminal V1 through the switch control circuit 12; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4, the first terminal of the switch control circuit 12 is electrically connected to the first voltage terminal V1, the second terminal of the switch control circuit 12 is electrically connected to the first terminal of the driving circuit 11, and the switch control circuit 12 is configured to control the connection between the first voltage terminal V1 and the first terminal of the driving circuit 11 under the control of the potential of the switch control terminal N4; The second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the first selection control terminal X1, the scanning terminal G1, the reference voltage terminal and the first electrode of the light emitting element E1, respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the first selection control signal provided by the first selection control terminal X1 and the scanning signal provided by the scanning terminal G1;

[0049] The first electrode of the light emitting element E1 is electrically connected to the second node N2. As shown in FIG. 4, the pixel circuit described in the embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13 and a first reset circuit 14; The first terminal of the driving circuit 11 is electrically connected to the first voltage terminal; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4, the first terminal of the switch control circuit 12 is electrically connected to the second terminal of the driving circuit 11, the second terminal of the switch control circuit 12 is electrically connected to the first electrode of the light emitting element E1, and the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; The switch control circuit 12 is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the first selection control terminal X1, the scanning terminal G1, the reference voltage terminal and the first electrode of the light emitting element E1, respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the first selection control signal provided by the first selection control terminal X1 and the scanning signal provided by the scanning terminal G1;

[0050] The first electrode of the light emitting element E1 is electrically connected to the second node. In at least one embodiment of the present disclosure, the driving circuit is electrically connected to the first electrode of the light emitting element through the switch control circuit, and the switch control circuit is configured to control the connection between the driving circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; the second electrode of the light emitting element is electrically connected to the second voltage terminal;

[0051] The first reset circuit is configured to write a set voltage into the first electrode of the light emitting element under the control of the set control signal during a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage.

[0052] In a specific implementation, the driving circuit can be electrically connected to the first electrode of the light emitting element through the switch control circuit. At this time, the first reset circuit can write the set voltage into the first electrode of the light emitting element under the control of the set control signal during the reset time period, so as to initialize the potential of the first electrode of the light emitting element before emitting light in each display cycle, clear the residual charge in the first electrode of the light emitting element, and improve the flicker phenomenon.

[0053] In at least one embodiment of the present disclosure, when the potential of the first electrode of the light emitting element is initialized, the light emitting element does not emit light. When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase which are set in sequence; the first display phase may include a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase may include a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence; In the first reset time period and the second reset time period, the first reset circuit writes a set voltage into the first electrode of the light emitting element under the control of the set control signal; In a first writing-in time period, writing-in a display data voltage; In the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage; In the second writing-in time period, writing-in the light emitting time control data voltage; In the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to control whether the light emitting element emits light.

[0054] The reset time period provided between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage may be the second reset time period. Optionally, the first electrode of the light emitting element is electrically connected to the first voltage terminal; The driving circuit is electrically connected to the second electrode of the light emitting element through the switch control circuit, and the switch control circuit is configured to control the connection between the driving circuit and the first voltage terminal under the control of the potential of the switch control terminal;

[0055] The first reset circuit is configured to write a set voltage into the second electrode of the light emitting element under the control of the set control signal.

[0056] In a specific implementation, the first electrode of the light emitting element can be electrically connected to the first voltage terminal, and the driving circuit can be electrically connected to the second electrode of the light emitting element through the switch control circuit. At this time, the first reset circuit can write the set voltage into the second electrode of the light emitting element under the control of the set control signal during the reset time period, so as to initialize the potential of the second electrode of the light emitting element before emitting light in each display cycle, clear the residual charge at the second electrode of the light emitting element, and improve the flicker phenomenon.

[0057] In at least one embodiment of the present disclosure, when the potential of the second electrode of the light emitting element is initialized, the light emitting element does not emit light.

[0058] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase which are set in sequence; the first display phase may include a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase may include a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence. In the first reset time period and the second reset time period, the first reset circuit writes a set voltage into the second electrode of the light emitting element under the control of the set control signal; In a first writing-in time period, writing-in a display data voltage; In the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage; In the second writing-in time period, writing-in the light emitting time control data voltage; In the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to control whether the light emitting element emits light.

[0059] The reset time period provided between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage may be the second reset time period. In at least one embodiment of the present disclosure, the pixel circuit further includes an energy storage circuit; The first terminal of the energy storage circuit is electrically connected to the first node, the second terminal of the energy storage circuit is electrically connected to the first electrode of the light emitting element, and the energy storage circuit is configured to store electrical energy; The first terminal of the switch control circuit is electrically connected to the first voltage terminal, the second terminal of the switch control circuit is electrically connected to the first terminal of the driving circuit, the second terminal of the driving circuit is electrically connected to the first electrode of the light emitting element, and the second electrode of the light emitting element is electrically connected to the second voltage terminal; the switch control circuit is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the potential of the switch control terminal; or the first terminal of the driving circuit is electrically connected to the first voltage terminal; the first terminal of the switch control circuit is electrically connected to the second terminal of the driving circuit, the second terminal of the switch control circuit is electrically connected to the first electrode of the light emitting element, and the second terminal of the light emitting element is electrically connected to the second voltage terminal; the switch control circuit is configured to control the connection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scanning terminal and a first selection control terminal; The compensation circuit is electrically connected to the scanning terminal, the first electrode of the light emitting element and the control node respectively, and is configured to control the first electrode of the light emitting element to be connected to the control node under the control of the scanning signal provided by the scanning terminal; or, the compensation circuit is electrically connected to the scanning terminal, the second terminal of the driving circuit and the control node respectively, and is configured to control the second terminal of the driving circuit to be connected to the control node under the control of the scanning signal;

[0060] The switch circuit is connected to the first selection control terminal, the control node and the set voltage terminal respectively, and is configured to provide the set voltage written by the set voltage terminal provided to the control node under the control of the first selection control signal provided by the first selection control terminal. As shown in FIG. 5, based on the pixel circuit shown in FIG. 3, the pixel circuit further includes a storage circuit 10 and a first reset circuit; The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, the second terminal of the energy storage circuit 10 is electrically connected to the first electrode of the light emitting element E1, and the energy storage circuit 10 is configured to store electrical energy; The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scanning terminal G1 and a first selection control terminal X1; The compensation circuit 21 is electrically connected to the scanning terminal G1, the first electrode of the light emitting element E1 and the control node N0 respectively, and is configured to control the connection between the first electrode of the light emitting element E1 and the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0061] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is configured to provide the reference voltage Vref written by the reference voltage terminal to the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1. As shown in FIG. 6, based on the pixel circuit shown in FIG. 4, the pixel circuit further includes a storage circuit 10 and a first reset circuit; The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, the second terminal of the energy storage circuit 10 is electrically connected to the first electrode of the light emitting element E1, and the energy storage circuit 10 is configured to store electrical energy; The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scanning terminal G1 and a first selection control terminal X1; The compensation circuit 21 is electrically connected to the scanning terminal G1, the first electrode of the light emitting element E1 and the control node N0 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0062] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is configured to provide the reference voltage Vref provided by the reference voltage terminal to the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1. In at least one embodiment of the present disclosure, the pixel circuit further includes an energy storage circuit; a first terminal of the energy storage circuit is electrically connected to the first node, a second terminal of the energy storage circuit is electrically connected to the second electrode of the light emitting element, and the energy storage circuit is configured to store electrical energy; the first electrode of the light emitting element is electrically connected to the first voltage terminal, the first terminal of the switch control circuit is electrically connected to the second electrode of the light emitting element, the second terminal of the switch control circuit is electrically connected to the first terminal of the driving circuit, and the second terminal of the driving circuit is electrically connected to the second voltage terminal; the switch control circuit is configured to control the second electrode of the light emitting element to be connected to the first terminal of the driving circuit under the control of the potential of the switch control terminal; or the first electrode of the light emitting element is electrically connected to the first voltage terminal, and the second electrode of the light emitting element is electrically connected to the first terminal of the driving circuit; the first terminal of the switch control circuit is electrically connected to the second terminal of the driving circuit, and the second terminal of the switch control circuit is electrically connected to the second voltage terminal; the switch control circuit is configured to control the second terminal of the driving circuit to be connected to the first electrode of the light emitting element under the control of the potential of the switch control terminal; The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scanning terminal and a first selection control terminal; The compensation circuit is electrically connected to the scanning terminal, the second electrode of the light emitting element and the control node respectively, and is configured to control the second electrode of the light emitting element to be connected to the control node under the control of the scanning signal; or the compensation circuit is electrically connected to the scanning terminal, the first terminal of the driving circuit and the control node respectively, and is configured to control the first terminal of the driving circuit to be connected to the control node under the control of the scanning signal;

[0063] The switch circuit is connected to the first selection control terminal, the control node and the set voltage terminal respectively, and is configured to write the set voltage provided by the set voltage terminal to the control node under the control of the first selection control signal provided by the first selection control terminal. As shown in FIG. 7, the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13, an energy storage circuit 10 and a first reset circuit; The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, the second terminal of the energy storage circuit 10 is electrically connected to the second electrode of the light emitting element E1, and the energy storage circuit 10 is configured to store electric energy; the second electrode of the light emitting element E1 is electrically connected to the second node N2; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1, the first terminal of the switch control circuit 12 is electrically connected to the second electrode of the light emitting element E1, the second terminal of the switch control circuit 12 is electrically connected to the first terminal of the driving circuit 11, and the second terminal of the driving circuit 11 is electrically connected to the second voltage terminal V2; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the switch control circuit 12 is configured to control the second electrode of the light emitting element E1 to be connected to the first terminal of the driving circuit 11 under the control of the potential of the switch control terminal N4; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scanning terminal G1 and a first selection control terminal; The compensation circuit 21 is electrically connected to the scanning terminal G1, the second electrode of the light emitting element E1 and the control node N0 respectively, and is configured to control the second electrode of the light emitting element E1 to be connected to the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0064] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1. As shown in FIG. 8, the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13, a storage circuit 10 and a first reset circuit; The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, the second terminal of the energy storage circuit 10 is electrically connected to the second electrode of the light emitting element E1, and the energy storage circuit 10 is configured to store electric energy; the second electrode of the light emitting element E1 is electrically connected to the second node N2; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1, and the second electrode of the light emitting element E1 is electrically connected to the first terminal of the driving circuit 11; the first terminal of the switch control circuit 12 is electrically connected to the second terminal of the driving circuit 11, and the second terminal of the switch control circuit 12 is electrically connected to the second voltage terminal V2; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the switch control circuit 12 is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scanning terminal G1 and a first selection control terminal X1; The compensation circuit 21 is electrically connected to the scanning terminal G1, the second electrode of the light emitting element E1 and the control node N0 respectively, and is configured to control the connection between the first terminal of the driving circuit 11 and the control node N0 under the control of the scanning signal provided by the scanning terminal G1; The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1.

[0065] In at least one embodiment of the present disclosure, the driving control circuit is also electrically connected to the second control terminal and the second initial voltage terminal, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the switch control terminal under the control of a second control signal provided by the second control terminal, and to maintain the potential of the switch control terminal.

[0066] In a specific implementation, the driving control circuit may also write the second initial voltage into the switch control terminal and maintain the potential of the switch control terminal under the control of the second control signal.

[0067] As shown in FIG. 9, based on the pixel circuit shown in FIG. 1, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0068] As shown in FIG. 10, based on the pixel circuit shown in FIG. 2, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0069] As shown in FIG. 11, based on the pixel circuit shown in FIG. 5, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0070] As shown in FIG. 12, based on the pixel circuit shown in FIG. 6, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0071] As shown in FIG. 13, based on the pixel circuit shown in FIG. 7, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0072] As shown in FIG. 14, based on the pixel circuit shown in FIG. 8, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4. Optionally, the first terminal of the driving circuit is electrically connected to the first voltage terminal; The switch control circuit is electrically connected to the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and the second electrode of the light emitting element is electrically connected to the second voltage terminal; The switch control circuit is configured to control the connection between the second terminal of the driving circuit and the first terminal of the light emitting element under the control of the potential of the switch control terminal.

[0073] In a specific implementation, the switch control circuit can control the connection between the second terminal of the driving circuit and the first terminal of the light emitting element under the control of the potential of the switch control terminal. The pixel circuit described in at least one embodiment of the present disclosure further includes a light emitting control circuit and a compensation control circuit; The switch control circuit is electrically connected to the first electrode of the light emitting element through the light emitting control circuit; The light emitting control circuit is also electrically connected to the light emitting control terminal, and is configured to control the connection between the switch control circuit and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the second terminal of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0074] In a specific implementation, the pixel circuit may further include a light emitting control circuit and a compensation control circuit. The light emitting control circuit controls the switch control circuit to be connected to the first electrode of the light emitting element under the control of a light emitting control signal, to perform light emitting control; and the compensation control circuit controls the control terminal of the driving circuit to be connected to the second terminal of the driving circuit under the control of a scanning signal, to perform threshold voltage compensation.

[0075] Optionally, the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit is greater than 1, the width-to-length ratio of the transistor included in the light emitting control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0076] In a specific implementation, the light emitting element may be an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit may be greater than 1, the width-to-length ratio of the transistor included in the light emitting control circuit may be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5. As shown in FIG. 15, based on at least one embodiment of the driving circuit shown in FIG. 9, the pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting control circuit 31 and a compensation control circuit 32 (T5); The switch control circuit 12 is electrically connected to the first electrode of the light emitting element E1 through the light emitting control circuit 31; The light emitting control circuit E1 is also electrically connected to the light emitting control terminal EM, and is configured to control the connection between the switch control circuit 12 and the first electrode of the light emitting element E1 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0077] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the connection between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1. In at least one embodiment of the present disclosure, the first electrode of the light emitting element is electrically connected to the first voltage terminal, the switch control circuit is electrically connected to the second electrode of the light emitting element and the first terminal of the driving circuit respectively, and the second terminal of the driving circuit is electrically connected to the second voltage terminal;

[0078] The switch control circuit is configured to control the connection between the second electrode of the light emitting element and the first terminal of the driving circuit under the control of the potential of the switch control terminal. The pixel circuit described in at least one embodiment of the present disclosure further includes a light emitting control circuit and a compensation control circuit; The switch control circuit is electrically connected to the first terminal of the driving circuit through the light emitting control circuit; The light emitting control circuit is also electrically connected to the light emitting control terminal, and is configured to control the connection between the switch control circuit and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the first terminal of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0079] In a specific implementation, the pixel circuit may further include a light emitting control circuit and a compensation control circuit. The light emitting control circuit controls the switch control circuit to be connected to the first terminal of the driving circuit under the control of a light emitting control signal, to perform light emitting control; the compensation control circuit controls the control terminal of the driving circuit to be connected to the first terminal of the driving circuit under the control of a scanning signal, to perform threshold voltage compensation. As shown in FIG. 16, based on at least one embodiment of the driving circuit shown in FIG. 10, the pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting control circuit 31 and a compensation control circuit 32 (T5); The switch control circuit 12 is electrically connected to a first terminal of the driving circuit 11 through the light emitting control circuit 31; a second terminal of the driving circuit 11 is electrically connected to a second voltage terminal V2; The light emitting control circuit 31 is also electrically connected to the light emitting control terminal EM, and is configured to control the connection between the switch control circuit 12 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0080] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the connection between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1. The pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit and a first control circuit; The control terminal of the driving circuit is electrically connected to the first node; The display data writing-in circuit is electrically connected to the scanning terminal, the second data line and the second node respectively, and is configured to write the display data voltage provided by the second data line into the second node under the control of the scanning signal provided by the scanning terminal; The first control circuit is electrically connected to the light emitting control terminal, the reference voltage terminal and the second node respectively, and is configured to write the reference voltage provided by the reference voltage terminal into the second node under the control of the light emitting control signal provided by the light emitting control terminal.

[0081] In a specific implementation, the pixel circuit described in at least one embodiment of the present disclosure may also include a display data writing-in circuit and a first control circuit; the display data writing-in circuit writes the display data voltage provided by the second data line into the second node under the control of the scanning signal; the first control circuit writes the reference voltage into the second node under the control of the light emitting control signal. As shown in FIG. 17, based on the pixel circuit shown in FIG. 15, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41 and a first control circuit 42; The control terminal of the driving circuit 11 is electrically connected to the first node N1; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the second node N2 respectively, and is configured to write the display data voltage provided by the second data line DI into the second node N2 under the control of the scanning signal provided by the scanning terminal G1;

[0082] The first control circuit 42 is electrically connected to the light emitting control terminal EM, the reference voltage terminal and the second node N2 respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM. As shown in FIG. 18, based on the pixel circuit shown in FIG. 16, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41 and a first control circuit 42; The control terminal of the driving circuit 11 is electrically connected to the first node N1; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the second node N2 respectively, and is configured to write the display data voltage provided by the second data line DI into the second node N2 under the control of the scanning signal provided by the scanning terminal G1;

[0083] The first control circuit 42 is electrically connected to the light emitting control terminal EM, the reference voltage terminal and the second node N2 respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM. The pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit;

[0084] The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal.

[0085] In a specific implementation, the pixel circuit may further include a second reset circuit; the second reset circuit writes a first initial voltage into the first node under the control of the first reset control signal. As shown in FIG. 19, based on the pixel circuit shown in FIG. 17, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit 51;

[0086] The second reset circuit 51 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal. As shown in FIG. 20, based on the pixel circuit shown in FIG. 19, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit 51;

[0087] The second reset circuit 51 is electrically connected to the first reset control terminal RST, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal. The pixel circuit described in at least one embodiment of the present disclosure further includes an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit, and a display data writing-in circuit; The first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit, the second terminal of the energy storage circuit is electrically connected to the first voltage terminal, and the energy storage circuit is configured to store electrical energy; The first terminal of the driving circuit is electrically connected to the first voltage terminal through the first light emitting control circuit; The second terminal of the driving circuit is electrically connected to the switch control circuit through the second light emitting control circuit; The first light emitting control circuit is also electrically connected to the light emitting control terminal, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is also electrically connected to the light emitting control terminal, and is configured to control the second terminal of the driving circuit to be connected to the switch control circuit under the control of the light emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the second terminal of the driving circuit respectively, and is configured to control the communication between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal; The display data writing-in circuit is electrically connected to the scanning terminal, the second data line and the first terminal of the driving circuit respectively, and is configured to write the display data voltage provided by the second data line into the first terminal of the driving circuit under the control of the scanning signal.

[0088] In a specific implementation, the pixel circuit may further include a storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit and a display data writing-in circuit; the first light emitting control circuit controls the first voltage terminal to be connected to the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be connected to the switch control circuit under the control of the light emitting control signal, to perform light emitting control; the compensation control circuit controls the control terminal of the driving circuit to be connected to the second terminal of the driving circuit under the control of a scanning signal, to perform threshold voltage compensation; the display data writing-in circuit writes the display data voltage provided by the second data line into the first terminal of the driving circuit under the control of the scanning signal, to perform display data voltage writing-in.

[0089] In at least one embodiment of the present disclosure, the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit is greater than 1, the width-to-length ratio of the transistor included in the first light emitting control circuit is greater than 1, the width-to-length ratio of the transistor included in the second light emitting control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0090] In a specific implementation, the light emitting element may be an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit may be greater than 1, the width-to-length ratio of the transistor included in the first light emitting control circuit may be greater than 1, the width-to-length ratio of the transistor included in the second light emitting control circuit may be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5. As shown in FIG. 21, the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13, a first reset circuit 14, a storage circuit 10, a first light emitting control circuit 61, a second light emitting control circuit 62, a compensation control circuit 32, and a display data writing-in circuit 41; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The first reset circuit 14 is electrically connected to the first reset control terminal RST, the first initial voltage terminal I1 and the first electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first electrode of the light emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST; The first terminal of the energy storage circuit 10 is electrically connected to the control terminal of the driving circuit 11, the second terminal of the energy storage circuit 10 is electrically connected to the first voltage terminal V1, and the energy storage circuit 10 is configured to store electric energy; The first terminal of the driving circuit 11 is electrically connected to the first voltage terminal V1 through the first light emitting control circuit 61; The second terminal of the driving circuit 11 is electrically connected to the switch control circuit 12 through the second light emitting control circuit 62; The first light emitting control circuit 61 is also electrically connected to the light emitting control terminal EM, and is configured to control the connection between the first voltage terminal V1 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is also electrically connected to the light emitting control terminal EM, and is configured to control the second terminal of the driving circuit 11 to be connected to the switch control circuit 12 under the control of the light emitting control signal; The switch control circuit 12 is electrically connected to the switch control terminal N4, the second light emitting control circuit 62 and the first electrode of the light emitting element E1 respectively. The switch control circuit 12 is configured to control the second light emitting control circuit 62 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; The driving control circuit 13 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second initial voltage terminal I2 and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB, and write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the control terminal of the driving circuit 11 to communicate with the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0091] The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the first terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the scanning signal. In at least one embodiment of the present disclosure, the pixel circuit further includes an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit, and a display data writing-in circuit; The first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit, the second terminal of the energy storage circuit is electrically connected to the second voltage terminal, and the energy storage circuit is configured to store electrical energy; The first light emitting control circuit is electrically connected to the light emitting control terminal, the switch control circuit and the first terminal of the driving circuit respectively, and is configured to control the connection between the switch control circuit and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the second voltage terminal respectively, and is configured to control the second terminal of the driving circuit to be electrically connected to the second voltage terminal under the control of the light emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the first terminal of the driving circuit respectively, and is configured to control the communication between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal; The display data writing-in circuit is electrically connected to the scanning terminal, the second data line and the second terminal of the driving circuit respectively, and is configured to write the display data voltage provided by the second data line into the second terminal of the driving circuit under the control of the scanning signal.

[0092] In a specific implementation, the pixel circuit may further include an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit and a display data writing-in circuit; the first light emitting control circuit controls the connection between the switch control circuit and the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be electrically connected to the first electrode of the light emitting element under the control of the light emitting control signal; the compensation control circuit controls the connection between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of a scanning signal; the display data writing-in circuit writes the display data voltage provided by the second data line into the second terminal of the driving circuit under the control of the scanning signal. As shown in FIG. 22, the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13, a first reset circuit 14, an energy storage circuit 10, a first light emitting control circuit 61, a second light emitting control circuit 62, a compensation control circuit 32, and a display data writing-in circuit 41; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The switch control circuit 12 is electrically connected to the switch control terminal N4, the first light control circuit 61 and the second electrode of the light emitting element E1 respectively, and the switch control circuit 12 is configured to control the second electrode of the light emitting element E1 to be connected to the first light control circuit 61 under the control of the potential of the switch control terminal N4; The driving control circuit 13 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second initial voltage terminal I2 and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB, and write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the second electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second electrode of the light emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST1, so as to clear the residual charge of the second electrode of the light emitting element E1; The first terminal of the energy storage circuit 10 is electrically connected to the control terminal of the driving circuit 11, the second terminal of the energy storage circuit 10 is electrically connected to the second voltage terminal V2, and the energy storage circuit 10 is configured to store electrical energy; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the switch control circuit 12 and the first terminal of the driving circuit 11 respectively, and is configured to control the connection between the switch control circuit 12 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the second voltage terminal V2 respectively, and is configured to control the second terminal of the driving circuit 11 to be electrically connected to the second voltage terminal V2 under the control of the light emitting control signal; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the connection between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0093] The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the second terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the scanning signal. The pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit; The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0094] In a specific implementation, the pixel circuit may further include a second reset circuit, and the second reset circuit writes the first initial voltage into the first node under the control of a reset control signal. As shown in FIG. 23, based on the pixel circuit shown in FIG. 21, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit 71;

[0095] The second reset circuit 71 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal RST1.

[0096] As shown in FIG. 24, based on the pixel circuit shown in FIG. 22, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit 71; The second reset circuit 71 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal RST1.

[0097] The pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit; The display data writing-in circuit is electrically connected to the scanning terminal, the second data line and the control terminal of the driving circuit respectively, and is configured to write the display data voltage provided by the second data line into the control terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0098] In at least one embodiment of the present disclosure, the switch circuit is also connected to a second selection control terminal and a compensation terminal, and is configured to control the connection between the control node and the compensation terminal under the control of a second selection control signal provided by the second selection control terminal.

[0099] In a specific implementation, the switch circuit can control the connection between the control node and the compensation terminal under the control of the second selection control signal to transmit the potential of the control node to the compensation terminal, so as to perform threshold voltage compensation according to the potential of the compensation terminal. As shown in FIG. 25, based on the pixel circuit shown in FIG. 5, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0100] The switch circuit 22 is also connected to the second selection control terminal X2 and the compensation terminal SENS respectively, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of the second selection control signal provided by the second selection control terminal X2. As shown in FIG. 26, based on the pixel circuit shown in FIG. 6, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0101] The switch circuit 22 is also connected to the second selection control terminal X2 and the compensation terminal SENS, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of a second selection control signal provided by the second selection control terminal X2. As shown in FIG. 27, based on the pixel circuit shown in FIG. 7, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0102] The switch circuit 22 is also connected to the second selection control terminal X2 and the compensation terminal SENS, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of a second selection control signal provided by the second selection control terminal X2. As shown in FIG. 28, based on the pixel circuit shown in FIG. 8, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0103] The switch circuit 22 is also connected to the second selection control terminal X2 and the compensation terminal SENS, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of a second selection control signal provided by the second selection control terminal X2. The pixel circuit described in at least one embodiment of the present disclosure may further include a third reset circuit;

[0104] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal and the first electrode of the light emitting element, respectively, and is configured to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light emitting element under the control of the reset control signal provided by the second reset control terminal during a reset time period set between a time period for writing-in the display data voltage and a time period for writing-in the light emitting time control data voltage. As shown in FIG. 29, based on the pixel circuit shown in FIG. 17, the pixel circuit described in at least one embodiment of the present disclosure may further include a third reset circuit 81;

[0105] The third reset circuit 81 is electrically connected to the second reset control terminal RST2, the third initial voltage terminal I3 and the first electrode of the light emitting element E1, respectively, and is configured to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RST2.

[0106] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase which are set in sequence; the first display phase may include a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase may include a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence. In the first reset time period and the second reset time period, the third reset circuit writes a third initial voltage into the first electrode of the light emitting element under the control of the second reset control signal; In a first writing-in time period, writing-in a display data voltage; In the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage; In the second writing-in time period, writing-in the light emitting time control data voltage;

[0107] In the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to control whether the light emitting element emits light.

[0108] The reset time period provided between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage may be the second reset time period. The pixel circuit described in at least one embodiment of the present disclosure may further include a third reset circuit;

[0109] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal and the first electrode of the light emitting element, respectively, and is configured to write the third initial voltage provided by the third initial voltage terminal into the second electrode of the light emitting element under the control of the second reset control signal provided by the second reset control terminal during a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage.

[0110] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase which are set in sequence; the first display phase may include a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase may include a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence. In the first reset time period and the second reset time period, the third reset circuit writes a third initial voltage into the second electrode of the light emitting element under the control of the second reset control signal; In a first writing-in time period, writing-in a display data voltage; In the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage; In the second writing-in time period, writing-in the light emitting time control data voltage; In the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to control whether the light emitting element emits light.

[0111] The reset time period provided between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage may be the second reset time period. As shown in FIG. 30, based on the pixel circuit shown in FIG. 18, the pixel circuit described in at least one embodiment of the present disclosure may further include a third reset circuit 81;

[0112] The third reset circuit 81 is electrically connected to the second reset control terminal RST2, the third initial voltage terminal I3 and the second electrode of the light emitting element E1, respectively, and is configured to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the second electrode of the light emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RST2. Optionally, the driving control circuit includes a first transistor, a second transistor and a first capacitor; A gate electrode of the first transistor is electrically connected to the first control terminal, a first electrode of the first transistor is electrically connected to the first data line, and a second electrode of the first transistor is electrically connected to the switch control terminal; a gate electrode of the second transistor is electrically connected to the second control terminal, a first electrode of the second transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second transistor is electrically connected to the switch control terminal; a first terminal of the first capacitor is electrically connected to the switch control terminal, and a second terminal of the first capacitor is electrically connected to the DC voltage terminal.

[0113] In at least one embodiment of the present disclosure, the DC voltage terminal may be, for example, a common electrode voltage terminal, a ground terminal, a high voltage terminal or a low voltage terminal, but is not limited thereto.

[0114] Optionally, the driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor; a gate electrode of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the first voltage terminal, and a second electrode of the driving transistor is electrically connected to the third node; a gate electrode of the fourth transistor is electrically connected to the light emitting control terminal, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element; A gate electrode of the fifth transistor is electrically connected to the scanning terminal, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to a third node.

[0115] Optionally, the driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the third transistor is electrically connected to a first electrode of the fourth transistor; a gate electrode of the fourth transistor is electrically connected to the light emitting control terminal, a second electrode of the fourth transistor is electrically connected to a first electrode of the driving transistor; a first electrode of the driving transistor is electrically connected to the third node; a gate electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the second voltage terminal; A gate electrode of the fifth transistor is electrically connected to the scanning terminal, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the third node.

[0116] Optionally, the display data writing-in circuit includes a sixth transistor, and the first control circuit includes a seventh transistor; a gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the second node; A gate electrode of the seventh transistor is electrically connected to the light emitting control terminal, a first electrode of the seventh transistor is electrically connected to the reference voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second node.

[0117] Optionally, the first reset circuit includes an eighth transistor; a gate electrode of the eighth transistor is electrically connected to the set control terminal, a first electrode of the eighth transistor is electrically connected to the set voltage terminal, and a second electrode of the eighth transistor is electrically connected to the second node, a first electrode of the light emitting element, or a second electrode of the light emitting element; The set voltage terminal is configured to provide the set voltage.

[0118] Optionally, the second reset circuit includes a ninth transistor, A gate electrode of the ninth transistor is electrically connected to the first reset control terminal, a first electrode of the ninth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the first node.

[0119] Optionally, the driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor, the first light emitting control circuit includes an eleventh transistor, the second light emitting control circuit includes a twelfth transistor, the switch control circuit includes a third transistor, the compensation control circuit includes a fifth transistor, and the display data writing-in circuit includes a sixth transistor; a first terminal of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal; a gate electrode of the eleventh transistor is electrically connected to the light emitting control terminal, a first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the twelfth transistor is electrically connected to the light emitting control terminal, a first electrode of the twelfth transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the twelfth transistor is electrically connected to the first electrode of the third transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element; a gate electrode of the fifth transistor is electrically connected to the scanning terminal, a first electrode of the fifth transistor is electrically connected to the gate electrode of the driving transistor, and a second electrode of the fifth transistor is electrically connected to the second electrode of the driving transistor; A gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to a first electrode of the driving transistor.

[0120] Optionally, the driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor, the first light emitting control circuit includes an eleventh transistor, the second light emitting control circuit includes a twelfth transistor, the switch control circuit includes a third transistor, the compensation control circuit includes a fifth transistor, and the display data writing-in circuit includes a sixth transistor; a first terminal of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the second voltage terminal; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the third transistor is electrically connected to a first electrode of the eleventh transistor; a gate electrode of the eleventh transistor is electrically connected to the light emitting control terminal, and a second electrode of the eleventh transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the twelfth transistor is electrically connected to the light emitting control terminal, a first electrode of the twelfth transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the twelfth transistor is electrically connected to the second voltage terminal; a gate electrode of the fifth transistor is electrically connected to the scanning terminal, a first electrode of the fifth transistor is electrically connected to the gate electrode of the driving transistor, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; A gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to a second electrode of the driving transistor.

[0121] Optionally, the second reset circuit includes a ninth transistor; A gate electrode of the ninth transistor is electrically connected to the first reset control terminal, a first electrode of the ninth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the first node.

[0122] Optionally, the third reset circuit includes a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the second reset control terminal, a first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

[0123] Optionally, the third reset circuit includes a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the second reset control terminal, a first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the tenth transistor is electrically connected to the second electrode of the light emitting element.

[0124] Optionally, the switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the first electrode of the driving transistor;

[0125] The second electrode of the driving transistor is electrically connected to the first electrode of the light emitting element.

[0126] Optionally, the switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0127] The first electrode of the driving transistor is electrically connected to the first voltage terminal. Optionally, the switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the light emitting element, a second electrode of the third transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the driving transistor is electrically connected to the second voltage terminal.

[0128] Optionally, the switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; the second electrode of the light emitting element is electrically connected to the first electrode of the driving transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element.

[0129] Optionally, the display data writing-in circuit includes a sixth transistor; A gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the control terminal of the driving circuit.

[0130] Optionally, the energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch; a first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the second terminal of the driving circuit; a gate electrode of the thirteenth transistor is electrically connected to the scanning terminal, a first electrode of the thirteenth transistor is electrically connected to the first electrode of the light emitting element or the second terminal of the driving circuit, and a second electrode of the thirteenth transistor is electrically connected to the control node; a control terminal of the first switch is electrically connected to the first selection control terminal, a first terminal of the first switch is electrically connected to the control node, and a second terminal of the first switch is electrically connected to the reference voltage terminal.

[0131] Optionally, the energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch; a first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the first terminal of the driving circuit; a gate electrode of the thirteenth transistor is electrically connected to the scanning terminal, a first electrode of the thirteenth transistor is electrically connected to the second electrode of the light emitting element or the first terminal of the driving circuit, and a second electrode of the thirteenth transistor is electrically connected to the control node; a control terminal of the first switch is electrically connected to the first selection control terminal, a first terminal of the first switch is electrically connected to the control node, and a second terminal of the first switch is electrically connected to the reference voltage terminal.

[0132] Optionally, the switch circuit further includes a second switch; a control terminal of the second switch is electrically connected to the second selection control terminal, a first terminal of the second switch is electrically connected to the control node, and a second terminal of the second switch is electrically connected to the compensation terminal.

[0133] As shown in FIG. 31, based on the pixel circuit shown in FIG. 17, the light emitting element is a light emitting diode E0; the cathode of the light emitting diode E0 is electrically connected to the low voltage terminal VSS; The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1; The gate electrode of the first transistor T1 is electrically connected to the first control terminal GB, the source electrode of the first transistor T1 is electrically connected to the first data line DT, and the drain electrode of the first transistor T1 is electrically connected to the switch control terminal N4; The gate electrode of the second transistor T2 is electrically connected to the second control terminal GA, the source electrode of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain electrode of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is configured to provide a second initial voltage Vi2; A first terminal of the first capacitor C1 is electrically connected to the switch control terminal N4, and a second terminal of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM; The driving circuit includes a driving transistor T0, the switch control circuit includes a third transistor T3, the light emitting control circuit includes a fourth transistor T4, and the compensation control circuit includes a fifth transistor T5; The gate electrode of the driving transistor T0 is electrically connected to the first node N1, the source electrode of the driving transistor T0 is electrically connected to the high voltage terminal VDD, and the drain electrode of the driving transistor T0 is electrically connected to the third node N3; The gate electrode of the fourth transistor T4 is electrically connected to the light emitting control terminal EM, the source electrode of the fourth transistor T4 is electrically connected to the third node N3, and the drain electrode of the fourth transistor T4 is electrically connected to the source electrode of the third transistor T3; The gate electrode of the third transistor T3 is electrically connected to the switch control terminal N4, and the drain electrode of the third transistor T3 is electrically connected to the anode of the light emitting diode E0; The gate electrode of the fifth transistor T5 is electrically connected to the scanning terminal G1, the source electrode of the fifth transistor T5 is electrically connected to the first node N1, and the drain electrode of the fifth transistor T5 is electrically connected to the third node N3; The display data writing-in circuit includes a sixth transistor T6, and the first control circuit includes a seventh transistor T7; The gate electrode of the sixth transistor T6 is electrically connected to the scanning terminal G1, the source electrode of the sixth transistor T6 is electrically connected to the second data line DI, and the drain electrode of the sixth transistor T6 is electrically connected to the second node N2; The gate electrode of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, the source electrode of the seventh transistor T7 is electrically connected to the reference voltage terminal, and the drain electrode of the seventh transistor T7 is electrically connected to the second node N2; the reference voltage terminal is configured to provide a reference voltage Vref; The first reset circuit comprises an eighth transistor T8; The gate electrode of the eighth transistor T8 is electrically connected to the first reset control terminal RST1, the source electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal, and the drain electrode of the eighth transistor T8 is electrically connected to the second node N2;

[0134] The second reset circuit comprises a ninth transistor T9, The gate electrode of the ninth transistor T9 is electrically connected to the first reset control terminal RST1, the source electrode of the ninth transistor T9 is electrically connected to the first initial voltage terminal I1, and the drain electrode of the ninth transistor T9 is electrically connected to the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vi1; The energy storage circuit includes a storage capacitor Cst; A first terminal of the storage capacitor Cst is electrically connected to the first node N1, and a second terminal of the storage capacitor Cst is electrically connected to the second node N2.

[0135] In the pixel circuit shown in FIG. 31, all transistors are p-type transistors, but the present invention is not limited thereto.

[0136] In the pixel circuit shown in FIG. 31, E0 may be OLED (organic light emitting diode), Mini LED (mini light emitting diode) or Micro LED (micro light emitting diode), but is not limited thereto.

[0137] When the pixel circuit shown in FIG. 31 of the present disclosure is working, the pixel circuit delays writing-in the light emitting time control data voltage provided by the first data line DT into the pixel circuit to realize PAM (pulse amplitude modulation) + PWM (pulse width modulation) pixel driving.

[0138] In the pixel circuit shown in FIG. 31 of the present disclosure, Vi1 is less than Vdd+Vth, and when the second initial voltage Vi2 is written into N4, T3 can be turned on; wherein Vdd is the voltage value of the high voltage signal provided by VDD, and Vth is the threshold voltage of T0.

[0139] The value of Vdata_I and the value of Vref need to satisfy the driving current of E0 while Vref is less than or equal to Vdata_I to achieve grayscale display; In high grayscale display, in a preferred case, Vdata_T is equal to Vdata_I; In low grayscale display, when Vdata_T is written into N4, T3 can be turned off.

[0140] As shown in FIG. 32, when the pixel circuit shown in FIG. 31 of the present disclosure is in operation, a display cycle (the display cycle may be a frame display time) includes a first display phase S1 and a second display phase S2 which are successively arranged; The first display phase S1 includes a first reset time period S11, a first writing-in time period S12 and a first light emitting time period S13 which are set successively; the second display phase S2 includes a second writing-in time period S22 and a second light emitting time period S23 which are set successively; In the first reset time period S11, RST provides a low voltage signal, as shown in FIG. 33A, T8 and T9 are turned on to write the reference voltage Vref into the second node N2, and write the first initial voltage Vi1 provided by I1 into the first node N1; In the first writing-in time period S12, G1 provides a low voltage signal, as shown in FIG. 33B, T6 is turned on, DI provides a display data voltage Vdata_I to the second node N2, and T5 is turned on; At the beginning of the first writing-in time period S12, T0 is turned on to charge Cst through Vdata_I until the first node N1 becomes Vdd+Vth, and T0 is turned off to perform threshold voltage compensation; Vth is the threshold voltage of T0, and Vdd is the voltage value of the high voltage signal provided by VDD; In the first writing-in time period S12, the voltage signal provided by GA, T2 is turned on to write the second initial voltage Vi2 into the fourth node N4, T3 is turned on; In the first light emitting time period S13, EM provides a low voltage signal, as shown in FIG. 33C, T7 and T4 are turned on, T3 is turned on, and T0 drivings E0 to emit light; In the first light emitting time period S13, the potential of N2 is Vref. Due to the capacitive coupling effect, the potential of N1 is Vdd+Vth+Vref-Vdata_I. The gate-source voltage Vgs of T0 is equal to Vth+Vref-Vdata_I. Id is equal to K×(Vref-Vdata_I) 2< ; K is the current coefficient of T0; Id is the driving current of T0 driving E0 to emit light.

[0141] In the second writing-in time period S22, the first time t1 is delayed (the first time t1 is the light emitting time required for the low grayscale), GB outputs a low voltage signal, as shown in FIG. 33D, T1 is turned on, and DT provides the light emitting time control data voltage Vdata_T to N4; t1 is the duration of the first light emitting time period S13;

[0142] FIG. 33E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in the second light emitting time period S23. When Vdata_T is a high voltage signal, in the second light emitting time period S23, T3 is turned off, E0 does not emit light, and a short-time light emitting is achieved, and the light emitting duration is t1; When Vdata_T is a low voltage signal, the optimal voltage value of Vdata_T is the same as the voltage value of Vi2, T3 is turned on, T0 drivings E0 to emit light, E0 continues to emit light, and long-term light emitting is achieved. The light emitting duration is t1+t2, t2 is the second time, and t2 is the duration of the second writing-in time period S22.

[0143] When the pixel circuit shown in FIG. 31 is working, the second control signal provided by GA can be the same as the scanning signal provided by G1, or the second control signal provided by GA can be the same as the reset control signal provided by RST, that is, the second initial voltage Vi2 can be written into N4 in the first reset time period S11 or the first writing-in time period S12, and GA can share the GOA (Gate On Array, a gate driving circuit arranged on the array substrate) circuit with G1 or RST; in addition, since Vi2 is a DC voltage signal, GA can also not use a shift register, and can be turned on for one frame of time to reset the potential of N4 of all pixel circuits at once.

[0144] FIG. 34A is a schematic diagram of simulation results of high grayscale display of the pixel circuit shown in FIG. 31; FIG. 34B is a schematic diagram of simulation results of low grayscale display of the pixel circuit shown in FIG. 31.

[0145] In at least one embodiment of the present disclosure, Id is the driving current generated at T0.

[0146] As shown in FIG. 34A, when displaying at a high gray scale, Vdd is equal to 4.6V, Vss is equal to -3V, Vi1 is equal to -3V, Vi2 is equal to -5V, Vdata_I is equal to 4V, Vref is equal to 2V, and Vdata_T is equal to -5V; wherein Vss is the voltage value of the low voltage signal provided by VSS;

[0147] As shown in FIG. 34B, in low grayscale display, Vdd is equal to 4.6V, Vss is equal to -3V, Vi1 is equal to -3V, Vi2 is equal to -5V, Vdata_I is equal to 4V, Vref is equal to 2V, and Vdata_T is equal to 5V. As shown in FIG. 35, when the pixel circuit shown in FIG. 31 is working, a display cycle (the display cycle may be one frame of time) may include a first display phase and n second display phases that are arranged in sequence; in a writing-in time period in the first display phase, DI writes a display data voltage, and in a second display phase, DT writes a light emitting time control data voltage; In FIG. 35, the first display phase is labeled S1, the first second display phase is labeled S01, the (n-1)th first display phase is labeled S0n-1, and the nth first display phase is labeled S0n; n is an integer greater than 2; The first display phase S1 includes a first reset time period S11, a first writing-in time period S12 and a first light emitting time period S13 which are arranged successively; The first second display phase S01 includes a first second writing-in time period S012 and a first second light emitting time period S013 which are successively arranged; The (n-1)th second display phase S0n-1 includes the (n-1)th second writing-in time period S0n-12 and the (n-1)th second light emitting time period S0n-13 which are arranged successively; The nth second display phase S0n includes an nth second writing-in time period S0n2 and an nth second light emitting time period S0n3 which are arranged successively; In the first reset time period S11, RST provides a low voltage signal, T8 and T9 are turned on to write the reference voltage Vref into the second node N2, and write the first initial voltage Vi1 provided by I1 into the first node N1; In the first writing-in time period S12, G1 provides a low voltage signal, T6 is turned on, DI provides a display data voltage Vdata_I to the second node N2, and T5 is turned on to charge Cst until the first node N1 becomes Vdd+Vth; Vth is the threshold voltage of T0, and Vdd is the voltage value of the high voltage signal provided by VDD; In the first writing-in time period S12, the voltage signal provided by GA, T2 is turned on to write the second initial voltage Vi2 into the fourth node N4, T3 is turned on; In the first light emitting time period S13, EM provides a low voltage signal, T7 and T4 are turned on, T3 is turned on, and T0 drivings E0 to emit light; In the first light emitting time period S13, the potential of N2 is Vref. Due to the capacitive coupling effect, the potential of N1 is Vdd+Vth+Vref-Vdata_I. The gate-source voltage Vgs of T0 is equal to Vth+Vref-Vdata_I. Id is equal to K×(Vref-Vdata_I) 2< ; K is the current coefficient of T0; Id is the driving current of T0 driving E0 to emit light.

[0148] In S012, EM provides a high voltage signal, RST provides a high voltage signal, G1 provides a high voltage signal, GA provides a high voltage signal, GB provides a low voltage signal, T1 is turned on, and DT provides a first light emitting time control data voltage to N4; When DT provides a low voltage signal at S012, T3 is turned on, T4 is turned on, and T0 drivings E0 to emit light at S013; When DT provides a high voltage signal at S012, T3 is turned off at S013, and E0 does not emit light; At S0n-12, EM provides a high voltage signal, RST provides a high voltage signal, G1 provides a high voltage signal, GA provides a high voltage signal, GB provides a low voltage signal, T1 is turned on, and DT provides the (n-1)th light emitting time control data voltage to N4; When DT provides a low voltage signal at S0n-12, T3 is turned on at S0n-13, T4 is turned on, and T0 drivings E0 to emit light; When DT provides a high voltage signal at S0n-12, T3 is turned off at S0n-13, and E0 does not emit light; At S0n2, EM provides a high voltage signal, RST provides a high voltage signal, G1 provides a high voltage signal, GA provides a high voltage signal, GB provides a low voltage signal, T1 is turned on, and DT provides the nth light emitting time control data voltage to N4; When DT provides a low voltage signal at S0n2, T3 is turned on at S0n3, T4 is turned on, and T0 drivings E0 to emit light; When DT provides a high voltage signal at S0n2, T3 is turned off at S0n3, and E0 does not emit light; According to the light emitting time control data voltage provided by DT in each second writing-in time period, it can be determined whether E0 emits light in each second light emitting time period.

[0149] As shown in FIG. 35, when the pixel circuit shown in FIG. 31 is working, the light emitting time control data voltage is written multiple times within one frame of time, and the light emitting time control data voltage is written at a high frequency, so that the low grayscale short-time light emitting is divided into multiple segments of short-time light emitting, so as to realize low grayscale short-time high-frequency light emitting, reduce the continuous non-light emitting time within one frame of time, and further reduce the low grayscale flicker, realize healthy display, and improve display performance.

[0150] In specific implementation, the high-frequency writing-in of the light emitting time control data voltage can be input by multiple groups of first data lines, or a frame is divided into multiple sub-frames and a single first data line is input multiple times, or the second initial voltage and the light emitting time control data voltage can be written alternately at high frequency. FIG. 36 is a schematic diagram of the light emitting time of the pixel circuit shown in FIG. 31 when emitting light at a high grayscale and a low grayscale; As shown in FIG. 36, n is equal to 5; When high grayscale display is performed, the light emitting duration may be t1+t2+t3+t4+t5+t6; When performing low grayscale display, the light emitting duration may be t1+t3+t5; t1 is the first time, t2 is the second time, t3 is the third time, t4 is the fourth time, t5 is the fifth time, and t6 is the sixth time; t1 is the duration of the first light emitting time period, t2 is the duration of the first second light emitting time period, t3 is the duration of the second second light emitting time period, t4 is the duration of the third second light emitting time period, t5 is the duration of the fourth second light emitting time period, and t6 is the duration of the fifth second light emitting time period.

[0151] The difference between the pixel circuit shown in FIG. 37 and the pixel circuit shown in FIG. 31 is that T1, T2, T5, T6, T8, and T9 are all NMOS transistors.

[0152] The pixel circuit shown in FIG. 37 utilizes the low leakage current advantage of oxide thin film transistors to change T8, T6, T9, T5, T1, T2 or part of them into NMOS (N-type metal-oxide-semiconductor) transistors to reduce the leakage of N1, N2, and N4; utilizing the high mobility of PMOS transistors, T0, T3, T4, and T7 are set to PMOS transistors to meet threshold voltage compensation, current driving requirements, and reduce charging time, thereby further improving display performance.

[0153] FIG. 38 is a timing diagram of the pixel circuit shown in FIG. 37.

[0154] The difference between the pixel circuit shown in FIG. 39 and the pixel circuit shown in FIG. 37 is that all transistors are NMOS transistors.

[0155] The pixel circuit shown in FIG. 39 adopts NMOS TFT technology to realize a pixel circuit of current control + light emitting duration control, and can be applied to oxide display products.

[0156] In the pixel circuit shown in FIG. 39, E0 may be a Mini LED or a Micro LED, but is not limited thereto. In the pixel circuit shown in FIG. 39, Vi1 is greater than Vss+Vth, where Vss is the voltage value of the low voltage signal provided by VSS, and Vth is the threshold voltage of T0; When Vi2 is written to N4, T3 can be turned on; The values of Vdata_I and Vref need to satisfy the driving current of E0 while Vref needs to be greater than or equal to V data _I to achieve grayscale display; In high grayscale display, in the preferred case, Vdata_T is equal to Vi2; In low grayscale display, when Vdata_T is input to N4, T3 needs to be turned off.

[0157] FIG. 40 is a timing diagram of the pixel circuit shown in FIG. 39. In FIG. 40, the first display phase is labeled S1, and the second display phase is labeled S2; The time period labeled S11 is the first reset time period, the time period labeled S12 is the first writing-in time period, and the time period labeled S13 is the first light emitting time period; The time period labeled S22 is the second writing-in time period, and the time period labeled S23 is the second light emitting time period.

[0158] FIG. 41A is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the first reset time period S11; FIG. 41B is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the first writing-in time period S12; FIG. 41C is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the first light emitting time period S13; FIG. 41D is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the second writing-in time period S22; FIG. 41E is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the second light emitting time period S23.

[0159] FIG. 42A is a schematic diagram of simulation results of high grayscale display of the pixel circuit shown in FIG. 39; FIG. 42B is a schematic diagram of simulation results of low grayscale display of the pixel circuit shown in FIG. 39. As shown in FIG. 42A, when displaying at a high gray scale, Vdd is equal to 7V, Vss is equal to 0V, Vi1 is equal to 8V, Vi2 is equal to 5V, Vdata_I is equal to 2V, Vref is equal to 6V, and Vdata_T is equal to 5V; wherein Vdd is the voltage value of the high voltage signal provided by VDD;

[0160] As shown in FIG. 42B, in low grayscale display, Vdd is equal to 7V, Vss is equal to 0V, Vi1 is equal to 8V, Vi2 is equal to 5V, Vdata_I is equal to 2V, Vref is equal to 6V, and Vdata_T is equal to -5V. The difference between the pixel circuit shown in FIG. 43A and the pixel circuit shown in FIG. 31 is that: a third reset circuit is further included; The third reset circuit includes a tenth transistor T10; the gate electrode of the tenth transistor T10 is electrically connected to the second reset control terminal RST2, the source electrode of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain electrode of the tenth transistor T10 is electrically connected to the anode of the light emitting diode E0; the third initial voltage terminal I3 is configured to provide a third initial voltage Vi3.

[0161] The pixel circuit shown in FIG. 43A of the present disclosure adds a tenth transistor T10 for resetting the potential of the anode of the light emitting diode E0, thereby improving the display contrast.

[0162] In the pixel circuit shown in FIG. 43A of the present disclosure, Vi3-Vss is smaller than Vled, ensuring that when Vi3 is written to the anode of E0, E0 does not emit light; wherein Vss is the voltage value of the low voltage signal provided by VSS, and Vled is the light emitting voltage of E0.

[0163] FIG. 43B is a first timing diagram of the pixel circuit shown in FIG. 43A of the present disclosure.

[0164] FIG. 43C is a second timing diagram of the pixel circuit shown in FIG. 43A of the present disclosure. In FIG. 43C, the first display phase is labeled S1, and the second display phase is labeled S2; The time period labeled S11 is the first reset time period, the time period labeled S12 is the first writing-in time period, and the time period labeled S13 is the first light emitting time period; The time period labeled S21 is the second reset time period, the time period labeled S22 is the second writing-in time period, and the time period labeled S23 is the second light emitting time period.

[0165] As shown in FIG. 43C, when the pixel circuit shown in FIG. 43A of the present disclosure is in operation, in the first reset time period S11 and the second reset time period S21, RST2 provides a low voltage signal and T11 is turned on to write the second initial voltage Vi2 provided by I2 into the anode of E0, so as to be able to clear the residual charge at the anode of E0 at high frequency and improve display flicker.

[0166] Based on the pixel circuit shown in FIG. 37 and the pixel circuit shown in FIG. 39, a third reset circuit can be added, and the third reset circuit can include a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the second reset control terminal, a source electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and a drain electrode of the tenth transistor is electrically connected to the cathode of the light emitting diode. As shown in FIG. 44, based on the pixel circuit shown in FIG. 23, the light emitting element is a light emitting diode E0; The driving circuit includes a driving transistor T0; the energy storage circuit includes a storage capacitor Cst, the first light emitting control circuit includes an eleventh transistor T11, the second light emitting control circuit includes a twelfth transistor T12, the switch control circuit includes a third transistor T3, the compensation control circuit includes a fifth transistor T5, and the display data writing-in circuit includes a sixth transistor T6; The first terminal of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T0, and the second terminal of the storage capacitor Cst is electrically connected to the high voltage terminal VDD; the gate electrode of the driving transistor T0 is electrically connected to the first node N1; The gate electrode of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, the source electrode of the eleventh transistor T11 is electrically connected to the high voltage terminal VDD, and the drain electrode of the eleventh transistor T11 is electrically connected to the source electrode of the driving transistor T0; The gate electrode of the twelfth transistor T12 is electrically connected to the light emitting control terminal EM, the source electrode of the twelfth transistor T12 is electrically connected to the drain electrode of the driving transistor T0, and the drain electrode of the twelfth transistor T12 is electrically connected to the source electrode of the third transistor T3; The gate electrode of the third transistor T3 is electrically connected to the switch control terminal N4, and the drain electrode of the third transistor T4 is electrically connected to the anode of the light emitting diode E0; The gate electrode of the fifth transistor T5 is electrically connected to the scanning terminal G1, the source electrode of the fifth transistor T5 is electrically connected to the gate electrode of the driving transistor T0, and the drain electrode of the fifth transistor T5 is electrically connected to the drain electrode of the driving transistor T0; The gate electrode of the sixth transistor T6 is electrically connected to the scanning terminal G1, the source electrode of the sixth transistor T6 is electrically connected to the second data line DI, and the drain electrode of the sixth transistor T6 is electrically connected to the source electrode of the driving transistor T0; The first reset circuit comprises an eighth transistor T8; The gate electrode of the eighth transistor T8 is electrically connected to the second reset control terminal RST2, the source electrode of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain electrode of the eighth transistor T8 is electrically connected to the anode of the light emitting diode E0; the third initial voltage terminal I3 is configured to provide a third initial voltage Vi3; The second reset circuit includes a ninth transistor T9; The gate electrode of the ninth transistor T9 is electrically connected to the first reset control terminal RST1, the source electrode of the ninth transistor T9 is electrically connected to the first initial voltage terminal I1, and the drain electrode of the ninth transistor T9 is electrically connected to the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vi1; The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1; The gate electrode of the first transistor T1 is electrically connected to the first control terminal GB, the source electrode of the first transistor T1 is electrically connected to the first data line DT, and the drain electrode of the first transistor T1 is electrically connected to the switch control terminal N4; The gate electrode of the second transistor T2 is electrically connected to the second control terminal GA, the source electrode of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain electrode of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is configured to provide a second initial voltage Vi2; A first terminal of the first capacitor C1 is electrically connected to the switch control terminal N4, and a second terminal of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM.

[0167] In the pixel circuit shown in FIG. 44, all transistors are p-type transistors, but the present invention is not limited thereto.

[0168] In the pixel circuit shown in FIG. 44, the contrast is increased and the display performance is enhanced by resetting the eighth transistor configured to reset the potential of the anode of the light emitting diode E0.

[0169] When the pixel circuit shown in FIG. 44 is working, the second control signal provided by GA can be the same as the scanning signal provided by G1, or the second control signal provided by GA can be the same as the second reset control signal provided by RST2, that is, the second initial voltage Vi2 can be written into N4 in the first reset time period S11 or the first writing-in time period S12, and GA can share the GOA (Gate On Array, a gate driving circuit arranged on the array substrate) circuit with G1 or RST; the number of control signals can be reduced, and the proportion of control signal writing-in time can be reduced. As shown in FIG. 45A, the pixel circuit shown in FIG. 44 is at work, the display cycle (the display cycle may be a frame of time) may include a first display phase S1 and a second display phase S2 which are successively set; The first display phase S1 may include a first reset time period S11, a first writing-in time period S12 and a first light emitting time period S13 which are set successively; the second display phase S2 may include a second writing-in time period S22 and a second light emitting time period S23 which are set successively; In the first reset time period S11, RST1 provides a low voltage signal, RST2 provides a low voltage signal, T9 and T8 are turned on, and the anode of the first node N1 and E0 are reset; In the first writing-in time period S12, G1 provides a low voltage signal, T6 is turned on, DI writes the display data voltage to the first node N1, and T5 is turned on; At the beginning of the first writing-in time period S12, T0 is turned on, and Cst is charged by display data voltage until T0 is turned off, and until the gate voltage of T0 becomes Vdd+Vth, threshold voltage compensation is performed; wherein Vdd is the voltage value of the high voltage signal provided by VDD, and Vth is the threshold voltage of T0; In the first writing-in time period S12, GA provides a low voltage signal, T2 is turned on, the second initial voltage Vi2 provided by I2 is written into N4, and T3 is turned on; In the first light emitting time period S13, EM provides a low voltage signal, T11 and T12 are turned on, and T0 drivings E0 to emit light; In the second writing-in time period S22, the first time t1 is delayed, GB provides a low voltage signal, T1 is turned on, and DT provides a light emitting time control data voltage Vdata_T to N4; t1 is the duration of the first light emitting time period S13; When Vdata_T is a high voltage signal, in the second light emitting time period S23, T3 is turned off, E0 does not emit light, and a short-time light emitting is achieved, and the light emitting duration is t1; When Vdata_T is a low voltage signal, the optimal voltage value of Vdata_T is the same as the voltage value of Vi2. In the second light emitting time period S23, T3 is turned on, T0 drivings E0 to emit light, and E0 continues to emit light to achieve long-term light emitting. The light emitting time is t1+t2, t2 is the second time, and t2 is the duration of the second light emitting time period S23.

[0170] FIG. 45B is a second timing diagram of the pixel circuit shown in FIG. 44. In FIG. 45B, the time period labeled S21 is the second reset time period;

[0171] In the first reset time period S11 and the second reset time period S21, RST2 provides a low voltage signal and T8 is turned on to write the third initial voltage Vi3 provided by I3 into the anode of E0, so as to clear the residual charge of the anode of E0 at high frequency and improve display flicker. As shown in FIG. 46, based on the pixel circuit shown in FIG. 24, the light emitting element is a light emitting diode E0; The driving circuit includes a driving transistor T0; the energy storage circuit includes a storage capacitor Cst, the first light emitting control circuit includes an eleventh transistor T11, the second light emitting control circuit includes a twelfth transistor T12, the switch control circuit includes a third transistor T3, the compensation control circuit includes a fifth transistor T5, and the display data writing-in circuit includes a sixth transistor T6; The anode of the light emitting diode E0 is electrically connected to the high voltage terminal VDD; The first terminal of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T0, and the second terminal of the storage capacitor Cst is electrically connected to the low voltage terminal VSS; the gate electrode of the driving transistor T0 is electrically connected to the first node N1; The gate electrode of the third transistor T3 is electrically connected to the switch control terminal N4, the drain electrode of the third transistor T3 is electrically connected to the cathode of the light emitting diode E1, and the source electrode of the third transistor T3 is electrically connected to the drain electrode of the eleventh transistor T11; The gate electrode of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, and the source electrode of the eleventh transistor T11 is electrically connected to the drain electrode of the driving transistor T0; The gate electrode of the twelfth transistor T12 is electrically connected to the light emitting control terminal EM, the drain electrode of the twelfth transistor T12 is electrically connected to the source electrode of the driving transistor T0, and the source electrode of the twelfth transistor T12 is electrically connected to the low voltage terminal VSS; The gate electrode of the fifth transistor T5 is electrically connected to the scanning terminal G1, the drain electrode of the fifth transistor T5 is electrically connected to the gate electrode of the driving transistor T0, and the drain electrode of the fifth transistor T5 is electrically connected to the drain electrode of the driving transistor T0; The gate electrode of the sixth transistor T6 is electrically connected to the scanning terminal G1, the drain electrode of the sixth transistor T6 is electrically connected to the second data line DI, and the source electrode of the sixth transistor T6 is electrically connected to the source electrode of the driving transistor T0; The first reset circuit comprises an eighth transistor T8; The gate electrode of the eighth transistor T8 is electrically connected to the second reset control terminal RST2, the source electrode of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain electrode of the eighth transistor T8 is electrically connected to the cathode of the light emitting diode E0; The second reset circuit includes a ninth transistor T9; The gate electrode of the ninth transistor T9 is electrically connected to the first reset control terminal RST1, the source electrode of the ninth transistor T9 is electrically connected to the first initial voltage terminal I1, and the drain electrode of the ninth transistor T9 is electrically connected to the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vi1; The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1; The gate electrode of the first transistor T1 is electrically connected to the first control terminal GB, the source electrode of the first transistor T1 is electrically connected to the first data line DT, and the drain electrode of the first transistor T1 is electrically connected to the switch control terminal N4; The gate electrode of the second transistor T2 is electrically connected to the second control terminal GA, the source electrode of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain electrode of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is configured to provide a second initial voltage Vi2; A first terminal of the first capacitor C1 is electrically connected to the switch control terminal N4, and a second terminal of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM.

[0172] In the pixel circuit shown in FIG. 46, all transistors are NMOS transistors, but the present invention is not limited thereto.

[0173] FIG. 47A is a first timing diagram of the pixel circuit shown in FIG. 46. In FIG. 47A, the first display phase is labeled S1 and the second display phase is labeled S2; The time period labeled S11 is the first reset time period, the time period labeled S12 is the first writing-in time period, and the time period labeled S13 is the first light emitting time period; The time period labeled S22 is the second writing-in time period, and the time period labeled S23 is the second light emitting time period.

[0174] FIG. 48A is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the first reset time period S11; FIG. 48B is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the first writing-in time period S12; FIG. 48C is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the first light emitting time period S13; FIG. 48D is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the second writing-in time period S22; FIG. 48E is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the second light emitting time period S23.

[0175] FIG. 47B is a first timing diagram of the pixel circuit shown in FIG. 46. In FIG. 47B, the time period labeled S21 is the second reset time period;

[0176] In the first reset time period S11 and the second reset time period S21, RST2 provides a low voltage signal and T8 is turned on to write the third initial voltage Vi3 provided by I3 into the cathode of E0, so as to clear the residual charge of the cathode of E0 at high frequency and improve the display flicker.

[0177] In at least one embodiment of the present disclosure, when the potential of the cathode of E0 is initialized, E0 does not emit light.

[0178] The difference between the pixel circuit shown in FIG. 49 and the pixel circuit shown in FIG. 44 is that T9, T8, T5, T6, T1 and T2 are NMOS TFTs, T9, T8, T5, T6, T1 and T2 are oxide TFTs, and T0, T11, T12 and T3 are PMOS TFTs.

[0179] The pixel circuit shown in FIG. 49 adopts LTPO technology, takes advantage of the low leakage current of oxide TFT, reduces the leakage of the anode of the first node N1 and E0, and sets T9, T8, T5, T6, T1 and T2 as NMOS TFT; takes advantage of the high mobility of PMOS TFT, sets T0, T11, T12 and T3 as PMOS TFT, meets the threshold voltage compensation, current driving requirements and reduces the charging time, and further improves the display performance. FIG. 50A is a first timing diagram of the pixel circuit shown in FIG. 49. In FIG. 50, the first display phase is labeled S1, and the second display phase is labeled S2; The time period labeled S11 is the first reset time period, the time period labeled S12 is the first writing-in time period, and the time period labeled S13 is the first light emitting time period;

[0180] The time period labeled S22 is the second writing-in time period, and the time period labeled S23 is the second light emitting time period. FIG. 50B is a second timing diagram of the pixel circuit shown in FIG. 49; in FIG. 50B, the time period labeled S21 is a second reset time period;

[0181] In the first reset time period S11 and the second reset time period S21, RST2 provides a low voltage signal and T8 is turned on to write the third initial voltage Vi3 provided by I3 into the anode of E0, so as to clear the residual charge of the anode of E0 at high frequency and improve display flicker. As shown in FIG. 51, based on the pixel circuit shown in FIG. 24, the light emitting element is a light emitting diode E0; The energy storage circuit includes a storage capacitor Cst, the compensation circuit includes a thirteenth transistor T13, the switch circuit includes a first switch K1; the driving circuit includes a driving transistor T0; The first terminal of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T0, and the second terminal of the storage capacitor Cst is electrically connected to the drain electrode of the driving transistor T0; the gate electrode of the driving transistor T0 is electrically connected to the first node N1; the drain electrode of the driving transistor T0 is electrically connected to the anode of E0; the anode of E0 is electrically connected to the second node N2; The gate electrode of the thirteenth transistor T13 is electrically connected to the scanning terminal G1, the source electrode of the thirteenth transistor T13 is electrically connected to the anode of E0, and the drain electrode of the thirteenth transistor T 13 is electrically connected to the control node N0; The control terminal of the first switch K1 is electrically connected to the first selection control terminal X1, the first terminal of the first switch K1 is electrically connected to the control node N0, and the second terminal of the first switch K1 is electrically connected to a reference voltage terminal; the reference voltage terminal provides a reference voltage Vref; The switch circuit also includes a second switch K2; The control terminal of the second switch K2 is electrically connected to the second selection control terminal X2, the first terminal of the second switch K2 is electrically connected to the control node N0, and the second terminal of the second switch K2 is electrically connected to the compensation terminal SENS; The display data writing-in circuit includes a sixth transistor T6; The gate electrode of the sixth transistor T6 is electrically connected to the scanning terminal G1, the source electrode of the sixth transistor T6 is electrically connected to the second data line DI, and the drain electrode of the sixth transistor T6 is electrically connected to the gate electrode of the driving transistor T0; The switch control circuit includes a third transistor T3; The gate electrode of T3 is electrically connected to the switch control terminal N4, the source electrode of T4 is electrically connected to the high voltage terminal VDD, the drain electrode of T4 is electrically connected to the source electrode of T0; the cathode of E0 is electrically connected to the low voltage terminal VSS; The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1; The gate electrode of the first transistor T1 is electrically connected to the first control terminal GB, the source electrode of the first transistor T1 is electrically connected to the first data line DT, and the drain electrode of the first transistor T1 is electrically connected to the switch control terminal N4; The gate electrode of the second transistor T2 is electrically connected to the scanning terminal G1, the source electrode of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain electrode of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is configured to provide a second initial voltage Vi2; A first terminal of the first capacitor C1 is electrically connected to the switch control terminal N4, and a second terminal of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM.

[0182] In the pixel circuit shown in FIG. 51, the second control terminal is the scanning terminal G1, but the present invention is not limited thereto.

[0183] In the pixel circuit shown in FIG. 51, all transistors are p-type transistors, but the present invention is not limited thereto.

[0184] In the pixel circuit shown in FIG. 51, T6, K1, and K2 form an extraction circuit for extracting Vth and Id. As shown in FIG. 52, when the pixel circuit shown in FIG. 51 of the present disclosure is in operation, a display cycle may include a display phase SX and a sensing phase SC; The display phase SX includes a first writing-in time period S12, a first light emitting time period S13, a second writing-in time period S21 and a second light emitting time period S22 which are arranged successively; The sensing phase SC includes a reset time period SC1, a compensation time period SC2 and an extraction time period SC3 which are arranged successively; In the first writing-in time period S12, G1 provides a low voltage signal, T6 and T2 are turned on, DI provides a display data voltage Vdata_I, Vdata_I is written into the first node N1, T0 is turned on, and the second initial voltage Vi2 provided by I2 is written into N4 through T2; T3 is turned on; In the first light emitting time period S13, G1 provides a high voltage signal, T3 is turned on, and T0 drivings E0 to emit light; the first light emitting time period S13 lasts for a first time t1; In the second writing-in time period S21, GB provides a low voltage signal, T1 is turned on, and DT provides a light emitting control data voltage; As shown in FIG. 52, in the second writing-in time period S21, the light emitting control data voltage provided by DT is a high voltage signal; In the second light emitting time period S22, T3 is turned off, E0 does not emit light, and a short-time light emitting is realized, and the light emitting duration is t1; When the light emitting control data voltage provided by DT is a low voltage signal in the second writing-in time period S21, T3 is turned on in the second light emitting time period S22, and T0 drivings E0 to emit light, realizing long-time light emitting, and the light emitting time is t1+t2, where t2 is the duration of the second light emitting time period S22; As shown in FIG. 52, in the reset time period SC1, G1 provides a low voltage signal, T13, T0, T6, T3, and T2 are turned on, K1 is turned on, and N2 is reset through Vref; DI provides a data voltage Vdata to the first node N1; In the compensation time period SC2, K1 is turned off, Vref is less than Vdata, and Vdata is less than Vdd, Vdd is the voltage value of the high voltage signal provided by VDD, when the potential of N2 is Vdata-Vth, the gate-source voltage of T0 is equal to Vth, Vth is the threshold voltage of T0, T0 is turned off, and Vth is written into N2; In the extraction time period SC3, K2 is turned on and the IC (integrated circuit) extracts Vth through SENS.

[0185] As shown in FIG. 52, in a time period other than the second writing-in time period, DT may provide the second initial voltage Vi2, but is not limited thereto. FIG. 53A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 in the first writing-in time period S12 and the first light emitting time period S22; FIG. 53B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 in a second writing-in time period S21 and a second light emitting time period S22; FIG. 53C is a schematic diagram of the working state of the pixel circuit shown in FIG. 51 during a reset time period SC1; FIG. 53D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 during the compensation time period SC2; FIG. 53E is a schematic diagram of the working state of the pixel circuit shown in FIG. 51 during the extraction time period SC3. FIG. 54A is a schematic diagram showing simulation results of high grayscale display in a display phase of the pixel circuit shown in FIG. 51;

[0186] FIG. 54B is a schematic diagram showing simulation results of low grayscale display during the display phase of the pixel circuit shown in FIG. 51. The difference between the pixel circuit shown in FIG. 55 and the pixel circuit shown in FIG. 51 is that: all transistors are NMOS TFTs to realize a pixel circuit of driving current control + light emitting duration control; The pixel circuit shown in FIG. 55 can be applied to oxide display products.

[0187] FIG. 56 is a timing diagram of the pixel circuit shown in FIG. 55.

[0188] The difference between the pixel circuit shown in FIG. 57 and the pixel circuit shown in FIG. 51 is that: T13, T1 and T2 are NMOS TFTs, T6, T0 and T3 are PMOS TFTs; the gate electrode of T2 and the gate electrode of T13 are both electrically connected to the second control terminal GA.

[0189] The pixel circuit shown in FIG. 57 is an LTPO pixel circuit, which adopts LTPO technology and utilizes the advantages of low leakage current of oxide TFT and high mobility of PMOS TFT. T13, T1 and T2 are set as NMOS TFT, and T6, T0 and T3 are set as PMOS TFT to meet threshold voltage compensation, current driving and PPI (current density) requirements, thereby further improving display performance.

[0190] FIG. 58 is a timing diagram of the pixel circuit shown in FIG. 57. The pixel circuit described in the embodiment of the present disclosure includes a light emitting element, a driving circuit, a first reset circuit and a data writing-in circuit; The control terminal of the driving circuit is electrically connected to the first node, the driving circuit is electrically connected to the first electrode of the light emitting element, and the driving circuit is configured to generate a driving current to drive the light emitting element under the control of the potential of the first node; The data writing-in circuit is electrically connected to the writing-in control terminal and the writing-in node respectively, and is configured to sequentially provide a display data voltage and a light emitting time control data voltage to the writing-in node under the control of a writing-in control signal provided by the writing-in control terminal; The first reset circuit is electrically connected to a first reset control terminal, a first initial voltage terminal and a first electrode of the light emitting element, respectively, and is configured to write a first initial voltage provided by the first initial voltage terminal into the first electrode of the light emitting element under the control of a first reset control signal provided by the first reset control terminal during a reset time period set between a time period for writing-in the display data voltage and a time period for writing-in the light emitting time control data voltage. When the pixel circuit of the embodiment of the present disclosure is working, a display cycle (the display cycle may include a frame of time) includes a first display phase and a second display phase which are set successively, the first display phase includes a first writing-in time period; the second display phase includes a reset time period and a second writing-in time period which are set successively; In the first writing-in time period, the data writing-in circuit provides a display data voltage to the writing-in node under the control of the writing-in control signal; In the reset time period, the first reset circuit writes the first initial voltage into the first electrode of the light emitting element under the control of the first reset control signal; In the second writing-in time period, the data writing-in circuit provides the light emitting time control data voltage to the writing-in node under the control of the writing-in control signal.

[0191] In a specific implementation, when the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage, the first reset circuit writes a first initial voltage to the first electrode of the light emitting element under the control of a first reset control signal, to release the residual charge in the first electrode of the light emitting element and improve display uniformity. When the pixel circuit according to the embodiment of the present disclosure is working, the reset time period may be a second reset time period, and the first display phase may include a first reset time period set before the first writing-in time period;

[0192] In the first reset time period, the first reset circuit writes a first initial voltage into the first electrode of the light emitting element under the control of the first reset control signal, to release residual charges in the first electrode of the light emitting element and improve display uniformity.

[0193] When the pixel circuit described in the embodiment of the present disclosure is in operation, in a first reset time period and a second reset time period, the first reset circuit writes a first initial voltage into the first electrode of the light emitting element under the control of a first reset control signal, so as to release the residual charge in the first electrode of the light emitting element at a high frequency, thereby improving display uniformity.

[0194] In at least one embodiment of the present disclosure, the first terminal of the driving circuit is electrically connected to the first electrode of the light emitting element, and the writing-in node is electrically connected to the second terminal of the driving circuit; or, the second terminal of the driving circuit is electrically connected to the first electrode of the light emitting element, and the writing-in node is electrically connected to the first terminal of the driving circuit.

[0195] Optionally, the light emitting element is an inorganic light emitting diode, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0196] In at least one embodiment of the present disclosure, the width-to-length ratio of a transistor is a ratio of a channel width W to a channel length L of the transistor.

[0197] In a specific implementation, the light emitting element may be an inorganic light emitting diode, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5.

[0198] In at least one embodiment of the present disclosure, the light emitting element may be an inorganic light emitting diode, but is not limited thereto; for example, the light emitting element may be a micro light emitting diode or a mini light emitting diode.

[0199] In a specific implementation, the light emitting element may also be an organic light emitting diode. The pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit;

[0200] The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first node respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the first node during the reset time period under the control of the second reset control signal provided by the second reset control terminal. In a specific implementation, the driving circuit may further include a second reset circuit, and in the second reset time period, the second reset circuit writes a second initial voltage into the first node under the control of a second reset control signal; The second reset circuit also writes a second initial voltage into the first node under the control of a second reset control signal during the first reset time period; The first display phase may further include a first light emitting time period set after the first writing-in time period, and the second display phase may further include a second light emitting time period set after the second writing-in time period, in the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage, and in the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to drive the light emitting element to emit light; At least one embodiment of the present disclosure resets the potential of the first node N1 before a first writing-in time period and before a second writing-in time period, so that when the display data voltage and the light emitting time control data voltage have the same voltage value, the difference between the driving current generated by the driving circuit in the first light emitting time period and the driving current generated by the driving circuit in the second light emitting time period is reduced, thereby reducing the brightness difference between the first light emitting time period and the second light emitting time period in the same frame time.

[0201] Optionally, the first reset control terminal and the second reset control terminal may be the same reset control terminal, but not limited thereto; in actual operation, the first reset control terminal and the second reset control terminal may be different reset control terminals. In at least one embodiment of the present disclosure, the writing-in control terminal includes a first control terminal and a second control terminal, and the data writing-in circuit is also electrically connected to the first data line and the second data line respectively; the display cycle of the pixel circuit includes a first writing-in time period and a second writing-in time period which are set successively;

[0202] The data writing-in circuit is configured to write the display data voltage provided by the second data line to the writing-in node under the control of the second control signal provided by the second control terminal during the first writing-in time period, and is configured to write the light emitting time control data voltage provided by the first data line to the writing-in node under the control of the first control signal provided by the first control terminal during the second writing-in time period.

[0203] In a specific implementation, the writing-in control terminal may include a first control terminal and a second control terminal. In the first writing-in time period, under the control of a second control signal, the data writing-in circuit writes the display data voltage provided by the second data line into the writing-in node. In the second writing-in time period, the data writing-in circuit writes the light emitting time control data voltage provided by the first data line into the writing-in node under the control of a first control signal. The pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; The first light emitting control circuit is electrically connected to the light emitting control terminal, the first voltage terminal and the first terminal of the driving circuit respectively, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and is configured to control the second terminal of the driving circuit to be connected to the first electrode of the light emitting element under the control of the light emitting control signal; the second electrode of the light emitting element is electrically connected to the second voltage terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the second terminal of the driving circuit respectively, and is configured to control the communication between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal;

[0204] The first electrode of the light emitting element is a first electrode of the light emitting element.

[0205] In a specific implementation, the pixel circuit may further include a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; the first light emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the connection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the light emitting control signal; the compensation control circuit controls the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of a scanning signal to perform threshold voltage compensation.

[0206] In at least one embodiment of the present disclosure, the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the transistor included in the first light emitting control circuit is greater than 1, the width-to-length ratio of the transistor included in the second light emitting control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0207] In a specific implementation, the light emitting element may be an inorganic light emitting diode, the width-to-length ratio of the transistor included in the first light emitting control circuit may be greater than 1, the width-to-length ratio of the transistor included in the second light emitting control circuit may be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5.

[0208] Optionally, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal.

[0209] In at least one embodiment of the present disclosure, the pixel circuit may further include an energy storage circuit, wherein the energy storage circuit is electrically connected to the first node and is configured to store electrical energy. Optionally, the energy storage circuit includes a storage capacitor; the light emitting element is an inorganic light emitting diode;

[0210] The capacitance value of the storage capacitor is greater than 3 times the gate-source capacitance of the transistor in the driving circuit. In a specific implementation, the energy storage circuit may include a storage capacitor; the light emitting element may be an inorganic light emitting diode;

[0211] The capacitance value of the storage capacitor may be greater than 3 times the gate-source capacitance of the transistor in the driving circuit.

[0212] In a specific implementation, the capacitance value of the storage capacitor is set to be greater than 3 times the gate-source capacitance of the transistor in the driving circuit, so that when the source potential of the transistor in the driving circuit changes, the gate potential of the transistor in the driving circuit can be maintained to ensure display accuracy.

[0213] In at least one embodiment of the present disclosure, the gate-source capacitance of the transistor in the driving circuit may be a parasitic capacitance between the gate electrode and the source electrode of the transistor in the driving circuit, which may be calculated based on the facing area of the gate electrode and the source electrode of the transistor in the driving circuit, and a dielectric constant, wherein the dielectric constant may be calculated based on the material and thickness of the insulating layer between the gate electrode and the source electrode of the transistor in the driving circuit. As shown in FIG. 59, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a first reset circuit 14, a data writing-in circuit 15, a second reset circuit 51, a first light emitting control circuit 61, a second light emitting control circuit 62 and a compensation control circuit 32; the writing-in control terminal includes a first control terminal GB and a second control terminal GA; The energy storage circuit 10 is electrically connected to the first node N1 and is configured to store electrical energy; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The data writing-in circuit 15 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second data line DI and the first terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the second control signal provided by the second control terminal GA, and is configured to write the light emitting time control data voltage provided by the first data line DT into the first terminal of the driving circuit 11 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first electrode of the light emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset time period between the time period of writing-in the display data voltage and the time period of writing-in the light emitting time control data voltage; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the first terminal of the driving circuit 11 respectively, and is configured to control the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the first electrode of the light emitting element E1 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the light emitting control signal; the second electrode of the light emitting element 31 is electrically connected to the second voltage terminal V2; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the control terminal of the driving circuit 11 to communicate with the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0214] The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 during the reset time period under the control of the reset control signal provided by the reset control terminal RST. In at least one embodiment of the present disclosure, the light emitting element may be a light emitting diode, the first electrode of the light emitting element may be an anode of the light emitting diode, and the second electrode of the light emitting element may be a cathode of the light emitting diode;

[0215] The light emitting diode may be an organic light emitting diode, a mini light emitting diode or a micro light emitting diode.

[0216] In the pixel circuit shown in FIG. 59, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, the first electrode of the light emitting element is the first electrode of the light emitting element, and the writing-in node is electrically connected to the first terminal of the driving circuit, but is not limited to this. The pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; The first electrode of the light emitting element is electrically connected to the first voltage terminal; The first light emitting control circuit is electrically connected to the light emitting control terminal, the second electrode of the light emitting element and the first terminal of the driving circuit respectively, and is configured to control the second electrode of the light emitting element to be connected to the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the second voltage terminal respectively, and is configured to control the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the first terminal of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0217] In a specific implementation, the pixel circuit may further include a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; the first light emitting control circuit controls the second electrode of the light emitting element to be connected to the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal; the compensation control circuit controls the control terminal of the driving circuit to be connected to the first terminal of the driving circuit under the control of a scanning signal to perform threshold voltage compensation. As shown in FIG. 60, the pixel circuit described in the embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a first reset circuit 14, a data writing-in circuit 15, a second reset circuit 51, a first light emitting control circuit 61, a second light emitting control circuit 62 and a compensation control circuit 32; the writing-in control terminal includes a first control terminal GB and a second control terminal GA; The energy storage circuit 10 is electrically connected to the first node N1 and is configured to store electrical energy; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is electrically connected to the second electrode of the light emitting element E1 through the first light emitting control circuit 61. The driving circuit 11 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The data writing-in circuit 15 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second data line DI and the second terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the second control signal provided by the second control terminal GA, and is configured to write the light emitting time control data voltage provided by the first data line DT into the second terminal of the driving circuit 11 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the second electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second electrode of the light emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the second electrode of the light emitting element E1 and the first terminal of the driving circuit 11 respectively, and is configured to control the second electrode of the light emitting element E1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the second voltage terminal V2 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 during the reset time period under the control of the reset control signal provided by the reset control terminal RST.

[0218] In the pixel circuit shown in FIG. 60, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, the first electrode of the light emitting element is the second electrode of the light emitting element, and the writing-in node is electrically connected to the second terminal of the driving circuit, but is not limited to this. As shown in FIG. 61, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a first reset circuit 14, a data writing-in circuit 15, a second reset circuit 51, a first light emitting control circuit 61, a second light emitting control circuit 62 and a compensation control circuit 32; the writing-in control terminal includes a first control terminal GB and a second control terminal GA; The energy storage circuit 10 is electrically connected to the first node N1 and is configured to store electrical energy; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The data writing-in circuit 15 is electrically connected to the scanning terminal G1, the data line D0 and the first terminal of the driving circuit 11 respectively, and is configured to write the display data voltage and the light emitting time control data voltage provided by the data line D0 into the first terminal of the driving circuit 11 in sequence under the control of the scanning signal provided by the scanning terminal G1; The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first electrode of the light emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset time period between the time period of writing-in the display data voltage and the time period of writing-in the light emitting time control data voltage; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the first terminal of the driving circuit 11 respectively, and is configured to control the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the first electrode of the light emitting element E1 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the light emitting control signal; the second electrode of the light emitting element 31 is electrically connected to the second voltage terminal V2; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the control terminal of the driving circuit 11 to communicate with the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 during the reset time period under the control of the reset control signal provided by the reset control terminal RST.

[0219] In the pixel circuit shown in FIG. 61, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, and the first electrode of the light emitting element is the second electrode of the light emitting element. As shown in FIG. 62, the pixel circuit described in the embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a first reset circuit 14, a data writing-in circuit 15, a second reset circuit 51, a first light emitting control circuit 61, a second light emitting control circuit 62 and a compensation control circuit 32; the writing-in control terminal includes a first control terminal GB and a second control terminal GA; The energy storage circuit 10 is electrically connected to the first node N1 and is configured to store electrical energy; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is electrically connected to the second electrode of the light emitting element E1 through the first light emitting control circuit 61. The driving circuit 11 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The data writing-in circuit 15 is electrically connected to the scanning terminal G1, the data line D0 and the second terminal of the driving circuit 11 respectively, and is configured to write the display data voltage and the light emitting time control data voltage provided by the data line D0 into the second terminal of the driving circuit 11 in sequence under the control of the scanning signal provided by the scanning terminal G1; The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the second electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second electrode of the light emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the second electrode of the light emitting element E1 and the first terminal of the driving circuit 11 respectively, and is configured to control the second electrode of the light emitting element E1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the second voltage terminal V2 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 during the reset time period under the control of the reset control signal provided by the reset control terminal RST.

[0220] In the pixel circuit shown in FIG. 62, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, and the first electrode of the light emitting element is the second electrode of the light emitting element. In the pixel circuit shown in FIG. 61 and FIG. 62, the data writing-in circuit may include a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the scanning terminal, a first electrode of the tenth transistor is electrically connected to the data line, and the tenth transistor is electrically connected to the first terminal of the driving circuit or the second terminal of the driving circuit. In at least one embodiment of the present disclosure, the writing-in node includes a first writing-in node and a second writing-in node;

[0221] The first writing-in node is electrically connected to the first terminal of the driving circuit; the pixel circuit also includes a switch control circuit; the second terminal of the driving circuit is electrically connected to the first electrode of the light emitting element through the switch control circuit, and the switch control circuit is electrically connected to the switch control terminal, and the switch control circuit is configured to control the connection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; the second writing-in node is electrically connected to the switch control terminal. In at least one embodiment of the present disclosure, the writing-in node includes a first writing-in node and a second writing-in node;

[0222] The first writing-in node is electrically connected to the second terminal of the driving circuit; the pixel circuit also includes a switch control circuit; the first terminal of the driving circuit is electrically connected to the first electrode of the light emitting element through the switch control circuit, and the switch control circuit is electrically connected to the switch control terminal, and the switch control circuit is configured to control the connection between the first terminal of the driving circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; the second writing-in node is electrically connected to the switch control terminal.

[0223] Optionally, the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0224] In a specific implementation, the light emitting element may be an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit may be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5. In at least one embodiment of the present disclosure, the data writing-in circuit includes a first writing-in sub-circuit and a second writing-in sub-circuit; the writing-in control terminal includes a scanning terminal and a first control terminal; The first writing-in sub-circuit is electrically connected to the first control terminal, the first data line and the second writing-in node respectively, and is configured to write the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of the first control signal provided by the first control terminal; The second writing-in sub-circuit is electrically connected to the scanning terminal, the second data line and the first writing-in node respectively, and is configured to write the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal provided by the scanning terminal.

[0225] In a specific implementation, the data writing-in circuit may include a first writing-in sub-circuit and a second writing-in sub-circuit, wherein the first writing-in sub-circuit writes the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of a first control signal; and the second writing-in sub-circuit writes the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal. The pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit, an initialization circuit and a voltage maintenance circuit; The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first node respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the second reset control signal provided by the second reset control terminal; The initialization circuit is electrically connected to the second control terminal, the third initial voltage terminal and the second writing-in node respectively, and is configured to write the third initial voltage provided by the third initial voltage terminal into the second writing-in node under the control of the second control signal provided by the second control terminal; The voltage maintenance circuit is electrically connected to the switch control terminal and is configured to maintain the potential of the switch control terminal.

[0226] In a specific implementation, the pixel circuit may further include a second reset circuit and an initialization circuit; the second reset circuit writes the second initial voltage provided by the second initial voltage terminal into the first node under the control of a second reset control signal; the initialization circuit writes into the second writing-in node under the control of a second control signal.

[0227] Optionally, the voltage maintenance circuit may include a second capacitor; a first terminal of the second capacitor is electrically connected to the switch control terminal, and a second terminal of the second capacitor is electrically connected to the DC voltage terminal.

[0228] In at least one embodiment of the present disclosure, the DC voltage terminal may be a common electrode voltage terminal, a low voltage terminal or a ground terminal, but is not limited thereto. The pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; The first light emitting control circuit is electrically connected to the light emitting control terminal, the first voltage terminal and the first terminal of the driving circuit respectively, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first terminal of the switch control circuit respectively, and is configured to control the second terminal of the driving circuit to be connected to the first terminal of the switch control circuit under the control of the light emitting control signal; The second terminal of the switch control circuit is electrically connected to the first electrode of the light emitting element; the second electrode of the light emitting element is electrically connected to the second voltage terminal; the switch control circuit is configured to control the second light emitting control circuit to be connected to the first electrode of the light emitting element under the control of the potential of the switch control terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the second terminal of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0229] In a specific implementation, the pixel circuit may further include a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; the first light emitting control circuit controls the first voltage terminal to be connected to the first terminal of the driving circuit under the control of the light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be connected to the first terminal of the switch control circuit under the control of the light emitting control signal; the switch control circuit controls the second light emitting control circuit to be connected to the first electrode of the light emitting element under the control of the potential of the switch control terminal; the compensation control circuit controls the control terminal of the driving circuit to be connected to the second terminal of the driving circuit under the control of the scanning signal to perform threshold voltage compensation. As shown in FIG. 63, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a switch control circuit 12, a first reset circuit 14, a data writing-in circuit, a second reset circuit 51, an initialization circuit 50, a voltage maintenance circuit 103, a first light emitting control circuit 61, a second light emitting control circuit 62, and a compensation control circuit 32; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal I1 into the first electrode of the light emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST1 during a reset time period between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage; The data writing-in circuit includes a first writing-in sub-circuit 151 and a second writing-in sub-circuit 152; the writing-in control terminal includes a scanning terminal G1 and a first control terminal GB; The first writing-in sub-circuit 151 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The second writing-in sub-circuit 152 is electrically connected to the scanning terminal G1, the second data line DI and the first terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the second reset control terminal RST2, the second initial voltage terminal I2 and the first node N1 respectively, and is configured to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the second reset control signal provided by the second reset control terminal RST2; The initialization circuit 50 is electrically connected to the second control terminal GA, the third initial voltage terminal I3 and the switch control terminal N4 respectively, and is configured to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA; The voltage maintenance circuit 103 is electrically connected to the switch control terminal N4, and is configured to maintain the potential of the switch control terminal N4; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the first terminal of the driving circuit 11 respectively, and is configured to control the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the first terminal of the switch control circuit 12 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the first terminal of the switch control circuit 12 under the control of the light emitting control signal; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the second terminal of the switch control circuit 12 is electrically connected to the first electrode of the light emitting element E1; the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; the switch control circuit 12 is configured to control the second light emitting control circuit 62 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the control terminal of the driving circuit 11 to communicate with the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The first electrode of the light emitting element E1 is a first electrode of the light emitting element E1.

[0230] Optionally, the light emitting element may be a light emitting diode, and the first electrode of the light emitting element may be an anode. When the pixel circuit shown in FIG. 63 of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase that are arranged in sequence; The first display phase includes a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase includes a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence; In the first reset time period, the first reset circuit 14 writes the first initial voltage into the first electrode of the light emitting element E1 under the control of the first reset control signal; the second reset circuit 51 writes the second initial voltage Vi2 into the first node N1 under the control of the second reset control signal; In the first writing-in time period, the second writing-in sub-circuit 152 writes the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the scanning signal; the initialization circuit 50 writes the third initial voltage Vi3 into the switch control terminal N4 under the control of the second control signal to control the switch control circuit 12 to be turned on under the control of the potential of the switch control terminal N4; the compensation control circuit 32 controls the control terminal of the driving circuit 11 to be connected to the second terminal of the driving circuit 11 under the control of the scanning signal; In the first light emitting time period, the first light emitting control circuit 61 is configured to control the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal; the second light emitting control circuit 62 is configured to control the second terminal of the driving circuit 11 to be connected to the first terminal of the switch control circuit 12 under the control of the light emitting control signal; the driving circuit 11 drivings the light emitting element E1 to emit light; In the second reset time period, the first reset circuit 14 writes the first initial voltage into the first electrode of the light emitting element E1 under the control of the first reset control signal; In the second writing-in time period, the first writing-in sub-circuit 151 writes the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal; In the second light emitting time period, the first light emitting control circuit 61 controls the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal; the second light emitting control circuit 62 controls the second terminal of the driving circuit 11 to be connected to the first terminal of the switch control circuit 12 under the control of the light emitting control signal; the driving circuit 11 controls whether the light emitting element E1 emits light according to the light emitting time control data voltage.

[0231] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a first reset time period and a second reset time period, the first reset circuit writes a first initial voltage into the first electrode of the light emitting element under the control of a first reset control signal, so as to release the residual charge in the first electrode of the light emitting element at a high frequency, thereby improving display uniformity. The pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; The first electrode of the light emitting element is electrically connected to the first voltage terminal; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the first terminal of the switch control circuit is electrically connected to the second electrode of the light emitting element, and the second terminal of the switch control circuit is electrically connected to the first light emitting control circuit; the switch control circuit is configured to control the second electrode of the light emitting element to be connected to the first light emitting control circuit under the control of the potential of the switch control terminal; The first light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the switch control circuit and the first terminal of the driving circuit respectively, and is configured to control the second terminal of the switch control circuit to be connected to the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the second voltage terminal respectively, and is configured to control the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the first terminal of the driving circuit respectively, and is configured to control the communication between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal;

[0232] The first electrode of the light emitting element E1 is the second electrode of the light emitting element E1.

[0233] Optionally, the light emitting element may be a light emitting diode, and the second electrode of the light emitting element may be a cathode.

[0234] In a specific implementation, the pixel circuit may also include a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; the switch control circuit controls the second electrode of the light emitting element to be connected to the first light emitting control circuit under the control of the potential of the switch control terminal; the first light emitting control circuit controls the second terminal of the switch control circuit to be connected to the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal; and the compensation control circuit controls the control terminal of the driving circuit to be connected to the first terminal of the driving circuit under the control of the scanning signal. As shown in FIG. 64, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a switch control circuit 12, a first reset circuit 14, a data writing-in circuit, a second reset circuit 51, an initialization circuit 50, a voltage maintenance circuit 103, a first light emitting control circuit 61, a second light emitting control circuit 62, and a compensation control circuit 32; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the second electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal I1 into the second electrode of the light emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST1 during a reset time period between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage; The data writing-in circuit includes a first writing-in sub-circuit 151 and a second writing-in sub-circuit 152; the writing-in control terminal includes a scanning terminal G1 and a first control terminal GB; The first writing-in sub-circuit 151 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The second writing-in sub-circuit 152 is electrically connected to the scanning terminal G1, the second data line DI and the second terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the second reset control terminal RST2, the second initial voltage terminal I2 and the first node N1 respectively, and is configured to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the second reset control signal provided by the second reset control terminal RST2; The initialization circuit 50 is electrically connected to the second control terminal GA, the third initial voltage terminal I3 and the switch control terminal N4 respectively, and is configured to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA; The voltage maintenance circuit 103 is electrically connected to the switch control terminal N4, and is configured to maintain the potential of the switch control terminal N4; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the first terminal of the switch control circuit 12 is electrically connected to the second electrode of the light emitting element E1, and the second terminal of the switch control circuit 12 is electrically connected to the first light emitting control circuit 61; the switch control circuit 12 is configured to control the second electrode of the light emitting element E1 to be connected to the first light emitting control circuit 61 under the control of the potential of the switch control terminal N4; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the second terminal of the switch control circuit 12 and the first terminal of the driving circuit 11 respectively, and is configured to control the second terminal of the switch control circuit 12 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the second voltage terminal V2 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal;

[0235] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the connection between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1. When the pixel circuit shown in FIG. 64 of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase that are arranged in sequence; The first display phase includes a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase includes a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence; In the first reset time period, the first reset circuit 14 writes the first initial voltage into the second electrode of the light emitting element E1 under the control of the first reset control signal; the second reset circuit 51 writes the second initial voltage Vi2 into the first node N1 under the control of the second reset control signal; In the first writing-in time period, the second writing-in sub-circuit 152 writes the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the scanning signal; the initialization circuit 50 writes the third initial voltage Vi3 into the switch control terminal N4 under the control of the second control signal, to control the switch control circuit 12 to be turned on under the control of the potential of the switch control terminal N4; the compensation control circuit 32 controls the control terminal of the driving circuit 11 to be connected to the first terminal of the driving circuit 11 under the control of the scanning signal; In the first light emitting time period, the first light emitting control circuit 61 controls the second terminal of the switch control circuit 12 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; the second light emitting control circuit 62 controls the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal; the driving circuit 11 drivings the light emitting element E1 to emit light; In the second reset time period, the first reset circuit 14 writes the first initial voltage into the second electrode of the light emitting element E1 under the control of the first reset control signal; In the second writing-in time period, the first writing-in sub-circuit 151 writes the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal; In the second light emitting time period, the first light emitting control circuit 61 controls the second terminal of the switch control circuit 12 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; the second light emitting control circuit 62 controls the second terminal of the driving circuit 11 to be connected with the second voltage terminal V2 under the control of the light emitting control signal; the driving circuit 11 controls whether the light emitting element E1 emits light according to the light emitting time control data voltage.

[0236] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a first reset time period and a second reset time period, the first reset circuit writes a first initial voltage into the second electrode of the light emitting element under the control of a first reset control signal, so as to release the residual charge of the first electrode of the light emitting element at a high frequency, thereby improving display uniformity. Optionally, the first reset circuit includes a first transistor, and the second reset transistor includes a second transistor; a gate electrode of the first transistor is electrically connected to the first reset control terminal, a first electrode of the first transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first transistor is electrically connected to the first electrode of the light emitting element; A gate electrode of the second transistor is electrically connected to the second reset control terminal, a first electrode of the second transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second transistor is electrically connected to the first node.

[0237] Optionally, the data writing-in circuit includes a third transistor and a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the writing-in node; A gate electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the writing-in node.

[0238] Optionally, the driving circuit includes a driving transistor, the first light emitting control circuit includes a fifth transistor, the second light emitting control circuit includes a sixth transistor, and the compensation control circuit includes a seventh transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the sixth transistor is electrically connected to the light emitting control terminal, a first electrode of the sixth transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element; a gate electrode of the driving transistor is electrically connected to the first node; A gate electrode of the seventh transistor is electrically connected to the scanning terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to a second electrode of the driving transistor.

[0239] Optionally, the driving circuit includes a driving transistor, the first light emitting control circuit includes a fifth transistor, the second light emitting control circuit includes a sixth transistor, and the compensation control circuit includes a seventh transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the sixth transistor is electrically connected to the light emitting control terminal, a first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal; a gate electrode of the driving transistor is electrically connected to the first node;

[0240] A gate electrode of the seventh transistor is electrically connected to the scanning terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to a first electrode of the driving transistor. Optionally, the first writing-in sub-circuit includes a third transistor, and the second writing-in sub-circuit includes a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the second writing-in node; A gate electrode of the fourth transistor is electrically connected to the scanning terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the first writing-in node.

[0241] Optionally, the initialization circuit includes an eighth transistor; A gate electrode of the eighth transistor is electrically connected to the second control terminal, a first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the second writing-in node.

[0242] Optionally, the switch control circuit includes a ninth transistor; the driving circuit includes a driving transistor, the first light emitting control circuit includes a fifth transistor, the second light emitting control circuit includes a sixth transistor, and the compensation control circuit includes a seventh transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the sixth transistor is electrically connected to the light emitting control terminal, and a first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor; a gate electrode of the ninth transistor is electrically connected to the switch control terminal, a first electrode of the ninth transistor is electrically connected to the second electrode of the sixth transistor, and a second electrode of the ninth transistor is electrically connected to the first electrode of the light emitting element; a gate electrode of the driving transistor is electrically connected to the first node;

[0243] A gate electrode of the seventh transistor is electrically connected to the scanning terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to a second electrode of the driving transistor.

[0244] Optionally, the switch control circuit includes a ninth transistor; the driving circuit includes a driving transistor, the first light emitting control circuit includes a fifth transistor, the second light emitting control circuit includes a sixth transistor, and the compensation control circuit includes a seventh transistor; a gate electrode of the ninth transistor is electrically connected to the switch control terminal, a first electrode of the ninth transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the ninth transistor is electrically connected to the first electrode of the fifth transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to a first electrode of the sixth transistor; a gate electrode of the sixth transistor is electrically connected to the light emitting control terminal, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal;

[0245] A gate electrode of the seventh transistor is electrically connected to the scanning terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to a first electrode of the driving transistor. As shown in FIG. 65, based on the pixel circuit shown in FIG. 59, the light emitting element is a light emitting diode E0; the driving circuit includes a driving transistor T0; the energy storage circuit includes a first capacitor C1; A first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the high voltage terminal VDD; The first reset circuit includes a first transistor T1, and the second reset transistor includes a second transistor T2; The gate electrode of the first transistor T1 is electrically connected to the reset control terminal RST, the source electrode of the first transistor T1 is electrically connected to the first initial voltage terminal I1, the drain electrode of the first transistor T1 is electrically connected to the anode of the light emitting diode E0; the cathode of the light emitting diode E0 is electrically connected to the low voltage terminal VSS; the first initial voltage terminal I1 is configured to provide a first initial voltage Vi1; The gate electrode of the second transistor T2 is electrically connected to the reset control terminal RST, the source electrode of the second transistor T2 is electrically connected to the first initial voltage terminal I1, and the drain electrode of the second transistor T2 is electrically connected to the first node N1; The data writing-in circuit includes a third transistor T3 and a fourth transistor T4; The gate electrode of the third transistor T3 is electrically connected to the first control terminal GB, the source electrode of the third transistor T3 is electrically connected to the first data line DT, and the drain electrode of the third transistor T3 is electrically connected to the source electrode of the driving transistor T0; The gate electrode of the fourth transistor T4 is electrically connected to the second control terminal GA, the source electrode of the fourth transistor T4 is electrically connected to the second data line DI, and the drain electrode of the fourth transistor T4 is electrically connected to the source electrode of the driving transistor T0; The first light emitting control circuit includes a fifth transistor T5, the second light emitting control circuit includes a sixth transistor T6, and the compensation control circuit includes a seventh transistor T7; The gate electrode of the fifth transistor T5 is electrically connected to the light emitting control terminal EM, the source electrode of the fifth transistor T5 is electrically connected to the high voltage terminal VDD, and the drain electrode of the fifth transistor T5 is electrically connected to the source electrode of the driving transistor T0; The gate electrode of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source electrode of the sixth transistor T6 is electrically connected to the drain electrode of the driving transistor T0, the drain electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting diode E0; the cathode of the light emitting diode E0 is electrically connected to the low voltage terminal VSS; The gate electrode of the driving transistor T0 is electrically connected to the first node N1; A gate electrode of the seventh transistor T7 is electrically connected to the scanning terminal G1, a source electrode of the seventh transistor T7 is electrically connected to the first node N1, and a drain electrode of the seventh transistor T7 is electrically connected to the drain electrode of the driving transistor T0.

[0246] In the pixel circuit shown in FIG. 65, all transistors are PMOS (P-type metal-oxide-semiconductor) TFTs (thin film transistors).

[0247] In at least one embodiment of the present disclosure, the light emitting diode may be a Micro LED, a Mini LED or an OLED (organic light emitting diode), but is not limited thereto. As shown in FIG. 66, when the pixel circuit shown in FIG. 65 of the present disclosure is in operation, the display cycle includes a first display phase S1 and a second display phase S2; the first display phase S1 includes a first reset time period S11, a first writing-in time period S12 and a first light emitting time period S13 that are successively set; the second display phase S2 includes a second reset time period S21, a second writing-in time period S22 and a second light emitting time period S23 that are successively set; In the first reset time period S11, RST provides a low voltage signal, as shown in 67A, T2 and T1 are turned on, and the gate electrode of T0 and the anode of E0 are reset through Vi1, the residual charge of the anode of E0 is cleared, and T0 can be turned on at the beginning of the first writing-in time period S12; In the first writing-in time period S12, GA provides a low voltage signal, as shown in FIG. 67B, T4 is turned on, DI provides a display data voltage Vdata_I to the gate electrode of T0, and T7 is turned on; At the beginning of the first writing-in time period S12, T0 is turned on to charge C1 to change the potential of N1 until the potential of N1 becomes Vdata_I+Vth, and T0 is turned off; Vth is the threshold voltage of T0; In the first light emitting time period S13, EM outputs a low voltage signal, as shown in FIG. 67C, T5 and T6 are turned on, and T0 drivings E0 to emit light; In the second reset time period S21, after the first time t1, RST outputs a low voltage signal, as shown in FIG. 67D, T1 and T2 are turned on, the gate electrode of T0 and the anode of E0 are reset, and the residual charge of the anode of E0 is cleared, so that before the light emitting time control data voltage Vdata_T is written, the potential of the gate electrode of T0 and the anode voltage of E0 are consistent with those before the display data voltage is written, and the charging time and voltage jump difference are reduced, so that when Vdata_T and Vdata_I have the same voltage value, the driving current difference between the first light emitting time period and the second light emitting time period is reduced, and the brightness difference between the first light emitting time period and the second light emitting time period in the same frame is reduced; wherein, the first time t1 is the duration of the first light emitting time period S21; In the second writing-in time period S22, GB provides a low voltage signal, as shown in FIG. 67E, T3 is turned on, EM outputs a high voltage signal, T5 and T6 are turned off; G1 provides a low voltage signal, T7 is turned on; DT writes the light emitting time control data voltage Vdata_T to the source electrode of T0; At the beginning of the second writing-in time period S22, T0 is turned on, charging C1, changing the potential of N1 until the potential of N1 becomes Vdata_T + Vth, and T0 is turned off; In the second light emitting time period S23, the EM outputs a low voltage signal, as shown in FIG. 67F, and T5 and T6 are turned on; When Vdata_T is a high voltage signal and the gate-source voltage of T0 is greater than Vth, T0 is turned off, E0 does not emit light, and a short-time light emitting is realized, and the light emitting time is t1, so as to perform low grayscale display; When Vdata_T is equal to Vdata_I, Vdata_I+Vth is written to the gate electrode of T0 again, as shown in FIG. 67F, T0 is turned on, and T0 drivings E0 to emit light, achieving long-time light emitting for high grayscale display; the light emitting duration is t1+t2, t2 is the second time, and t2 is the duration of the second light emitting time period S23.

[0248] When the pixel circuit shown in FIG. 65 is in operation, in the first light emitting time period, the driving current Id generated by T0 is K(Vdata_I-Vdd+ ΔVth) 2< ; wherein K is the current coefficient of T0, ΔVth is the difference between the threshold voltage Vth of T0 during threshold voltage compensation and during light emitting, Id is greater than or equal to 0 and less than or equal to Imax, and Imax is the driving current corresponding to the highest grayscale; and Vdd is the voltage value of the high voltage signal provided by VDD.

[0249] When the pixel circuit shown in FIG. 65 is in operation, When high grayscale display is performed, Vdata_T is equal to Vdata_I; When low gray scale display is performed, Vdata_T may be greater than Vdd to ensure that T0 is turned off during the second light emitting time period.

[0250] In the pixel circuit shown in FIG. 65, Vi1-Vdata_I-min is less than Vth, and Vi1-Vss is less than Vled, so as to ensure that after Vi1 is written into N1, T0 can be turned on normally at the beginning of the first writing-in time period to write the display data voltage and compensate the threshold voltage. At the same time, when the anode potential of E0 is reset by Vi1, E0 does not emit light.

[0251] Wherein, Vdata_I-min is the minimum voltage value of the display data voltage, Vss is the voltage value of the low voltage signal provided by VSS, and Vled is the light emitting voltage of E0.

[0252] FIG. 68A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 66 when performing high grayscale display; FIG. 68B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 66 when performing low grayscale display.

[0253] In FIG. 68A and FIG. 68B, Id is the driving current generated at T0. In at least one embodiment corresponding to FIG. 68A, Vdd is equal to 4.6V, Vss is equal to -3V, Vi1 is equal to -3V, Vdata_I is equal to 2V, and Vdata_T is equal to 2V; In at least one embodiment corresponding to FIG. 68B, Vdd is equal to 4.6V, Vss is equal to -3V, Vi1 is equal to -3V, Vdata_I is equal to 2V, and Vdata_T is equal to 6V.

[0254] The difference between the pixel circuit shown in FIG. 69 and the pixel circuit shown in FIG. 66 is that T7, T2, and T1 are NMOS (N-type metal-oxide-semiconductor) TFTs.

[0255] The pixel circuit shown in FIG. 69 of the present disclosure adopts LTPO (low-temperature polycrystalline oxide) technology, and utilizes the advantage of low leakage current of oxide TFT to reduce the gate leakage of T0 and the anode leakage of E0, that is, T7, T2 and T1 or part of them are changed from PMOS TFT to NMOS TFT; utilizing the advantage of high mobility of PMOS TFT, T4, T0, T5, T6 and T3 are PMOS TFTs, which meets the threshold voltage compensation, current driving requirements and reduces the charging time, thereby further improving the display performance.

[0256] FIG. 70 is a timing diagram of the pixel circuit shown in FIG. 69 of the present disclosure. As shown in FIG. 71, based on the pixel circuit shown in FIG. 60, the light emitting element is a light emitting diode E0; the driving circuit includes a driving transistor T0; the energy storage circuit includes a first capacitor C1; A first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to a low voltage terminal VSS; The first reset circuit includes a first transistor T1, and the second reset transistor includes a second transistor T2; The gate electrode of the first transistor T1 is electrically connected to the reset control terminal RST, the drain electrode of the first transistor T1 is electrically connected to the first initial voltage terminal I1, the sou...

Examples

Embodiment Construction

[0031]The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present disclosure.

[0032]The transistors used in all embodiments of the present disclosure may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiment of the present disclosure, in order to distinguish the two electrodes of the transistor except the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode.

[0033]In actu...

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display technology, in particular to a pixel circuit, a driving method and a display device.BACKGROUND

[0002] Micro Light Emitting Diode (Micro LED) and Mini Light Emitting Diode (Mini LED) will be widely used in the future display field due to its high brightness and high reliability. As a self-light emitting device, the light emitting efficiency, brightness and color coordinates of LED will change with the current density at low current density. To achieve grayscale display, LED needs to be under high current density, that is, high current to achieve grayscale display. Traditional current control driving circuits cannot meet the requirements of grayscale display requirements of Micro LED and Mini LED.SUMMARY

[0003] In one aspect, the present disclosure provides in some embodiments a pixel circuit, including a driving circuit, a light emitting element, an energy storage circuit and a data writing-in circuit; a control terminal of the driving circuit is electrically connected to a first node, and the driving circuit is configured to generate a driving current to drive the light emitting element under the control of a potential of the first node; a first terminal of the energy storage circuit is electrically connected to the first node, a second terminal of the energy storage circuit is electrically connected to a second node, and the energy storage circuit is configured to store electrical energy; the data writing-in circuit is electrically connected to a writing-in control terminal and a writing-in node respectively, and is configured to sequentially provide a display data voltage and a light emitting time control data voltage to the writing-in node under the control of a writing-in control signal provided by the writing-in control terminal; the writing-in node is the second node; or, the pixel circuit also includes a switch control circuit; the switch control circuit is electrically connected to a switch control terminal, the driving circuit and the light emitting element, respectively, and is configured to control the connection between the driving circuit and the light emitting element under the control of a potential of the switch control terminal; the writing-in node includes a first writing-in node and a second writing-in node; the first writing-in node is the second node, and the second writing-in node is electrically connected to the switch control terminal.

[0004] Optionally, the writing-in node is the second node; the pixel circuit further comprises a first reset circuit and a second reset circuit; the first reset circuit is electrically connected to the reset control terminal, a reference voltage terminal and the second node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the second node under the control of a reset control signal provided by the reset control terminal during a reset time period set between a time period for writing the display data voltage and a time period for writing the light emitting time control data voltage; the second reset circuit is electrically connected to the reset control terminal, a first initial voltage terminal and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the reset control signal during the reset time period.

[0005] Optionally, the writing-in node is the second node; the writing-in control terminal includes a first control terminal and a second control terminal; the data line includes a first data line and a second data line; the display cycle of the pixel circuit includes a first writing-in time period and a second writing-in time period which are set successively; the data writing-in circuit is electrically connected to the first control terminal, the second control terminal, the first data line and the second data line respectively, and is configured to write the display data voltage provided by the second data line into the second node under the control of the second control signal provided by the second control terminal in the first writing-in time period, and to write the light emitting time control data voltage provided by the first data line into the second node under the control of the first control signal provided by the first control terminal in the second writing-in time period.

[0006] Optionally, the writing-in node is the second node; the pixel circuit further comprises a light emitting control circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to a third node; the light emitting control circuit is electrically connected to the light emitting control terminal, the third node and the first electrode of the light emitting element respectively, and is configured to control the connection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal; the second electrode of the light emitting element is electrically connected to the second voltage terminal; or, the first electrode of the light emitting element is electrically connected to the first voltage terminal; the light emitting control circuit is electrically connected to the light emitting control terminal, the second electrode of the light emitting element and the first terminal of the driving circuit respectively, and is configured to control the connection between the second electrode of the light emitting element and the first terminal of the driving circuit under the control of the light emitting control signal; the second terminal of the driving circuit is electrically connected to the second voltage terminal.

[0007] Optionally, the pixel circuit further comprises a switch control circuit; the writing-in node comprises a first writing-in node and a second writing-in node; the data writing-in circuit comprises a first writing-in sub-circuit and a second writing-in sub-circuit; the writing-in control terminal comprises a first control terminal and a scanning terminal; the first writing-in sub-circuit is electrically connected to the first control terminal, the first data line and the second writing-in node respectively, and is configured to write the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of the first control signal provided by the first control terminal; the second writing-in sub-circuit is electrically connected to the scanning terminal, the second data line and the first writing-in node respectively, and is configured to write the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal provided by the scanning terminal.

[0008] Optionally, the pixel circuit further comprises a light emitting control circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal; the second terminal of the driving circuit is electrically connected to the third node; the light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the switch control circuit respectively, and is configured to control the second terminal of the driving circuit to be connected to the switch control circuit under the control of the light emitting control signal provided by the light emitting control terminal; the first terminal of the switch control circuit is electrically connected to the second terminal of the driving circuit through the light emitting control circuit, the second terminal of the switch control circuit is electrically connected to the first electrode of the light emitting element, and the switch control circuit is configured to control the connection between the light emitting control circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; the second electrode of the light emitting element is electrically connected to the second voltage terminal.

[0009] Optionally, the pixel circuit further comprises a light emitting control circuit; the first electrode of the light emitting element is electrically connected to the first voltage terminal; the first terminal of the driving circuit is electrically connected to a third node; a first terminal of the switch control circuit is electrically connected to the second electrode of the light emitting element, a second terminal of the switch control circuit is electrically connected to the first terminal of the driving circuit through the light emitting control circuit, and the switch control circuit is configured to control the connection between the second electrode of the light emitting element and the light emitting control circuit under the control of the potential of the switch control terminal; the light emitting control circuit is electrically connected to the light emitting control terminal, the switch control circuit and the first terminal of the driving circuit respectively, and is configured to control the switch control circuit to be connected to the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; the second terminal of the driving circuit is electrically connected to the second voltage terminal.

[0010] Optionally, the pixel circuit further includes an initialization circuit and a voltage maintenance circuit; wherein the initialization circuit is electrically connected to the second control terminal, the second initial voltage terminal and the second writing-in node respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the second writing-in node under the control of the second control signal provided by the second control terminal; the voltage maintaining circuit is electrically connected to the switch control terminal and is configured to maintain a potential of the switch control terminal.

[0011] Optionally, the pixel circuit further includes a compensation control circuit and a voltage control circuit; wherein the compensation control circuit is electrically connected to the scanning terminal, the first node and the third node respectively, and is configured to control the connection between the first node and the third node under the control of the scanning signal provided by the scanning terminal; the voltage control circuit is electrically connected to the light emitting control terminal, the reference voltage terminal and the second node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the second node under the control of the light emitting control signal provided by the light emitting control terminal.

[0012] Optionally, the light emitting element is an inorganic light emitting diode, a width-to-length ratio of a transistor included in the light emitting control circuit is greater than 1, and a width-to-length ratio of a transistor included in the driving circuit is greater than 0.5.

[0013] Optionally, the light emitting element is an inorganic light emitting diode, a width-to-length ratio of a transistor included in the switch control circuit is greater than 1, and a width-to-length ratio of a transistor included in the driving circuit is greater than 0.5.

[0014] Optionally, the energy storage circuit comprises a storage capacitor; the light emitting element is an inorganic light emitting diode; a capacitance value of the storage capacitor is greater than 3 times a gate-source capacitance of the transistor in the driving circuit.

[0015] Optionally, the first reset circuit comprises a first transistor, and the second reset circuit comprises a second transistor; a gate electrode of the first transistor is electrically connected to the reset control terminal, a first electrode of the first transistor is electrically connected to the reference voltage terminal, and a second electrode of the first transistor is electrically connected to the second node; a gate electrode of the second transistor is electrically connected to the reset control terminal, a first electrode of the second transistor is electrically connected to the first initial voltage terminal, and a second electrode of the second transistor is electrically connected to the first node.

[0016] Optionally, the data writing-in circuit comprises a third transistor and a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the second node; a gate electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the second node.

[0017] Optionally, the data writing-in circuit comprises a third transistor; a gate electrode of the third transistor is electrically connected to the scanning terminal, a first electrode of the third transistor is electrically connected to the data line, and a second electrode of the third transistor is electrically connected to the second node; the data line is configured to provide display data voltage and light emitting time control data voltage in time division manner.

[0018] Optionally, the first writing-in sub-circuit comprises a third transistor, and the second writing-in sub-circuit comprises a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the second writing-in node; a gate electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the first writing-in node.

[0019] Optionally, the light emitting control circuit comprises a fifth transistor; and the driving circuit comprises a driving transistor; a second electrode of the driving transistor is electrically connected to the third node; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the fifth transistor is electrically connected to the first electrode of the light emitting element; a gate electrode of the driving transistor is electrically connected to the first node, and a first electrode of the driving transistor is electrically connected to the first voltage terminal; or, the first electrode of the light emitting element is electrically connected to the first voltage terminal, the gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the light emitting element, and the second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; the gate electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second voltage terminal.

[0020] Optionally, the compensation control circuit comprises a sixth transistor, and the voltage control circuit comprises a seventh transistor; a gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the first node, and a second electrode of the sixth transistor is electrically connected to the third node; a gate electrode of the seventh transistor is electrically connected to the light emitting control terminal, a first electrode of the seventh transistor is electrically connected to a reference voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second node.

[0021] Optionally, the light emission control circuit comprises a fifth transistor; the switch control circuit comprises an eighth transistor; and the driving circuit comprises a driving transistor; a gate electrode of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the first voltage terminal, and a second electrode of the driving transistor is electrically connected to the third node; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the third node, and a second electrode of the fifth transistor is electrically connected to a first electrode of the eighth transistor; a gate electrode of the eighth transistor is electrically connected to the switch control terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.

[0022] Optionally, the light emitting control circuit comprises a fifth transistor; the switch control circuit comprises an eighth transistor; and the driving circuit comprises a driving transistor; a gate electrode of the eighth transistor is electrically connected to the switch control terminal, a first electrode of the eighth transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the eighth transistor is electrically connected to a first electrode of the fifth transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, and a second electrode of the fifth transistor is electrically connected to a first electrode of the driving transistor; a gate electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the second voltage terminal.

[0023] Optionally, the initialization circuit comprises a ninth transistor, the energy storage circuit comprises a first capacitor; and the voltage maintenance circuit comprises a second capacitor; a gate electrode of the ninth transistor is electrically connected to the second control terminal, a first electrode of the ninth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the second writing-in node; a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the second node; a first terminal of the second capacitor is electrically connected to the switch control terminal, and a second terminal of the second capacitor is electrically connected to a DC voltage terminal.

[0024] In a second aspect, an embodiment of the present disclosure provides a driving method, applied to the pixel circuit, the driving method comprises: generating, by the driving circuit, the driving current for driving the light emitting element; providing, by the data writing-in circuit, under the control of the writing-in control signal provided by the writing-in control terminal, the display data voltage and the light emitting time control data voltage to the writing-in node successively.

[0025] Optionally, the writing-in node is the second node; the pixel circuit further comprises a first reset circuit and a second reset circuit; the display cycle of the pixel circuit comprises a first display phase and a second display phase which are arranged successively, the first display phase comprises a first reset time period, and the second display phase comprises a second reset time period; the driving method comprises: in the first reset time period and the second reset time period, writing, by the first reset circuit, the reference voltage into the second node under the control of the reset control signal, and writing, by the second reset circuit, the first initial voltage into the first node under the control of the reset control signal.

[0026] Optionally, the first display phase includes a first writing-in time period arranged after the first reset time period, and the second display period includes a second writing-in time period arranged after the second reset time period; the driving method comprises: in the first writing-in time period, providing, by the data writing-in circuit, a display data voltage to the second node under the control of a writing-in control signal; in the second writing-in period, providing, by the data writing-in circuit, the light emitting time control data voltage to the second node under the control of a writing-in control signal.

[0027] Optionally, the writing-in node is the second node; the pixel circuit further comprises a first reset circuit and a second reset circuit; the display cycle comprises a first display phase and A second display phases; A is an integer greater than 1, and a is a positive integer less than but equal to A; the first display stage is set before the A second display phases; the first display phase comprises a first reset time period and a first writing-in time period which are set in sequence, and an ath second display phase comprises an ath second reset time period and an ath second writing-in time period which are set in sequence; the driving method comprises: in the first reset time period and the ath second reset time period, writing, by the first reset circuit, the reference voltage into the second node under the control of the reset control signal, and writing, by the second reset circuit, the first initial voltage into the first node under the control of the reset control signal; in a first writing-in period, providing, by the data writing-in circuit, a display data voltage to the second node under the control of a writing-in control signal; in the ath second writing-in period, providing, by the data writing-in circuit, the ath light emitting time control data voltage to the second node under the control of the writing-in control signal.

[0028] Optionally, the first display phase includes a first writing-in time period, the second display period includes a second writing-in time period; the pixel circuit further includes a switch control circuit; the writing-in node includes a first writing-in node and a second writing-in node; the data writing-in circuit includes a first writing-in sub-circuit and a second writing-in sub-circuit; the driving method includes: in a first writing-in time period, writing, by the second writing-in sub-circuit, the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal; in the second writing-in time period, writing, by the first writing-in sub-circuit, the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of the first control signal provided by the first control terminal.

[0029] In a third aspect, an embodiment of the present disclosure provides a display device comprising the pixel circuit.BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 12 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 14 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 17 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 18 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 19 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 20 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 21 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 22 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 23 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 24 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 25 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 26 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 27 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 28 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 29 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 30 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 31 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 32 is a timing diagram of the pixel circuit shown in FIG. 31; FIG. 33A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in a first reset time period S11; FIG. 33B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in the first writing-in time period S12; FIG. 33C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in the first light emitting time period S13; FIG. 33D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in a second reset time period S21; FIG. 33E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in a second writing-in time period S22; FIG. 34A is a schematic diagram of simulation results of a high grayscale display of the pixel circuit shown in FIG. 31; FIG. 34B is a schematic diagram showing simulation results of low grayscale display of the pixel circuit shown in FIG. 31; FIG. 35 is a timing diagram of the pixel circuit shown in FIG. 31; FIG. 36 is a schematic diagram of the light emitting time of the pixel circuit shown in FIG. 31 when emitting light at a high grayscale and a low grayscale; FIG. 37 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 38 is a timing diagram of the pixel circuit shown in FIG. 37; FIG. 39 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 40 is a timing diagram of the pixel circuit shown in FIG. 39; FIG. 41A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in a first reset time period S11; FIG. 41B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in the first writing-in time period S12; FIG. 41C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in the first light emitting time period S13; FIG. 41D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in a second writing-in time period S22; FIG. 41E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 39 in the second light emitting time period S23; FIG. 42A is a schematic diagram showing simulation results of a high grayscale display of the pixel circuit shown in FIG. 39; FIG. 42B is a schematic diagram showing simulation results of low grayscale display of the pixel circuit shown in FIG. 39; FIG. 43A is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 43B is a first timing diagram of the pixel circuit shown in FIG. 43A of the present disclosure; FIG. 43C is a second timing diagram of the pixel circuit shown in FIG. 43A of the present disclosure; FIG. 44 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 45A is a first timing diagram of the pixel circuit shown in FIG. 44; FIG. 45B is a timing diagram of the pixel circuit shown in FIG. 44; FIG. 46 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 47A is a first timing diagram of the pixel circuit shown in FIG. 46 of the present disclosure; FIG. 47B is a second timing diagram of the pixel circuit shown in FIG. 46 of the present disclosure; FIG. 48A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 46 in a first reset time period S11; FIG. 48B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 46 in the first writing-in time period S12; FIG. 48C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 46 in the first light emitting time period S13; FIG. 48D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 46 in the second writing-in time period S22; FIG. 48E is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the second light emitting time period S23; FIG. 49 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 50A is a first timing diagram of the pixel circuit shown in FIG. 49; FIG. 50B is a second timing diagram of the pixel circuit shown in FIG. 49; FIG. 51 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 52 is a timing diagram of the pixel circuit shown in FIG. 51; FIG. 53A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 in the first writing-in time period S12 and the first light emitting time period S22; FIG. 53B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 in a second writing-in time period S21 and a second light emitting time period S22; FIG. 53C is a schematic diagram of the working state of the pixel circuit shown in FIG. 51 during a reset time period SC1; FIG. 53D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 during the compensation time period SC2; FIG. 53E is a schematic diagram of the working state of the pixel circuit shown in FIG. 51 during the extraction time period SC3; FIG. 54A is a schematic diagram showing simulation results of high grayscale display in a display phase of the pixel circuit shown in FIG. 51; FIG. 54B is a schematic diagram of simulation results of performing low grayscale display in the display phase of the pixel circuit shown in FIG. 51; FIG. 55 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 56 is a timing diagram of the pixel circuit shown in FIG. 55; FIG. 57 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 58 is a timing diagram of the pixel circuit shown in FIG. 57; FIG. 59 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 60 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 61 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 62 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 63 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 64 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 65 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 66 is a timing diagram of the pixel circuit shown in FIG. 65; FIG. 67A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 in a first reset time period; FIG. 67B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 during a first writing-in time period; FIG. 67C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 in the first light emitting time period; FIG. 67D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 in a second reset time period; FIG. 67E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 during a second writing-in time period; FIG. 67F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 65 in the second light emitting time period; FIG. 68A is a schematic diagram showing simulation results of a the pixel circuit shown in FIG. 66 when performing high grayscale display; FIG. 68B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 66 when performing low grayscale display; FIG. 69 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 70 is a timing diagram of the pixel circuit shown in FIG. 69; FIG. 71 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 72 is a timing diagram of the pixel circuit shown in FIG. 71; FIG. 73A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 71 when performing high grayscale display; FIG. 73B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 71 when performing low grayscale display; FIG. 74 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 75 is a timing diagram of the pixel circuit shown in FIG. 74; FIG. 76A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 in a first reset time period; FIG. 76B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 during a first writing-in time period; FIG. 76C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 in the first light emitting time period; FIG. 76D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 in a second reset time period; FIG. 76E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 during a second writing-in time period; FIG. 76F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 74 in the second light emitting time period; FIG. 77A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 74 when performing high grayscale display; FIG. 77B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 74 when performing low grayscale display; FIG. 78 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 79 is a timing diagram of the pixel circuit shown in FIG. 78; FIG. 80 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 81 is a timing diagram of the pixel circuit shown in FIG. 80; FIG. 82 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 83 is a timing diagram of the pixel circuit shown in FIG. 82; FIG. 84A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 83 when performing high grayscale display; FIG. 84B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 83 when performing low grayscale display; FIG. 85 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 86 is a first timing diagram of the pixel circuit shown in FIG. 85; FIG. 87 is a second timing diagram of the pixel circuit shown in FIG. 85; FIG. 88 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 89 is a first timing diagram of the pixel circuit shown in FIG. 88; FIG. 90 is a second timing diagram of the pixel circuit shown in FIG. 88; FIG. 91A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in a first reset time period S11; FIG. 91B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in the first writing-in time period S12; FIG. 91C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in the first light emitting time period S13; FIG. 91D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in the second writing-in time period S22; FIG. 91E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 88 in the second light emitting time period S23; FIG. 92 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 93 is a first timing diagram of the pixel circuit shown in FIG. 92; FIG. 94 is a second timing diagram of the pixel circuit shown in FIG. 92; FIG. 95 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 96 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 97 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 98 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 99 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 100 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 101 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 102 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 103 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 104 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 105 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 106 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 107 is a timing diagram of the pixel circuit shown in FIG. 106; FIG. 108A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in a first reset time period; FIG. 108B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in the first writing-in time period; FIG. 108C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in the first light emitting time period; FIG. 108D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in a second reset time period; FIG. 108E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 during a second writing-in time period; FIG. 108F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 106 in a second light emitting time period; FIG. 109A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 106 of the present disclosure when performing a low grayscale display; FIG. 109B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 106 of the present disclosure when performing a high grayscale display; FIG. 110 is a timing diagram of the pixel circuit shown in FIG. 106; FIG. 111 is a schematic diagram of the light emitting time of the pixel circuit shown in FIG. 106 when emitting light at a high grayscale and at a low grayscale; FIG. 112 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 113 is a timing diagram of the pixel circuit shown in FIG. 112; FIG. 114 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 115A is a timing diagram of the pixel circuit shown in FIG. 114; FIG. 115B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 114 when performing high grayscale display; FIG. 115C is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 114 when performing high grayscale display; FIG. 116 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 117 is a timing diagram of the pixel circuit shown in FIG. 116; FIG. 118 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 119 is a timing diagram of the pixel circuit shown in FIG. 118; FIG. 120A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 in a first reset time period; FIG. 120B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 in a first writing-in time period; FIG. 120C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 in the first light emitting time period; FIG. 120D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 during a second writing-in time period; FIG. 120E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 118 in the second light emitting time period; FIG. 121A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 118 when performing high grayscale display; FIG. 121B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 118 when performing low grayscale display; FIG. 122 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 123 is a timing diagram of the pixel circuit shown in FIG. 122; FIG. 124A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in a first reset time period S11; FIG. 124B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in the first writing-in time period S12; FIG. 124C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in the first light emitting time period S13; FIG. 124D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in the second writing-in time period S22; FIG. 124E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 122 in the second light emitting time period S23; FIG. 125A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 122 when performing high grayscale display; FIG. 125B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 122 when performing low grayscale display; FIG. 126 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 127 is a timing diagram of the pixel circuit shown in FIG. 126; FIG. 128 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 129 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 130 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 131 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 132 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 133 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 134 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 135 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 136 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 137 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 138 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 139 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 140 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 141 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 142 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 143 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 144 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 145 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 146 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 147 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 148 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 149 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 150 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 151 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 152 is a timing diagram of the pixel circuit shown in FIG. 151; FIG. 153A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 in a first reset time period; FIG. 153B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 during a first compensation time period; FIG. 153C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 during a first writing-in time period; FIG. 153D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 in a second reset time period; FIG. 153E is a schematic diagram of the working state of the pixel circuit shown in FIG. 151 in the first light emitting time period; FIG. 153F is a schematic diagram of the working state of the pixel circuit shown in FIG. 151 in a third reset time period; FIG. 153G is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 during a second compensation time period; FIG. 153H is a schematic diagram showing the working state of the pixel circuit shown in FIG. 151 during a second writing-in time period; FIG. 153I is a schematic diagram of the working state of the pixel circuit shown in FIG. 151 in a fourth reset time period; FIG. 153J is a schematic diagram of the working state of the pixel circuit shown in FIG. 151 in the second light emitting time period; FIG. 154A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 151 of the present disclosure when performing high grayscale display; FIG. 154B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 151 of the present disclosure when performing low grayscale display; FIG. 155 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 156 is a timing diagram of the pixel circuit shown in FIG. 155; FIG. 157 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 158 is a timing diagram of the pixel circuit shown in FIG. 157; FIG. 159 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 160 is a timing diagram of the pixel circuit shown in FIG. 159; FIG. 161 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 162 is a timing diagram of the pixel circuit shown in FIG. 161; FIG. 163 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 164 is a timing diagram of the pixel circuit shown in FIG. 163; FIG. 165 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 166 is a timing diagram of the pixel circuit shown in FIG. 165; FIG. 167 is a timing diagram of the pixel circuit shown in FIG. 165; FIG. 168 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 169 is a first timing diagram of the pixel circuit shown in FIG. 168; FIG. 170 is a second timing diagram of the pixel circuit shown in FIG. 168; FIG. 171 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 172 is a timing diagram of the pixel circuit shown in FIG. 171; FIG. 173A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 in a first reset time period; FIG. 173B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 during a first compensation time period; FIG. 173C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 during a first writing-in time period; FIG. 173D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 in the first light emitting time period; FIG. 173E is a schematic diagram of the working state of the pixel circuit shown in FIG. 171 during a second reset time period; FIG. 173F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 during a second compensation time period; FIG. 173G is a schematic diagram of the working state of the pixel circuit shown in FIG. 171 during a second writing-in time period; FIG. 173H is a schematic diagram showing the working state of the pixel circuit shown in FIG. 171 in the second light emitting time period; FIG. 174A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 171 when performing high grayscale display; FIG. 174B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 171 when performing low grayscale display; FIG. 175 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 176 is a timing diagram of the pixel circuit shown in FIG. 175 of the present disclosure; FIG. 177 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 178 is a timing diagram of the pixel circuit shown in FIG. 177 of the present disclosure; FIG. 179 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 180 is a first timing diagram of the pixel circuit shown in FIG. 179 of the present disclosure; FIG. 181 is a second timing diagram of the pixel circuit shown in FIG. 179 of the present disclosure; FIG. 182 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 183 is a first timing diagram of the pixel circuit shown in FIG. 182 of the present disclosure; FIG. 184 is a second timing diagram of the pixel circuit shown in FIG. 182 of the present disclosure; FIG. 185 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 186 is a timing diagram of the pixel circuit shown in FIG. 185; FIG. 187A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 in a first reset time period; FIG. 187B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 during a first compensation time period; FIG. 187C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 in the first light emitting time period; FIG. 187D is a schematic diagram of the working state of the pixel circuit shown in FIG. 185 in a third reset time period; FIG. 187E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 during a second compensation time period; FIG. 187F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 185 in the second light emitting time period; FIG. 188A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 185 when performing high grayscale display; FIG. 188B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 185 when performing low grayscale display; FIG. 189 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 190 is a timing diagram of the pixel circuit shown in FIG. 189 of the present disclosure; FIG. 191 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 192 is a timing diagram of the pixel circuit shown in FIG. 191 of the present disclosure; FIG. 193 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 194 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 195 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 196 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 197 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 198 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 199 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 200 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 201 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 202 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 203 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 204 is a timing diagram of the pixel circuit shown in FIG. 203; FIG. 205A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 in a first writing-in time period; FIG. 205B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 in the first light emitting time period; FIG. 205C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 during a second writing-in time period; FIG. 205D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 in the second light emitting time period; FIG. 205E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 during a sensing reset time period; FIG. 205F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 203 during a compensation time period; FIG. 205G is a schematic diagram of the working state of the pixel circuit shown in FIG. 203 during an extraction time period; FIG. 206A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 203 when performing high grayscale display; FIG. 206B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 203 when performing low grayscale display; FIG. 207 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 208 is a timing diagram of the pixel circuit shown in FIG. 207; FIG. 209A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 in a first writing-in time period; FIG. 209B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 in the first light emitting time period; FIG. 209C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 during a second writing-in time period; FIG. 209D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 in the second light emitting time period; FIG. 209E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 during a sensing reset time period; FIG. 209F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 during a compensation time period; FIG. 209G is a schematic diagram showing the working state of the pixel circuit shown in FIG. 207 during an extraction time period; FIG. 210A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 207 when performing high grayscale display; FIG. 210B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 207 when performing low grayscale display; FIG. 211 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 212 is a timing diagram of the pixel circuit shown in FIG. 211; FIG. 213A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 211 when performing high grayscale display; FIG. 213B is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 211 when performing low grayscale display; FIG. 214 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 215 is a timing diagram of the pixel circuit shown in FIG. 214; FIG. 216 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 217 is a timing diagram of the pixel circuit shown in FIG. 216; FIG. 218 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 219 is a timing diagram of the pixel circuit shown in FIG. 218; FIG. 220 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 221 is a timing diagram of the pixel circuit shown in FIG. 220; FIG. 222 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 223 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 224 is a timing diagram of the pixel circuit shown in FIG. 223; FIG. 225 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 226 is a timing diagram of the pixel circuit shown in FIG. 225; FIG. 227 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 228 is a timing diagram of the pixel circuit shown in FIG. 227; FIG. 229A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 during a first writing-in time period; FIG. 229B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 in the first light emitting time period; FIG. 229C is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 during a second writing-in time period; FIG. 229D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 in the second light emitting time period; FIG. 229E is a schematic diagram of the working state of the pixel circuit shown in FIG. 227 during a sensing reset time period; FIG. 229F is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 during a compensation time period; FIG. 229G is a schematic diagram showing the working state of the pixel circuit shown in FIG. 227 during an extraction time period; FIG. 230 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure; FIG. 231 is a circuit diagram of a pixel circuit described in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present disclosure.

[0032] The transistors used in all embodiments of the present disclosure may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiment of the present disclosure, in order to distinguish the two electrodes of the transistor except the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode.

[0033] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode. The pixel circuit described in the embodiment of the present disclosure includes a driving circuit, a switch control circuit, a light emitting element, a driving control circuit and a first reset circuit; a control terminal of the driving circuit is electrically connected to a first node, and is configured to generate a driving current to drive the light emitting element under the control of a potential of the first node; The driving circuit is electrically connected to the light emitting element or a first voltage terminal through the switch control circuit, and the switch control circuit is electrically connected to a switch control terminal, and the switch control circuit is configured to control the connection between the driving circuit and the light emitting element or the first voltage terminal under the control of a potential of the switch control terminal; The driving control circuit is electrically connected to a first control terminal and a first data line respectively, and is configured to write a light emitting time control data voltage provided by the first data line into the switch control terminal under the control of a first control signal provided by the first control terminal; The first reset circuit is configured to write a set voltage into a second node, a first electrode of the light emitting element or a second electrode of the light emitting element under the control of a set control signal provided by a set control terminal.

[0034] In at least one embodiment of the present disclosure, the pixel circuit may include a driving circuit, a switch control circuit, a light emitting element, a driving control circuit and a first reset circuit; the driving control circuit writes a light emitting time control data voltage into the switch control terminal under the control of a first control signal; the first reset circuit writes a set voltage into a second node, a first electrode of the light emitting element or a second electrode of the light emitting element under the control of a set control signal, so as to initialize the potential of the second node, the potential of the first electrode of the light emitting element or the potential of the second electrode of the light emitting element before the light emitting phase; At least one embodiment of the present disclosure writes a light emitting time control data voltage into a switch control terminal through the driving control circuit in a second data writing-in time period included in a second display phase arranged after the first display phase, so as to control the light emitting time of the light emitting element according to the light emitting time control data voltage during the light emitting time period included in the second display phase, so as to delay writing-in the light emitting time control data voltage into the pixel circuit, control the pixel circuit with a driving current + light emitting time, and improve the display effect of the light emitting element.

[0035] Optionally, the light emitting element is an inorganic light emitting diode, a width-to-length ratio of a transistor included in the switch control circuit is greater than 1, and a width-to-length ratio of a transistor included in the driving circuit is greater than 0.5.

[0036] In at least one embodiment of the present disclosure, the light emitting element may be an inorganic light emitting diode, for example, the light emitting element may be a micro light emitting diode or a mini light emitting diode.

[0037] In a specific implementation, when the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the driving transistor included in the driving circuit is greater than 0.5, and the width-to-length ratio of the transistor included in the switch control circuit is greater than 1.

[0038] Optionally, the light emitting element may also be an organic light emitting diode.

[0039] In at least one embodiment of the present disclosure, the width-to-length ratio of a transistor is a ratio of a channel width W to a channel length L of the transistor.

[0040] In at least one embodiment of the present disclosure, the set voltage may be a reference voltage, a first initial voltage, or a second initial voltage, but is not limited thereto.

[0041] Optionally, the set control terminal may be a reset control terminal, but is not limited thereto.

[0042] Optionally, the light emitting element may be an OLED (organic light emitting diode), a Mini LED (mini light emitting diode) or a Micro-LED (micro light emitting diode), but is not limited thereto.

[0043] Optionally, the first electrode of the light emitting element may be an anode, and the second electrode of the light emitting element may be a cathode. Optionally, the pixel circuit described in at least one embodiment of the present disclosure further includes an energy storage circuit; The first terminal of the energy storage circuit is electrically connected to the first node, the second terminal of the energy storage circuit is electrically connected to the second node, and the energy storage circuit is configured to store electrical energy; The first reset circuit is configured to write a set voltage into the second node under the control of the set control signal.

[0044] Optionally, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal, but is not limited thereto.

[0045] In at least one embodiment of the present disclosure, the energy storage circuit may include a storage capacitor; the light emitting element may be an inorganic light emitting diode; The capacitance value of the storage capacitor is greater than 3 times the gate-source capacitance of the transistor in the driving circuit. In a specific implementation, the capacitance value of the storage capacitor is set to be greater than 3 times the gate-source capacitance of the transistor in the driving circuit, so that when the source potential of the transistor in the driving circuit changes, the potential of the gate electrode of the transistor in the driving circuit can be maintained to ensure display accuracy.

[0046] In at least one embodiment of the present disclosure, the gate-source capacitance of the transistor in the driving circuit may be a parasitic capacitance between the gate electrode and the source electrode of the transistor in the driving circuit, which may be calculated based on the facing area of the gate electrode and the source electrode of the transistor in the driving circuit, and a dielectric constant, wherein the dielectric constant may be calculated based on the material and thickness of the insulating layer between the gate electrode and the source electrode of the transistor in the driving circuit. As shown in FIG. 1, the pixel circuit described in the embodiment of the present disclosure includes an energy storage circuit 10, a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13 and a first reset circuit 14; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving circuit 11 is electrically connected to the first electrode of the light emitting element E1 through the switch control circuit 12; The first terminal of the driving circuit 11 is electrically connected to the first voltage terminal V1; The switch control circuit 12 is electrically connected to the switch control terminal N4, the second terminal of the driving circuit 11 and the first electrode of the light emitting element E1 respectively. The switch control circuit is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the reference voltage terminal and the second node N2 respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the reset control signal provided by the first reset control terminal RST1;

[0047] The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, and the second terminal of the energy storage circuit 10 is electrically connected to the second node N2. The energy storage circuit 10 is configured to store electrical energy. As shown in FIG. 2, the pixel circuit described in the embodiment of the present disclosure includes a storage circuit 10, a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13 and a first reset circuit 14; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving circuit 11 is electrically connected to the second electrode of the light emitting element E1 through the switch control circuit 12; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The switch control circuit 12 is electrically connected to the switch control terminal N4, the first terminal of the driving circuit 11 and the second electrode of the light emitting element E1 respectively, and the switch control circuit 12 is configured to control the connection between the first terminal of the driving circuit 11 and the second electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the reference voltage terminal and the second node N2 respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the first reset control signal provided by the first reset control terminal RST1;

[0048] The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, and the second terminal of the energy storage circuit 10 is electrically connected to the second node N2. The energy storage circuit 10 is configured to store electrical energy. As shown in FIG. 3, the pixel circuit described in the embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13 and a first reset circuit 14; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving circuit 11 is electrically connected to the first voltage terminal V1 through the switch control circuit 12; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4, the first terminal of the switch control circuit 12 is electrically connected to the first voltage terminal V1, the second terminal of the switch control circuit 12 is electrically connected to the first terminal of the driving circuit 11, and the switch control circuit 12 is configured to control the connection between the first voltage terminal V1 and the first terminal of the driving circuit 11 under the control of the potential of the switch control terminal N4; The second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the first selection control terminal X1, the scanning terminal G1, the reference voltage terminal and the first electrode of the light emitting element E1, respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the first selection control signal provided by the first selection control terminal X1 and the scanning signal provided by the scanning terminal G1;

[0049] The first electrode of the light emitting element E1 is electrically connected to the second node N2. As shown in FIG. 4, the pixel circuit described in the embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13 and a first reset circuit 14; The first terminal of the driving circuit 11 is electrically connected to the first voltage terminal; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4, the first terminal of the switch control circuit 12 is electrically connected to the second terminal of the driving circuit 11, the second terminal of the switch control circuit 12 is electrically connected to the first electrode of the light emitting element E1, and the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; The switch control circuit 12 is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the first selection control terminal X1, the scanning terminal G1, the reference voltage terminal and the first electrode of the light emitting element E1, respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the first selection control signal provided by the first selection control terminal X1 and the scanning signal provided by the scanning terminal G1;

[0050] The first electrode of the light emitting element E1 is electrically connected to the second node. In at least one embodiment of the present disclosure, the driving circuit is electrically connected to the first electrode of the light emitting element through the switch control circuit, and the switch control circuit is configured to control the connection between the driving circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; the second electrode of the light emitting element is electrically connected to the second voltage terminal;

[0051] The first reset circuit is configured to write a set voltage into the first electrode of the light emitting element under the control of the set control signal during a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage.

[0052] In a specific implementation, the driving circuit can be electrically connected to the first electrode of the light emitting element through the switch control circuit. At this time, the first reset circuit can write the set voltage into the first electrode of the light emitting element under the control of the set control signal during the reset time period, so as to initialize the potential of the first electrode of the light emitting element before emitting light in each display cycle, clear the residual charge in the first electrode of the light emitting element, and improve the flicker phenomenon.

[0053] In at least one embodiment of the present disclosure, when the potential of the first electrode of the light emitting element is initialized, the light emitting element does not emit light. When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase which are set in sequence; the first display phase may include a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase may include a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence; In the first reset time period and the second reset time period, the first reset circuit writes a set voltage into the first electrode of the light emitting element under the control of the set control signal; In a first writing-in time period, writing-in a display data voltage; In the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage; In the second writing-in time period, writing-in the light emitting time control data voltage; In the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to control whether the light emitting element emits light.

[0054] The reset time period provided between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage may be the second reset time period. Optionally, the first electrode of the light emitting element is electrically connected to the first voltage terminal; The driving circuit is electrically connected to the second electrode of the light emitting element through the switch control circuit, and the switch control circuit is configured to control the connection between the driving circuit and the first voltage terminal under the control of the potential of the switch control terminal;

[0055] The first reset circuit is configured to write a set voltage into the second electrode of the light emitting element under the control of the set control signal.

[0056] In a specific implementation, the first electrode of the light emitting element can be electrically connected to the first voltage terminal, and the driving circuit can be electrically connected to the second electrode of the light emitting element through the switch control circuit. At this time, the first reset circuit can write the set voltage into the second electrode of the light emitting element under the control of the set control signal during the reset time period, so as to initialize the potential of the second electrode of the light emitting element before emitting light in each display cycle, clear the residual charge at the second electrode of the light emitting element, and improve the flicker phenomenon.

[0057] In at least one embodiment of the present disclosure, when the potential of the second electrode of the light emitting element is initialized, the light emitting element does not emit light.

[0058] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase which are set in sequence; the first display phase may include a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase may include a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence. In the first reset time period and the second reset time period, the first reset circuit writes a set voltage into the second electrode of the light emitting element under the control of the set control signal; In a first writing-in time period, writing-in a display data voltage; In the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage; In the second writing-in time period, writing-in the light emitting time control data voltage; In the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to control whether the light emitting element emits light.

[0059] The reset time period provided between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage may be the second reset time period. In at least one embodiment of the present disclosure, the pixel circuit further includes an energy storage circuit; The first terminal of the energy storage circuit is electrically connected to the first node, the second terminal of the energy storage circuit is electrically connected to the first electrode of the light emitting element, and the energy storage circuit is configured to store electrical energy; The first terminal of the switch control circuit is electrically connected to the first voltage terminal, the second terminal of the switch control circuit is electrically connected to the first terminal of the driving circuit, the second terminal of the driving circuit is electrically connected to the first electrode of the light emitting element, and the second electrode of the light emitting element is electrically connected to the second voltage terminal; the switch control circuit is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the potential of the switch control terminal; or the first terminal of the driving circuit is electrically connected to the first voltage terminal; the first terminal of the switch control circuit is electrically connected to the second terminal of the driving circuit, the second terminal of the switch control circuit is electrically connected to the first electrode of the light emitting element, and the second terminal of the light emitting element is electrically connected to the second voltage terminal; the switch control circuit is configured to control the connection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scanning terminal and a first selection control terminal; The compensation circuit is electrically connected to the scanning terminal, the first electrode of the light emitting element and the control node respectively, and is configured to control the first electrode of the light emitting element to be connected to the control node under the control of the scanning signal provided by the scanning terminal; or, the compensation circuit is electrically connected to the scanning terminal, the second terminal of the driving circuit and the control node respectively, and is configured to control the second terminal of the driving circuit to be connected to the control node under the control of the scanning signal;

[0060] The switch circuit is connected to the first selection control terminal, the control node and the set voltage terminal respectively, and is configured to provide the set voltage written by the set voltage terminal provided to the control node under the control of the first selection control signal provided by the first selection control terminal. As shown in FIG. 5, based on the pixel circuit shown in FIG. 3, the pixel circuit further includes a storage circuit 10 and a first reset circuit; The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, the second terminal of the energy storage circuit 10 is electrically connected to the first electrode of the light emitting element E1, and the energy storage circuit 10 is configured to store electrical energy; The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scanning terminal G1 and a first selection control terminal X1; The compensation circuit 21 is electrically connected to the scanning terminal G1, the first electrode of the light emitting element E1 and the control node N0 respectively, and is configured to control the connection between the first electrode of the light emitting element E1 and the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0061] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is configured to provide the reference voltage Vref written by the reference voltage terminal to the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1. As shown in FIG. 6, based on the pixel circuit shown in FIG. 4, the pixel circuit further includes a storage circuit 10 and a first reset circuit; The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, the second terminal of the energy storage circuit 10 is electrically connected to the first electrode of the light emitting element E1, and the energy storage circuit 10 is configured to store electrical energy; The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scanning terminal G1 and a first selection control terminal X1; The compensation circuit 21 is electrically connected to the scanning terminal G1, the first electrode of the light emitting element E1 and the control node N0 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0062] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is configured to provide the reference voltage Vref provided by the reference voltage terminal to the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1. In at least one embodiment of the present disclosure, the pixel circuit further includes an energy storage circuit; a first terminal of the energy storage circuit is electrically connected to the first node, a second terminal of the energy storage circuit is electrically connected to the second electrode of the light emitting element, and the energy storage circuit is configured to store electrical energy; the first electrode of the light emitting element is electrically connected to the first voltage terminal, the first terminal of the switch control circuit is electrically connected to the second electrode of the light emitting element, the second terminal of the switch control circuit is electrically connected to the first terminal of the driving circuit, and the second terminal of the driving circuit is electrically connected to the second voltage terminal; the switch control circuit is configured to control the second electrode of the light emitting element to be connected to the first terminal of the driving circuit under the control of the potential of the switch control terminal; or the first electrode of the light emitting element is electrically connected to the first voltage terminal, and the second electrode of the light emitting element is electrically connected to the first terminal of the driving circuit; the first terminal of the switch control circuit is electrically connected to the second terminal of the driving circuit, and the second terminal of the switch control circuit is electrically connected to the second voltage terminal; the switch control circuit is configured to control the second terminal of the driving circuit to be connected to the first electrode of the light emitting element under the control of the potential of the switch control terminal; The first reset circuit includes a compensation circuit and a switch circuit; the set control terminal includes a scanning terminal and a first selection control terminal; The compensation circuit is electrically connected to the scanning terminal, the second electrode of the light emitting element and the control node respectively, and is configured to control the second electrode of the light emitting element to be connected to the control node under the control of the scanning signal; or the compensation circuit is electrically connected to the scanning terminal, the first terminal of the driving circuit and the control node respectively, and is configured to control the first terminal of the driving circuit to be connected to the control node under the control of the scanning signal;

[0063] The switch circuit is connected to the first selection control terminal, the control node and the set voltage terminal respectively, and is configured to write the set voltage provided by the set voltage terminal to the control node under the control of the first selection control signal provided by the first selection control terminal. As shown in FIG. 7, the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13, an energy storage circuit 10 and a first reset circuit; The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, the second terminal of the energy storage circuit 10 is electrically connected to the second electrode of the light emitting element E1, and the energy storage circuit 10 is configured to store electric energy; the second electrode of the light emitting element E1 is electrically connected to the second node N2; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1, the first terminal of the switch control circuit 12 is electrically connected to the second electrode of the light emitting element E1, the second terminal of the switch control circuit 12 is electrically connected to the first terminal of the driving circuit 11, and the second terminal of the driving circuit 11 is electrically connected to the second voltage terminal V2; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the switch control circuit 12 is configured to control the second electrode of the light emitting element E1 to be connected to the first terminal of the driving circuit 11 under the control of the potential of the switch control terminal N4; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scanning terminal G1 and a first selection control terminal; The compensation circuit 21 is electrically connected to the scanning terminal G1, the second electrode of the light emitting element E1 and the control node N0 respectively, and is configured to control the second electrode of the light emitting element E1 to be connected to the control node N0 under the control of the scanning signal provided by the scanning terminal G1;

[0064] The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1. As shown in FIG. 8, the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13, a storage circuit 10 and a first reset circuit; The first terminal of the energy storage circuit 10 is electrically connected to the first node N1, the second terminal of the energy storage circuit 10 is electrically connected to the second electrode of the light emitting element E1, and the energy storage circuit 10 is configured to store electric energy; the second electrode of the light emitting element E1 is electrically connected to the second node N2; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1, and the second electrode of the light emitting element E1 is electrically connected to the first terminal of the driving circuit 11; the first terminal of the switch control circuit 12 is electrically connected to the second terminal of the driving circuit 11, and the second terminal of the switch control circuit 12 is electrically connected to the second voltage terminal V2; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the switch control circuit 12 is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The driving control circuit 13 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The first reset circuit includes a compensation circuit 21 and a switch circuit 22; the set control terminal includes a scanning terminal G1 and a first selection control terminal X1; The compensation circuit 21 is electrically connected to the scanning terminal G1, the second electrode of the light emitting element E1 and the control node N0 respectively, and is configured to control the connection between the first terminal of the driving circuit 11 and the control node N0 under the control of the scanning signal provided by the scanning terminal G1; The switch circuit 22 is connected to the first selection control terminal X1, the control node N0 and the reference voltage terminal respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the control node N0 under the control of the first selection control signal provided by the first selection control terminal X1.

[0065] In at least one embodiment of the present disclosure, the driving control circuit is also electrically connected to the second control terminal and the second initial voltage terminal, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the switch control terminal under the control of a second control signal provided by the second control terminal, and to maintain the potential of the switch control terminal.

[0066] In a specific implementation, the driving control circuit may also write the second initial voltage into the switch control terminal and maintain the potential of the switch control terminal under the control of the second control signal.

[0067] As shown in FIG. 9, based on the pixel circuit shown in FIG. 1, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0068] As shown in FIG. 10, based on the pixel circuit shown in FIG. 2, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0069] As shown in FIG. 11, based on the pixel circuit shown in FIG. 5, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0070] As shown in FIG. 12, based on the pixel circuit shown in FIG. 6, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0071] As shown in FIG. 13, based on the pixel circuit shown in FIG. 7, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4.

[0072] As shown in FIG. 14, based on the pixel circuit shown in FIG. 8, the driving control circuit 12 is also electrically connected to the second control terminal GA and the second initial voltage terminal I2, respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA, and to maintain the potential of the switch control terminal N4. Optionally, the first terminal of the driving circuit is electrically connected to the first voltage terminal; The switch control circuit is electrically connected to the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and the second electrode of the light emitting element is electrically connected to the second voltage terminal; The switch control circuit is configured to control the connection between the second terminal of the driving circuit and the first terminal of the light emitting element under the control of the potential of the switch control terminal.

[0073] In a specific implementation, the switch control circuit can control the connection between the second terminal of the driving circuit and the first terminal of the light emitting element under the control of the potential of the switch control terminal. The pixel circuit described in at least one embodiment of the present disclosure further includes a light emitting control circuit and a compensation control circuit; The switch control circuit is electrically connected to the first electrode of the light emitting element through the light emitting control circuit; The light emitting control circuit is also electrically connected to the light emitting control terminal, and is configured to control the connection between the switch control circuit and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the second terminal of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0074] In a specific implementation, the pixel circuit may further include a light emitting control circuit and a compensation control circuit. The light emitting control circuit controls the switch control circuit to be connected to the first electrode of the light emitting element under the control of a light emitting control signal, to perform light emitting control; and the compensation control circuit controls the control terminal of the driving circuit to be connected to the second terminal of the driving circuit under the control of a scanning signal, to perform threshold voltage compensation.

[0075] Optionally, the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit is greater than 1, the width-to-length ratio of the transistor included in the light emitting control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0076] In a specific implementation, the light emitting element may be an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit may be greater than 1, the width-to-length ratio of the transistor included in the light emitting control circuit may be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5. As shown in FIG. 15, based on at least one embodiment of the driving circuit shown in FIG. 9, the pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting control circuit 31 and a compensation control circuit 32 (T5); The switch control circuit 12 is electrically connected to the first electrode of the light emitting element E1 through the light emitting control circuit 31; The light emitting control circuit E1 is also electrically connected to the light emitting control terminal EM, and is configured to control the connection between the switch control circuit 12 and the first electrode of the light emitting element E1 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0077] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the connection between the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1. In at least one embodiment of the present disclosure, the first electrode of the light emitting element is electrically connected to the first voltage terminal, the switch control circuit is electrically connected to the second electrode of the light emitting element and the first terminal of the driving circuit respectively, and the second terminal of the driving circuit is electrically connected to the second voltage terminal;

[0078] The switch control circuit is configured to control the connection between the second electrode of the light emitting element and the first terminal of the driving circuit under the control of the potential of the switch control terminal. The pixel circuit described in at least one embodiment of the present disclosure further includes a light emitting control circuit and a compensation control circuit; The switch control circuit is electrically connected to the first terminal of the driving circuit through the light emitting control circuit; The light emitting control circuit is also electrically connected to the light emitting control terminal, and is configured to control the connection between the switch control circuit and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the first terminal of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0079] In a specific implementation, the pixel circuit may further include a light emitting control circuit and a compensation control circuit. The light emitting control circuit controls the switch control circuit to be connected to the first terminal of the driving circuit under the control of a light emitting control signal, to perform light emitting control; the compensation control circuit controls the control terminal of the driving circuit to be connected to the first terminal of the driving circuit under the control of a scanning signal, to perform threshold voltage compensation. As shown in FIG. 16, based on at least one embodiment of the driving circuit shown in FIG. 10, the pixel circuit according to at least one embodiment of the present disclosure further includes a light emitting control circuit 31 and a compensation control circuit 32 (T5); The switch control circuit 12 is electrically connected to a first terminal of the driving circuit 11 through the light emitting control circuit 31; a second terminal of the driving circuit 11 is electrically connected to a second voltage terminal V2; The light emitting control circuit 31 is also electrically connected to the light emitting control terminal EM, and is configured to control the connection between the switch control circuit 12 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0080] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the connection between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1. The pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit and a first control circuit; The control terminal of the driving circuit is electrically connected to the first node; The display data writing-in circuit is electrically connected to the scanning terminal, the second data line and the second node respectively, and is configured to write the display data voltage provided by the second data line into the second node under the control of the scanning signal provided by the scanning terminal; The first control circuit is electrically connected to the light emitting control terminal, the reference voltage terminal and the second node respectively, and is configured to write the reference voltage provided by the reference voltage terminal into the second node under the control of the light emitting control signal provided by the light emitting control terminal.

[0081] In a specific implementation, the pixel circuit described in at least one embodiment of the present disclosure may also include a display data writing-in circuit and a first control circuit; the display data writing-in circuit writes the display data voltage provided by the second data line into the second node under the control of the scanning signal; the first control circuit writes the reference voltage into the second node under the control of the light emitting control signal. As shown in FIG. 17, based on the pixel circuit shown in FIG. 15, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41 and a first control circuit 42; The control terminal of the driving circuit 11 is electrically connected to the first node N1; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the second node N2 respectively, and is configured to write the display data voltage provided by the second data line DI into the second node N2 under the control of the scanning signal provided by the scanning terminal G1;

[0082] The first control circuit 42 is electrically connected to the light emitting control terminal EM, the reference voltage terminal and the second node N2 respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM. As shown in FIG. 18, based on the pixel circuit shown in FIG. 16, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41 and a first control circuit 42; The control terminal of the driving circuit 11 is electrically connected to the first node N1; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the second node N2 respectively, and is configured to write the display data voltage provided by the second data line DI into the second node N2 under the control of the scanning signal provided by the scanning terminal G1;

[0083] The first control circuit 42 is electrically connected to the light emitting control terminal EM, the reference voltage terminal and the second node N2 respectively, and is configured to write the reference voltage Vref provided by the reference voltage terminal into the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM. The pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit;

[0084] The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal.

[0085] In a specific implementation, the pixel circuit may further include a second reset circuit; the second reset circuit writes a first initial voltage into the first node under the control of the first reset control signal. As shown in FIG. 19, based on the pixel circuit shown in FIG. 17, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit 51;

[0086] The second reset circuit 51 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal. As shown in FIG. 20, based on the pixel circuit shown in FIG. 19, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit 51;

[0087] The second reset circuit 51 is electrically connected to the first reset control terminal RST, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal. The pixel circuit described in at least one embodiment of the present disclosure further includes an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit, and a display data writing-in circuit; The first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit, the second terminal of the energy storage circuit is electrically connected to the first voltage terminal, and the energy storage circuit is configured to store electrical energy; The first terminal of the driving circuit is electrically connected to the first voltage terminal through the first light emitting control circuit; The second terminal of the driving circuit is electrically connected to the switch control circuit through the second light emitting control circuit; The first light emitting control circuit is also electrically connected to the light emitting control terminal, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is also electrically connected to the light emitting control terminal, and is configured to control the second terminal of the driving circuit to be connected to the switch control circuit under the control of the light emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the second terminal of the driving circuit respectively, and is configured to control the communication between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal; The display data writing-in circuit is electrically connected to the scanning terminal, the second data line and the first terminal of the driving circuit respectively, and is configured to write the display data voltage provided by the second data line into the first terminal of the driving circuit under the control of the scanning signal.

[0088] In a specific implementation, the pixel circuit may further include a storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit and a display data writing-in circuit; the first light emitting control circuit controls the first voltage terminal to be connected to the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be connected to the switch control circuit under the control of the light emitting control signal, to perform light emitting control; the compensation control circuit controls the control terminal of the driving circuit to be connected to the second terminal of the driving circuit under the control of a scanning signal, to perform threshold voltage compensation; the display data writing-in circuit writes the display data voltage provided by the second data line into the first terminal of the driving circuit under the control of the scanning signal, to perform display data voltage writing-in.

[0089] In at least one embodiment of the present disclosure, the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit is greater than 1, the width-to-length ratio of the transistor included in the first light emitting control circuit is greater than 1, the width-to-length ratio of the transistor included in the second light emitting control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0090] In a specific implementation, the light emitting element may be an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit may be greater than 1, the width-to-length ratio of the transistor included in the first light emitting control circuit may be greater than 1, the width-to-length ratio of the transistor included in the second light emitting control circuit may be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5. As shown in FIG. 21, the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13, a first reset circuit 14, a storage circuit 10, a first light emitting control circuit 61, a second light emitting control circuit 62, a compensation control circuit 32, and a display data writing-in circuit 41; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The first reset circuit 14 is electrically connected to the first reset control terminal RST, the first initial voltage terminal I1 and the first electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first electrode of the light emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST; The first terminal of the energy storage circuit 10 is electrically connected to the control terminal of the driving circuit 11, the second terminal of the energy storage circuit 10 is electrically connected to the first voltage terminal V1, and the energy storage circuit 10 is configured to store electric energy; The first terminal of the driving circuit 11 is electrically connected to the first voltage terminal V1 through the first light emitting control circuit 61; The second terminal of the driving circuit 11 is electrically connected to the switch control circuit 12 through the second light emitting control circuit 62; The first light emitting control circuit 61 is also electrically connected to the light emitting control terminal EM, and is configured to control the connection between the first voltage terminal V1 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is also electrically connected to the light emitting control terminal EM, and is configured to control the second terminal of the driving circuit 11 to be connected to the switch control circuit 12 under the control of the light emitting control signal; The switch control circuit 12 is electrically connected to the switch control terminal N4, the second light emitting control circuit 62 and the first electrode of the light emitting element E1 respectively. The switch control circuit 12 is configured to control the second light emitting control circuit 62 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; The driving control circuit 13 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second initial voltage terminal I2 and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB, and write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the control terminal of the driving circuit 11 to communicate with the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0091] The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the first terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the scanning signal. In at least one embodiment of the present disclosure, the pixel circuit further includes an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit, and a display data writing-in circuit; The first terminal of the energy storage circuit is electrically connected to the control terminal of the driving circuit, the second terminal of the energy storage circuit is electrically connected to the second voltage terminal, and the energy storage circuit is configured to store electrical energy; The first light emitting control circuit is electrically connected to the light emitting control terminal, the switch control circuit and the first terminal of the driving circuit respectively, and is configured to control the connection between the switch control circuit and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the second voltage terminal respectively, and is configured to control the second terminal of the driving circuit to be electrically connected to the second voltage terminal under the control of the light emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the first terminal of the driving circuit respectively, and is configured to control the communication between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal; The display data writing-in circuit is electrically connected to the scanning terminal, the second data line and the second terminal of the driving circuit respectively, and is configured to write the display data voltage provided by the second data line into the second terminal of the driving circuit under the control of the scanning signal.

[0092] In a specific implementation, the pixel circuit may further include an energy storage circuit, a first light emitting control circuit, a second light emitting control circuit, a compensation control circuit and a display data writing-in circuit; the first light emitting control circuit controls the connection between the switch control circuit and the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be electrically connected to the first electrode of the light emitting element under the control of the light emitting control signal; the compensation control circuit controls the connection between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of a scanning signal; the display data writing-in circuit writes the display data voltage provided by the second data line into the second terminal of the driving circuit under the control of the scanning signal. As shown in FIG. 22, the pixel circuit according to at least one embodiment of the present disclosure includes a driving circuit 11, a switch control circuit 12, a light emitting element E1, a driving control circuit 13, a first reset circuit 14, an energy storage circuit 10, a first light emitting control circuit 61, a second light emitting control circuit 62, a compensation control circuit 32, and a display data writing-in circuit 41; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The switch control circuit 12 is electrically connected to the switch control terminal N4, the first light control circuit 61 and the second electrode of the light emitting element E1 respectively, and the switch control circuit 12 is configured to control the second electrode of the light emitting element E1 to be connected to the first light control circuit 61 under the control of the potential of the switch control terminal N4; The driving control circuit 13 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second initial voltage terminal I2 and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB, and write the second initial voltage provided by the second initial voltage terminal I2 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the second electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second electrode of the light emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST1, so as to clear the residual charge of the second electrode of the light emitting element E1; The first terminal of the energy storage circuit 10 is electrically connected to the control terminal of the driving circuit 11, the second terminal of the energy storage circuit 10 is electrically connected to the second voltage terminal V2, and the energy storage circuit 10 is configured to store electrical energy; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the switch control circuit 12 and the first terminal of the driving circuit 11 respectively, and is configured to control the connection between the switch control circuit 12 and the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the second voltage terminal V2 respectively, and is configured to control the second terminal of the driving circuit 11 to be electrically connected to the second voltage terminal V2 under the control of the light emitting control signal; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the connection between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0093] The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the second terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the scanning signal. The pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit; The second reset circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset control terminal.

[0094] In a specific implementation, the pixel circuit may further include a second reset circuit, and the second reset circuit writes the first initial voltage into the first node under the control of a reset control signal. As shown in FIG. 23, based on the pixel circuit shown in FIG. 21, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit 71;

[0095] The second reset circuit 71 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal RST1.

[0096] As shown in FIG. 24, based on the pixel circuit shown in FIG. 22, the pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit 71; The second reset circuit 71 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal RST1.

[0097] The pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit; The display data writing-in circuit is electrically connected to the scanning terminal, the second data line and the control terminal of the driving circuit respectively, and is configured to write the display data voltage provided by the second data line into the control terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0098] In at least one embodiment of the present disclosure, the switch circuit is also connected to a second selection control terminal and a compensation terminal, and is configured to control the connection between the control node and the compensation terminal under the control of a second selection control signal provided by the second selection control terminal.

[0099] In a specific implementation, the switch circuit can control the connection between the control node and the compensation terminal under the control of the second selection control signal to transmit the potential of the control node to the compensation terminal, so as to perform threshold voltage compensation according to the potential of the compensation terminal. As shown in FIG. 25, based on the pixel circuit shown in FIG. 5, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0100] The switch circuit 22 is also connected to the second selection control terminal X2 and the compensation terminal SENS respectively, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of the second selection control signal provided by the second selection control terminal X2. As shown in FIG. 26, based on the pixel circuit shown in FIG. 6, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0101] The switch circuit 22 is also connected to the second selection control terminal X2 and the compensation terminal SENS, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of a second selection control signal provided by the second selection control terminal X2. As shown in FIG. 27, based on the pixel circuit shown in FIG. 7, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0102] The switch circuit 22 is also connected to the second selection control terminal X2 and the compensation terminal SENS, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of a second selection control signal provided by the second selection control terminal X2. As shown in FIG. 28, based on the pixel circuit shown in FIG. 8, the pixel circuit described in at least one embodiment of the present disclosure further includes a display data writing-in circuit 41; The display data writing-in circuit 41 is electrically connected to the scanning terminal G1, the second data line DI and the control terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the control terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0103] The switch circuit 22 is also connected to the second selection control terminal X2 and the compensation terminal SENS, and is configured to control the connection between the control node N0 and the compensation terminal SENS under the control of a second selection control signal provided by the second selection control terminal X2. The pixel circuit described in at least one embodiment of the present disclosure may further include a third reset circuit;

[0104] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal and the first electrode of the light emitting element, respectively, and is configured to write the third initial voltage provided by the third initial voltage terminal into the first electrode of the light emitting element under the control of the reset control signal provided by the second reset control terminal during a reset time period set between a time period for writing-in the display data voltage and a time period for writing-in the light emitting time control data voltage. As shown in FIG. 29, based on the pixel circuit shown in FIG. 17, the pixel circuit described in at least one embodiment of the present disclosure may further include a third reset circuit 81;

[0105] The third reset circuit 81 is electrically connected to the second reset control terminal RST2, the third initial voltage terminal I3 and the first electrode of the light emitting element E1, respectively, and is configured to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the first electrode of the light emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RST2.

[0106] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase which are set in sequence; the first display phase may include a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase may include a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence. In the first reset time period and the second reset time period, the third reset circuit writes a third initial voltage into the first electrode of the light emitting element under the control of the second reset control signal; In a first writing-in time period, writing-in a display data voltage; In the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage; In the second writing-in time period, writing-in the light emitting time control data voltage;

[0107] In the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to control whether the light emitting element emits light.

[0108] The reset time period provided between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage may be the second reset time period. The pixel circuit described in at least one embodiment of the present disclosure may further include a third reset circuit;

[0109] The third reset circuit is electrically connected to the second reset control terminal, the third initial voltage terminal and the first electrode of the light emitting element, respectively, and is configured to write the third initial voltage provided by the third initial voltage terminal into the second electrode of the light emitting element under the control of the second reset control signal provided by the second reset control terminal during a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage.

[0110] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase which are set in sequence; the first display phase may include a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase may include a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence. In the first reset time period and the second reset time period, the third reset circuit writes a third initial voltage into the second electrode of the light emitting element under the control of the second reset control signal; In a first writing-in time period, writing-in a display data voltage; In the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage; In the second writing-in time period, writing-in the light emitting time control data voltage; In the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to control whether the light emitting element emits light.

[0111] The reset time period provided between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage may be the second reset time period. As shown in FIG. 30, based on the pixel circuit shown in FIG. 18, the pixel circuit described in at least one embodiment of the present disclosure may further include a third reset circuit 81;

[0112] The third reset circuit 81 is electrically connected to the second reset control terminal RST2, the third initial voltage terminal I3 and the second electrode of the light emitting element E1, respectively, and is configured to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the second electrode of the light emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RST2. Optionally, the driving control circuit includes a first transistor, a second transistor and a first capacitor; A gate electrode of the first transistor is electrically connected to the first control terminal, a first electrode of the first transistor is electrically connected to the first data line, and a second electrode of the first transistor is electrically connected to the switch control terminal; a gate electrode of the second transistor is electrically connected to the second control terminal, a first electrode of the second transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second transistor is electrically connected to the switch control terminal; a first terminal of the first capacitor is electrically connected to the switch control terminal, and a second terminal of the first capacitor is electrically connected to the DC voltage terminal.

[0113] In at least one embodiment of the present disclosure, the DC voltage terminal may be, for example, a common electrode voltage terminal, a ground terminal, a high voltage terminal or a low voltage terminal, but is not limited thereto.

[0114] Optionally, the driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor; a gate electrode of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the first voltage terminal, and a second electrode of the driving transistor is electrically connected to the third node; a gate electrode of the fourth transistor is electrically connected to the light emitting control terminal, a first electrode of the fourth transistor is electrically connected to the third node, and a second electrode of the fourth transistor is electrically connected to the first electrode of the third transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element; A gate electrode of the fifth transistor is electrically connected to the scanning terminal, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to a third node.

[0115] Optionally, the driving circuit includes a driving transistor, the switch control circuit includes a third transistor, the light emitting control circuit includes a fourth transistor, and the compensation control circuit includes a fifth transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the third transistor is electrically connected to a first electrode of the fourth transistor; a gate electrode of the fourth transistor is electrically connected to the light emitting control terminal, a second electrode of the fourth transistor is electrically connected to a first electrode of the driving transistor; a first electrode of the driving transistor is electrically connected to the third node; a gate electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the second voltage terminal; A gate electrode of the fifth transistor is electrically connected to the scanning terminal, a first electrode of the fifth transistor is electrically connected to the first node, and a second electrode of the fifth transistor is electrically connected to the third node.

[0116] Optionally, the display data writing-in circuit includes a sixth transistor, and the first control circuit includes a seventh transistor; a gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the second node; A gate electrode of the seventh transistor is electrically connected to the light emitting control terminal, a first electrode of the seventh transistor is electrically connected to the reference voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second node.

[0117] Optionally, the first reset circuit includes an eighth transistor; a gate electrode of the eighth transistor is electrically connected to the set control terminal, a first electrode of the eighth transistor is electrically connected to the set voltage terminal, and a second electrode of the eighth transistor is electrically connected to the second node, a first electrode of the light emitting element, or a second electrode of the light emitting element; The set voltage terminal is configured to provide the set voltage.

[0118] Optionally, the second reset circuit includes a ninth transistor, A gate electrode of the ninth transistor is electrically connected to the first reset control terminal, a first electrode of the ninth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the first node.

[0119] Optionally, the driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor, the first light emitting control circuit includes an eleventh transistor, the second light emitting control circuit includes a twelfth transistor, the switch control circuit includes a third transistor, the compensation control circuit includes a fifth transistor, and the display data writing-in circuit includes a sixth transistor; a first terminal of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the first voltage terminal; a gate electrode of the eleventh transistor is electrically connected to the light emitting control terminal, a first electrode of the eleventh transistor is electrically connected to the first voltage terminal, and a second electrode of the eleventh transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the twelfth transistor is electrically connected to the light emitting control terminal, a first electrode of the twelfth transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the twelfth transistor is electrically connected to the first electrode of the third transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element; a gate electrode of the fifth transistor is electrically connected to the scanning terminal, a first electrode of the fifth transistor is electrically connected to the gate electrode of the driving transistor, and a second electrode of the fifth transistor is electrically connected to the second electrode of the driving transistor; A gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to a first electrode of the driving transistor.

[0120] Optionally, the driving circuit includes a driving transistor; the energy storage circuit includes a storage capacitor, the first light emitting control circuit includes an eleventh transistor, the second light emitting control circuit includes a twelfth transistor, the switch control circuit includes a third transistor, the compensation control circuit includes a fifth transistor, and the display data writing-in circuit includes a sixth transistor; a first terminal of the storage capacitor is electrically connected to the gate electrode of the driving transistor, and a second terminal of the storage capacitor is electrically connected to the second voltage terminal; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the third transistor is electrically connected to a first electrode of the eleventh transistor; a gate electrode of the eleventh transistor is electrically connected to the light emitting control terminal, and a second electrode of the eleventh transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the twelfth transistor is electrically connected to the light emitting control terminal, a first electrode of the twelfth transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the twelfth transistor is electrically connected to the second voltage terminal; a gate electrode of the fifth transistor is electrically connected to the scanning terminal, a first electrode of the fifth transistor is electrically connected to the gate electrode of the driving transistor, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; A gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to a second electrode of the driving transistor.

[0121] Optionally, the second reset circuit includes a ninth transistor; A gate electrode of the ninth transistor is electrically connected to the first reset control terminal, a first electrode of the ninth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the first node.

[0122] Optionally, the third reset circuit includes a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the second reset control terminal, a first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the tenth transistor is electrically connected to the first electrode of the light emitting element.

[0123] Optionally, the third reset circuit includes a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the second reset control terminal, a first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the tenth transistor is electrically connected to the second electrode of the light emitting element.

[0124] Optionally, the switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the first electrode of the driving transistor;

[0125] The second electrode of the driving transistor is electrically connected to the first electrode of the light emitting element.

[0126] Optionally, the switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element;

[0127] The first electrode of the driving transistor is electrically connected to the first voltage terminal. Optionally, the switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the light emitting element, a second electrode of the third transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the driving transistor is electrically connected to the second voltage terminal.

[0128] Optionally, the switch control circuit includes a third transistor, and the driving circuit includes a driving transistor; the second electrode of the light emitting element is electrically connected to the first electrode of the driving transistor; a gate electrode of the third transistor is electrically connected to the switch control terminal, a first electrode of the third transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the third transistor is electrically connected to the first electrode of the light emitting element.

[0129] Optionally, the display data writing-in circuit includes a sixth transistor; A gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the second data line, and a second electrode of the sixth transistor is electrically connected to the control terminal of the driving circuit.

[0130] Optionally, the energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch; a first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the second terminal of the driving circuit; a gate electrode of the thirteenth transistor is electrically connected to the scanning terminal, a first electrode of the thirteenth transistor is electrically connected to the first electrode of the light emitting element or the second terminal of the driving circuit, and a second electrode of the thirteenth transistor is electrically connected to the control node; a control terminal of the first switch is electrically connected to the first selection control terminal, a first terminal of the first switch is electrically connected to the control node, and a second terminal of the first switch is electrically connected to the reference voltage terminal.

[0131] Optionally, the energy storage circuit includes a storage capacitor, the compensation circuit includes a thirteenth transistor, and the switch circuit includes a first switch; a first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the first terminal of the driving circuit; a gate electrode of the thirteenth transistor is electrically connected to the scanning terminal, a first electrode of the thirteenth transistor is electrically connected to the second electrode of the light emitting element or the first terminal of the driving circuit, and a second electrode of the thirteenth transistor is electrically connected to the control node; a control terminal of the first switch is electrically connected to the first selection control terminal, a first terminal of the first switch is electrically connected to the control node, and a second terminal of the first switch is electrically connected to the reference voltage terminal.

[0132] Optionally, the switch circuit further includes a second switch; a control terminal of the second switch is electrically connected to the second selection control terminal, a first terminal of the second switch is electrically connected to the control node, and a second terminal of the second switch is electrically connected to the compensation terminal.

[0133] As shown in FIG. 31, based on the pixel circuit shown in FIG. 17, the light emitting element is a light emitting diode E0; the cathode of the light emitting diode E0 is electrically connected to the low voltage terminal VSS; The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1; The gate electrode of the first transistor T1 is electrically connected to the first control terminal GB, the source electrode of the first transistor T1 is electrically connected to the first data line DT, and the drain electrode of the first transistor T1 is electrically connected to the switch control terminal N4; The gate electrode of the second transistor T2 is electrically connected to the second control terminal GA, the source electrode of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain electrode of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is configured to provide a second initial voltage Vi2; A first terminal of the first capacitor C1 is electrically connected to the switch control terminal N4, and a second terminal of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM; The driving circuit includes a driving transistor T0, the switch control circuit includes a third transistor T3, the light emitting control circuit includes a fourth transistor T4, and the compensation control circuit includes a fifth transistor T5; The gate electrode of the driving transistor T0 is electrically connected to the first node N1, the source electrode of the driving transistor T0 is electrically connected to the high voltage terminal VDD, and the drain electrode of the driving transistor T0 is electrically connected to the third node N3; The gate electrode of the fourth transistor T4 is electrically connected to the light emitting control terminal EM, the source electrode of the fourth transistor T4 is electrically connected to the third node N3, and the drain electrode of the fourth transistor T4 is electrically connected to the source electrode of the third transistor T3; The gate electrode of the third transistor T3 is electrically connected to the switch control terminal N4, and the drain electrode of the third transistor T3 is electrically connected to the anode of the light emitting diode E0; The gate electrode of the fifth transistor T5 is electrically connected to the scanning terminal G1, the source electrode of the fifth transistor T5 is electrically connected to the first node N1, and the drain electrode of the fifth transistor T5 is electrically connected to the third node N3; The display data writing-in circuit includes a sixth transistor T6, and the first control circuit includes a seventh transistor T7; The gate electrode of the sixth transistor T6 is electrically connected to the scanning terminal G1, the source electrode of the sixth transistor T6 is electrically connected to the second data line DI, and the drain electrode of the sixth transistor T6 is electrically connected to the second node N2; The gate electrode of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, the source electrode of the seventh transistor T7 is electrically connected to the reference voltage terminal, and the drain electrode of the seventh transistor T7 is electrically connected to the second node N2; the reference voltage terminal is configured to provide a reference voltage Vref; The first reset circuit comprises an eighth transistor T8; The gate electrode of the eighth transistor T8 is electrically connected to the first reset control terminal RST1, the source electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal, and the drain electrode of the eighth transistor T8 is electrically connected to the second node N2;

[0134] The second reset circuit comprises a ninth transistor T9, The gate electrode of the ninth transistor T9 is electrically connected to the first reset control terminal RST1, the source electrode of the ninth transistor T9 is electrically connected to the first initial voltage terminal I1, and the drain electrode of the ninth transistor T9 is electrically connected to the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vi1; The energy storage circuit includes a storage capacitor Cst; A first terminal of the storage capacitor Cst is electrically connected to the first node N1, and a second terminal of the storage capacitor Cst is electrically connected to the second node N2.

[0135] In the pixel circuit shown in FIG. 31, all transistors are p-type transistors, but the present invention is not limited thereto.

[0136] In the pixel circuit shown in FIG. 31, E0 may be OLED (organic light emitting diode), Mini LED (mini light emitting diode) or Micro LED (micro light emitting diode), but is not limited thereto.

[0137] When the pixel circuit shown in FIG. 31 of the present disclosure is working, the pixel circuit delays writing-in the light emitting time control data voltage provided by the first data line DT into the pixel circuit to realize PAM (pulse amplitude modulation) + PWM (pulse width modulation) pixel driving.

[0138] In the pixel circuit shown in FIG. 31 of the present disclosure, Vi1 is less than Vdd+Vth, and when the second initial voltage Vi2 is written into N4, T3 can be turned on; wherein Vdd is the voltage value of the high voltage signal provided by VDD, and Vth is the threshold voltage of T0.

[0139] The value of Vdata_I and the value of Vref need to satisfy the driving current of E0 while Vref is less than or equal to Vdata_I to achieve grayscale display; In high grayscale display, in a preferred case, Vdata_T is equal to Vdata_I; In low grayscale display, when Vdata_T is written into N4, T3 can be turned off.

[0140] As shown in FIG. 32, when the pixel circuit shown in FIG. 31 of the present disclosure is in operation, a display cycle (the display cycle may be a frame display time) includes a first display phase S1 and a second display phase S2 which are successively arranged; The first display phase S1 includes a first reset time period S11, a first writing-in time period S12 and a first light emitting time period S13 which are set successively; the second display phase S2 includes a second writing-in time period S22 and a second light emitting time period S23 which are set successively; In the first reset time period S11, RST provides a low voltage signal, as shown in FIG. 33A, T8 and T9 are turned on to write the reference voltage Vref into the second node N2, and write the first initial voltage Vi1 provided by I1 into the first node N1; In the first writing-in time period S12, G1 provides a low voltage signal, as shown in FIG. 33B, T6 is turned on, DI provides a display data voltage Vdata_I to the second node N2, and T5 is turned on; At the beginning of the first writing-in time period S12, T0 is turned on to charge Cst through Vdata_I until the first node N1 becomes Vdd+Vth, and T0 is turned off to perform threshold voltage compensation; Vth is the threshold voltage of T0, and Vdd is the voltage value of the high voltage signal provided by VDD; In the first writing-in time period S12, the voltage signal provided by GA, T2 is turned on to write the second initial voltage Vi2 into the fourth node N4, T3 is turned on; In the first light emitting time period S13, EM provides a low voltage signal, as shown in FIG. 33C, T7 and T4 are turned on, T3 is turned on, and T0 drivings E0 to emit light; In the first light emitting time period S13, the potential of N2 is Vref. Due to the capacitive coupling effect, the potential of N1 is Vdd+Vth+Vref-Vdata_I. The gate-source voltage Vgs of T0 is equal to Vth+Vref-Vdata_I. Id is equal to K×(Vref-Vdata_I) 2< ; K is the current coefficient of T0; Id is the driving current of T0 driving E0 to emit light.

[0141] In the second writing-in time period S22, the first time t1 is delayed (the first time t1 is the light emitting time required for the low grayscale), GB outputs a low voltage signal, as shown in FIG. 33D, T1 is turned on, and DT provides the light emitting time control data voltage Vdata_T to N4; t1 is the duration of the first light emitting time period S13;

[0142] FIG. 33E is a schematic diagram showing the working state of the pixel circuit shown in FIG. 31 in the second light emitting time period S23. When Vdata_T is a high voltage signal, in the second light emitting time period S23, T3 is turned off, E0 does not emit light, and a short-time light emitting is achieved, and the light emitting duration is t1; When Vdata_T is a low voltage signal, the optimal voltage value of Vdata_T is the same as the voltage value of Vi2, T3 is turned on, T0 drivings E0 to emit light, E0 continues to emit light, and long-term light emitting is achieved. The light emitting duration is t1+t2, t2 is the second time, and t2 is the duration of the second writing-in time period S22.

[0143] When the pixel circuit shown in FIG. 31 is working, the second control signal provided by GA can be the same as the scanning signal provided by G1, or the second control signal provided by GA can be the same as the reset control signal provided by RST, that is, the second initial voltage Vi2 can be written into N4 in the first reset time period S11 or the first writing-in time period S12, and GA can share the GOA (Gate On Array, a gate driving circuit arranged on the array substrate) circuit with G1 or RST; in addition, since Vi2 is a DC voltage signal, GA can also not use a shift register, and can be turned on for one frame of time to reset the potential of N4 of all pixel circuits at once.

[0144] FIG. 34A is a schematic diagram of simulation results of high grayscale display of the pixel circuit shown in FIG. 31; FIG. 34B is a schematic diagram of simulation results of low grayscale display of the pixel circuit shown in FIG. 31.

[0145] In at least one embodiment of the present disclosure, Id is the driving current generated at T0.

[0146] As shown in FIG. 34A, when displaying at a high gray scale, Vdd is equal to 4.6V, Vss is equal to -3V, Vi1 is equal to -3V, Vi2 is equal to -5V, Vdata_I is equal to 4V, Vref is equal to 2V, and Vdata_T is equal to -5V; wherein Vss is the voltage value of the low voltage signal provided by VSS;

[0147] As shown in FIG. 34B, in low grayscale display, Vdd is equal to 4.6V, Vss is equal to -3V, Vi1 is equal to -3V, Vi2 is equal to -5V, Vdata_I is equal to 4V, Vref is equal to 2V, and Vdata_T is equal to 5V. As shown in FIG. 35, when the pixel circuit shown in FIG. 31 is working, a display cycle (the display cycle may be one frame of time) may include a first display phase and n second display phases that are arranged in sequence; in a writing-in time period in the first display phase, DI writes a display data voltage, and in a second display phase, DT writes a light emitting time control data voltage; In FIG. 35, the first display phase is labeled S1, the first second display phase is labeled S01, the (n-1)th first display phase is labeled S0n-1, and the nth first display phase is labeled S0n; n is an integer greater than 2; The first display phase S1 includes a first reset time period S11, a first writing-in time period S12 and a first light emitting time period S13 which are arranged successively; The first second display phase S01 includes a first second writing-in time period S012 and a first second light emitting time period S013 which are successively arranged; The (n-1)th second display phase S0n-1 includes the (n-1)th second writing-in time period S0n-12 and the (n-1)th second light emitting time period S0n-13 which are arranged successively; The nth second display phase S0n includes an nth second writing-in time period S0n2 and an nth second light emitting time period S0n3 which are arranged successively; In the first reset time period S11, RST provides a low voltage signal, T8 and T9 are turned on to write the reference voltage Vref into the second node N2, and write the first initial voltage Vi1 provided by I1 into the first node N1; In the first writing-in time period S12, G1 provides a low voltage signal, T6 is turned on, DI provides a display data voltage Vdata_I to the second node N2, and T5 is turned on to charge Cst until the first node N1 becomes Vdd+Vth; Vth is the threshold voltage of T0, and Vdd is the voltage value of the high voltage signal provided by VDD; In the first writing-in time period S12, the voltage signal provided by GA, T2 is turned on to write the second initial voltage Vi2 into the fourth node N4, T3 is turned on; In the first light emitting time period S13, EM provides a low voltage signal, T7 and T4 are turned on, T3 is turned on, and T0 drivings E0 to emit light; In the first light emitting time period S13, the potential of N2 is Vref. Due to the capacitive coupling effect, the potential of N1 is Vdd+Vth+Vref-Vdata_I. The gate-source voltage Vgs of T0 is equal to Vth+Vref-Vdata_I. Id is equal to K×(Vref-Vdata_I) 2< ; K is the current coefficient of T0; Id is the driving current of T0 driving E0 to emit light.

[0148] In S012, EM provides a high voltage signal, RST provides a high voltage signal, G1 provides a high voltage signal, GA provides a high voltage signal, GB provides a low voltage signal, T1 is turned on, and DT provides a first light emitting time control data voltage to N4; When DT provides a low voltage signal at S012, T3 is turned on, T4 is turned on, and T0 drivings E0 to emit light at S013; When DT provides a high voltage signal at S012, T3 is turned off at S013, and E0 does not emit light; At S0n-12, EM provides a high voltage signal, RST provides a high voltage signal, G1 provides a high voltage signal, GA provides a high voltage signal, GB provides a low voltage signal, T1 is turned on, and DT provides the (n-1)th light emitting time control data voltage to N4; When DT provides a low voltage signal at S0n-12, T3 is turned on at S0n-13, T4 is turned on, and T0 drivings E0 to emit light; When DT provides a high voltage signal at S0n-12, T3 is turned off at S0n-13, and E0 does not emit light; At S0n2, EM provides a high voltage signal, RST provides a high voltage signal, G1 provides a high voltage signal, GA provides a high voltage signal, GB provides a low voltage signal, T1 is turned on, and DT provides the nth light emitting time control data voltage to N4; When DT provides a low voltage signal at S0n2, T3 is turned on at S0n3, T4 is turned on, and T0 drivings E0 to emit light; When DT provides a high voltage signal at S0n2, T3 is turned off at S0n3, and E0 does not emit light; According to the light emitting time control data voltage provided by DT in each second writing-in time period, it can be determined whether E0 emits light in each second light emitting time period.

[0149] As shown in FIG. 35, when the pixel circuit shown in FIG. 31 is working, the light emitting time control data voltage is written multiple times within one frame of time, and the light emitting time control data voltage is written at a high frequency, so that the low grayscale short-time light emitting is divided into multiple segments of short-time light emitting, so as to realize low grayscale short-time high-frequency light emitting, reduce the continuous non-light emitting time within one frame of time, and further reduce the low grayscale flicker, realize healthy display, and improve display performance.

[0150] In specific implementation, the high-frequency writing-in of the light emitting time control data voltage can be input by multiple groups of first data lines, or a frame is divided into multiple sub-frames and a single first data line is input multiple times, or the second initial voltage and the light emitting time control data voltage can be written alternately at high frequency. FIG. 36 is a schematic diagram of the light emitting time of the pixel circuit shown in FIG. 31 when emitting light at a high grayscale and a low grayscale; As shown in FIG. 36, n is equal to 5; When high grayscale display is performed, the light emitting duration may be t1+t2+t3+t4+t5+t6; When performing low grayscale display, the light emitting duration may be t1+t3+t5; t1 is the first time, t2 is the second time, t3 is the third time, t4 is the fourth time, t5 is the fifth time, and t6 is the sixth time; t1 is the duration of the first light emitting time period, t2 is the duration of the first second light emitting time period, t3 is the duration of the second second light emitting time period, t4 is the duration of the third second light emitting time period, t5 is the duration of the fourth second light emitting time period, and t6 is the duration of the fifth second light emitting time period.

[0151] The difference between the pixel circuit shown in FIG. 37 and the pixel circuit shown in FIG. 31 is that T1, T2, T5, T6, T8, and T9 are all NMOS transistors.

[0152] The pixel circuit shown in FIG. 37 utilizes the low leakage current advantage of oxide thin film transistors to change T8, T6, T9, T5, T1, T2 or part of them into NMOS (N-type metal-oxide-semiconductor) transistors to reduce the leakage of N1, N2, and N4; utilizing the high mobility of PMOS transistors, T0, T3, T4, and T7 are set to PMOS transistors to meet threshold voltage compensation, current driving requirements, and reduce charging time, thereby further improving display performance.

[0153] FIG. 38 is a timing diagram of the pixel circuit shown in FIG. 37.

[0154] The difference between the pixel circuit shown in FIG. 39 and the pixel circuit shown in FIG. 37 is that all transistors are NMOS transistors.

[0155] The pixel circuit shown in FIG. 39 adopts NMOS TFT technology to realize a pixel circuit of current control + light emitting duration control, and can be applied to oxide display products.

[0156] In the pixel circuit shown in FIG. 39, E0 may be a Mini LED or a Micro LED, but is not limited thereto. In the pixel circuit shown in FIG. 39, Vi1 is greater than Vss+Vth, where Vss is the voltage value of the low voltage signal provided by VSS, and Vth is the threshold voltage of T0; When Vi2 is written to N4, T3 can be turned on; The values of Vdata_I and Vref need to satisfy the driving current of E0 while Vref needs to be greater than or equal to V data _I to achieve grayscale display; In high grayscale display, in the preferred case, Vdata_T is equal to Vi2; In low grayscale display, when Vdata_T is input to N4, T3 needs to be turned off.

[0157] FIG. 40 is a timing diagram of the pixel circuit shown in FIG. 39. In FIG. 40, the first display phase is labeled S1, and the second display phase is labeled S2; The time period labeled S11 is the first reset time period, the time period labeled S12 is the first writing-in time period, and the time period labeled S13 is the first light emitting time period; The time period labeled S22 is the second writing-in time period, and the time period labeled S23 is the second light emitting time period.

[0158] FIG. 41A is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the first reset time period S11; FIG. 41B is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the first writing-in time period S12; FIG. 41C is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the first light emitting time period S13; FIG. 41D is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the second writing-in time period S22; FIG. 41E is a schematic diagram of the working state of the pixel circuit shown in FIG. 39 in the second light emitting time period S23.

[0159] FIG. 42A is a schematic diagram of simulation results of high grayscale display of the pixel circuit shown in FIG. 39; FIG. 42B is a schematic diagram of simulation results of low grayscale display of the pixel circuit shown in FIG. 39. As shown in FIG. 42A, when displaying at a high gray scale, Vdd is equal to 7V, Vss is equal to 0V, Vi1 is equal to 8V, Vi2 is equal to 5V, Vdata_I is equal to 2V, Vref is equal to 6V, and Vdata_T is equal to 5V; wherein Vdd is the voltage value of the high voltage signal provided by VDD;

[0160] As shown in FIG. 42B, in low grayscale display, Vdd is equal to 7V, Vss is equal to 0V, Vi1 is equal to 8V, Vi2 is equal to 5V, Vdata_I is equal to 2V, Vref is equal to 6V, and Vdata_T is equal to -5V. The difference between the pixel circuit shown in FIG. 43A and the pixel circuit shown in FIG. 31 is that: a third reset circuit is further included; The third reset circuit includes a tenth transistor T10; the gate electrode of the tenth transistor T10 is electrically connected to the second reset control terminal RST2, the source electrode of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain electrode of the tenth transistor T10 is electrically connected to the anode of the light emitting diode E0; the third initial voltage terminal I3 is configured to provide a third initial voltage Vi3.

[0161] The pixel circuit shown in FIG. 43A of the present disclosure adds a tenth transistor T10 for resetting the potential of the anode of the light emitting diode E0, thereby improving the display contrast.

[0162] In the pixel circuit shown in FIG. 43A of the present disclosure, Vi3-Vss is smaller than Vled, ensuring that when Vi3 is written to the anode of E0, E0 does not emit light; wherein Vss is the voltage value of the low voltage signal provided by VSS, and Vled is the light emitting voltage of E0.

[0163] FIG. 43B is a first timing diagram of the pixel circuit shown in FIG. 43A of the present disclosure.

[0164] FIG. 43C is a second timing diagram of the pixel circuit shown in FIG. 43A of the present disclosure. In FIG. 43C, the first display phase is labeled S1, and the second display phase is labeled S2; The time period labeled S11 is the first reset time period, the time period labeled S12 is the first writing-in time period, and the time period labeled S13 is the first light emitting time period; The time period labeled S21 is the second reset time period, the time period labeled S22 is the second writing-in time period, and the time period labeled S23 is the second light emitting time period.

[0165] As shown in FIG. 43C, when the pixel circuit shown in FIG. 43A of the present disclosure is in operation, in the first reset time period S11 and the second reset time period S21, RST2 provides a low voltage signal and T11 is turned on to write the second initial voltage Vi2 provided by I2 into the anode of E0, so as to be able to clear the residual charge at the anode of E0 at high frequency and improve display flicker.

[0166] Based on the pixel circuit shown in FIG. 37 and the pixel circuit shown in FIG. 39, a third reset circuit can be added, and the third reset circuit can include a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the second reset control terminal, a source electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and a drain electrode of the tenth transistor is electrically connected to the cathode of the light emitting diode. As shown in FIG. 44, based on the pixel circuit shown in FIG. 23, the light emitting element is a light emitting diode E0; The driving circuit includes a driving transistor T0; the energy storage circuit includes a storage capacitor Cst, the first light emitting control circuit includes an eleventh transistor T11, the second light emitting control circuit includes a twelfth transistor T12, the switch control circuit includes a third transistor T3, the compensation control circuit includes a fifth transistor T5, and the display data writing-in circuit includes a sixth transistor T6; The first terminal of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T0, and the second terminal of the storage capacitor Cst is electrically connected to the high voltage terminal VDD; the gate electrode of the driving transistor T0 is electrically connected to the first node N1; The gate electrode of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, the source electrode of the eleventh transistor T11 is electrically connected to the high voltage terminal VDD, and the drain electrode of the eleventh transistor T11 is electrically connected to the source electrode of the driving transistor T0; The gate electrode of the twelfth transistor T12 is electrically connected to the light emitting control terminal EM, the source electrode of the twelfth transistor T12 is electrically connected to the drain electrode of the driving transistor T0, and the drain electrode of the twelfth transistor T12 is electrically connected to the source electrode of the third transistor T3; The gate electrode of the third transistor T3 is electrically connected to the switch control terminal N4, and the drain electrode of the third transistor T4 is electrically connected to the anode of the light emitting diode E0; The gate electrode of the fifth transistor T5 is electrically connected to the scanning terminal G1, the source electrode of the fifth transistor T5 is electrically connected to the gate electrode of the driving transistor T0, and the drain electrode of the fifth transistor T5 is electrically connected to the drain electrode of the driving transistor T0; The gate electrode of the sixth transistor T6 is electrically connected to the scanning terminal G1, the source electrode of the sixth transistor T6 is electrically connected to the second data line DI, and the drain electrode of the sixth transistor T6 is electrically connected to the source electrode of the driving transistor T0; The first reset circuit comprises an eighth transistor T8; The gate electrode of the eighth transistor T8 is electrically connected to the second reset control terminal RST2, the source electrode of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain electrode of the eighth transistor T8 is electrically connected to the anode of the light emitting diode E0; the third initial voltage terminal I3 is configured to provide a third initial voltage Vi3; The second reset circuit includes a ninth transistor T9; The gate electrode of the ninth transistor T9 is electrically connected to the first reset control terminal RST1, the source electrode of the ninth transistor T9 is electrically connected to the first initial voltage terminal I1, and the drain electrode of the ninth transistor T9 is electrically connected to the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vi1; The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1; The gate electrode of the first transistor T1 is electrically connected to the first control terminal GB, the source electrode of the first transistor T1 is electrically connected to the first data line DT, and the drain electrode of the first transistor T1 is electrically connected to the switch control terminal N4; The gate electrode of the second transistor T2 is electrically connected to the second control terminal GA, the source electrode of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain electrode of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is configured to provide a second initial voltage Vi2; A first terminal of the first capacitor C1 is electrically connected to the switch control terminal N4, and a second terminal of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM.

[0167] In the pixel circuit shown in FIG. 44, all transistors are p-type transistors, but the present invention is not limited thereto.

[0168] In the pixel circuit shown in FIG. 44, the contrast is increased and the display performance is enhanced by resetting the eighth transistor configured to reset the potential of the anode of the light emitting diode E0.

[0169] When the pixel circuit shown in FIG. 44 is working, the second control signal provided by GA can be the same as the scanning signal provided by G1, or the second control signal provided by GA can be the same as the second reset control signal provided by RST2, that is, the second initial voltage Vi2 can be written into N4 in the first reset time period S11 or the first writing-in time period S12, and GA can share the GOA (Gate On Array, a gate driving circuit arranged on the array substrate) circuit with G1 or RST; the number of control signals can be reduced, and the proportion of control signal writing-in time can be reduced. As shown in FIG. 45A, the pixel circuit shown in FIG. 44 is at work, the display cycle (the display cycle may be a frame of time) may include a first display phase S1 and a second display phase S2 which are successively set; The first display phase S1 may include a first reset time period S11, a first writing-in time period S12 and a first light emitting time period S13 which are set successively; the second display phase S2 may include a second writing-in time period S22 and a second light emitting time period S23 which are set successively; In the first reset time period S11, RST1 provides a low voltage signal, RST2 provides a low voltage signal, T9 and T8 are turned on, and the anode of the first node N1 and E0 are reset; In the first writing-in time period S12, G1 provides a low voltage signal, T6 is turned on, DI writes the display data voltage to the first node N1, and T5 is turned on; At the beginning of the first writing-in time period S12, T0 is turned on, and Cst is charged by display data voltage until T0 is turned off, and until the gate voltage of T0 becomes Vdd+Vth, threshold voltage compensation is performed; wherein Vdd is the voltage value of the high voltage signal provided by VDD, and Vth is the threshold voltage of T0; In the first writing-in time period S12, GA provides a low voltage signal, T2 is turned on, the second initial voltage Vi2 provided by I2 is written into N4, and T3 is turned on; In the first light emitting time period S13, EM provides a low voltage signal, T11 and T12 are turned on, and T0 drivings E0 to emit light; In the second writing-in time period S22, the first time t1 is delayed, GB provides a low voltage signal, T1 is turned on, and DT provides a light emitting time control data voltage Vdata_T to N4; t1 is the duration of the first light emitting time period S13; When Vdata_T is a high voltage signal, in the second light emitting time period S23, T3 is turned off, E0 does not emit light, and a short-time light emitting is achieved, and the light emitting duration is t1; When Vdata_T is a low voltage signal, the optimal voltage value of Vdata_T is the same as the voltage value of Vi2. In the second light emitting time period S23, T3 is turned on, T0 drivings E0 to emit light, and E0 continues to emit light to achieve long-term light emitting. The light emitting time is t1+t2, t2 is the second time, and t2 is the duration of the second light emitting time period S23.

[0170] FIG. 45B is a second timing diagram of the pixel circuit shown in FIG. 44. In FIG. 45B, the time period labeled S21 is the second reset time period;

[0171] In the first reset time period S11 and the second reset time period S21, RST2 provides a low voltage signal and T8 is turned on to write the third initial voltage Vi3 provided by I3 into the anode of E0, so as to clear the residual charge of the anode of E0 at high frequency and improve display flicker. As shown in FIG. 46, based on the pixel circuit shown in FIG. 24, the light emitting element is a light emitting diode E0; The driving circuit includes a driving transistor T0; the energy storage circuit includes a storage capacitor Cst, the first light emitting control circuit includes an eleventh transistor T11, the second light emitting control circuit includes a twelfth transistor T12, the switch control circuit includes a third transistor T3, the compensation control circuit includes a fifth transistor T5, and the display data writing-in circuit includes a sixth transistor T6; The anode of the light emitting diode E0 is electrically connected to the high voltage terminal VDD; The first terminal of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T0, and the second terminal of the storage capacitor Cst is electrically connected to the low voltage terminal VSS; the gate electrode of the driving transistor T0 is electrically connected to the first node N1; The gate electrode of the third transistor T3 is electrically connected to the switch control terminal N4, the drain electrode of the third transistor T3 is electrically connected to the cathode of the light emitting diode E1, and the source electrode of the third transistor T3 is electrically connected to the drain electrode of the eleventh transistor T11; The gate electrode of the eleventh transistor T11 is electrically connected to the light emitting control terminal EM, and the source electrode of the eleventh transistor T11 is electrically connected to the drain electrode of the driving transistor T0; The gate electrode of the twelfth transistor T12 is electrically connected to the light emitting control terminal EM, the drain electrode of the twelfth transistor T12 is electrically connected to the source electrode of the driving transistor T0, and the source electrode of the twelfth transistor T12 is electrically connected to the low voltage terminal VSS; The gate electrode of the fifth transistor T5 is electrically connected to the scanning terminal G1, the drain electrode of the fifth transistor T5 is electrically connected to the gate electrode of the driving transistor T0, and the drain electrode of the fifth transistor T5 is electrically connected to the drain electrode of the driving transistor T0; The gate electrode of the sixth transistor T6 is electrically connected to the scanning terminal G1, the drain electrode of the sixth transistor T6 is electrically connected to the second data line DI, and the source electrode of the sixth transistor T6 is electrically connected to the source electrode of the driving transistor T0; The first reset circuit comprises an eighth transistor T8; The gate electrode of the eighth transistor T8 is electrically connected to the second reset control terminal RST2, the source electrode of the eighth transistor T8 is electrically connected to the third initial voltage terminal I3, and the drain electrode of the eighth transistor T8 is electrically connected to the cathode of the light emitting diode E0; The second reset circuit includes a ninth transistor T9; The gate electrode of the ninth transistor T9 is electrically connected to the first reset control terminal RST1, the source electrode of the ninth transistor T9 is electrically connected to the first initial voltage terminal I1, and the drain electrode of the ninth transistor T9 is electrically connected to the first node N1; the first initial voltage terminal I1 is configured to provide a first initial voltage Vi1; The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1; The gate electrode of the first transistor T1 is electrically connected to the first control terminal GB, the source electrode of the first transistor T1 is electrically connected to the first data line DT, and the drain electrode of the first transistor T1 is electrically connected to the switch control terminal N4; The gate electrode of the second transistor T2 is electrically connected to the second control terminal GA, the source electrode of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain electrode of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is configured to provide a second initial voltage Vi2; A first terminal of the first capacitor C1 is electrically connected to the switch control terminal N4, and a second terminal of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM.

[0172] In the pixel circuit shown in FIG. 46, all transistors are NMOS transistors, but the present invention is not limited thereto.

[0173] FIG. 47A is a first timing diagram of the pixel circuit shown in FIG. 46. In FIG. 47A, the first display phase is labeled S1 and the second display phase is labeled S2; The time period labeled S11 is the first reset time period, the time period labeled S12 is the first writing-in time period, and the time period labeled S13 is the first light emitting time period; The time period labeled S22 is the second writing-in time period, and the time period labeled S23 is the second light emitting time period.

[0174] FIG. 48A is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the first reset time period S11; FIG. 48B is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the first writing-in time period S12; FIG. 48C is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the first light emitting time period S13; FIG. 48D is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the second writing-in time period S22; FIG. 48E is a schematic diagram of the working state of the pixel circuit shown in FIG. 46 in the second light emitting time period S23.

[0175] FIG. 47B is a first timing diagram of the pixel circuit shown in FIG. 46. In FIG. 47B, the time period labeled S21 is the second reset time period;

[0176] In the first reset time period S11 and the second reset time period S21, RST2 provides a low voltage signal and T8 is turned on to write the third initial voltage Vi3 provided by I3 into the cathode of E0, so as to clear the residual charge of the cathode of E0 at high frequency and improve the display flicker.

[0177] In at least one embodiment of the present disclosure, when the potential of the cathode of E0 is initialized, E0 does not emit light.

[0178] The difference between the pixel circuit shown in FIG. 49 and the pixel circuit shown in FIG. 44 is that T9, T8, T5, T6, T1 and T2 are NMOS TFTs, T9, T8, T5, T6, T1 and T2 are oxide TFTs, and T0, T11, T12 and T3 are PMOS TFTs.

[0179] The pixel circuit shown in FIG. 49 adopts LTPO technology, takes advantage of the low leakage current of oxide TFT, reduces the leakage of the anode of the first node N1 and E0, and sets T9, T8, T5, T6, T1 and T2 as NMOS TFT; takes advantage of the high mobility of PMOS TFT, sets T0, T11, T12 and T3 as PMOS TFT, meets the threshold voltage compensation, current driving requirements and reduces the charging time, and further improves the display performance. FIG. 50A is a first timing diagram of the pixel circuit shown in FIG. 49. In FIG. 50, the first display phase is labeled S1, and the second display phase is labeled S2; The time period labeled S11 is the first reset time period, the time period labeled S12 is the first writing-in time period, and the time period labeled S13 is the first light emitting time period;

[0180] The time period labeled S22 is the second writing-in time period, and the time period labeled S23 is the second light emitting time period. FIG. 50B is a second timing diagram of the pixel circuit shown in FIG. 49; in FIG. 50B, the time period labeled S21 is a second reset time period;

[0181] In the first reset time period S11 and the second reset time period S21, RST2 provides a low voltage signal and T8 is turned on to write the third initial voltage Vi3 provided by I3 into the anode of E0, so as to clear the residual charge of the anode of E0 at high frequency and improve display flicker. As shown in FIG. 51, based on the pixel circuit shown in FIG. 24, the light emitting element is a light emitting diode E0; The energy storage circuit includes a storage capacitor Cst, the compensation circuit includes a thirteenth transistor T13, the switch circuit includes a first switch K1; the driving circuit includes a driving transistor T0; The first terminal of the storage capacitor Cst is electrically connected to the gate electrode of the driving transistor T0, and the second terminal of the storage capacitor Cst is electrically connected to the drain electrode of the driving transistor T0; the gate electrode of the driving transistor T0 is electrically connected to the first node N1; the drain electrode of the driving transistor T0 is electrically connected to the anode of E0; the anode of E0 is electrically connected to the second node N2; The gate electrode of the thirteenth transistor T13 is electrically connected to the scanning terminal G1, the source electrode of the thirteenth transistor T13 is electrically connected to the anode of E0, and the drain electrode of the thirteenth transistor T 13 is electrically connected to the control node N0; The control terminal of the first switch K1 is electrically connected to the first selection control terminal X1, the first terminal of the first switch K1 is electrically connected to the control node N0, and the second terminal of the first switch K1 is electrically connected to a reference voltage terminal; the reference voltage terminal provides a reference voltage Vref; The switch circuit also includes a second switch K2; The control terminal of the second switch K2 is electrically connected to the second selection control terminal X2, the first terminal of the second switch K2 is electrically connected to the control node N0, and the second terminal of the second switch K2 is electrically connected to the compensation terminal SENS; The display data writing-in circuit includes a sixth transistor T6; The gate electrode of the sixth transistor T6 is electrically connected to the scanning terminal G1, the source electrode of the sixth transistor T6 is electrically connected to the second data line DI, and the drain electrode of the sixth transistor T6 is electrically connected to the gate electrode of the driving transistor T0; The switch control circuit includes a third transistor T3; The gate electrode of T3 is electrically connected to the switch control terminal N4, the source electrode of T4 is electrically connected to the high voltage terminal VDD, the drain electrode of T4 is electrically connected to the source electrode of T0; the cathode of E0 is electrically connected to the low voltage terminal VSS; The driving control circuit includes a first transistor T1, a second transistor T2 and a first capacitor C1; The gate electrode of the first transistor T1 is electrically connected to the first control terminal GB, the source electrode of the first transistor T1 is electrically connected to the first data line DT, and the drain electrode of the first transistor T1 is electrically connected to the switch control terminal N4; The gate electrode of the second transistor T2 is electrically connected to the scanning terminal G1, the source electrode of the second transistor T2 is electrically connected to the second initial voltage terminal I2, and the drain electrode of the second transistor T2 is electrically connected to the switch control terminal N4; the second initial voltage terminal I2 is configured to provide a second initial voltage Vi2; A first terminal of the first capacitor C1 is electrically connected to the switch control terminal N4, and a second terminal of the first capacitor C1 is electrically connected to the common electrode voltage terminal VCOM.

[0182] In the pixel circuit shown in FIG. 51, the second control terminal is the scanning terminal G1, but the present invention is not limited thereto.

[0183] In the pixel circuit shown in FIG. 51, all transistors are p-type transistors, but the present invention is not limited thereto.

[0184] In the pixel circuit shown in FIG. 51, T6, K1, and K2 form an extraction circuit for extracting Vth and Id. As shown in FIG. 52, when the pixel circuit shown in FIG. 51 of the present disclosure is in operation, a display cycle may include a display phase SX and a sensing phase SC; The display phase SX includes a first writing-in time period S12, a first light emitting time period S13, a second writing-in time period S21 and a second light emitting time period S22 which are arranged successively; The sensing phase SC includes a reset time period SC1, a compensation time period SC2 and an extraction time period SC3 which are arranged successively; In the first writing-in time period S12, G1 provides a low voltage signal, T6 and T2 are turned on, DI provides a display data voltage Vdata_I, Vdata_I is written into the first node N1, T0 is turned on, and the second initial voltage Vi2 provided by I2 is written into N4 through T2; T3 is turned on; In the first light emitting time period S13, G1 provides a high voltage signal, T3 is turned on, and T0 drivings E0 to emit light; the first light emitting time period S13 lasts for a first time t1; In the second writing-in time period S21, GB provides a low voltage signal, T1 is turned on, and DT provides a light emitting control data voltage; As shown in FIG. 52, in the second writing-in time period S21, the light emitting control data voltage provided by DT is a high voltage signal; In the second light emitting time period S22, T3 is turned off, E0 does not emit light, and a short-time light emitting is realized, and the light emitting duration is t1; When the light emitting control data voltage provided by DT is a low voltage signal in the second writing-in time period S21, T3 is turned on in the second light emitting time period S22, and T0 drivings E0 to emit light, realizing long-time light emitting, and the light emitting time is t1+t2, where t2 is the duration of the second light emitting time period S22; As shown in FIG. 52, in the reset time period SC1, G1 provides a low voltage signal, T13, T0, T6, T3, and T2 are turned on, K1 is turned on, and N2 is reset through Vref; DI provides a data voltage Vdata to the first node N1; In the compensation time period SC2, K1 is turned off, Vref is less than Vdata, and Vdata is less than Vdd, Vdd is the voltage value of the high voltage signal provided by VDD, when the potential of N2 is Vdata-Vth, the gate-source voltage of T0 is equal to Vth, Vth is the threshold voltage of T0, T0 is turned off, and Vth is written into N2; In the extraction time period SC3, K2 is turned on and the IC (integrated circuit) extracts Vth through SENS.

[0185] As shown in FIG. 52, in a time period other than the second writing-in time period, DT may provide the second initial voltage Vi2, but is not limited thereto. FIG. 53A is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 in the first writing-in time period S12 and the first light emitting time period S22; FIG. 53B is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 in a second writing-in time period S21 and a second light emitting time period S22; FIG. 53C is a schematic diagram of the working state of the pixel circuit shown in FIG. 51 during a reset time period SC1; FIG. 53D is a schematic diagram showing the working state of the pixel circuit shown in FIG. 51 during the compensation time period SC2; FIG. 53E is a schematic diagram of the working state of the pixel circuit shown in FIG. 51 during the extraction time period SC3. FIG. 54A is a schematic diagram showing simulation results of high grayscale display in a display phase of the pixel circuit shown in FIG. 51;

[0186] FIG. 54B is a schematic diagram showing simulation results of low grayscale display during the display phase of the pixel circuit shown in FIG. 51. The difference between the pixel circuit shown in FIG. 55 and the pixel circuit shown in FIG. 51 is that: all transistors are NMOS TFTs to realize a pixel circuit of driving current control + light emitting duration control; The pixel circuit shown in FIG. 55 can be applied to oxide display products.

[0187] FIG. 56 is a timing diagram of the pixel circuit shown in FIG. 55.

[0188] The difference between the pixel circuit shown in FIG. 57 and the pixel circuit shown in FIG. 51 is that: T13, T1 and T2 are NMOS TFTs, T6, T0 and T3 are PMOS TFTs; the gate electrode of T2 and the gate electrode of T13 are both electrically connected to the second control terminal GA.

[0189] The pixel circuit shown in FIG. 57 is an LTPO pixel circuit, which adopts LTPO technology and utilizes the advantages of low leakage current of oxide TFT and high mobility of PMOS TFT. T13, T1 and T2 are set as NMOS TFT, and T6, T0 and T3 are set as PMOS TFT to meet threshold voltage compensation, current driving and PPI (current density) requirements, thereby further improving display performance.

[0190] FIG. 58 is a timing diagram of the pixel circuit shown in FIG. 57. The pixel circuit described in the embodiment of the present disclosure includes a light emitting element, a driving circuit, a first reset circuit and a data writing-in circuit; The control terminal of the driving circuit is electrically connected to the first node, the driving circuit is electrically connected to the first electrode of the light emitting element, and the driving circuit is configured to generate a driving current to drive the light emitting element under the control of the potential of the first node; The data writing-in circuit is electrically connected to the writing-in control terminal and the writing-in node respectively, and is configured to sequentially provide a display data voltage and a light emitting time control data voltage to the writing-in node under the control of a writing-in control signal provided by the writing-in control terminal; The first reset circuit is electrically connected to a first reset control terminal, a first initial voltage terminal and a first electrode of the light emitting element, respectively, and is configured to write a first initial voltage provided by the first initial voltage terminal into the first electrode of the light emitting element under the control of a first reset control signal provided by the first reset control terminal during a reset time period set between a time period for writing-in the display data voltage and a time period for writing-in the light emitting time control data voltage. When the pixel circuit of the embodiment of the present disclosure is working, a display cycle (the display cycle may include a frame of time) includes a first display phase and a second display phase which are set successively, the first display phase includes a first writing-in time period; the second display phase includes a reset time period and a second writing-in time period which are set successively; In the first writing-in time period, the data writing-in circuit provides a display data voltage to the writing-in node under the control of the writing-in control signal; In the reset time period, the first reset circuit writes the first initial voltage into the first electrode of the light emitting element under the control of the first reset control signal; In the second writing-in time period, the data writing-in circuit provides the light emitting time control data voltage to the writing-in node under the control of the writing-in control signal.

[0191] In a specific implementation, when the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage, the first reset circuit writes a first initial voltage to the first electrode of the light emitting element under the control of a first reset control signal, to release the residual charge in the first electrode of the light emitting element and improve display uniformity. When the pixel circuit according to the embodiment of the present disclosure is working, the reset time period may be a second reset time period, and the first display phase may include a first reset time period set before the first writing-in time period;

[0192] In the first reset time period, the first reset circuit writes a first initial voltage into the first electrode of the light emitting element under the control of the first reset control signal, to release residual charges in the first electrode of the light emitting element and improve display uniformity.

[0193] When the pixel circuit described in the embodiment of the present disclosure is in operation, in a first reset time period and a second reset time period, the first reset circuit writes a first initial voltage into the first electrode of the light emitting element under the control of a first reset control signal, so as to release the residual charge in the first electrode of the light emitting element at a high frequency, thereby improving display uniformity.

[0194] In at least one embodiment of the present disclosure, the first terminal of the driving circuit is electrically connected to the first electrode of the light emitting element, and the writing-in node is electrically connected to the second terminal of the driving circuit; or, the second terminal of the driving circuit is electrically connected to the first electrode of the light emitting element, and the writing-in node is electrically connected to the first terminal of the driving circuit.

[0195] Optionally, the light emitting element is an inorganic light emitting diode, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0196] In at least one embodiment of the present disclosure, the width-to-length ratio of a transistor is a ratio of a channel width W to a channel length L of the transistor.

[0197] In a specific implementation, the light emitting element may be an inorganic light emitting diode, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5.

[0198] In at least one embodiment of the present disclosure, the light emitting element may be an inorganic light emitting diode, but is not limited thereto; for example, the light emitting element may be a micro light emitting diode or a mini light emitting diode.

[0199] In a specific implementation, the light emitting element may also be an organic light emitting diode. The pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit;

[0200] The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first node respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the first node during the reset time period under the control of the second reset control signal provided by the second reset control terminal. In a specific implementation, the driving circuit may further include a second reset circuit, and in the second reset time period, the second reset circuit writes a second initial voltage into the first node under the control of a second reset control signal; The second reset circuit also writes a second initial voltage into the first node under the control of a second reset control signal during the first reset time period; The first display phase may further include a first light emitting time period set after the first writing-in time period, and the second display phase may further include a second light emitting time period set after the second writing-in time period, in the first light emitting time period, the driving circuit drivings the light emitting element to emit light according to the display data voltage, and in the second light emitting time period, the driving circuit controls the data voltage according to the light emitting time to drive the light emitting element to emit light; At least one embodiment of the present disclosure resets the potential of the first node N1 before a first writing-in time period and before a second writing-in time period, so that when the display data voltage and the light emitting time control data voltage have the same voltage value, the difference between the driving current generated by the driving circuit in the first light emitting time period and the driving current generated by the driving circuit in the second light emitting time period is reduced, thereby reducing the brightness difference between the first light emitting time period and the second light emitting time period in the same frame time.

[0201] Optionally, the first reset control terminal and the second reset control terminal may be the same reset control terminal, but not limited thereto; in actual operation, the first reset control terminal and the second reset control terminal may be different reset control terminals. In at least one embodiment of the present disclosure, the writing-in control terminal includes a first control terminal and a second control terminal, and the data writing-in circuit is also electrically connected to the first data line and the second data line respectively; the display cycle of the pixel circuit includes a first writing-in time period and a second writing-in time period which are set successively;

[0202] The data writing-in circuit is configured to write the display data voltage provided by the second data line to the writing-in node under the control of the second control signal provided by the second control terminal during the first writing-in time period, and is configured to write the light emitting time control data voltage provided by the first data line to the writing-in node under the control of the first control signal provided by the first control terminal during the second writing-in time period.

[0203] In a specific implementation, the writing-in control terminal may include a first control terminal and a second control terminal. In the first writing-in time period, under the control of a second control signal, the data writing-in circuit writes the display data voltage provided by the second data line into the writing-in node. In the second writing-in time period, the data writing-in circuit writes the light emitting time control data voltage provided by the first data line into the writing-in node under the control of a first control signal. The pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; The first light emitting control circuit is electrically connected to the light emitting control terminal, the first voltage terminal and the first terminal of the driving circuit respectively, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and is configured to control the second terminal of the driving circuit to be connected to the first electrode of the light emitting element under the control of the light emitting control signal; the second electrode of the light emitting element is electrically connected to the second voltage terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the second terminal of the driving circuit respectively, and is configured to control the communication between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal;

[0204] The first electrode of the light emitting element is a first electrode of the light emitting element.

[0205] In a specific implementation, the pixel circuit may further include a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; the first light emitting control circuit controls the connection between the first voltage terminal and the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the connection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the light emitting control signal; the compensation control circuit controls the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of a scanning signal to perform threshold voltage compensation.

[0206] In at least one embodiment of the present disclosure, the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the transistor included in the first light emitting control circuit is greater than 1, the width-to-length ratio of the transistor included in the second light emitting control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0207] In a specific implementation, the light emitting element may be an inorganic light emitting diode, the width-to-length ratio of the transistor included in the first light emitting control circuit may be greater than 1, the width-to-length ratio of the transistor included in the second light emitting control circuit may be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5.

[0208] Optionally, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal.

[0209] In at least one embodiment of the present disclosure, the pixel circuit may further include an energy storage circuit, wherein the energy storage circuit is electrically connected to the first node and is configured to store electrical energy. Optionally, the energy storage circuit includes a storage capacitor; the light emitting element is an inorganic light emitting diode;

[0210] The capacitance value of the storage capacitor is greater than 3 times the gate-source capacitance of the transistor in the driving circuit. In a specific implementation, the energy storage circuit may include a storage capacitor; the light emitting element may be an inorganic light emitting diode;

[0211] The capacitance value of the storage capacitor may be greater than 3 times the gate-source capacitance of the transistor in the driving circuit.

[0212] In a specific implementation, the capacitance value of the storage capacitor is set to be greater than 3 times the gate-source capacitance of the transistor in the driving circuit, so that when the source potential of the transistor in the driving circuit changes, the gate potential of the transistor in the driving circuit can be maintained to ensure display accuracy.

[0213] In at least one embodiment of the present disclosure, the gate-source capacitance of the transistor in the driving circuit may be a parasitic capacitance between the gate electrode and the source electrode of the transistor in the driving circuit, which may be calculated based on the facing area of the gate electrode and the source electrode of the transistor in the driving circuit, and a dielectric constant, wherein the dielectric constant may be calculated based on the material and thickness of the insulating layer between the gate electrode and the source electrode of the transistor in the driving circuit. As shown in FIG. 59, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a first reset circuit 14, a data writing-in circuit 15, a second reset circuit 51, a first light emitting control circuit 61, a second light emitting control circuit 62 and a compensation control circuit 32; the writing-in control terminal includes a first control terminal GB and a second control terminal GA; The energy storage circuit 10 is electrically connected to the first node N1 and is configured to store electrical energy; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The data writing-in circuit 15 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second data line DI and the first terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the second control signal provided by the second control terminal GA, and is configured to write the light emitting time control data voltage provided by the first data line DT into the first terminal of the driving circuit 11 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first electrode of the light emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset time period between the time period of writing-in the display data voltage and the time period of writing-in the light emitting time control data voltage; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the first terminal of the driving circuit 11 respectively, and is configured to control the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the first electrode of the light emitting element E1 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the light emitting control signal; the second electrode of the light emitting element 31 is electrically connected to the second voltage terminal V2; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the control terminal of the driving circuit 11 to communicate with the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1;

[0214] The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 during the reset time period under the control of the reset control signal provided by the reset control terminal RST. In at least one embodiment of the present disclosure, the light emitting element may be a light emitting diode, the first electrode of the light emitting element may be an anode of the light emitting diode, and the second electrode of the light emitting element may be a cathode of the light emitting diode;

[0215] The light emitting diode may be an organic light emitting diode, a mini light emitting diode or a micro light emitting diode.

[0216] In the pixel circuit shown in FIG. 59, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, the first electrode of the light emitting element is the first electrode of the light emitting element, and the writing-in node is electrically connected to the first terminal of the driving circuit, but is not limited to this. The pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; The first electrode of the light emitting element is electrically connected to the first voltage terminal; The first light emitting control circuit is electrically connected to the light emitting control terminal, the second electrode of the light emitting element and the first terminal of the driving circuit respectively, and is configured to control the second electrode of the light emitting element to be connected to the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the second voltage terminal respectively, and is configured to control the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the first terminal of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0217] In a specific implementation, the pixel circuit may further include a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; the first light emitting control circuit controls the second electrode of the light emitting element to be connected to the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal; the compensation control circuit controls the control terminal of the driving circuit to be connected to the first terminal of the driving circuit under the control of a scanning signal to perform threshold voltage compensation. As shown in FIG. 60, the pixel circuit described in the embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a first reset circuit 14, a data writing-in circuit 15, a second reset circuit 51, a first light emitting control circuit 61, a second light emitting control circuit 62 and a compensation control circuit 32; the writing-in control terminal includes a first control terminal GB and a second control terminal GA; The energy storage circuit 10 is electrically connected to the first node N1 and is configured to store electrical energy; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is electrically connected to the second electrode of the light emitting element E1 through the first light emitting control circuit 61. The driving circuit 11 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The data writing-in circuit 15 is electrically connected to the first control terminal GB, the second control terminal GA, the first data line DT, the second data line DI and the second terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the second control signal provided by the second control terminal GA, and is configured to write the light emitting time control data voltage provided by the first data line DT into the second terminal of the driving circuit 11 under the control of the first control signal provided by the first control terminal GB; The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the second electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second electrode of the light emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the second electrode of the light emitting element E1 and the first terminal of the driving circuit 11 respectively, and is configured to control the second electrode of the light emitting element E1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the second voltage terminal V2 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 during the reset time period under the control of the reset control signal provided by the reset control terminal RST.

[0218] In the pixel circuit shown in FIG. 60, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, the first electrode of the light emitting element is the second electrode of the light emitting element, and the writing-in node is electrically connected to the second terminal of the driving circuit, but is not limited to this. As shown in FIG. 61, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a first reset circuit 14, a data writing-in circuit 15, a second reset circuit 51, a first light emitting control circuit 61, a second light emitting control circuit 62 and a compensation control circuit 32; the writing-in control terminal includes a first control terminal GB and a second control terminal GA; The energy storage circuit 10 is electrically connected to the first node N1 and is configured to store electrical energy; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The data writing-in circuit 15 is electrically connected to the scanning terminal G1, the data line D0 and the first terminal of the driving circuit 11 respectively, and is configured to write the display data voltage and the light emitting time control data voltage provided by the data line D0 into the first terminal of the driving circuit 11 in sequence under the control of the scanning signal provided by the scanning terminal G1; The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first electrode of the light emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset time period between the time period of writing-in the display data voltage and the time period of writing-in the light emitting time control data voltage; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the first terminal of the driving circuit 11 respectively, and is configured to control the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the first electrode of the light emitting element E1 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the first electrode of the light emitting element E1 under the control of the light emitting control signal; the second electrode of the light emitting element 31 is electrically connected to the second voltage terminal V2; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the control terminal of the driving circuit 11 to communicate with the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 during the reset time period under the control of the reset control signal provided by the reset control terminal RST.

[0219] In the pixel circuit shown in FIG. 61, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, and the first electrode of the light emitting element is the second electrode of the light emitting element. As shown in FIG. 62, the pixel circuit described in the embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a first reset circuit 14, a data writing-in circuit 15, a second reset circuit 51, a first light emitting control circuit 61, a second light emitting control circuit 62 and a compensation control circuit 32; the writing-in control terminal includes a first control terminal GB and a second control terminal GA; The energy storage circuit 10 is electrically connected to the first node N1 and is configured to store electrical energy; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The control terminal of the driving circuit 11 is electrically connected to the first node N1, and the driving circuit 11 is electrically connected to the second electrode of the light emitting element E1 through the first light emitting control circuit 61. The driving circuit 11 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1; The data writing-in circuit 15 is electrically connected to the scanning terminal G1, the data line D0 and the second terminal of the driving circuit 11 respectively, and is configured to write the display data voltage and the light emitting time control data voltage provided by the data line D0 into the second terminal of the driving circuit 11 in sequence under the control of the scanning signal provided by the scanning terminal G1; The first reset circuit 14 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the second electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the second electrode of the light emitting element E1 under the control of the reset control signal provided by the reset control terminal RST during a reset time period set between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the second electrode of the light emitting element E1 and the first terminal of the driving circuit 11 respectively, and is configured to control the second electrode of the light emitting element E1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the second voltage terminal V2 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the communication between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the reset control terminal RST, the first initial voltage terminal I1 and the first node N1, respectively, and is configured to write the first initial voltage Vi1 provided by the first initial voltage terminal I1 into the first node N1 during the reset time period under the control of the reset control signal provided by the reset control terminal RST.

[0220] In the pixel circuit shown in FIG. 62, the first reset control terminal and the second reset control terminal are the same reset control terminal, the first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal, and the first electrode of the light emitting element is the second electrode of the light emitting element. In the pixel circuit shown in FIG. 61 and FIG. 62, the data writing-in circuit may include a tenth transistor; a gate electrode of the tenth transistor is electrically connected to the scanning terminal, a first electrode of the tenth transistor is electrically connected to the data line, and the tenth transistor is electrically connected to the first terminal of the driving circuit or the second terminal of the driving circuit. In at least one embodiment of the present disclosure, the writing-in node includes a first writing-in node and a second writing-in node;

[0221] The first writing-in node is electrically connected to the first terminal of the driving circuit; the pixel circuit also includes a switch control circuit; the second terminal of the driving circuit is electrically connected to the first electrode of the light emitting element through the switch control circuit, and the switch control circuit is electrically connected to the switch control terminal, and the switch control circuit is configured to control the connection between the second terminal of the driving circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; the second writing-in node is electrically connected to the switch control terminal. In at least one embodiment of the present disclosure, the writing-in node includes a first writing-in node and a second writing-in node;

[0222] The first writing-in node is electrically connected to the second terminal of the driving circuit; the pixel circuit also includes a switch control circuit; the first terminal of the driving circuit is electrically connected to the first electrode of the light emitting element through the switch control circuit, and the switch control circuit is electrically connected to the switch control terminal, and the switch control circuit is configured to control the connection between the first terminal of the driving circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; the second writing-in node is electrically connected to the switch control terminal.

[0223] Optionally, the light emitting element is an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit is greater than 1, and the width-to-length ratio of the transistor included in the driving circuit is greater than 0.5.

[0224] In a specific implementation, the light emitting element may be an inorganic light emitting diode, the width-to-length ratio of the transistor included in the switch control circuit may be greater than 1, and the width-to-length ratio of the transistor included in the driving circuit may be greater than 0.5. In at least one embodiment of the present disclosure, the data writing-in circuit includes a first writing-in sub-circuit and a second writing-in sub-circuit; the writing-in control terminal includes a scanning terminal and a first control terminal; The first writing-in sub-circuit is electrically connected to the first control terminal, the first data line and the second writing-in node respectively, and is configured to write the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of the first control signal provided by the first control terminal; The second writing-in sub-circuit is electrically connected to the scanning terminal, the second data line and the first writing-in node respectively, and is configured to write the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal provided by the scanning terminal.

[0225] In a specific implementation, the data writing-in circuit may include a first writing-in sub-circuit and a second writing-in sub-circuit, wherein the first writing-in sub-circuit writes the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of a first control signal; and the second writing-in sub-circuit writes the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal. The pixel circuit described in at least one embodiment of the present disclosure further includes a second reset circuit, an initialization circuit and a voltage maintenance circuit; The second reset circuit is electrically connected to the second reset control terminal, the second initial voltage terminal and the first node respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the first node under the control of the second reset control signal provided by the second reset control terminal; The initialization circuit is electrically connected to the second control terminal, the third initial voltage terminal and the second writing-in node respectively, and is configured to write the third initial voltage provided by the third initial voltage terminal into the second writing-in node under the control of the second control signal provided by the second control terminal; The voltage maintenance circuit is electrically connected to the switch control terminal and is configured to maintain the potential of the switch control terminal.

[0226] In a specific implementation, the pixel circuit may further include a second reset circuit and an initialization circuit; the second reset circuit writes the second initial voltage provided by the second initial voltage terminal into the first node under the control of a second reset control signal; the initialization circuit writes into the second writing-in node under the control of a second control signal.

[0227] Optionally, the voltage maintenance circuit may include a second capacitor; a first terminal of the second capacitor is electrically connected to the switch control terminal, and a second terminal of the second capacitor is electrically connected to the DC voltage terminal.

[0228] In at least one embodiment of the present disclosure, the DC voltage terminal may be a common electrode voltage terminal, a low voltage terminal or a ground terminal, but is not limited thereto. The pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; The first light emitting control circuit is electrically connected to the light emitting control terminal, the first voltage terminal and the first terminal of the driving circuit respectively, and is configured to control the connection between the first voltage terminal and the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the first terminal of the switch control circuit respectively, and is configured to control the second terminal of the driving circuit to be connected to the first terminal of the switch control circuit under the control of the light emitting control signal; The second terminal of the switch control circuit is electrically connected to the first electrode of the light emitting element; the second electrode of the light emitting element is electrically connected to the second voltage terminal; the switch control circuit is configured to control the second light emitting control circuit to be connected to the first electrode of the light emitting element under the control of the potential of the switch control terminal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the second terminal of the driving circuit respectively, and is configured to control the connection between the control terminal of the driving circuit and the second terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal.

[0229] In a specific implementation, the pixel circuit may further include a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; the first light emitting control circuit controls the first voltage terminal to be connected to the first terminal of the driving circuit under the control of the light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be connected to the first terminal of the switch control circuit under the control of the light emitting control signal; the switch control circuit controls the second light emitting control circuit to be connected to the first electrode of the light emitting element under the control of the potential of the switch control terminal; the compensation control circuit controls the control terminal of the driving circuit to be connected to the second terminal of the driving circuit under the control of the scanning signal to perform threshold voltage compensation. As shown in FIG. 63, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a switch control circuit 12, a first reset circuit 14, a data writing-in circuit, a second reset circuit 51, an initialization circuit 50, a voltage maintenance circuit 103, a first light emitting control circuit 61, a second light emitting control circuit 62, and a compensation control circuit 32; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the first electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal I1 into the first electrode of the light emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST1 during a reset time period between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage; The data writing-in circuit includes a first writing-in sub-circuit 151 and a second writing-in sub-circuit 152; the writing-in control terminal includes a scanning terminal G1 and a first control terminal GB; The first writing-in sub-circuit 151 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The second writing-in sub-circuit 152 is electrically connected to the scanning terminal G1, the second data line DI and the first terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the second reset control terminal RST2, the second initial voltage terminal I2 and the first node N1 respectively, and is configured to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the second reset control signal provided by the second reset control terminal RST2; The initialization circuit 50 is electrically connected to the second control terminal GA, the third initial voltage terminal I3 and the switch control terminal N4 respectively, and is configured to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA; The voltage maintenance circuit 103 is electrically connected to the switch control terminal N4, and is configured to maintain the potential of the switch control terminal N4; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the first terminal of the driving circuit 11 respectively, and is configured to control the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the first terminal of the switch control circuit 12 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the first terminal of the switch control circuit 12 under the control of the light emitting control signal; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the second terminal of the switch control circuit 12 is electrically connected to the first electrode of the light emitting element E1; the second electrode of the light emitting element E1 is electrically connected to the second voltage terminal V2; the switch control circuit 12 is configured to control the second light emitting control circuit 62 to be connected to the first electrode of the light emitting element E1 under the control of the potential of the switch control terminal N4; The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the second terminal of the driving circuit 11 respectively, and is configured to control the control terminal of the driving circuit 11 to communicate with the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The first electrode of the light emitting element E1 is a first electrode of the light emitting element E1.

[0230] Optionally, the light emitting element may be a light emitting diode, and the first electrode of the light emitting element may be an anode. When the pixel circuit shown in FIG. 63 of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase that are arranged in sequence; The first display phase includes a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase includes a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence; In the first reset time period, the first reset circuit 14 writes the first initial voltage into the first electrode of the light emitting element E1 under the control of the first reset control signal; the second reset circuit 51 writes the second initial voltage Vi2 into the first node N1 under the control of the second reset control signal; In the first writing-in time period, the second writing-in sub-circuit 152 writes the display data voltage provided by the second data line DI into the first terminal of the driving circuit 11 under the control of the scanning signal; the initialization circuit 50 writes the third initial voltage Vi3 into the switch control terminal N4 under the control of the second control signal to control the switch control circuit 12 to be turned on under the control of the potential of the switch control terminal N4; the compensation control circuit 32 controls the control terminal of the driving circuit 11 to be connected to the second terminal of the driving circuit 11 under the control of the scanning signal; In the first light emitting time period, the first light emitting control circuit 61 is configured to control the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal; the second light emitting control circuit 62 is configured to control the second terminal of the driving circuit 11 to be connected to the first terminal of the switch control circuit 12 under the control of the light emitting control signal; the driving circuit 11 drivings the light emitting element E1 to emit light; In the second reset time period, the first reset circuit 14 writes the first initial voltage into the first electrode of the light emitting element E1 under the control of the first reset control signal; In the second writing-in time period, the first writing-in sub-circuit 151 writes the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal; In the second light emitting time period, the first light emitting control circuit 61 controls the first voltage terminal V1 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal; the second light emitting control circuit 62 controls the second terminal of the driving circuit 11 to be connected to the first terminal of the switch control circuit 12 under the control of the light emitting control signal; the driving circuit 11 controls whether the light emitting element E1 emits light according to the light emitting time control data voltage.

[0231] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a first reset time period and a second reset time period, the first reset circuit writes a first initial voltage into the first electrode of the light emitting element under the control of a first reset control signal, so as to release the residual charge in the first electrode of the light emitting element at a high frequency, thereby improving display uniformity. The pixel circuit described in at least one embodiment of the present disclosure further includes a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; The first electrode of the light emitting element is electrically connected to the first voltage terminal; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the first terminal of the switch control circuit is electrically connected to the second electrode of the light emitting element, and the second terminal of the switch control circuit is electrically connected to the first light emitting control circuit; the switch control circuit is configured to control the second electrode of the light emitting element to be connected to the first light emitting control circuit under the control of the potential of the switch control terminal; The first light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the switch control circuit and the first terminal of the driving circuit respectively, and is configured to control the second terminal of the switch control circuit to be connected to the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the second voltage terminal respectively, and is configured to control the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal; The compensation control circuit is electrically connected to the scanning terminal, the control terminal of the driving circuit and the first terminal of the driving circuit respectively, and is configured to control the communication between the control terminal of the driving circuit and the first terminal of the driving circuit under the control of the scanning signal provided by the scanning terminal;

[0232] The first electrode of the light emitting element E1 is the second electrode of the light emitting element E1.

[0233] Optionally, the light emitting element may be a light emitting diode, and the second electrode of the light emitting element may be a cathode.

[0234] In a specific implementation, the pixel circuit may also include a first light emitting control circuit, a second light emitting control circuit and a compensation control circuit; the switch control circuit controls the second electrode of the light emitting element to be connected to the first light emitting control circuit under the control of the potential of the switch control terminal; the first light emitting control circuit controls the second terminal of the switch control circuit to be connected to the first terminal of the driving circuit under the control of a light emitting control signal; the second light emitting control circuit controls the second terminal of the driving circuit to be connected to the second voltage terminal under the control of the light emitting control signal; and the compensation control circuit controls the control terminal of the driving circuit to be connected to the first terminal of the driving circuit under the control of the scanning signal. As shown in FIG. 64, the pixel circuit according to at least one embodiment of the present disclosure includes a light emitting element E1, a storage circuit 10, a driving circuit 11, a switch control circuit 12, a first reset circuit 14, a data writing-in circuit, a second reset circuit 51, an initialization circuit 50, a voltage maintenance circuit 103, a first light emitting control circuit 61, a second light emitting control circuit 62, and a compensation control circuit 32; The first reset circuit 14 is electrically connected to the first reset control terminal RST1, the first initial voltage terminal I1 and the second electrode of the light emitting element E1 respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal I1 into the second electrode of the light emitting element E1 under the control of the first reset control signal provided by the first reset control terminal RST1 during a reset time period between the time period for writing-in the display data voltage and the time period for writing-in the light emitting time control data voltage; The data writing-in circuit includes a first writing-in sub-circuit 151 and a second writing-in sub-circuit 152; the writing-in control terminal includes a scanning terminal G1 and a first control terminal GB; The first writing-in sub-circuit 151 is electrically connected to the first control terminal GB, the first data line DT and the switch control terminal N4 respectively, and is configured to write the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal provided by the first control terminal GB; The second writing-in sub-circuit 152 is electrically connected to the scanning terminal G1, the second data line DI and the second terminal of the driving circuit 11 respectively, and is configured to write the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1; The second reset circuit 51 is electrically connected to the second reset control terminal RST2, the second initial voltage terminal I2 and the first node N1 respectively, and is configured to write the second initial voltage Vi2 provided by the second initial voltage terminal I2 into the first node N1 under the control of the second reset control signal provided by the second reset control terminal RST2; The initialization circuit 50 is electrically connected to the second control terminal GA, the third initial voltage terminal I3 and the switch control terminal N4 respectively, and is configured to write the third initial voltage Vi3 provided by the third initial voltage terminal I3 into the switch control terminal N4 under the control of the second control signal provided by the second control terminal GA; The voltage maintenance circuit 103 is electrically connected to the switch control terminal N4, and is configured to maintain the potential of the switch control terminal N4; The first electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1; The control terminal of the switch control circuit 12 is electrically connected to the switch control terminal N4; the first terminal of the switch control circuit 12 is electrically connected to the second electrode of the light emitting element E1, and the second terminal of the switch control circuit 12 is electrically connected to the first light emitting control circuit 61; the switch control circuit 12 is configured to control the second electrode of the light emitting element E1 to be connected to the first light emitting control circuit 61 under the control of the potential of the switch control terminal N4; The first light emitting control circuit 61 is electrically connected to the light emitting control terminal EM, the second terminal of the switch control circuit 12 and the first terminal of the driving circuit 11 respectively, and is configured to control the second terminal of the switch control circuit 12 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; The second light emitting control circuit 62 is electrically connected to the light emitting control terminal EM, the second terminal of the driving circuit 11 and the second voltage terminal V2 respectively, and is configured to control the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal;

[0235] The compensation control circuit 32 is electrically connected to the scanning terminal G1, the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 respectively, and is configured to control the connection between the control terminal of the driving circuit 11 and the first terminal of the driving circuit 11 under the control of the scanning signal provided by the scanning terminal G1. When the pixel circuit shown in FIG. 64 of the present disclosure is in operation, a display cycle may include a first display phase and a second display phase that are arranged in sequence; The first display phase includes a first reset time period, a first writing-in time period and a first light emitting time period which are set in sequence, and the second display phase includes a second reset time period, a second writing-in time period and a second light emitting time period which are set in sequence; In the first reset time period, the first reset circuit 14 writes the first initial voltage into the second electrode of the light emitting element E1 under the control of the first reset control signal; the second reset circuit 51 writes the second initial voltage Vi2 into the first node N1 under the control of the second reset control signal; In the first writing-in time period, the second writing-in sub-circuit 152 writes the display data voltage provided by the second data line DI into the second terminal of the driving circuit 11 under the control of the scanning signal; the initialization circuit 50 writes the third initial voltage Vi3 into the switch control terminal N4 under the control of the second control signal, to control the switch control circuit 12 to be turned on under the control of the potential of the switch control terminal N4; the compensation control circuit 32 controls the control terminal of the driving circuit 11 to be connected to the first terminal of the driving circuit 11 under the control of the scanning signal; In the first light emitting time period, the first light emitting control circuit 61 controls the second terminal of the switch control circuit 12 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; the second light emitting control circuit 62 controls the second terminal of the driving circuit 11 to be connected to the second voltage terminal V2 under the control of the light emitting control signal; the driving circuit 11 drivings the light emitting element E1 to emit light; In the second reset time period, the first reset circuit 14 writes the first initial voltage into the second electrode of the light emitting element E1 under the control of the first reset control signal; In the second writing-in time period, the first writing-in sub-circuit 151 writes the light emitting time control data voltage provided by the first data line DT into the switch control terminal N4 under the control of the first control signal; In the second light emitting time period, the first light emitting control circuit 61 controls the second terminal of the switch control circuit 12 to be connected to the first terminal of the driving circuit 11 under the control of the light emitting control signal provided by the light emitting control terminal EM; the second light emitting control circuit 62 controls the second terminal of the driving circuit 11 to be connected with the second voltage terminal V2 under the control of the light emitting control signal; the driving circuit 11 controls whether the light emitting element E1 emits light according to the light emitting time control data voltage.

[0236] When the pixel circuit described in at least one embodiment of the present disclosure is in operation, in a first reset time period and a second reset time period, the first reset circuit writes a first initial voltage into the second electrode of the light emitting element under the control of a first reset control signal, so as to release the residual charge of the first electrode of the light emitting element at a high frequency, thereby improving display uniformity. Optionally, the first reset circuit includes a first transistor, and the second reset transistor includes a second transistor; a gate electrode of the first transistor is electrically connected to the first reset control terminal, a first electrode of the first transistor is electrically connected to the first initial voltage terminal, and a second electrode of the first transistor is electrically connected to the first electrode of the light emitting element; A gate electrode of the second transistor is electrically connected to the second reset control terminal, a first electrode of the second transistor is electrically connected to the second initial voltage terminal, and a second electrode of the second transistor is electrically connected to the first node.

[0237] Optionally, the data writing-in circuit includes a third transistor and a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the writing-in node; A gate electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the writing-in node.

[0238] Optionally, the driving circuit includes a driving transistor, the first light emitting control circuit includes a fifth transistor, the second light emitting control circuit includes a sixth transistor, and the compensation control circuit includes a seventh transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the sixth transistor is electrically connected to the light emitting control terminal, a first electrode of the sixth transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light emitting element; a gate electrode of the driving transistor is electrically connected to the first node; A gate electrode of the seventh transistor is electrically connected to the scanning terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to a second electrode of the driving transistor.

[0239] Optionally, the driving circuit includes a driving transistor, the first light emitting control circuit includes a fifth transistor, the second light emitting control circuit includes a sixth transistor, and the compensation control circuit includes a seventh transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the sixth transistor is electrically connected to the light emitting control terminal, a first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal; a gate electrode of the driving transistor is electrically connected to the first node;

[0240] A gate electrode of the seventh transistor is electrically connected to the scanning terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to a first electrode of the driving transistor. Optionally, the first writing-in sub-circuit includes a third transistor, and the second writing-in sub-circuit includes a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the second writing-in node; A gate electrode of the fourth transistor is electrically connected to the scanning terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the first writing-in node.

[0241] Optionally, the initialization circuit includes an eighth transistor; A gate electrode of the eighth transistor is electrically connected to the second control terminal, a first electrode of the eighth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the second writing-in node.

[0242] Optionally, the switch control circuit includes a ninth transistor; the driving circuit includes a driving transistor, the first light emitting control circuit includes a fifth transistor, the second light emitting control circuit includes a sixth transistor, and the compensation control circuit includes a seventh transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the sixth transistor is electrically connected to the light emitting control terminal, and a first electrode of the sixth transistor is electrically connected to the second electrode of the driving transistor; a gate electrode of the ninth transistor is electrically connected to the switch control terminal, a first electrode of the ninth transistor is electrically connected to the second electrode of the sixth transistor, and a second electrode of the ninth transistor is electrically connected to the first electrode of the light emitting element; a gate electrode of the driving transistor is electrically connected to the first node;

[0243] A gate electrode of the seventh transistor is electrically connected to the scanning terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to a second electrode of the driving transistor.

[0244] Optionally, the switch control circuit includes a ninth transistor; the driving circuit includes a driving transistor, the first light emitting control circuit includes a fifth transistor, the second light emitting control circuit includes a sixth transistor, and the compensation control circuit includes a seventh transistor; a gate electrode of the ninth transistor is electrically connected to the switch control terminal, a first electrode of the ninth transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the ninth transistor is electrically connected to the first electrode of the fifth transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, and a second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; a gate electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to a first electrode of the sixth transistor; a gate electrode of the sixth transistor is electrically connected to the light emitting control terminal, and a second electrode of the sixth transistor is electrically connected to the second voltage terminal;

[0245] A gate electrode of the seventh transistor is electrically connected to the scanning terminal, a first electrode of the seventh transistor is electrically connected to the first node, and a second electrode of the seventh transistor is electrically connected to a first electrode of the driving transistor. As shown in FIG. 65, based on the pixel circuit shown in FIG. 59, the light emitting element is a light emitting diode E0; the driving circuit includes a driving transistor T0; the energy storage circuit includes a first capacitor C1; A first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the high voltage terminal VDD; The first reset circuit includes a first transistor T1, and the second reset transistor includes a second transistor T2; The gate electrode of the first transistor T1 is electrically connected to the reset control terminal RST, the source electrode of the first transistor T1 is electrically connected to the first initial voltage terminal I1, the drain electrode of the first transistor T1 is electrically connected to the anode of the light emitting diode E0; the cathode of the light emitting diode E0 is electrically connected to the low voltage terminal VSS; the first initial voltage terminal I1 is configured to provide a first initial voltage Vi1; The gate electrode of the second transistor T2 is electrically connected to the reset control terminal RST, the source electrode of the second transistor T2 is electrically connected to the first initial voltage terminal I1, and the drain electrode of the second transistor T2 is electrically connected to the first node N1; The data writing-in circuit includes a third transistor T3 and a fourth transistor T4; The gate electrode of the third transistor T3 is electrically connected to the first control terminal GB, the source electrode of the third transistor T3 is electrically connected to the first data line DT, and the drain electrode of the third transistor T3 is electrically connected to the source electrode of the driving transistor T0; The gate electrode of the fourth transistor T4 is electrically connected to the second control terminal GA, the source electrode of the fourth transistor T4 is electrically connected to the second data line DI, and the drain electrode of the fourth transistor T4 is electrically connected to the source electrode of the driving transistor T0; The first light emitting control circuit includes a fifth transistor T5, the second light emitting control circuit includes a sixth transistor T6, and the compensation control circuit includes a seventh transistor T7; The gate electrode of the fifth transistor T5 is electrically connected to the light emitting control terminal EM, the source electrode of the fifth transistor T5 is electrically connected to the high voltage terminal VDD, and the drain electrode of the fifth transistor T5 is electrically connected to the source electrode of the driving transistor T0; The gate electrode of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source electrode of the sixth transistor T6 is electrically connected to the drain electrode of the driving transistor T0, the drain electrode of the sixth transistor T6 is electrically connected to the anode of the light emitting diode E0; the cathode of the light emitting diode E0 is electrically connected to the low voltage terminal VSS; The gate electrode of the driving transistor T0 is electrically connected to the first node N1; A gate electrode of the seventh transistor T7 is electrically connected to the scanning terminal G1, a source electrode of the seventh transistor T7 is electrically connected to the first node N1, and a drain electrode of the seventh transistor T7 is electrically connected to the drain electrode of the driving transistor T0.

[0246] In the pixel circuit shown in FIG. 65, all transistors are PMOS (P-type metal-oxide-semiconductor) TFTs (thin film transistors).

[0247] In at least one embodiment of the present disclosure, the light emitting diode may be a Micro LED, a Mini LED or an OLED (organic light emitting diode), but is not limited thereto. As shown in FIG. 66, when the pixel circuit shown in FIG. 65 of the present disclosure is in operation, the display cycle includes a first display phase S1 and a second display phase S2; the first display phase S1 includes a first reset time period S11, a first writing-in time period S12 and a first light emitting time period S13 that are successively set; the second display phase S2 includes a second reset time period S21, a second writing-in time period S22 and a second light emitting time period S23 that are successively set; In the first reset time period S11, RST provides a low voltage signal, as shown in 67A, T2 and T1 are turned on, and the gate electrode of T0 and the anode of E0 are reset through Vi1, the residual charge of the anode of E0 is cleared, and T0 can be turned on at the beginning of the first writing-in time period S12; In the first writing-in time period S12, GA provides a low voltage signal, as shown in FIG. 67B, T4 is turned on, DI provides a display data voltage Vdata_I to the gate electrode of T0, and T7 is turned on; At the beginning of the first writing-in time period S12, T0 is turned on to charge C1 to change the potential of N1 until the potential of N1 becomes Vdata_I+Vth, and T0 is turned off; Vth is the threshold voltage of T0; In the first light emitting time period S13, EM outputs a low voltage signal, as shown in FIG. 67C, T5 and T6 are turned on, and T0 drivings E0 to emit light; In the second reset time period S21, after the first time t1, RST outputs a low voltage signal, as shown in FIG. 67D, T1 and T2 are turned on, the gate electrode of T0 and the anode of E0 are reset, and the residual charge of the anode of E0 is cleared, so that before the light emitting time control data voltage Vdata_T is written, the potential of the gate electrode of T0 and the anode voltage of E0 are consistent with those before the display data voltage is written, and the charging time and voltage jump difference are reduced, so that when Vdata_T and Vdata_I have the same voltage value, the driving current difference between the first light emitting time period and the second light emitting time period is reduced, and the brightness difference between the first light emitting time period and the second light emitting time period in the same frame is reduced; wherein, the first time t1 is the duration of the first light emitting time period S21; In the second writing-in time period S22, GB provides a low voltage signal, as shown in FIG. 67E, T3 is turned on, EM outputs a high voltage signal, T5 and T6 are turned off; G1 provides a low voltage signal, T7 is turned on; DT writes the light emitting time control data voltage Vdata_T to the source electrode of T0; At the beginning of the second writing-in time period S22, T0 is turned on, charging C1, changing the potential of N1 until the potential of N1 becomes Vdata_T + Vth, and T0 is turned off; In the second light emitting time period S23, the EM outputs a low voltage signal, as shown in FIG. 67F, and T5 and T6 are turned on; When Vdata_T is a high voltage signal and the gate-source voltage of T0 is greater than Vth, T0 is turned off, E0 does not emit light, and a short-time light emitting is realized, and the light emitting time is t1, so as to perform low grayscale display; When Vdata_T is equal to Vdata_I, Vdata_I+Vth is written to the gate electrode of T0 again, as shown in FIG. 67F, T0 is turned on, and T0 drivings E0 to emit light, achieving long-time light emitting for high grayscale display; the light emitting duration is t1+t2, t2 is the second time, and t2 is the duration of the second light emitting time period S23.

[0248] When the pixel circuit shown in FIG. 65 is in operation, in the first light emitting time period, the driving current Id generated by T0 is K(Vdata_I-Vdd+ ΔVth) 2< ; wherein K is the current coefficient of T0, ΔVth is the difference between the threshold voltage Vth of T0 during threshold voltage compensation and during light emitting, Id is greater than or equal to 0 and less than or equal to Imax, and Imax is the driving current corresponding to the highest grayscale; and Vdd is the voltage value of the high voltage signal provided by VDD.

[0249] When the pixel circuit shown in FIG. 65 is in operation, When high grayscale display is performed, Vdata_T is equal to Vdata_I; When low gray scale display is performed, Vdata_T may be greater than Vdd to ensure that T0 is turned off during the second light emitting time period.

[0250] In the pixel circuit shown in FIG. 65, Vi1-Vdata_I-min is less than Vth, and Vi1-Vss is less than Vled, so as to ensure that after Vi1 is written into N1, T0 can be turned on normally at the beginning of the first writing-in time period to write the display data voltage and compensate the threshold voltage. At the same time, when the anode potential of E0 is reset by Vi1, E0 does not emit light.

[0251] Wherein, Vdata_I-min is the minimum voltage value of the display data voltage, Vss is the voltage value of the low voltage signal provided by VSS, and Vled is the light emitting voltage of E0.

[0252] FIG. 68A is a schematic diagram showing simulation results of the pixel circuit shown in FIG. 66 when performing high grayscale display; FIG. 68B is a schematic diagram of simulation results of the pixel circuit shown in FIG. 66 when performing low grayscale display.

[0253] In FIG. 68A and FIG. 68B, Id is the driving current generated at T0. In at least one embodiment corresponding to FIG. 68A, Vdd is equal to 4.6V, Vss is equal to -3V, Vi1 is equal to -3V, Vdata_I is equal to 2V, and Vdata_T is equal to 2V; In at least one embodiment corresponding to FIG. 68B, Vdd is equal to 4.6V, Vss is equal to -3V, Vi1 is equal to -3V, Vdata_I is equal to 2V, and Vdata_T is equal to 6V.

[0254] The difference between the pixel circuit shown in FIG. 69 and the pixel circuit shown in FIG. 66 is that T7, T2, and T1 are NMOS (N-type metal-oxide-semiconductor) TFTs.

[0255] The pixel circuit shown in FIG. 69 of the present disclosure adopts LTPO (low-temperature polycrystalline oxide) technology, and utilizes the advantage of low leakage current of oxide TFT to reduce the gate leakage of T0 and the anode leakage of E0, that is, T7, T2 and T1 or part of them are changed from PMOS TFT to NMOS TFT; utilizing the advantage of high mobility of PMOS TFT, T4, T0, T5, T6 and T3 are PMOS TFTs, which meets the threshold voltage compensation, current driving requirements and reduces the charging time, thereby further improving the display performance.

[0256] FIG. 70 is a timing diagram of the pixel circuit shown in FIG. 69 of the present disclosure. As shown in FIG. 71, based on the pixel circuit shown in FIG. 60, the light emitting element is a light emitting diode E0; the driving circuit includes a driving transistor T0; the energy storage circuit includes a first capacitor C1; A first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to a low voltage terminal VSS; The first reset circuit includes a first transistor T1, and the second reset transistor includes a second transistor T2; The gate electrode of the first transistor T1 is electrically connected to the reset control terminal RST, the drain electrode of the first transistor T1 is electrically connected to the first initial voltage terminal I1, the sou...

Examples

Embodiment Construction

[0031]The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present disclosure.

[0032]The transistors used in all embodiments of the present disclosure may be transistors, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiment of the present disclosure, in order to distinguish the two electrodes of the transistor except the control electrode, one electrode is called the first electrode and the other electrode is called the second electrode.

[0033]In actu...

Claims

1. A pixel circuit, comprising a driving circuit, a light emitting element, an energy storage circuit and a data writing-in circuit; a control terminal of the driving circuit is electrically connected to a first node, and the driving circuit is configured to generate a driving current to drive the light emitting element under the control of a potential of the first node; a first terminal of the energy storage circuit is electrically connected to the first node, a second terminal of the energy storage circuit is electrically connected to a second node, and the energy storage circuit is configured to store electrical energy; the data writing-in circuit is electrically connected to a writing-in control terminal and a writing-in node respectively, and is configured to sequentially provide a display data voltage and a light emitting time control data voltage to the writing-in node under the control of a writing-in control signal provided by the writing-in control terminal; the writing-in node is the second node; or, the pixel circuit also includes a switch control circuit; the switch control circuit is electrically connected to a switch control terminal, the driving circuit and the light emitting element, respectively, and is configured to control the connection between the driving circuit and the light emitting element under the control of a potential of the switch control terminal; the writing-in node includes a first writing-in node and a second writing-in node; the first writing-in node is the second node, and the second writing-in node is electrically connected to the switch control terminal.

2. The pixel circuit according to claim 1, wherein the writing-in node is the second node; the pixel circuit further comprises a first reset circuit and a second reset circuit; the first reset circuit is electrically connected to the reset control terminal, a reference voltage terminal and the second node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the second node under the control of a reset control signal provided by the reset control terminal during a reset time period set between a time period for writing the display data voltage and a time period for writing the light emitting time control data voltage; the second reset circuit is electrically connected to the reset control terminal, a first initial voltage terminal and the first node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the reset control signal during the reset time period.

3. The pixel circuit according to claim 1, wherein the writing-in node is the second node; the writing-in control terminal includes a first control terminal and a second control terminal; the data line includes a first data line and a second data line; the display cycle of the pixel circuit includes a first writing-in time period and a second writing-in time period which are set successively; the data writing-in circuit is electrically connected to the first control terminal, the second control terminal, the first data line and the second data line respectively, and is configured to write the display data voltage provided by the second data line into the second node under the control of the second control signal provided by the second control terminal in the first writing-in time period, and to write the light emitting time control data voltage provided by the first data line into the second node under the control of the first control signal provided by the first control terminal in the second writing-in time period.

4. The pixel circuit according to claim 1, wherein the writing-in node is the second node; the pixel circuit further comprises a light emitting control circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal, and the second terminal of the driving circuit is electrically connected to a third node; the light emitting control circuit is electrically connected to the light emitting control terminal, the third node and the first electrode of the light emitting element respectively, and is configured to control the connection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal; the second electrode of the light emitting element is electrically connected to the second voltage terminal; or, the first electrode of the light emitting element is electrically connected to the first voltage terminal; the light emitting control circuit is electrically connected to the light emitting control terminal, the second electrode of the light emitting element and the first terminal of the driving circuit respectively, and is configured to control the connection between the second electrode of the light emitting element and the first terminal of the driving circuit under the control of the light emitting control signal; the second terminal of the driving circuit is electrically connected to the second voltage terminal.

5. The pixel circuit according to claim 1, wherein the pixel circuit further comprises a switch control circuit; the writing-in node comprises a first writing-in node and a second writing-in node; the data writing-in circuit comprises a first writing-in sub-circuit and a second writing-in sub-circuit; the writing-in control terminal comprises a first control terminal and a scanning terminal; the first writing-in sub-circuit is electrically connected to the first control terminal, the first data line and the second writing-in node respectively, and is configured to write the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of the first control signal provided by the first control terminal; the second writing-in sub-circuit is electrically connected to the scanning terminal, the second data line and the first writing-in node respectively, and is configured to write the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal provided by the scanning terminal.

6. The pixel circuit according to claim 5, wherein the pixel circuit further comprises a light emitting control circuit; the first terminal of the driving circuit is electrically connected to the first voltage terminal; the second terminal of the driving circuit is electrically connected to the third node; the light emitting control circuit is electrically connected to the light emitting control terminal, the second terminal of the driving circuit and the switch control circuit respectively, and is configured to control the second terminal of the driving circuit to be connected to the switch control circuit under the control of the light emitting control signal provided by the light emitting control terminal; the first terminal of the switch control circuit is electrically connected to the second terminal of the driving circuit through the light emitting control circuit, the second terminal of the switch control circuit is electrically connected to the first electrode of the light emitting element, and the switch control circuit is configured to control the connection between the light emitting control circuit and the first electrode of the light emitting element under the control of the potential of the switch control terminal; the second electrode of the light emitting element is electrically connected to the second voltage terminal.

7. The pixel circuit according to claim 5, wherein the pixel circuit further comprises a light emitting control circuit; the first electrode of the light emitting element is electrically connected to the first voltage terminal; the first terminal of the driving circuit is electrically connected to a third node; a first terminal of the switch control circuit is electrically connected to the second electrode of the light emitting element, a second terminal of the switch control circuit is electrically connected to the first terminal of the driving circuit through the light emitting control circuit, and the switch control circuit is configured to control the connection between the second electrode of the light emitting element and the light emitting control circuit under the control of the potential of the switch control terminal; the light emitting control circuit is electrically connected to the light emitting control terminal, the switch control circuit and the first terminal of the driving circuit respectively, and is configured to control the switch control circuit to be connected to the first terminal of the driving circuit under the control of the light emitting control signal provided by the light emitting control terminal; the second terminal of the driving circuit is electrically connected to the second voltage terminal.

8. The pixel circuit according to claim 5, further comprising an initialization circuit and a voltage maintenance circuit; wherein the initialization circuit is electrically connected to the second control terminal, the second initial voltage terminal and the second writing-in node respectively, and is configured to write the second initial voltage provided by the second initial voltage terminal into the second writing-in node under the control of the second control signal provided by the second control terminal; the voltage maintaining circuit is electrically connected to the switch control terminal and is configured to maintain a potential of the switch control terminal.

9. The pixel circuit according to claim 4, 6 or 7, further comprising a compensation control circuit and a voltage control circuit; wherein the compensation control circuit is electrically connected to the scanning terminal, the first node and the third node respectively, and is configured to control the connection between the first node and the third node under the control of the scanning signal provided by the scanning terminal; the voltage control circuit is electrically connected to the light emitting control terminal, the reference voltage terminal and the second node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the second node under the control of the light emitting control signal provided by the light emitting control terminal.

10. The pixel circuit according to claim 4, 6 or 7, wherein the light emitting element is an inorganic light emitting diode, a width-to-length ratio of a transistor included in the light emitting control circuit is greater than 1, and a width-to-length ratio of a transistor included in the driving circuit is greater than 0.5.

11. The pixel circuit according to any one of claims 5 to 7, wherein the light emitting element is an inorganic light emitting diode, a width-to-length ratio of a transistor included in the switch control circuit is greater than 1, and a width-to-length ratio of a transistor included in the driving circuit is greater than 0.5.

12. The pixel circuit according to claim 1, wherein the energy storage circuit comprises a storage capacitor; the light emitting element is an inorganic light emitting diode; a capacitance value of the storage capacitor is greater than 3 times a gate-source capacitance of the transistor in the driving circuit.

13. The pixel circuit according to claim 2, wherein the first reset circuit comprises a first transistor, and the second reset circuit comprises a second transistor; a gate electrode of the first transistor is electrically connected to the reset control terminal, a first electrode of the first transistor is electrically connected to the reference voltage terminal, and a second electrode of the first transistor is electrically connected to the second node; a gate electrode of the second transistor is electrically connected to the reset control terminal, a first electrode of the second transistor is electrically connected to the first initial voltage terminal, and a second electrode of the second transistor is electrically connected to the first node.

14. The pixel circuit according to claim 3, wherein the data writing-in circuit comprises a third transistor and a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the second node; a gate electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the second node.

15. The pixel circuit according to claim 1, wherein the data writing-in circuit comprises a third transistor; a gate electrode of the third transistor is electrically connected to the scanning terminal, a first electrode of the third transistor is electrically connected to the data line, and a second electrode of the third transistor is electrically connected to the second node; the data line is configured to provide display data voltage and light emitting time control data voltage in time division manner.

16. The pixel circuit according to claim 6, wherein the first writing-in sub-circuit comprises a third transistor, and the second writing-in sub-circuit comprises a fourth transistor; a gate electrode of the third transistor is electrically connected to the first control terminal, a first electrode of the third transistor is electrically connected to the first data line, and a second electrode of the third transistor is electrically connected to the second writing-in node; a gate electrode of the fourth transistor is electrically connected to the second control terminal, a first electrode of the fourth transistor is electrically connected to the second data line, and a second electrode of the fourth transistor is electrically connected to the first writing-in node.

17. The pixel circuit according to claim 4, wherein the light emitting control circuit comprises a fifth transistor; and the driving circuit comprises a driving transistor; a second electrode of the driving transistor is electrically connected to the third node; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to a second electrode of the driving transistor, and a second electrode of the fifth transistor is electrically connected to the first electrode of the light emitting element; a gate electrode of the driving transistor is electrically connected to the first node, and a first electrode of the driving transistor is electrically connected to the first voltage terminal; or, the first electrode of the light emitting element is electrically connected to the first voltage terminal, the gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, the first electrode of the fifth transistor is electrically connected to the second electrode of the light emitting element, and the second electrode of the fifth transistor is electrically connected to the first electrode of the driving transistor; the gate electrode of the driving transistor is electrically connected to the first node, and the second electrode of the driving transistor is electrically connected to the second voltage terminal.

18. The pixel circuit according to claim 9, wherein the compensation control circuit comprises a sixth transistor, and the voltage control circuit comprises a seventh transistor; a gate electrode of the sixth transistor is electrically connected to the scanning terminal, a first electrode of the sixth transistor is electrically connected to the first node, and a second electrode of the sixth transistor is electrically connected to the third node; a gate electrode of the seventh transistor is electrically connected to the light emitting control terminal, a first electrode of the seventh transistor is electrically connected to a reference voltage terminal, and a second electrode of the seventh transistor is electrically connected to the second node.

19. The pixel circuit according to claim 6, wherein the light emission control circuit comprises a fifth transistor; the switch control circuit comprises an eighth transistor; and the driving circuit comprises a driving transistor; a gate electrode of the driving transistor is electrically connected to the first node, a first electrode of the driving transistor is electrically connected to the first voltage terminal, and a second electrode of the driving transistor is electrically connected to the third node; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, a first electrode of the fifth transistor is electrically connected to the third node, and a second electrode of the fifth transistor is electrically connected to a first electrode of the eighth transistor; a gate electrode of the eighth transistor is electrically connected to the switch control terminal, and a second electrode of the eighth transistor is electrically connected to the first electrode of the light emitting element.

20. The pixel circuit according to claim 7, wherein the light emitting control circuit comprises a fifth transistor; the switch control circuit comprises an eighth transistor; and the driving circuit comprises a driving transistor; a gate electrode of the eighth transistor is electrically connected to the switch control terminal, a first electrode of the eighth transistor is electrically connected to the second electrode of the light emitting element, and a second electrode of the eighth transistor is electrically connected to a first electrode of the fifth transistor; a gate electrode of the fifth transistor is electrically connected to the light emitting control terminal, and a second electrode of the fifth transistor is electrically connected to a first electrode of the driving transistor; a gate electrode of the driving transistor is electrically connected to the first node, and a second electrode of the driving transistor is electrically connected to the second voltage terminal.

21. The pixel circuit according to claim 8, wherein the initialization circuit comprises a ninth transistor, the energy storage circuit comprises a first capacitor; and the voltage maintenance circuit comprises a second capacitor; a gate electrode of the ninth transistor is electrically connected to the second control terminal, a first electrode of the ninth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the ninth transistor is electrically connected to the second writing-in node; a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the second node; a first terminal of the second capacitor is electrically connected to the switch control terminal, and a second terminal of the second capacitor is electrically connected to a DC voltage terminal.

22. A driving method, applied to the pixel circuit according to any one of claims 1 to 21, the driving method comprises: generating, by the driving circuit, the driving current for driving the light emitting element; providing, by the data writing-in circuit, under the control of the writing-in control signal provided by the writing-in control terminal, the display data voltage and the light emitting time control data voltage to the writing-in node successively.

23. The driving method according to claim 22, wherein the writing-in node is the second node; the pixel circuit further comprises a first reset circuit and a second reset circuit; the display cycle of the pixel circuit comprises a first display phase and a second display phase which are arranged successively, the first display phase comprises a first reset time period, and the second display phase comprises a second reset time period; the driving method comprises: in the first reset time period and the second reset time period, writing, by the first reset circuit, the reference voltage into the second node under the control of the reset control signal, and writing, by the second reset circuit, the first initial voltage into the first node under the control of the reset control signal.

24. The driving method according to claim 23, wherein the first display phase includes a first writing-in time period arranged after the first reset time period, and the second display period includes a second writing-in time period arranged after the second reset time period; the driving method comprises: in the first writing-in time period, providing, by the data writing-in circuit, a display data voltage to the second node under the control of a writing-in control signal; in the second writing-in period, providing, by the data writing-in circuit, the light emitting time control data voltage to the second node under the control of a writing-in control signal.

25. The driving method according to claim 22, wherein the writing-in node is the second node; the pixel circuit further comprises a first reset circuit and a second reset circuit; the display cycle comprises a first display phase and A second display phases; A is an integer greater than 1, and a is a positive integer less than but equal to A; the first display stage is set before the A second display phases; the first display phase comprises a first reset time period and a first writing-in time period which are set in sequence, and an ath second display phase comprises an ath second reset time period and an ath second writing-in time period which are set in sequence; the driving method comprises: in the first reset time period and the ath second reset time period, writing, by the first reset circuit, the reference voltage into the second node under the control of the reset control signal, and writing, by the second reset circuit, the first initial voltage into the first node under the control of the reset control signal; in a first writing-in period, providing, by the data writing-in circuit, a display data voltage to the second node under the control of a writing-in control signal; in the ath second writing-in period, providing, by the data writing-in circuit, the ath light emitting time control data voltage to the second node under the control of the writing-in control signal.

26. The driving method according to claim 22, wherein the first display phase includes a first writing-in time period, the second display period includes a second writing-in time period; the pixel circuit further includes a switch control circuit; the writing-in node includes a first writing-in node and a second writing-in node; the data writing-in circuit includes a first writing-in sub-circuit and a second writing-in sub-circuit; the driving method includes: in a first writing-in time period, writing, by the second writing-in sub-circuit, the display data voltage provided by the second data line into the first writing-in node under the control of the scanning signal; in the second writing-in time period, writing, by the first writing-in sub-circuit, the light emitting time control data voltage provided by the first data line into the second writing-in node under the control of the first control signal provided by the first control terminal.

27. A display device comprising the pixel circuit according to any one of claims 1 to 21.

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