Methods and apparatuses for performing quantisation noise suppression

Abstract

Embodiments described herein relate to a method and apparatuses for performing quantization noise suppression in a first frequency band of an input signal. A signal processing system comprises a first signal path configured to receive a first digital signal and output a second analog signal, wherein the first signal path comprises: a first DAC configured to receive the first digital signal and output a first analog signal, and a first filter configured to generate a second analog signal Xa,f by filtering the first analog signal to remove components in the first frequency band. The signal processing system further comprises a second signal path configured to receive the first digital signal and output a third analog signal, ya,f, wherein the second signal path comprises: a second DAC configured to receive a second digital signal derived from the first digital signal wherein the second digital signal consists of frequencies within the first frequency band; a signal combination block configured to combine the second analog signal, xa,f, and the third analog signal, ya,f, to generate a fourth analog signal, z; and an output processing block configured to derive a fifth analog signal from the fourth analog signal for outputting to a transmitting block.

Description

[0001] METHODS AND APPARATUSES FOR PERFORMING QUANTISATION NOISE SUPPRESSION

[0002] TECHNICAL FIELD

[0003] Embodiments described herein relate to methods and apparatuses for performing quantization noise suppression in a first frequency band of an input signal.

[0004] BACKGROUND

[0005] In 3GPP Rel-18 a Sub-band Full Duplex (SBFD) proposal is discussed in which Frequency Division Duplex (FDD) transmission would be performed during a wideband Time Division Duplex (TDD) slot. Figure 1 illustrates an example carrier structure for Frequency Range 1 (FR1) frequencies in which DL-UL-DL is performed in a 100 MHz TDD slot, with frequency allocation of roughly 40-20-40 MHz to the DL-UL-DL slots.

[0006] Figure 2 illustrates example spectra of OFDM signals configured in the SBFD DL-UL- DL carrier structure of Figure 1.

[0007] In such a scenario, the large DL signals will affect the UL band through multiple mechanisms. Some of the most important contributors to this are:

[0008] • Effects in the Transmitter o Adjacent Channel Leakage Ratio (ACLR) through nonlinearities in the transmitter, mainly the power amplifier (PA) o Transmitter noise, mainly quantization noise from the Digital to Analog converter (DAC) o Frequency spreading due to CREST-factor reduction of the Orthogonal Frequency Division Multiplexing (OFDM) signal o Intermodulation in the DAC

[0009] • Effects in the Receiver o Large signal DL intermodulation due to receiver front end nonlinearities, i.e. limited third order input intercept point (RX I IPS) o Reciprocal mixing of strong DL with local oscillator phase noise in down conversion. o Increased noise figure due to automatic gain control (AGC) backing off receiver gain to mitigate receiver distortion. o Limited Adjacent Channel Selectivity (ACS) when doing Inverse Fast Fourier Transforms (IFFTs).

[0010] Existing solutions to reduce the quantization noise level in the UL band may be to increase the Effective Number of Bits (ENOB) and / or the sampling frequency of the DAC. However, both of these techniques are power hungry and constitute significant design challenges.

[0011] SUMMARY

[0012] The aforementioned mechanisms by which the large amplitude DL signals may affect the UL band will all, in various ways, have a negative impact on the UL Signal to Noise Ratio (SNR) when operating in SBFD. Embodiments described herein aim at mitigating SNR reduction due to transmitter quantization noise in UL sub-band.

[0013] According to some embodiments there is provided a method, performed by a signal processing system, for performing quantization noise suppression in a first frequency band of an input signal. The method comprises inputting a first digital signal, x, into a first DAC to generate a first analog signal, xa; generating a second analog signal xa,f by filtering the first analog signal to remove components in the first frequency band; generating a third analog signal, ya.f, by inputting a second digital signal derived from the first digital signal into a second DAC, wherein the second digital signal consists of frequencies within the first frequency band; combining the second analog signal, xa,f, and the third analog signal, ya.f, to generate a fourth analog signal, z; and processing the fourth analog signal, z, to provide a fifth analog signal zout for coupling to an input of a transmitting block.

[0014] According to some embodiments there is provided signal processing system for performing quantization noise suppression in a first frequency band of an input signal. The signal processing system comprises a first signal path configured to receive a first digital signal and output a second analog signal. The first signal path comprises: a first DAC configured to receive the first digital signal and output a first analog signal, and a first filter configured to generate a second analog signal xa,f by filtering the first analog signal to remove components in the first frequency band; The signal processing system comprises a second signal path configured to receive the first digital signal and output a third analog signal, ya,f. The second signal path comprises: second DAC configured to receive a second digital signal derived from the first digital signal wherein the second digital signal consists of frequencies within the first frequency band; a signal combination block configured to combine the second analog signal, xa,f, and the third analog signal, ya,f, to generate a fourth analog signal, z; and an output processing block configured to derive a fifth analog signal from the fourth analog signal for outputting to a transmitting block.

[0015] According to some embodiments there is provided a signal processing system for performing quantization noise suppression in a first frequency band of an input signal. The signal processing system comprises processing circuitry configured to cause the signal processing system to: input a first digital signal, x, into a first DAC to generate a first analog signal, xa; generate a second analog signal xa,f by filtering the first analog signal to remove components in the first frequency band; generate a third analog signal, ya,f, by inputting a second digital signal derived from the first digital signal into a second DAC, wherein the second digital signal consists of frequencies within the first frequency band; and combine the second analog signal, xa,f, and the third analog signal, ya.f, to generate a fourth analog signal, z; and output the fourth analog signal, z, for coupling to an input of a power amplifier.

[0016] According to some embodiments there is provided a base station comprising a signal processing system as described above.

[0017] According to some embodiments there is provided a user equipment comprising a signal processing system as described above.

[0018] Embodiments described herein are therefore able to offer significant reduction of transmitter quantization noise in the first frequency band (e.g. the sensitive UL band in an SFBD carrier structure). Embodiments described herein also allow for lower power consumption and reduced circuit complexity compared to using a single DAC with high enough dynamic range to meet the noise requirements in the first frequency band. Embodiments described herein are also integrated easily with a two-stage frequency selective DPD. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a better understanding of the embodiments of the present disclosure, and to show how it may be put into effect, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0020] Figure 1 illustrates an example carrier structure;

[0021] Figure 2 illustrates example spectra of OFDM signals configured in the SBFD DL-UL-DL carrier structure of Figure 1 ;

[0022] Figure 3 illustrates a method, performed by a signal processing system, for performing quantization noise suppression in a first frequency band of an input signal;

[0023] Figure 4 illustrates a signal processing system according to some embodiments;

[0024] Figure 5 illustrates an example implementation of the signal processing system;

[0025] Figure 6 illustrates an example implementation of the signal processing system in which a single stage DPD architecture is utilised;

[0026] Figure 7 illustrates an example implementation of the signal processing system in which a two-stage DPD architecture is utilised;

[0027] Figure 8 is a graph illustrating the transfer function for the filter 403 when the filter 403 is realised as a 5th order elliptic;

[0028] Figure 9 illustrates an example implementation of the signal processing system for use in a scenario to suppress quantization noise in a sensitive frequency band, such as the bands used for earth exploration services, EESS;

[0029] Figure 10 illustrates another example implementation of the signal processing system for use in a scenario to suppress quantization noise in a sensitive frequency band, such as the bands used for EESS; Figure 11 illustrates a network node in accordance with some embodiments;

[0030] Figure 12 is a block diagram illustrating a signal processing system according to some embodiments;

[0031] Figure 13 illustrates a UE in accordance with some embodiments;

[0032] Figure 14 illustrates the output of a high pass filter;

[0033] Figure 15 illustrates the combined BB TX signal from both the first DAC and the second DAC as well as total quantization noise are shown where > 10 dB suppression of quantization noise within UL sub-band is attained;

[0034] Figure 16 shows the output of the PA with and without using the 2 stage frequency selective DPD.

[0035] DETAILED DESCRIPTION

[0036] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. All references to a / an / the element, apparatus, component, means, step, etc. are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step. Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever appropriate. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following description.

[0037] The following sets forth specific details, such as particular embodiments or examples for purposes of explanation and not limitation. It will be appreciated by one skilled in the art that other examples may be employed apart from these specific details. In some instances, detailed descriptions of well-known methods, nodes, interfaces, circuits, and devices are omitted so as not obscure the description with unnecessary detail. Those skilled in the art will appreciate that the functions described may be implemented in one or more nodes using hardware circuitry (e.g., analog and / or discrete logic gates interconnected to perform a specialized function, ASICs, PLAs, etc.) and / or using software programs and data in conjunction with one or more digital microprocessors or general purpose computers. Nodes that communicate using the air interface also have suitable radio communications circuitry. Moreover, where appropriate the technology can additionally be considered to be embodied entirely within any form of computer- readable memory, such as (ROM, EEPROM, Flash memory, a memory disc, RAM etc.) solid-state memory, magnetic disk, or optical disk containing an appropriate set of computer instructions that would cause a processor to carry out the techniques described herein.

[0038] Hardware implementation may include or encompass, without limitation, digital signal processor (DSP) hardware, a reduced instruction set processor, hardware (e.g., digital or analogue) circuitry including but not limited to application specific integrated circuit(s) (ASIC) and / or field programmable gate array(s) (FPGA(s)), and (where appropriate) state machines capable of performing such functions.

[0039] Certain aspects of the present disclosure and their embodiments may provide solutions to these or other challenges. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step.

[0040] Particular embodiments are described more fully with reference to the accompanying drawings. Other embodiments, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the embodiments set forth herein; rather, these embodiments are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0041] Embodiments described herein may be utilised for example to generate an analog TX signal for use in SBFD. In particular, embodiments described herein may utilising two DACs, e.g. one high power, high bandwidth to generate the signal content for all frequencies except for frequencies within UL band, and one low power low bandwidth DAC to generate signal for the UL frequencies. It will be appreciated that high power DAC will produce more quantization noise than the low power DAC. Quantization noise may then be suppressed by filtering out, for example, with a high-pass filter, the UL portion of the signal from the high power DAC output signal, which is then combined with the signal from the low power DAC and used as transmit signal during a SBFD transmission.

[0042] Herein, a first frequency band may comprise any frequency band for which quantisation noise may require more suppression than other frequency bands. Such first frequency bands may for example comprise frequency bands which are not to be used to carry data or information in signal that is then transmitted.

[0043] For example, the first frequency band may be an uplink frequency band in a Sub-band Full Duplex, SBFD, format. In some examples, the first frequency band may consist of out-of-band components of the input signal. In some examples, the first frequency band may consist of earth exploration services (EESS) band frequencies.

[0044] Figure 3 illustrates a method, performed by a signal processing system, for performing quantization noise suppression in a first frequency band of an input signal.

[0045] The method 300 may be performed by a network node, which may comprise a physical or virtual node, and may be implemented in a computing device or server apparatus and / or in a virtualized environment, for example in a cloud, edge cloud or fog deployment. Examples of network nodes include, but are not limited to, access points (APs) (e.g., radio access points), base stations (BSs) (e.g., radio base stations, Node Bs, evolved Node Bs (eNBs) and NR NodeBs (gNBs)), O-RAN nodes or components of an O-RAN node (e.g., O-RU, O-DU, O-CU). The method of Figure 3 may be performed by the network node 1100 as described with reference to Figure 11.

[0046] Step 301 comprises inputting a first digital signal, x, into a first DAC to generate a first analog signal, xa. In some examples, the method of Figure 3 may further comprise applying a delay to the first digital signal before inputting the first signal into the first DAC. The delay may be applied such that the first digital signal is time aligned with a second digital signal that is derived from the first digital signal. The first digital signal may be derived by performing a first stage of digital predistortion on the input signal.

[0047] Step 302 comprises generating a second analog signal xa,f by filtering the first analog signal to remove components in the first frequency band.

[0048] Step 303 comprises generating a third analog signal, ya.f, by inputting a second digital signal derived from the first digital signal into a second DAC, wherein the second digital signal consists of frequencies within the first frequency band.

[0049] In some examples, step 303 further comprises filtering the output of the second DAC to suppress signal components having frequencies outside of the first frequency band.

[0050] For example, spectrum replicas may occur when the sampling rate of the second DAC is low, which could fall outside of the first frequency band, and to reduce these filtering may be performed. However, in some examples, the sampling rate of the second DAC is high enough, and the filtering may not be required.

[0051] The second digital signal may be derived from the first digital signal by filtering the first digital signal to remove frequencies outside of the first frequency band. In examples in which a two stage DPD is implemented, the second digital signal may be derived from the first digital signal further by: performing a second stage of digital predistortion on the filtered first digital signal to generate the second digital signal. However, in some examples, a single stage DPD may be implemented.

[0052] In some examples, wherein the second digital signal is derived from the first digital signal further by performing downsampling to provide the second digital signal with a sampling rate equal to or greater than the bandwidth of the first frequency band.

[0053] Step 304 comprises combining the second analog signal, xa,f, and the third analog signal, ya,f, to generate a fourth analog signal, z. In some examples, a delay may be applied at any point in the signal paths such that the second analog signal, xa,f and the third analog signal ya,f are time aligned.

[0054] In other words, the first digital signal is effectively separated in the frequency domain and fed to two DACs to generate the fourth analog signal. The task of the first DAC is effectively to generate the components of the fourth analog signal for all frequencies except those in the first frequency band, and the task of the second DAC is to generate the components of the fourth analog signal for frequencies in the first frequency band.

[0055] Step 305 comprises processing the fourth analog signal, z, to generate a fifth analog signal zout for coupling to an input of a transmitting block. The transmitting block may comprise one or more of a power amplifier and one or more output antennas.

[0056] It will be appreciated that one or more processing steps on the fourth analog signal, z, to generate the fifth analog signal for input into the transmitting block. The one or more processing steps may comprise one or more of: filtering to suppress one or more frequencies in the fourth analog signal, varying gain of the fourth analog signal, and applying up-conversion to the fourth analog signal such that the fifth analog signal is centered on a carrier frequency.

[0057] As the first DAC is dealing with the components outside of the first frequency band, the first DAC may have to support a higher output power than the second DAC. The first DAC may also have to support a higher bandwidth that the second DAC. The second DAC will only have to support low output power and / or low bandwidth as it is only required to produce the components within the first frequency band.

[0058] Since the first DAC is to output larger amplitude signals it may be required to support a large output signal, which means that the quantization noise generated by the first DAC can be significant. Significant quantisation noise may, for example, mean that the quantisation noise is the dominating noise source at some frequencies. A “large output” may for example indicate that the output generates a transmit signal with the peak output power required by the wireless system.

[0059] Typically, the quantisation noise is one of the main sources of noise in the transmitter. The first DAC is therefore followed by filter (e.g. step 302) to suppress the quantisation noise in the sensitive first frequency band. The first DAC produces higher quantisation noise in the first frequency band than the second DAC.

[0060] The first DAC may have a higher, lower or the same sampling rate as the second DAC.

[0061] For an SFBD example in which the first frequency band comprises an UL band, the second DAC may only generate the signal part for frequencies located in the UL band. I n other words, the output of the second DAC may only consist of out of band linearization signal from the DPD, which can be much lower (< -25dB) than the DL signal. Since the second DAC therefore only needs to support a low output power, its quantization noise power can be reduced without high requirements on DAC dynamic range. The analog signal from the first DAC may be filtered in the base band to suppress the quantization noise at the UL frequencies and then combined with the analog signal output from the second DAC (which may also be filtered). The combined signal from the two DACs, i.e. the filtered signal from the first DAC and the signal from the second DAC can then be used as the analog input signal to transmitter.

[0062] Figure 4 illustrates a signal processing system 400 according to some embodiments. The signal processing system 400 may be configured to perform the method as described above with reference to Figure 3. The signal processing system 400 may be comprised within a radio access network node, for example, a base station or a wireless device (e.g. a user equipment (UE)). The signal processing system 400 may be comprised within a network node 1100 as described with reference to Figure 11 .

[0063] The signal processing system 400 comprises a first signal path 401 configured to receive a first digital signal, x and output a second analog signal, xa,f.

[0064] The first signal path comprises a first DAC 402 configured to receive the first digital signal, x, and output a first analog signal, xa.

[0065] The first signal path 401 further comprises a first filter 403 configured to generate a second analog signal xa,f by filtering the first analog signal, xa, to remove components in the first frequency band.

[0066] The signal processing system 400 further comprises a second signal path 404 configured to receive the first digital signal, x, and output a third analog signal, ya,f.

[0067] The second signal path comprises a second DAC 405 configured to receive a second digital signal, y, derived from the first digital signal, x, wherein the second digital signal consists of frequencies within the first frequency band. The second signal path may comprise a processing block configured to derive the second digital signal from the first digital signal. The signal processing system further comprises a signal combination block 407 configured to combine the second analog signal, xa,f, and the third analog signal, ya,f, to generate a fourth analog signal, z.

[0068] The signal processing system further comprises an output processing block 408 configured to derive a fifth analog signal, zout from the fourth analog signal for outputting to a transmitting block 409. The transmitting block 409 may comprise one or more of: a power amplifier or one or more output antennas.

[0069] It will be appreciated that the signal processing system 400 (for example, within the first and second signal paths 401 and 404) may comprise one or more other components not illustrated in Figure 4.

[0070] Similarly as described above with reference to Figure 3, the first DAC 402 may have a higher output power than the second DAC 405. The first DAC 402 may have a higher or a lower sampling rate than the second DAC 405. The first DAC 402 may produce higher quantization noise in the first frequency band than the second DAC 405.

[0071] Figure 5 illustrates an example implementation of the signal processing system 400. This example of the signal processing system 400 may be implemented as a homodyne transmitter operating in SBFD. Therefore, the first frequency band may comprise the UL band in SBFD. It will be appreciated that in SBFD there may be a very low frequency separation between UL and DL. For example, the frequency separation between UL and DL may be the ISGB (Inter-subband Guard band) defined by a standard (3GPP). For example, in an FR1 100 MHz, carrier divided into DL / ISGB / UL / ISGB / DL, this ISGB is 5 PRBs which corresponds to 1.8 GHz (30 kHz Subcarrier Spacing (SCS) numerology). In some examples, the separation between UL and DL may be less than the bandwidth of either the UL band or the DL band.

[0072] In this example, it is assumed that the UL band is centred at the base band frequencies. However, it will be appreciated that this may not always be the case, and there may be different combinations of filters and / or frequency shifters employed to enable the first signal path and the second signal path to output appropriate signals.

[0073] In this example, the first filter 403 comprises a high pass filter. In the SBFD example, the first filter 403 therefore suppresses the frequency components in the UL band and passes the frequency components in the DL bands. A requirement to successfully suppress the quantization noise from the first DAC 402, while still being able to suppress PA distortion in the UL band is that the first filter 403 (e.g. the HP filter) has a frequency selectivity that is high enough to effectively suppress quantization noise in UL band, while still not significantly attenuating DL band frequencies. The attenuation and phase shift of the first filter 403 at DL frequencies can be compensated for with a digital filter having the opposite characteristic in the DL band. This may result in a PA signal that is closer to the characteristic expected by any preceding DPD stage (e.g. as illustrated in Figure 6), and the cancellation in the UL band will then be improved.

[0074] In this example, the second signal path further comprises a second filter 501 configured to filter the output of the second DAC 405 to suppress signal components having frequencies outside of the first frequency band. For the SFBD example, this second filter 501 therefore suppresses frequency components in DL band.

[0075] For example, when not operating in SBFD, the second DAC 405 may be turned off and the first filter 403 may be bypassed.

[0076] Figure 6 illustrates an example implementation of the signal processing system 400 in which a single stage DPD architecture is utilised. Figure 6 illustrates the processing block 406, the output processing block 408 and the transmitting block 409 in more detail.

[0077] In this example, the first processing block 406 comprises a downsampler 601. The downsampler 601 may be configured to provide the second digital signal, y, with a sampling rate equal to or greater than the bandwidth of the first frequency band.

[0078] In this example, the first processing block 406 also comprises a third filter 602. The third filter 602 may be configured to filter the first digital signal, x, to suppress frequencies outside of the first frequency band. It will be appreciated that for the SFBD example in which the UL band is a base band, the third filter 602 may comprise a low pass filter.

[0079] In the example of Figure 6 the signal processing system further comprises a first stage of digital predistortion, DPD, 603. The first stage DPD 603 may be configured to receive the input signal, Sm and output the first digital signal, x. It will be appreciated that the first stage DPD 603 may be configured to compensate for any non-linearities in the transmitting block 409 in order to provide an output signal, sout that is representative of the input signal Sm.

[0080] In the example of Figure 6, the first signal path 401 further comprises a delay block 604 configured to delay to the first digital signal before inputting the first digital signal into the first DAC 402. It will be appreciated that it may be desirable to time align the first signal path 401 and the second signal path 404. However, as the processing steps performed in each path may be different, the delay block 604 may be introduced in order to account for any delay caused by additional processing steps performed in the second signal path 404.

[0081] In this example, the output processing block 408 is configured to perform one or more processing steps on the fourth analog signal, z, to generate the fifth analog signal input. In this example, the one or more processing steps may be performed in the TX BB path 605 and may comprise one or more of: filtering to suppress one or more frequencies in the fourth analog signal, varying gain applied to the fourth analog signal, and applying up-conversion to center the fifth analog signal on a carrier frequency. The IQ mixer 606 upconverts and combines the complex base band signal received from the signal combination block 407 to a real signal at a carrier frequency.

[0082] In this example, the transmitting block 409 comprises a PA 607 and an antenna 608. The remaining elements of Figure 6 are the same as those illustrated in Figure 5.

[0083] Figure 7 illustrates an example implementation of the signal processing system 400 in which a two-stage DPD architecture is utilised. In this example, the first signal path 401 , the output processing block 408 and the transmitting block 409 are the same as illustrated in Figure 6.

[0084] However, in this example, the first processing block 406 further comprises a second stage of digital predistortion 701 configured to receive the filtered first digital signal to generate the second digital signal. It will be appreciated that the second stage of digital predistortion 701 may be configured to also receive the input signal x as an input. The input signal x may be utilized b the second stage of predistortion to construct a DPD model or generate a look-up table. The Two-stage frequency-selective DPD further suppresses non-linear distortion falling within a specific portion of spectrum. For example, SBFD may benefit from two-stage frequency-stage DPD by targeting the UL band for non-linear distortion suppression.

[0085] Embodiments described herein help to support the two-stage frequency-selective DPD by providing suppression through the first DAC 402 (with relaxed quantization noise requirements) while 2ndstage narrowband DPD output is fed through the second DAC 405.

[0086] Since the outputs of the two DPD stages are passed to the PA through two different DACs and they are combined as analogue signals, there is no need to align the rates of these two outputs. Therefore, an up-sampler and an anti-aliasing filter after the second stage DPD may be omitted. Moreover, the first stage DPD signal (e.g. within the UL subband) may not need to be subtracted in the digital domain when combing two stages DPD, instead, this may be done effortlessly by the analog high-pass filter 403. Consequently, a digital high pass filter may be avoided in combining the two DPD stages. This saves computational resources and delay in the digital front end.

[0087] It will be appreciated, that for all of embodiments illustrated in Figures 4 to 7 there may be one or more requirements on the first DAC 402 and the second DAC 405.

[0088] For the first DAC 402, the quantization noise requirements may be relaxed when compared to the very stringent requirements that would be imposed by a transceiver solution enabling SBFD transmissions using a single DAC. The lower quantisation noise requirements allow for a design with lower effective number of bits (ENOB), and / or lower sampling rate.

[0089] For the second DAC 405 the quantization noise level may need to be significantly lower (e.g. more than 10dB lower) than the quantisation noise level (measured in power spectral density) output by the first DAC 402. This is feasible since the output power of the second DAC 405 can be significantly relaxed compared to the first DAC 402. The Sampling rate for the second DAC 405 may also be lower than the sampling rate of the first DAC 402.

[0090] Figure 1 as described above illustrates the SBFD proposal for frequency range 1 (FR1) (e.g. sub- 6GHz frequency range), which contains frequency information about the proposed SBFD carrier structure (Downlink (DL), Guard Band (GB), Uplink (UL), GB, DL). It will be appreciated that there may be some requirements on filter 403. In these embodiments the filter 403 is realised as a high pass filter. Table 1 summarizes an indicative specification, derived from carrier structure and DAC output power difference for DL and UL signal frequencies. A rather relaxed maximum transfer function in stop band can be accepted since the noise contribution power falling on the UL will be the integrated power over the stop band.

[0091] Table 1 : Specification of HP filter

[0092] Figure 8 is a graph illustrating the transfer function for the filter 403 when the filter 403 is realised as a 5th order elliptic HP filter. A 5thorder elliptic HP filter, as illustrated in Figure 8, produces a transfer function that is well below the required suppression in the stopband and with very low pass band insertion loss and band ripple, as compared to the approximated requirements from table 1 .

[0093] As previously described, there are scenarios other than SFBD in which the embodiments described herein may be utilised to suppress quantization noise for a particular part of the frequency domain. For example, the system illustrated in Figures 4 to 7 may be utilised to reduce out of band quantization noise in a homodyne transmitter. A low bandwidth high power first DAC 402 may then be used for the in-band signal and the a wideband low power second DAC 405 for the out-of-band signals.

[0094] Figure 9 illustrates an example implementation of the signal processing system 400 for use in a scenario to suppress quantization noise in a sensitive frequency band, such as the bands used for earth exploration services (EESS).

[0095] In this example, the output of a high power low bandwidth first DAC 402 is filtered using a first low pass filter 403. The first low pass filter removes the EESS band frequencies from the signal in the first signal path 401. The output of a low power high bandwidth second DAC 405 is filtered using a second low pass filter 501. The second low pass filter 501 has a higher cut-off frequency than the first low pass filter, and does not filter out the EESS band frequencies from the second signal path 404.

[0096] Figure 10 illustrates another example implementation of the signal processing system 400 for use in a scenario to suppress quantization noise in a sensitive frequency band, such as the bands used for earth exploration services (EESS).

[0097] In this example, the output of a high power high bandwidth first DAC 402 is filtered using a first band stop filter 403. The first band stop filter 403 removes the EESS band frequencies from the signal in the first signal path 401.

[0098] The output of a lower power high bandwidth second DAC 405 is filtered using a band pass filter 405. The band pass filter 405 filters out all frequencies other than the EESS band frequencies in the second signal path 404.

[0099] Figure 11 illustrates a network node 1100 in accordance with some embodiments. As used herein, network node refers to equipment capable, configured, arranged and / or operable to communicate directly or indirectly with a UE and / or with other network nodes or equipment, in a telecommunication network. Examples of network nodes include, but are not limited to, access points (APs) (e.g., radio access points), base stations (BSs) (e.g., radio base stations, Node Bs, evolved Node Bs (eNBs) and NR NodeBs (gNBs)), O-RAN nodes or components of an O-RAN node (e.g., 0-Rll, 0-Dll, O-CU).

[0100] Base stations may be categorized based on the amount of coverage they provide (or, stated differently, their transmit power level) and so, depending on the provided amount of coverage, may be referred to as femto base stations, pico base stations, micro base stations, or macro base stations. A base station may be a relay node or a relay donor node controlling a relay. A network node may also include one or more (or all) parts of a distributed radio base station such as centralized digital units, distributed units (e.g., in an O-RAN access node) and / or remote radio units (RRUs), sometimes referred to as Remote Radio Heads (RRHs). Such remote radio units may or may not be integrated with an antenna as an antenna integrated radio. Parts of a distributed radio base station may also be referred to as nodes in a distributed antenna system (DAS).

[0101] Other examples of network nodes include multiple transmission point (multi-TRP) 5G access nodes, multi-standard radio (MSR) equipment such as MSR BSs, network controllers such as radio network controllers (RNCs) or base station controllers (BSCs), base transceiver stations (BTSs), transmission points, transmission nodes, multi- cell / multicast coordination entities (MCEs), Operation and Maintenance (O&M) nodes, Operations Support System (OSS) nodes, Self-Organizing Network (SON) nodes, positioning nodes (e.g., Evolved Serving Mobile Location Centers (E-SMLCs)), and / or Minimization of Drive Tests (MDTs).

[0102] The network node 1100 includes processing circuitry 1102, a memory 1104, a communication interface 1106, and a power source 1108, and / or any other component, or any combination thereof. The network node 1100 may be composed of multiple physically separate components (e.g., a NodeB component and a RNC component, or a BTS component and a BSC component, etc.), which may each have their own respective components. In certain scenarios in which the network node 1100 comprises multiple separate components (e.g., BTS and BSC components), one or more of the separate components may be shared among several network nodes. For example, a single RNC may control multiple NodeBs. In such a scenario, each unique NodeB and RNC pair, may in some instances be considered a single separate network node. In some embodiments, the network node 1100 may be configured to support multiple radio access technologies (RATs). In such embodiments, some components may be duplicated (e.g., separate memory 1104 for different RATs) and some components may be reused (e.g., a same antenna 1110 may be shared by different RATs). The network node 1100 may also include multiple sets of the various illustrated components for different wireless technologies integrated into network node 1100, for example GSM, WCDMA, LTE, NR, WiFi, Zigbee, Z-wave, LoRaWAN, Radio Frequency Identification (RFID) or Bluetooth wireless technologies. These wireless technologies may be integrated into the same or different chip or set of chips and other components within network node 1100.

[0103] The processing circuitry 1102 may comprise a combination of one or more of a microprocessor, controller, microcontroller, central processing unit, digital signal processor, application-specific integrated circuit, field programmable gate array, or any other suitable computing device, resource, or combination of hardware, software and / or encoded logic operable to provide, either alone or in conjunction with other network node 1100 components, such as the memory 1104, network node 1100 functionality. For example, the processing circuitry 1102 may be configured to cause the network node to perform the methods as described with reference to Figure 3.

[0104] In some embodiments, the processing circuitry 1102 includes a system on a chip (SOC). In some embodiments, the processing circuitry 1102 includes one or more of radio frequency (RF) transceiver circuitry 1112 and baseband processing circuitry 1114. In some embodiments, the radio frequency (RF) transceiver circuitry 1112 and the baseband processing circuitry 1114 may be on separate chips (or sets of chips), boards, or units, such as radio units and digital units. In alternative embodiments, part or all of RF transceiver circuitry 1112 and baseband processing circuitry 1114 may be on the same chip or set of chips, boards, or units.

[0105] The memory 1104 may comprise any form of volatile or non-volatile computer-readable memory including, without limitation, persistent storage, solid-state memory, remotely mounted memory, magnetic media, optical media, random access memory (RAM), readonly memory (ROM), mass storage media (for example, a hard disk), removable storage media (for example, a flash drive, a Compact Disk (CD) or a Digital Video Disk (DVD)), and / or any other volatile or non-volatile, non-transitory device-readable and / or computerexecutable memory devices that store information, data, and / or instructions that may be used by the processing circuitry 1102. The memory 1104 may store any suitable instructions, data, or information, including a computer program, software, an application including one or more of logic, rules, code, tables, and / or other instructions capable of being executed by the processing circuitry 1102 and utilized by the network node 1100. The memory 1104 may be used to store any calculations made by the processing circuitry 1102 and / or any data received via the communication interface 1106. In some embodiments, the processing circuitry 1102 and memory 1104 is integrated.

[0106] The communication interface 1106 is used in wired or wireless communication of signaling and / or data between a network node, access network, and / or UE. As illustrated, the communication interface 1106 comprises port(s) / terminal(s) 1116 to send and receive data, for example to and from a network over a wired connection. The communication interface 1106 also includes radio front-end circuitry 1118 that may be coupled to, or in certain embodiments a part of, the antenna 1110. Radio front-end circuitry 1118 comprises filters 1120 and amplifiers 1122. The radio front-end circuitry 1118 may be connected to an antenna 1110 and processing circuitry 1102. The radio front-end circuitry may be configured to condition signals communicated between antenna 1110 and processing circuitry 1102. The radio front-end circuitry 1118 may receive digital data that is to be sent out to other network nodes or UEs via a wireless connection. The radio front-end circuitry 1118 may convert the digital data into a radio signal having the appropriate channel and bandwidth parameters using a combination of filters 1120 and / or amplifiers 1122. The radio signal may then be transmitted via the antenna 1110. Similarly, when receiving data, the antenna 1110 may collect radio signals which are then converted into digital data by the radio front-end circuitry 1118. The digital data may be passed to the processing circuitry 1102. In other embodiments, the communication interface may comprise different components and / or different combinations of components.

[0107] In certain alternative embodiments, the network node 1100 does not include separate radio front-end circuitry 1118, instead, the processing circuitry 1102 includes radio frontend circuitry and is connected to the antenna 1110. Similarly, in some embodiments, all or some of the RF transceiver circuitry 1112 is part of the communication interface 1106. In still other embodiments, the communication interface 1106 includes one or more ports or terminals 1116, the radio front-end circuitry 1118, and the RF transceiver circuitry 1112, as part of a radio unit (not shown), and the communication interface 1106 communicates with the baseband processing circuitry 1114, which is part of a digital unit (not shown).

[0108] The antenna 1110 may include one or more antennas, or antenna arrays, configured to send and / or receive wireless signals. The antenna 1110 may be coupled to the radio front-end circuitry 1118 and may be any type of antenna capable of transmitting and receiving data and / or signals wirelessly. In certain embodiments, the antenna 1110 is separate from the network node 1100 and connectable to the network node 1100 through an interface or port.

[0109] The antenna 1110, communication interface 1106, and / or the processing circuitry 1102 may be configured to perform any receiving operations and / or certain obtaining operations described herein as being performed by the network node. Any information, data and / or signals may be received from a UE, another network node and / or any other network equipment. Similarly, the antenna 1110, the communication interface 1106, and / or the processing circuitry 1102 may be configured to perform any transmitting operations described herein as being performed by the network node. Any information, data and / or signals may be transmitted to a UE, another network node and / or any other network equipment.

[0110] The power source 1108 provides power to the various components of network node 1100 in a form suitable for the respective components (e.g., at a voltage and current level needed for each respective component). The power source 1108 may further comprise, or be coupled to, power management circuitry to supply the components of the network node 1100 with power for performing the functionality described herein. For example, the network node 1100 may be connectable to an external power source (e.g., the power grid, an electricity outlet) via an input circuitry or interface such as an electrical cable, whereby the external power source supplies power to power circuitry of the power source 1108. As a further example, the power source 1108 may comprise a source of power in the form of a battery or battery pack which is connected to, or integrated in, power circuitry. The battery may provide backup power should the external power source fail.

[0111] Embodiments of the network node 1100 may include additional components beyond those shown in Figure 11 for providing certain aspects of the network node’s functionality, including any of the functionality described herein and / or any functionality necessary to support the subject matter described herein. For example, the network node 1100 may include user interface equipment to allow input of information into the network node 1100 and to allow output of information from the network node 1100. This may allow a user to perform diagnostic, maintenance, repair, and other administrative functions for the network node 1100.

[0112] Figure 12 is a block diagram illustrating a signal processing system 1200 according to some embodiments. The signal processing system 1200 may perform quantization noise suppression in a first frequency band of an input signal. The signal processing system 1200 comprises an inputting module 1202 configured to input a first digital signal, x, into a first DAC to generate a first analog signal, xa. The signal processing system 1200 comprises a first generating module 1204 configured to generate a second analog signal xa,f by filtering the first analog signal to remove components in the first frequency band. The signal processing system 1200 comprises a second generating module 1204 configured to generate a third analog signal, ya,f, by inputting a second digital signal derived from the first digital signal into a second DAC, wherein the second digital signal consists of frequencies within the first frequency band. The signal processing system 1200 comprises a combining module 1208 configured to combine the second analog signal, xa,f, and the third analog signal, ya,f, to generate a fourth analog signal, z. The signal processing system 1200 further comprises a processing module 1210 configured to process the fourth analog signal, z, to provide a fifth analog signal zout for coupling to an input of a transmitting block.

[0113] The signal processing system 1200 may operate in the manner described herein in respect of a signal processing system.

[0114] Figure 13 shows a UE 1300 in accordance with some embodiments. As used herein, a UE refers to a device capable, configured, arranged and / or operable to communicate wirelessly with network nodes and / or other UEs. Examples of a UE include, but are not limited to, a smart phone, mobile phone, cell phone, voice over IP (VoIP) phone, wireless local loop phone, desktop computer, personal digital assistant (PDA), wireless camera, gaming console or device, music storage device, playback appliance, wearable terminal device, wireless endpoint, mobile station, tablet, laptop, laptop-embedded equipment (LEE), laptop-mounted equipment (LME), smart device, wireless customer-premise equipment (CPE), vehicle, vehicle-mounted or vehicle embedded / integrated wireless device, etc. Other examples include any UE identified by the 3rd Generation Partnership Project (3GPP), including a narrow band internet of things (NB-loT) UE, a machine type communication (MTC) UE, and / or an enhanced MTC (eMTC) UE.

[0115] A UE may support device-to-device (D2D) communication, for example by implementing a 3GPP standard for sidelink communication, Dedicated Short-Range Communication (DSRC), vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), orvehicle-to-everything (V2X). In other examples, a UE may not necessarily have a user in the sense of a human user who owns and / or operates the relevant device. Instead, a UE may represent a device that is intended for sale to, or operation by, a human user but which may not, or which may not initially, be associated with a specific human user (e.g., a smart sprinkler controller). Alternatively, a UE may represent a device that is not intended for sale to, or operation by, an end user but which may be associated with or operated for the benefit of a user (e.g., a smart power meter).

[0116] The UE 1300 includes processing circuitry 1302 that is operatively coupled via a bus 1304 to an input / output interface 1306, a power source 1308, a memory 1310, a communication interface 1312, and / or any other component, or any combination thereof. Certain UEs may utilize all or a subset of the components shown in Figure 13. The level of integration between the components may vary from one UE to another UE. Further, certain UEs may contain multiple instances of a component, such as multiple processors, memories, transceivers, transmitters, receivers, etc.

[0117] The processing circuitry 1302 is configured to process instructions and data and may be configured to implement any sequential state machine operative to execute instructions stored as machine-readable computer programs in the memory 1310. The processing circuitry 1302 may be implemented as one or more hardware-implemented state machines (e.g., in discrete logic, field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), etc.); programmable logic together with appropriate firmware; one or more stored computer programs, general-purpose processors, such as a microprocessor or digital signal processor (DSP), together with appropriate software; or any combination of the above. For example, the processing circuitry 1302 may include multiple central processing units (CPUs). The processing circuitry 1302 may be operable to provide, either alone or in conjunction with other UE 1300 components, such as the memory 1310, UE 1300 functionality. For example, the processing circuitry 1302 may be configured to cause the UE 1302 to perform the methods as described with reference to Figure 3.

[0118] In the example, the input / output interface 1306 may be configured to provide an interface or interfaces to an input device, output device, or one or more input and / or output devices. Examples of an output device include a speaker, a sound card, a video card, a display, a monitor, a printer, an actuator, an emitter, a smartcard, another output device, or any combination thereof. An input device may allow a user to capture information into the UE 1300. Examples of an input device include a touch-sensitive or presencesensitive display, a camera (e.g., a digital camera, a digital video camera, a web camera, etc.), a microphone, a sensor, a mouse, a trackball, a directional pad, a trackpad, a scroll wheel, a smartcard, and the like. The presence-sensitive display may include a capacitive or resistive touch sensor to sense input from a user. A sensor may be, for instance, an accelerometer, a gyroscope, a tilt sensor, a force sensor, a magnetometer, an optical sensor, a proximity sensor, a biometric sensor, etc., or any combination thereof. An output device may use the same type of interface port as an input device. For example, a Universal Serial Bus (USB) port may be used to provide an input device and an output device. In some embodiments, the power source 1308 is structured as a battery or battery pack. Other types of power sources, such as an external power source (e.g., an electricity outlet), photovoltaic device, or power cell, may be used. The power source 1308 may further include power circuitry for delivering power from the power source 1308 itself, and / or an external power source, to the various parts of the UE 1300 via input circuitry or an interface such as an electrical power cable. Delivering power may be, for example, for charging of the power source 1308. Power circuitry may perform any formatting, converting, or other modification to the power from the power source 1308 to make the power suitable for the respective components of the UE 1300 to which power is supplied.

[0119] The memory 1310 may be or be configured to include memory such as random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic disks, optical disks, hard disks, removable cartridges, flash drives, and so forth. In one example, the memory 1310 includes one or more application programs 1314, such as an operating system, web browser application, a widget, gadget engine, or other application, and corresponding data 1316. The memory 1310 may store, for use by the UE 1300, any of a variety of various operating systems or combinations of operating systems.

[0120] The memory 1310 may be configured to include a number of physical drive units, such as redundant array of independent disks (RAID), flash memory, USB flash drive, external hard disk drive, thumb drive, pen drive, key drive, high-density digital versatile disc (HD- DVD) optical disc drive, internal hard disk drive, Blu-Ray optical disc drive, holographic digital data storage (HDDS) optical disc drive, external mini-dual in-line memory module (DIMM), synchronous dynamic random access memory (SDRAM), external micro-DIMM SDRAM, smartcard memory such as tamper resistant module in the form of a universal integrated circuit card (UICC) including one or more subscriber identity modules (SIMs), such as a USIM and / or I SI M , other memory, or any combination thereof. The UICC may for example be an embedded UICC (eUlCC), integrated UICC (iUICC) or a removable UICC commonly known as ‘SIM card.’ The memory 1310 may allow the UE 1300 to access instructions, application programs and the like, stored on transitory or non- transitory memory media, to off-load data, or to upload data. An article of manufacture, such as one utilizing a communication system may be tangibly embodied as or in the memory 1310, which may be or comprise a device-readable storage medium. The processing circuitry 1302 may be configured to communicate with an access network or other network using the communication interface 1312. The communication interface 1312 may comprise one or more communication subsystems and may include or be communicatively coupled to an antenna 1322. The communication interface 1312 may include one or more transceivers used to communicate, such as by communicating with one or more remote transceivers of another device capable of wireless communication (e.g., another UE or a network node in an access network). Each transceiver may include a transmitter 1318 and / or a receiver 1320 appropriate to provide network communications (e.g., optical, electrical, frequency allocations, and so forth). Moreover, the transmitter 1318 and receiver 1320 may be coupled to one or more antennas (e.g., antenna 1322) and may share circuit components, software or firmware, or alternatively be implemented separately.

[0121] In some embodiments, communication functions of the communication interface 1312 may include cellular communication, Wi-Fi communication, LPWAN communication, data communication, voice communication, multimedia communication, short-range communications such as Bluetooth, near-field communication, location-based communication such as the use of the global positioning system (GPS) to determine a location, another like communication function, or any combination thereof. Communications may be implemented in according to one or more communication protocols and / or standards, such as IEEE 802.11 , Code Division Multiplexing Access (CDMA), Wideband Code Division Multiple Access (WCDMA), GSM, LTE, New Radio (NR), UMTS, WiMax, Ethernet, transmission control protocol / internet protocol (TCP / IP), synchronous optical networking (SONET), Asynchronous Transfer Mode (ATM), QUIC, Hypertext Transfer Protocol (HTTP), and so forth.

[0122] Regardless of the type of sensor, a UE may provide an output of data captured by its sensors, through its communication interface 1312, via a wireless connection to a network node. Data captured by sensors of a UE can be communicated through a wireless connection to a network node via another UE. The output may be periodic (e.g., once every 15 minutes if it reports the sensed temperature), random (e.g., to even out the load from reporting from several sensors), in response to a triggering event (e.g., when moisture is detected an alert is sent), in response to a request (e.g., a user initiated request), or a continuous stream (e.g., a live video feed of a patient). As another example, a UE comprises an actuator, a motor, or a switch, related to a communication interface configured to receive wireless input from a network node via a wireless connection. In response to the received wireless input the states of the actuator, the motor, or the switch may change. For example, the UE may comprise a motor that adjusts the control surfaces or rotors of a drone in flight according to the received input or controls a robotic arm performing a medical procedure according to the received input.

[0123] A UE, when in the form of an Internet of Things (loT) device, may be a device for use in one or more application domains, these domains comprising, but not limited to, city wearable technology, extended industrial application and healthcare. Non-limiting examples of such an loT device are devices which are or which are embedded in: a connected refrigerator or freezer, a TV, a connected lighting device, an electricity meter, a robot vacuum cleaner, a voice controlled smart speaker, a home security camera, a motion detector, a thermostat, a smoke detector, a door / window sensor, a flood / moisture sensor, an electrical door lock, a connected doorbell, an air conditioning system like a heat pump, an autonomous vehicle, a surveillance system, a weather monitoring device, a vehicle parking monitoring device, an electric vehicle charging station, a smart watch, a fitness tracker, a head-mounted display for Augmented Reality (AR) or Virtual Reality (VR), a wearable for tactile augmentation or sensory enhancement, a water sprinkler, an animal- or item-tracking device, a sensor for monitoring a plant or animal, an industrial robot, an Unmanned Aerial Vehicle (UAV), and any kind of medical device, like a heart rate monitor or a remote controlled surgical robot. A UE in the form of an loT device comprises circuitry and / or software in dependence on the intended application of the loT device in addition to other components as described in relation to the UE 1300 shown in Figure 13.

[0124] As yet another specific example, in an loT scenario, a UE may represent a machine or other device that performs monitoring and / or measurements, and transmits the results of such monitoring and / or measurements to another UE and / or a network node. The UE may in this case be an M2M device, which may in a 3GPP context be referred to as an MTC device. As one particular example, the UE may implement the 3GPP NB-loT standard. In other scenarios, a UE may represent a vehicle, such as a car, a bus, a truck, a ship and an airplane, or other equipment that is capable of monitoring and / or reporting on its operational status or other functions associated with its operation. In practice, any number of UEs may be used together with respect to a single use case. For example, a first UE might be or be integrated in a drone and provide the drone’s speed information (obtained through a speed sensor) to a second UE that is a remote controller operating the drone. When the user makes changes from the remote controller, the first UE may adjust the throttle on the drone (e.g. by controlling an actuator) to increase or decrease the drone’s speed. The first and / or the second UE can also include more than one of the functionalities described above. For example, a UE might comprise the sensor and the actuator, and handle communication of data for both the speed sensor and the actuators.

[0125] SIMULATIONS

[0126] To verify the proposed solution, simulations were carried out using SBFD configuration

[0127] (e.g. as illustrated in any one of Figures 1 to 7) with following parameters:

[0128] Figure 14 illustrates the output of the HP filter according to the simulation where signals components from the first DAC within the UL sub-band are suppressed.

[0129] Figure 15 illustrates the combined BB TX signal from both the first DAC and the second DAC as well as total quantization noise where > 10 dB suppression of quantization noise within UL sub-band is attained. Figure 16 shows the output of the PA with and without using the 2 stage frequency selective DPD. It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

CLAIMS1. A method, performed by a signal processing system, for performing quantization noise suppression in a first frequency band of an input signal, the method comprising: inputting (301) a first digital signal, x, into a first DAC to generate a first analog signal, xa; generating (302) a second analog signal Xa,f by filtering the first analog signal to remove components in the first frequency band; generating (303) a third analog signal, ya,f, by inputting a second digital signal derived from the first digital signal into a second DAC, wherein the second digital signal consists of frequencies within the first frequency band; combining (304) the second analog signal, xa,f, and the third analog signal, ya.f, to generate a fourth analog signal, z; and processing (305) the fourth analog signal, z, to provide a fifth analog signal Zout for coupling to an input of a transmitting block.

2. The method as claimed in claim 1 , wherein the first DAC has a higher output power than the second DAC.

3. The method as claimed in claim 1 or 2, wherein the first DAC has a higher sampling rate than the second DAC.

4. The method as claimed in claim 1 or 2, wherein the first DAC has a lower sampling rate than the second DAC.

5. The method as claimed in any one of claims 1 to 4, wherein the first DAC produces higher quantization noise in the first frequency band than the second DAC.

6. The method as claimed in any one of claims 1 to 5, wherein generating the third analog signal further comprises: filtering the output of the second DAC to suppress signal components having frequencies outside of the first frequency band.

7. The method as claimed in any preceding claim, wherein the first digital signal is derived by performing a first stage of digital predistortion on the input signal.

8. The method as claimed in any preceding claim, wherein the second digital signal is derived from the first digital signal by: filtering the first digital signal to remove frequencies outside of the first frequency band.

9. The method as claimed in claim 8, wherein the second digital signal is derived from the first digital signal further by: performing a second stage of digital predistortion on the filtered first digital signal to generate the second digital signal.

10. The method as claimed in claim 8 or 9, wherein the second digital signal is derived from the first digital signal further by: performing downsampling to provide the second digital signal with a sampling rate equal to or greater than the bandwidth of the first frequency band11 . The method as claimed in any preceding claim, wherein processing the fourth analog signal, z, comprises performing one or more processing steps on the fourth analog signal, z, to generate the fifth analog signal, zout input into the transmitting block.

12. The method as claimed in claim 11 , wherein the one or more processing steps comprise one or more of: filtering to suppress one or more frequencies in the fourth analog signal, varying gain of the fourth analog signal, and applying up-conversion to the fourth analog signal such that the fifth analog signal is centered on a carrier frequency.

13. The method as claimed in any preceding claim further comprising applying a delay to the first digital signal before inputting the first signal into the first DAC.

14. The method as claimed in any preceding claim, wherein the first frequency band is an uplink frequency band in a Sub-band Full Duplex, SBFD, format.

15. The method as claimed in any one of claims 1 to 13, wherein the first frequency band consists of out-of-band components of the input signal.

16. The method as claimed in any one of claims 1 to 13, wherein the first frequency band consists of Earth Exploration Services, EESS, band frequencies.

17. The method as claimed in any preceding claim wherein the transmitting block comprises a power amplifier and / or an output antenna.

18. A signal processing system (400) for performing quantization noise suppression in a first frequency band of an input signal, the signal processing system comprising: a first signal path (401) configured to receive a first digital signal and output a second analog signal, wherein the first signal path comprises: a first DAC (402) configured to receive the first digital signal and output a first analog signal, and a first filter (403) configured to generate a second analog signal Xa,f by filtering the first analog signal to remove components in the first frequency band; a second signal path (404) configured to receive the first digital signal and output a third analog signal, ya.f, wherein the second signal path comprises: a second DAC (405) configured to receive a second digital signal derived from the first digital signal wherein the second digital signal consists of frequencies within the first frequency band; a signal combination block (407) configured to combine the second analog signal, xa,f, and the third analog signal, ya.f, to generate a fourth analog signal, z; and an output processing block (408) configured to derive a fifth analog signal from the fourth analog signal for outputting to a transmitting block (409).

19. The signal processing system as claimed in claim 18 wherein the first DAC has a higher output power than the second DAC.

20. The signal processing system as claimed in claim 18 or 19 wherein the first DAC has a higher sampling rate than the second DAC.21 . The signal processing system as claimed in claim 18 or 19 wherein the first DAC has a lower sampling rate than the second DAC.

22. The signal processing system as claimed in any one of claims 18 to 21 wherein the first DAC produces higher quantization noise in the first frequency band than the second DAC.

23. The signal processing system as claimed in any one of claims 118 to 22 wherein the second signal path further comprises: a second filter (501) configured to filter the output of the second DAC to suppress signal components having frequencies outside of the first frequency band.

24. The signal processing system as claimed in any one of claims 18-23 further comprising a first stage of digital predistortion (603) configured to receive the input signal and output the first digital signal.

25. The signal processing system as claimed in any one of claims 18 to 24 wherein the second signal path further comprises a first processing block (406) configured to derive the second digital signal from the first digital signal.

26. The signal processing system as claimed in claim 25 wherein the first processing block comprises a third filter (602) configured to filter the first digital signal to suppress frequencies outside of the first frequency band.

27. The signal processing system as claimed in claim 26 wherein the first processing block further comprises: a second stage of digital predistortion (701) configured to receive the filtered first digital signal to generate the second digital signal.

28. The signal processing system as claimed in claim 26 or 27 wherein the first processing block further comprises a downsampler (601) configured to provide the second digital signal with a sampling rate equal to or greater than the bandwidth of the first frequency band29. The signal processing system as claimed in any one of claims 18 to 28 wherein the output processing block is configured to perform one or more processing steps on the fourth analog signal, z, to generate the fifth analog signal input.

30. The signal processing system as claimed in claim 29 wherein the one or more processing steps comprise one or more of: filtering to suppress one or more frequencies in the fourth analog signal, varying gain of the fourth analog signal, and applying up-conversion to the fourth analog signal such that the fifth analog signal is centered on a carrier frequency.

31. The signal processing system as claimed in any one of claims 18 to 30 wherein the first signal path further comprises a delay block (604) configured to delay to the first digital signal before inputting the first digital signal into the first DAC.

32. The signal processing system as claimed in any one of claims 18 to 31 wherein the first frequency band comprises an uplink frequency band in a Sub-band Full Duplex, SBFD, format.

33. The signal processing system as claimed in any one of claims 18 to 31 wherein the first frequency band consists of out-of-band components of the input signal.

34. The signal processing system as claimed in any one of claims 18 to 31 wherein the first frequency band consists of EESS band frequencies.

35. The signal processing system as claimed in any one of claims 18 to 34 wherein the transmitting block (409) comprises one or more of a power amplifier and an output antenna.

36. A base station comprising the signal processing system as claimed in any one of claims 18 to 35.

37. A user equipment comprising the signal processing system as claimed in any one of claims 18 to 35.

38. A signal processing system (400) for performing quantization noise suppression in a first frequency band of an input signal, the signal processing system comprisingprocessing circuitry (1102, 1302) configured to cause the signal processing system to: input (301) a first signal, x, into a first DAC to generate a first analog signal, xa; generate (302) a second analog signal Xa,f by filtering the first analog signal to remove components in the first frequency band; generate (303) a third analog signal, ya,f, by inputting a third signal derived from the first signal into a second DAC, wherein the third signal consists of frequencies within the first frequency band; and combine (304) the second analog signal, xa,f, and the third analog signal, ya.f, to generate a fourth analog signal, z; and process the fourth analog signal, z, to provide a fifth analog signal zout for coupling to an input of a transmitting block.

39. The signal processing system as claimed in claim 38 wherein the processing circuitry is further configured to perform the method as claimed in any one of claims 2 to 17.

40. A base station (1100) comprising the signal processing system as claimed in any one of claims 38 or 39.

41. A user equipment (1300) comprising the signal processing system as claimed in any one of claims 38 or 39.

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