Integrated circuit packages
By incorporating metal regions that thermally connect contact pads to the cover, the integrated circuit package addresses heat dissipation challenges, improving thermal management and performance.
Patent Information
- Application Number
- FR2022005899
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-06-16
- Publication Date
- 2025-06-20
- Estimated Expiration
- 2042-06-16
AI Technical Summary
Existing integrated circuit packages, such as BGA packages, face challenges in efficiently dissipating heat generated by electronic chips, which can lead to thermal management issues and reduced performance.
The integration of metal regions that thermally connect contact pads of the electronic chip to the cover of the package, allowing for heat dissipation through these metal regions and connection balls, thereby enhancing thermal management.
This solution effectively improves heat dissipation from the electronic chip, enhancing thermal management and reducing the risk of thermal-related performance issues.
Smart Images
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Abstract
Description
Title of the invention: Integrated circuit packages Technical field
[0001] The present description relates generally to electronic devices and more particularly to integrated circuit packages, for example ball grid array (BGA) packages and the mounting of electronic chips in these packages. Prior art
[0002] BGA packages allow an electronic chip to be electrically integrated into an external device or a printed circuit board (PCB). Such packages also allow the dissipation of heat produced by the chip through different thermal paths.
[0003] There is a need for improvement of electronic chip packages. Summary of the invention
[0004] One embodiment overcomes all or part of the drawbacks of known housings.
[0005] One embodiment provides an electronic device comprising an electronic chip electronics located between a cover and an interconnection substrate, in which: a. the electronic chip comprises contact pads located opposite a first face of the interconnection substrate; b. at least one metal region thermally connects at least one contact pad of the chip to the cover.
[0006] According to one embodiment, said at least one metal region is in contact on the one hand with said at least one contact pad, and on the other hand with the cover, or with a first thermally conductive layer itself in contact with the cover.
[0007] According to one embodiment, the first thermally conductive layer is electrically insulating.
[0008] According to one embodiment, the cover is metallic.
[0009] According to one embodiment, the interconnection substrate carries balls of connection on a second face, opposite the first face, said at least one metallic region being electrically connected to at least one connection ball.
[0010] According to one embodiment, the connection between said at least one metal region and said at least one connection ball is made by a metal via passing through the interconnection substrate.
[0011] According to one embodiment, said at least one metal region is connected to ground.
[0012] According to one embodiment, said at least one metal region is in contact with four contact pads.
[0013] According to one embodiment, said at least one metal region has three teeth, the central tooth being connected to two contact pads and the other two teeth each being connected to a contact pad.
[0014] According to one embodiment, a face of the electronic chip opposite the contact pads is in contact with a second thermally conductive layer itself in contact with the cover.
[0015] According to one embodiment, said at least one metal region is formed in a metal layer of the interconnect substrate.
[0016] According to one embodiment, said at least one metallic region is made of copper.
[0017] Another embodiment provides an assembly in which the electronic device electronics is mounted on a printed circuit board or external device. Brief description of the drawings
[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0019] [Fig.l] is a sectional view showing an example of an electronic device mounted on an external device;
[0020] [Fig.2A] is a sectional view showing an electronic device mounted on an external device according to one embodiment;
[0021] [Fig.2B] is a top view of the electronic device of [Fig.2A]. Description of the embodiments
[0022] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0023] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the electronic chip has been described only by its geometry and its electronic functions have not been described, the electronic device being compatible with conventional surface-mount chips.
[0024] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.
[0025] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.
[0026] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0027] [Fig.l] is a sectional view showing an example of an electronic device 100 mounted on an external device 108. More particularly, the electronic device 100 corresponds to an electronic chip 102 mounted in a housing 103.
[0028] The package 103 comprises a cover 104 and an interconnect substrate 106. Such a package 103 makes it possible to electrically connect the chip 102 to the external device or printed circuit 108. For this, the chip 102 is electrically connected to the substrate 106, and the substrate 106 is mounted and electrically connected to the external device 108.
[0029] The electronic chip 102 comprises a body 102a and one or more contact pads 102c located on the side of a first face of the body 102a, namely its lower face in the orientation of [Fig.l]. The contact pads 102c are located opposite a first face of the interconnection substrate 106, namely its upper face in the orientation of [Fig.l]. The body 102a of the chip 102 has, for example, in top view a substantially square or rectangular shape. The body 102a of the chip has, for example, dimensions in top view, greater than 5 mm by 5 mm, for example less than 25 mm by 25 mm, for example of the order of 15 mm by 15 mm.
[0030] The body 102a of the chip comprises, for example, integrated circuits and electronic elements, for example formed in and / or on a semiconductor material. By way of example, the body 102a of the chip comprises a semiconductor substrate (not detailed in the figure), for example made of silicon, in and on which electronic components are formed, for example transistors (not detailed in the figure), and a stack of insulating and conductive layers called an interconnection stack (not detailed in the figure), located on the side of the lower face of the substrate, in which interconnection elements of the electronic components are formed. The contact pads 102c are for example arranged on the lower face of the interconnection stack of the chip 102.
[0031] The connection between the chip 102 and the interconnection substrate 106 is made via the contact pads 102c of the chip. For example, the contact pads 102c are fixed and electrically connected to corresponding contact pads (not detailed in the figure) of the interconnection substrate 106, located on the side of the upper face of the interconnection substrate 106. For example, the chip 102 comprises several contact pads 102c. The chip comprises, for example, at least ten contact pads 102c, for example, at least a hundred contact pads 102c. For example, the contact pads 102c are regularly distributed on the lower face of the body 102a. For example, the contact pads 102c are arranged in a matrix network.
[0032] For example, the contact pads 102c are made of an electrically conductive material. For example, the contact pads 102c are made of a metallic material. The contact pads 102c are, for example, made of copper, silver or tin, or an alloy, for example based on tin and silver (SnAg).
[0033] The substrate 106 allows the integrated circuit chip 102 to be assembled to the external device 108 using a surface mounting technique.
[0034] For example, the substrate 106 has, in top view, a substantially square or rectangular shape. For example, the substrate 106 is, in top view, larger than the chip 102. The substrate 106 has, for example, dimensions in top view, greater than 10 mm by 10 mm, for example less than 110 mm by 110 mm, for example of the order of 25 mm by 25 mm.
[0035] The substrate 106 comprises, for example, a stack of metallic and insulating levels in which interconnection elements are formed. The substrate 106 comprises, for example, horizontal metallic tracks in the orientation of [Fig.l] (not detailed in the figure) and / or vertical metallic vias in the orientation of [Fig.l] (not detailed in the figure).
[0036] The substrate 106 is connected to the external device 108 by means of connection balls or columns 110, connecting metal contacts (not detailed in the figure) formed on the upper face of the external device 108, to metal contacts (not detailed in the figure) formed on a lower face of the substrate 106. Thus, the interconnection substrate 106 is crossed by metal vias and carries connection balls 110 on its face opposite the chip 102, namely its lower face in the orientation of [Fig.l]. The balls 110 are for example regularly distributed on the lower face of the substrate 106, for example according to a matrix network. The lateral dimensions of the balls 110 and the inter-ball pitch 110 are for example respectively greater than the lateral dimensions of the contact pads 102c and the inter-pad pitch 102c.The substrate 106 thus performs a function of spreading and redistributing the contacts of the chip 102 towards the contacts of the external device.
[0037] For example, the cover 104 has, in top view, a shape similar to the shape of the substrate 106. For example, in top view, the cover has a substantially square or rectangular shape. The lateral dimensions of the cover 104 are for example substantially identical to the lateral dimensions of the substrate 106. The cover 104 of the housing 103 is for example fixed to the substrate 106 using a layer 112. For example, the cover 104 is fixed to the substrate 106 in a localized manner, that is to say that the layer 112 does not extend over the entire periphery of the cover 104 and the substrate 106. For example, the cover 104 and the substrate 106 are fixed to each other by means of the layer 112 only on their four corners, the cover 104 and the substrate 106 thus being in contact, by means of the layer 112, only at four places. The layer 112 is for example made of a fixing adhesive. The layer 112 is for example in contact, by its lower face, with an electrically insulating region of the substrate 106, and, by its upper face, with the lower face of the cover 104. The cover 104 is for example made of metal.
[0038] The cover 104 of the housing 103 makes it possible in particular to dissipate the heat accumulated in the electronic chip 102. For this, a thermal interface layer 114, for example, forms an interface between the upper face of the chip 102 and the cover 104. The layer 114 is, for example, in contact, by its lower face, with the upper face of the chip 102, and, by its upper face, with the lower face of the cover 104. The layer 114 has, for example, a thermal conductivity greater than that of air. The layer 114 is, for example, thermal paste, grease or glue.
[0039] In the example described in relation to [Fig.l], part of the heat produced by the electronic chip 102 is dissipated by the cover 104. In practice, the heat exchanges in such a device are not always sufficient to dissipate the heat produced by the electronic chip optimally. It is then proposed below to increase the heat dissipations within the device.
[0040] [Fig.2A] is a sectional view showing an electronic device 200 mounted on an external device according to an embodiment 108.
[0041] [Fig.2B] is a top view of the electronic device 200 of [Fig.2A]. More specifically, [Fig.2B] is a top view of the device 200 of [Fig.2A] in which certain elements have been shown in transparency, such as the cover 104 and the body 102a of the chip 102. [Fig.2A] is a sectional view along the section plane AA of [Fig.2B].
[0042] The device 200 illustrated in FIGS. 2A and 2B is similar to the device 100 illustrated in [Fig.l] except that it comprises metal regions 202, thermally connecting contact pads 102c to the cover 104. In the example shown, the metal regions 202 are further thermally connected to connection balls 110.
[0043] The metal regions 202 are for example metal tracks or pads formed in an upper metallization level of the interconnect substrate 106.
[0044] The metal regions 202 extend, for example, in top view, from the corners of the chip 102 to the corners of the substrate 106. For example, the device 200 comprises four metal regions 202, each metal region extending from one corner of the chip to a corner of the substrate facing it.
[0045] For example, the metal regions 202 are connected, in the corners of the chip, to certain contact pads 102c. For example, each metal region 202 is connected to at least one contact pad 102c, for example a ground contact pad, located in a corner of the chip.
[0046] By way of example, each metal region 202 is connected to four adjacent contact pads 102c located in a corner of the chip. In this example, the metal regions 202 have the shape of a three-pronged fork in which the central prong is connected to a first contact pad 102c located in a corner of the chip and to a second contact pad 102c adjacent to the first pad in the direction of the center of the chip. Still in this example, the other two prongs of the metal region 202 are respectively connected to third and fourth contact pads 102c located on either side of the central prong. In this example, in each of the corners of the chip, the contact pads 102c connected to the metal regions 202 form, for example, a square matrix of 2x2 contact pads 102c.
[0047] The substrate 106 as illustrated in FIGS. 2A and 2B comprises, for example, several levels of metallizations 206 or tracks, stacked and insulated from each other at least partially by insulating layers 208.
[0048] The metal regions 202 are, for example, formed in a metal layer of the substrate 106, for example in the metal layer corresponding to the last metallization level of the substrate 106, that is to say the metal layer closest to the upper face of the substrate 106.
[0049] The substrate 106 further comprises metal vias 204 making it possible to electrically connect metal tracks 206 of two consecutive levels to each other, the tracks and vias forming an interconnection network within the substrate 106. The metal vias 204 pass through, for example, at least partially the substrate 106 and connect, for example, tracks 206 to connection balls 110.
[0050] By way of example, each of the metal regions 202 is electrically connected, by interconnection elements of the substrate 106, for example by means of a metal via 204 passing through the substrate 106, to at least one connection ball 110.
[0051] Thus, according to a preferred embodiment, each metal region 202 thermally connects at least one contact pad 102c of the chip to at least one connection ball 110 by means of at least one metal via 204.
[0052] In the embodiment of Figures 2A and 2B, the metal regions 202 create thermal paths between the contact pads 102c of the chip 102 and the cover 104, and, preferably, between the contact pads 102c and the device 108. The metal regions 202 thus make it possible to evacuate towards the cover 104 and, for example, towards the device 108, a part of the heat generated by the chip 102, in particular by the integrated circuits located on the underside of the chip 102.
[0053] In the example of Figures 2A and 2B, the cover 104 is thermally connected to the metal regions 202 at the corners of the substrate 106. The cover may be in direct contact, i.e. in mechanical contact, by its lower face, with the metal regions 202. As a variant, a thermally conductive layer 210 forms an interface between the lower face of the cover 104 and the upper face of the metal regions 202. The layer 210 is for example in direct contact, by its lower face, with the upper face of the metal regions 202, and, by its upper face, with the lower face of the cover 104. By way of example, the layer 210 is made of a material having a thermal conductivity greater than that of air. By way of example, the layer 210 is made of an electrically insulating material. By way of example, the thermally conductive material corresponds to a thermal glue or a thermal paste.Alternatively, layer 210 is made of an electrically conductive material, for example a metal.
[0054] An advantage of the embodiment illustrated in Figures 2A and 2B is that it allows for better thermal dissipation of the heat produced by the chip 102.
[0055] Another advantage of the embodiment illustrated in Figures 2A and 2B is that it allows thermal dissipation of heat through an upper portion of the chip and through a lower portion of the chip.
[0056] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will be apparent to those skilled in the art. In particular, although a device has been described having four metal regions located at the corners of the chip and the substrate, the number of metal regions may be other than four, for example greater than four. Metal regions will then be present outside the corners of the chip and the substrate. For example, the number of physical contact points, between the substrate 106 and the cover 104, possibly via the layer 210, is identical to the number of metal regions or less than it.
[0057] Furthermore, although the metal regions have been described as being able to be metal tracks of the substrate, they may correspond to layers formed on the upper face of the substrate 106 and connected to the substrate 106 by localized contacts.
[0058] In addition, the chip, substrate and cover have been described as having a substantially square or rectangular shape, however they may have a different shape such as an oblong shape, a square shape with rounded edges or any other shape. For example, the chip, cover and substrate do not have all the same shape.
[0059] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
Claims
1. An electronic device (200) comprising an electronic chip (102) located between a cover (104) and an interconnect substrate (106), wherein: a. the electronic chip (102) comprises contact pads (102c) located opposite a first face of the interconnect substrate (106); b. at least one metal region (202) thermally connects at least one contact pad (102c) of the chip to the cover (104), wherein said at least one metal region (202) is in contact with four contact pads (102c) and said at least one metal region (202) has three teeth, the central tooth being connected to two contact pads (102c) and the other two teeth each being connected to a contact pad (102c).
2. Device according to claim 1, in which said at least one metal region (202) is in contact on the one hand with said at least one contact pad (102c), and on the other hand with the cover (104), or with a first thermally conductive layer (210) itself in contact with the cover (104).
3. A device according to claim 2, wherein the first thermally conductive layer (210) is electrically insulating.
4. Device according to any one of claims 1 to 3, in which the cover (104) is metallic.
5. Device according to any one of claims 1 to 4, in which the interconnection substrate (106) carries connection balls (110) on a second face, opposite the first face, said at least one metal region (202) being electrically connected to at least one connection ball (110).
6. Device according to claim 5, wherein the connection between said at least one metal region (202) and said at least one connection ball (110) is made by a metal via (204) passing through the interconnection substrate (106).
7. A device according to any one of claims 1 to 6, wherein said at least one metal region (202) is connected to ground.
8. A device according to any one of claims 1 to 7, wherein a face of the electronic chip (102) opposite the contact pads (102c) is in contact with a second thermally conductive layer (114) itself in contact with the cover (104).
9. A device according to any one of claims 1 to 8, wherein said at least one metal region (202) is formed in a metal layer (206) of the interconnect substrate (106).
10. A device according to any one of claims 1 to 9, wherein said at least one metal region (202) is copper.
11. An assembly (100; 200) wherein the electronic device according to any one of claims 1 to 10 is mounted on a printed circuit (108) or an external device.