Dual CTIA for non-pinched photodiode

Abstract

Depth image acquisition device of a scene, the acquisition device having a plurality of depth pixels each comprising a readout circuit having a first integration capacitance (CINT1) for acquiring first samples of charges from the photodetector (PD) during first sampling phases (C0) carried out during an integration period comprising repeated sequences of several successive sampling phases (C0, C1, C2, C3) of charges, the first integration capacitance (CINT1) being located in a feedback branch between an input and an output of a first amplifier stage (A1) of a transimpedance capacitive amplifier structure, said input being connected to a detection node (ND) coupled to the photodetector (PD) and said output being connected to a readout node (NL1) coupled to an output stage (51) of said readout circuit,The reading circuit further comprises a polarization reset block (10) for polarizing the photodetector (PD), with a repolarization switch (11) configured to, during polarization reset phases of said photodetector (PD) performed between said first sampling phases, couple the polarization reset block (10) to the photodetector (PD) so as to apply a polarization potential to it. Figure for the abbreviation: 3.,

Description

Title of the invention: Double CTI A for non-pinched photodiode technical field

[0001] The present application relates to the field of readout circuits for scene depth image acquisition devices and more particularly those associated with non-pinched photodiodes. EARLIER ART

[0002] Image acquisition systems capable of acquiring depth information, for example such as systems using indirect time of flight (iTOF for indirect "Time Of Flight") detectors are known.

[0003] An iTOF system generally comprises a circuit that drives a light source, for example a light-emitting diode (LED), which emits a light signal at a wavelength, for example in the near-infrared spectrum, towards a scene. The light from a reflected signal from this scene is captured by an image acquisition device.

[0004] The image acquisition device also includes pixels capable of receiving the light signal reflected by the image scene and detecting the phase of the received signal to form a depth image. These pixels are hereinafter referred to as "depth pixels".

[0005] A series of acquisitions with a certain phase shift relative to the emitted light and the received light amplitude at each instant is stored in dedicated memory elements.

[0006] A digital system determines, on the basis of periodically amplitude-modulated signals captured by the depth pixels of the image acquisition device, the corresponding distances of objects in the image scene.

[0007] Fig. 1 is a graph representing, by a curve 3, an example of the evolution, as a function of time, of the light intensity of a light signal emitted by a light-emitting diode towards an image scene, and, by a curve 5, an example of the evolution, as a function of time, of a light intensity of a light signal received by one of the depth pixels of an image acquisition device.

[0008] The depth pixels are based on photodetectors used to detect the phase of the received light signal.

[0009] There is a phase shift A0 between the emitted light signal and the received light signal, which represents the time of flight of the light signal from the light-emitting diode to the image acquisition device via an object in the image scene that reflects the light signal.

[0010] An estimate of the distance d to the object in the image scene can be calculated using the equation: £* jf 'iltlltl 'TTTTTTTT- 2 /

[0011] where c denotes the speed of light, f the frequency of the light signal.

[0012] The phase shift A0 can be estimated on the basis of sampling the signal captured by one or more depth pixels for at least three windows also called distinct sampling phases, preferably for four windows or distinct sampling phases, during each period of the light signal.

[0013] Integration over a large number of periods, in particular greater than 10,000, is typically performed. Each sampling window or phase, for example, has a duration of up to one-quarter of the period of the light signal. These sampling phases typically each have the same duration, and the four sampling phases have a total cycle time equal to the period of the light signal.

[0014] The charge samples are stored in storage elements, for example in the form of capacitors.

[0015] Based on the integrated samples of the light signal, and for a sinusoidal light wave, the phase shift A0 of the light signal can, in the case of using 3 memory elements, be given by the following formula: fC2-Cl) - tU t G / ; (C0-Cl)+(C0~C2)

[0016] A technique based on the detection of four samples according to four phases C0, Cl, C2, and C3 per period is described in more detail in the publication by R. Lange and P. Seitz entitled "Solid-state TOF range camera", IEEE J. on Quantum Electronics, vol. 37, No.3, Tuesday 2001.

[0017] It is therefore possible to organize the detection differently by using 4 memory elements. In this case, the phase shift is given by the following formula: G; — Cl A » crc £ «w ™™ <

[0018] To determine the phase shift A0 between the emitted light signal and the received light signal, the received light signal is sampled by successively and at regular intervals transferring photogenerated charges into a photodetector during a first sampling phase C0, photogenerated charges into the same photodetector or into another photodetector during a second sampling phase C1 following the first phase, photogenerated charges during a third sampling phase C2 following the second phase, and charges photogenerated during a fourth sampling window C3 following the third phase. This sequence of four sampling phases is repeated a large number of times, for example 100,000 times, before the resulting signals are read by an output circuit.

[0019] When a photodiode is pinched and has a completely depleted and charge-free area, this area acts as a potential well which allows a certain number of charges to be retained, typically between several tens and several thousand depending on the characteristics of the diode while awaiting their transfer carried out through transfer gates.

[0020] Pinch-photodiode depth pixels comprising transfer grids and several storage elements per pixel are known.

[0021] The use of pinch diodes for a depth pixel is desirable but is not always possible.

[0022] For example, in the case of an IILV material such as InGaAs, which is particularly suited to infrared and therefore to the wavelengths commonly used for iTOF measurements, the implementation of a pinched photodiode is difficult.

[0023] However, maintaining the polarization of a photodiode is all the more critical when the photodiode is of the non-pinch type. This polarization should preferably be kept constant at the desired value in order to maintain good performance in terms of gain and to minimize dark current.

[0024] To polarize appropriately and to maintain a fixed polarization on the photodetector, a cascode-type structure can be considered in the reading circuit.

[0025] Such a structure typically consists of a transistor whose source is connected to the photodetector. However, it is unsuitable for certain applications, particularly those requiring high operating frequencies, for example above 100 MHz.

[0026] Active cascode readout circuits are known, but their bandwidth remains limited and it remains difficult to obtain a good compromise between power consumption and detection accuracy with such circuits.

[0027] Other structures involved in maintaining polarization are known.

[0028] We seek to have a reading circuit for the acquisition of depth images, improved with respect to the problems stated above, and in particular with respect to maintaining the polarization of the photodiode while preferably allowing us to keep a reduced pixel size. Description of the invention

[0029] One embodiment of the present invention relates to an acquisition device depth imaging of a scene by detecting a reflected light signal corresponding to the reflection on the scene of an incident light signal, particularly in the near-infrared, the acquisition device having a plurality of depth pixels, at least one first pixel among said depth pixels comprising an associated readout circuit connected to a photodetector, said readout circuit having at least one first storage element provided with a first integration capacity to acquire first samples of charges from the photodetector during first sampling phases carried out during an integration period comprising repeated sequences of several successive sampling phases of charges CO, Cl, C2, C3,

[0030] in which, the first integrating capacitance is located in a feedback branch between an input and an output of a first amplifier stage of a transimpedance capacitive amplifier structure, said input being connected to a detection node coupled to the photodetector and said output being connected to a reading node coupled to an output stage of said reading circuit,

[0031] and in which the reading circuit further comprises a polarization reset block for polarizing the photodetector, with a repolarization switch configured to, during polarization reset phases of said photodetector carried out between said first sampling phases, couple the polarization reset block to the photodetector so as to apply a polarization potential to it, during said first sampling phases, decouple the photodetector from the polarization reset block.

[0032] Thus, periods are used during which the first integration capacity does not perform sampling to allow the polarization of the photodetector to be reset.

[0033] The image acquisition device is typically equipped with at least one second storage element to acquire, during other sampling phases Cl of said sequences shifted relative to the first sampling phases C0 according to a determined phase shift of the sampling phases, other charge samples. The polarization reset of the photodetector can be performed during these other sampling phases CL

[0034] According to one embodiment, said sequences comprise a first sampling phase C0, a second sampling phase C1, a third sampling phase C2, and a fourth sampling phase C3, wherein the second storage element is integrated into said first pixel and is provided with a second integration capability to acquire, during said third sampling phases, charge samples from said photodetector, said polarization reset phases of said photodetector being carried out each between a first sampling phase and a third sampling phase of a given sequence or between a third sampling phase of a given sequence and a first sampling phase of a sequence following the given sequence.

[0035] According to an embodiment wherein each of said sequences comprises at least a first, a second, and a third sampling phase and wherein the second storage element is provided with a second integration capability integrated into said first pixel, the reading circuit further being provided:

[0036] - of a first sampling switch arranged between the first capacitor integration and the photodetector, the first sampling switch being configured to couple the photodetector to the first integration capacitor during said first sampling phases, said reading circuit of said first pixel being further equipped:

[0037] - of a second sampling switch between the second capacitor integration and the photodetector, the second sampling switch being configured to couple the photodetector to the second integration capacitor during said third sampling phases, the second integration capacitor being arranged in another feedback branch of another amplifier stage of said CTIA amplifier structure,

[0038] the first sampling switch being provided to decouple the photodetector from the first integration capacitor during said third sampling phases,

[0039] the second sampling switch being provided to decouple the photodetector from the second integration capacitance during the said first sampling phases.

[0040] According to one possible implementation, each of said sequences may include a first sampling phase C0, a second sampling phase Cl, a third sampling phase C2 and a fourth sampling phase C3, the second sampling phase and the fourth sampling phase being carried out on another photodetector of another depth pixel, said polarization reset phases of said photodetector being carried out during the second sampling phases and during the fourth sampling phases, the repolarization switch being provided to couple said photodetector to said polarization reset block during the second sampling phases and during said fourth sampling phases.

[0041] According to another possible embodiment, each of said sequences comprises at least a first sampling phase, a second phase sampling, a third sampling phase and in which the second storage element provided with said second integration capability is integrated into another depth pixel, said other sampling phases C2 being the second sampling phases, said polarization reset phases of said photo-detector being carried out during said second sampling phase.

[0042] Advantageously, the amplifier stage can be formed:

[0043] - of a first transistor having a gate connected to the photodetector and a electrode, in particular a drain electrode, connected to the first integrating capacitor,

[0044] - of a second transistor mounted as a current source and having an electrode common with the first transistor.

[0045] wherein said depth pixels have a matrix arrangement, the device further comprising an external polarization block common to the depth pixels of the same row, in particular a horizontal row or a line of depth pixels.

[0046] The external biasing block may include a portion of circuit mounted in current mirroring with said second transistor.

[0047] The output stage integrated into said first pixel may be equipped with a follower transistor. This follower transistor may be connected to an output transistor activated, after an integration period, by a selection signal common to several other depth pixels, in particular to other depth pixels located on the same horizontal row or on the same line as said first depth pixel.

[0048] The output stage integrated into said first pixel can also be integrated into the reset transistor of the read node.

[0049] The reading circuit may further be provided with a reset switch in parallel with said feedback branch, intended to, when closed, reset the first integration capability prior to said integration period, said reset switch being open during said integration period.

[0050] According to a particular embodiment, the first pixel is provided with a second integration capacitance, the CTIA transimpedance capacitive amplifier structure being provided with at least one second amplifier stage, the second integration capacitance being arranged in another feedback branch between an input of said second amplifier stage and an output of said second amplifier stage, said input being connected to said detection node coupled to the photodetector and said output of said second amplifier stage being connected to a second reading node coupled to another output stage of said reading circuit.

[0051] Advantageously, said second amplifier stage can be formed:

[0052] - of a transistor having a gate connected to the photodetector and to a gate of a first transistor of said amplifier stage,

[0053] - of another transistor having a gate connected to the gate of a second transistor said amplifier stage.

[0054] The other output stage may be equipped with:

[0055] - of a follower transistor connected to a so-called output transistor activated by a signal of selection common to several other pixels of depth, in particular to other pixels of depth located on the same horizontal row or on the same line as said first pixel of depth,

[0056] - of a read node reset transistor.

[0057] When equipped with a second integration capability, the reading circuit is further equipped with another reset switch intended to, when closed, reset the second integration capability prior to said integration period, said other reset switch being open during said integration period.

[0058] Advantageously, the repolarization reset block is formed of a transistor mounted as a current source coupled to another transistor whose gate and drain are connected.

[0059] The photodetector can be a non-pinched photodiode in particular based on an IILV material such as InGaAs. Brief description of the drawings

[0060] The present invention will be better understood upon reading the description of the exemplary embodiments given, by way of illustration only and in no way limiting, with reference to the accompanying drawings in which:

[0061] [Fig-1] serves, through examples of signals respectively emitted and received, to illustrate different sampling phases implemented within an iTOF system;

[0062] [Fig.2] serves to illustrate an example of an implementation of a reading circuit following the invention of a depth pixel equipped with a CTIA amplifier stage and a means for resetting the polarization of a photo-detector of the pixel;

[0063] [Fig.3] serves to illustrate another example of a pixel reading circuit implementation depth with two amplification stages and two memory elements;

[0064] [Fig.4] serves to illustrate a particular embodiment of a reading circuit with 3T output stages connected to an external reading device common to a row of pixels;

[0065] [Fig.5] serves to illustrate an example of a signal sequence implemented in a image acquisition device during an integration period and then during a phase reading samples of charges resulting from this integration;

[0066] [Fig.6] serves to illustrate, by way of comparison, a one-pixel depth reading circuit with two amplification stages and two storage elements, but which does not include a polarization reset stage;

[0067] [Fig.7] serves to illustrate a particular embodiment of an image acquisition device made on several superimposed levels of circuits;

[0068] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0069] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0070] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0071] Reference is now made to [Fig.2] on which an electrical diagram of an example of a depth pixel Pi of an image sensor configured to acquire depth images of a scene is given.

[0072] The pixel Pi comprises a photodetector PD such as a photodiode, in particular a non-pinched photodiode. The photodiode may in particular be based on at least one semiconductor material suitable for operation in the infrared or near-infrared range, for example in a range between 700 nm and 1100 nm, in particular a group III-V semiconductor such as ITnGaAs or InGaN, or an ILVI material such as ZnS. The photodiode has its cathode connected to an ND detection node and its anode set at a low potential, in particular a reference potential or to ground (GND).

[0073] The photodetector PD is associated and connected to a pixel-integrated readout circuit Pb. This readout circuit has a storage element equipped with a first integrating capacitor C1NTi for acquiring samples of charges from the photodetector PD and photogenerated by detecting a reflected light signal at least during initial sampling phases C0 for initial durations, typically equal to each other and phase-shifted by a constant phase difference. The first integrating capacitor C1Nn is arranged here in a feedback branch between an input and an output of an amplifier stage Al of a CTIA (Capacitive Transimpedance Amplifier) ​​transimpedance amplifier structure.

[0074] Such a structure is compact and helps maintain the polarization of the PD photodetector while allowing high-frequency operation, for example at least 100 MHz. The input of the amplifier stage Al is coupled to the PD photodetector, while the output of the amplifier Al is connected to a readout node NL1, itself coupled via an output stage (not shown in this figure) to an external sample readout device (not shown in this figure).

[0075] A reset switch 28, controlled by an SRES signal, is provided here in parallel with the feedback branch, to allow the integration capability C1NTi to be reset at the beginning of an integration period during which several distinct sampling phases are carried out by separate storage elements of the image acquisition device.

[0076] This integration period includes a significant number of repeated sequences of sampling phases, typically with between several hundred and several million sampling phases carried out in order to implement a depth measurement.

[0077] Each sequence typically comprises a succession of sampling phases. Thus, a first sampling phase C0 is performed, a second sampling phase C1 offset from the first sampling phase C0 by a constant offset or phase shift, and a third sampling phase C2 offset from both the second and third sampling phases by a constant offset or phase shift. Advantageously, the sequence also comprises a fourth sampling phase C3 offset from both the second and third sampling phases by a constant offset or phase shift. A sequence of four sampling phases C0, C1, C2, C3 is thus typically repeated a given number k of times, with k typically greater than 10,000 and, for example, between 10,000 and 100,000.

[0078] The amplifier stage Al is made with a reduced number of transistors, here two Mb M2 transistors, which makes it possible to limit the size of the reading circuit.

[0079] The first transistor M2 of the amplifier stage Al, in the illustrated example of NMOS type, has a source electrode set at low potential and a drain electrode connected to the integrating capacitance C1NTia as well as to a second transistor M^ in the illustrated example of PMOS type, forming a current source.

[0080] For this purpose, the second transistor M1 can be mounted in current mirror with a portion 210 of the circuit belonging to an external biasing block BPE, which is not part of the readout circuit and is arranged outside the pixel Pb

[0081] This portion 210 of the circuit can be formed from a current source 212 and a transistor Ti whose gate and drain are connected to the gate of the second transistor ML. The external biasing block BPE is typically a circuit located at the edge of a set of sensor pixels, these pixels being typically arranged in a matrix.

[0082] To ensure that the polarization of the photodetector PD is maintained during the integration period, the pixel Pi is equipped with a polarization reset block 10. A repolarization switch 11 is then put into a conducting state (i.e., the "ON" or closed state) during polarization reset phases denoted RAZ, which allows the application of a polarization potential to the detection node N D*

[0083] These polarization reset phases RAZ are carried out here at least between two successive first sampling phases Co implemented by the capacitance C^n, to couple the photo-detector PD to the polarization reset block 10.

[0084] During the first sampling phases Co implemented through the capacitance C^n to acquire first samples, the repolarization switch 11 is put in a blocked state (i.e. "OFF" or open state) to decouple the photo-detector PD from the polarization reset block 10.

[0085] The repolarization reset block 10 is here formed of a transistor M3, in the illustrated example of the PMOS type, mounted in current mirror with the portion 210 of the circuit belonging to the external bias block BPE.

[0086] The M3 transistor of the bias reset block 10 and the second Ml transistor of the amplifier stage Al have their gates connected together and set to a potential VG imposed by the external bias block BPE, their respective sources being set to a high supply potential, for example VDD.

[0087] The bias reset transistor M3 of block 10 is coupled to another transistor M4, in this example of the NMOS type, whose gate and drain are connected. The repolarization switch 11, controlled by an SRAZ signal, is arranged here between the gate of transistor M4 and the ND detection node.

[0088] During RAZ polarization reset phases, the cathode of the PD photodiode is coupled to the gate of transistor M4.

[0089] The polarization reset phases are performed here between at least two successive first sampling phases C0 implemented by the integration capacitor C1Nn and during a time interval in which at least one sampling phase C1, C2, or C3 is performed by another storage element equipped with a different integration capacitor (not shown here) and, in this embodiment, located at at least one other pixel depth. Preferably, in this embodiment with one integration capacitor per pixel depth, at least two or three other pixels depth, each equipped with its own integration capacitor, are used to perform second sampling phases C1, third sampling phases C2, and fourth sampling phases C3 before restarting a new sampling sequence C0, C1, C2, C3.

[0090] A variant embodiment of the Pi pixel is given in [Fig.3].

[0091] The Pid pixel differs from the previously described example in that it is now equipped with a second memory element having a second CiNT2 integration capability. Thus, in this example, there are two integration capabilities. CiNTbC^^per pixel depth.

[0092] The first integration capacity C^n is intended to acquire samples of charges from the photo-detector PD and photo-generated by detection of the light signal reflected at least during first CO sampling phases typically equal to each other and phase-shifted from each other by a constant phase shift, while the second integration capacity CIXT2cst is intended to acquire samples of charges from the photo-detector PD and photo-generated by detection of the light signal reflected at least during C2 sampling phases, distinct from the first CO phases, typically equal to each other, and phase-shifted from the first CO phases by a constant phase shift.

[0093] The reading circuit is here provided with a first sampling switch 21 controlled by a signal S1Nn and arranged between the first integration capacitance C^n and the photo-detector PD, and a second sampling switch 31 controlled by a separate signal SinT2 and arranged between the second integration capacitance CiNT2 and the photo-detector PD.

[0094] During the first sampling phases C0, the first sampling switch 21, for example formed of at least one transistor, is made conducting (i.e. closed or "ON") in order to couple the photo-detector PD to the first integration capacitance Cjnti and acquire samples C0, while the second sampling switch 31, for example formed of at least one transistor, is made blocked (i.e. closed or "OFF") in order to isolate the photo-detector PD from the second integration capacitance C1NT2.

[0095] During the other sampling phases C2, the second sampling switch 31 is made conducting (i.e. closed or "ON") in order to couple the photodetector PD to the second integration capacitance CIXI2 and acquire samples, while the first sampling switch 21 is made blocked (i.e. closed or "OFF") in order to isolate the photodetector PD from the first integration capacitance C1Nn.

[0096] Polarization reset phases of the PD photodetector via the polarization reset block can be implemented each between a first sampling phase C0 carried out via the capacitance C1Nn of the first storage element and a sampling phase carried out C2 via the capacitance C1NT2.

[0097] Thus, between a first sampling phase C0 implemented through the CiNTi capacitor to acquire first samples and another sampling phase C2 implemented through the CiNt2 capacitor, the repolarization switch 11 is put into a conducting state (i.e., the "ON" or closed state) to couple the PD photodetector of the polarization reset block 10.

[0098] During the first CO sampling phases and the other C2 sampling phases, the CIXT21 repolarization switch 11 capacitance is typically put into a blocked state (i.e., "OFF" or open state) to isolate the PD photodetector from the polarization reset block 10.

[0099] The CTIA transimpedance capacitive amplifier structure differs from the example described above, notably in that it includes a second amplifier stage A2. This second amplifier stage A2 typically has an arrangement identical to that of the first amplifier stage AL

[0100] Thus, the second integration capacitance C^^ is arranged here in a second feedback branch located between an input of the second amplifier stage A2, itself coupled to the detection node ND and an output connected to a reading node NL2 itself coupled to an output stage (not shown in this figure) of the reading circuit.

[0101] A reset switch 18, controlled by the same SRES signal as the reset switch 8, is provided in parallel with the second feedback branch. The reset of the Cint1 and Cint2 capacitors is typically performed at the start of each integration phase, each comprising a repeated sequence of sampling phases.

[0102] The second amplifier stage A2 is also made with a reduced number of transistors, here two Mil transistors, M22. The second amplifier stage A2 is provided with an M22 transistor, here of the NMOS type, whose gate is coupled to the PD photodetector.

[0103] The transistor M22, in the illustrated example of NMOS type, has a source electrode set at the reference potential and a drain electrode connected to the integrating capacitor C1NT2 and to a second transistor Mi in the illustrated example of PMOS type, forming a current source.

[0104] For this purpose, the Ml I transistor can be mounted in current mirror with the same portion of circuit belonging to the same external biasing block BPE.

[0105] The repolarization switch 10 is put into a conducting state (i.e. “ON” or “closed”), by means of the SRAZ control signal during RAZ reset phases each situated between a first sampling phase CO performed by means of the capacitance CINT1 and another sampling phase C2 performed by means of the capacitance CINT2.

[0106] Two successive sampling sequences Seql, Seq2 performed by the first pixel PI readout circuit are shown as examples in [Fig. 3]. Each Seql, Seq2 sequence comprises a first sampling phase C0 implemented by the Cinti capacitor, followed by a polarization reset phase RAZ of the photodetector PD, and then a sampling phase C2 implemented by the capacity Cint2, followed by another polarization reset phase RAZ of the PD photodetector.

[0107] Thus, the polarization reset phases of pixel Pi are carried out between a first sampling phase CO and a third sampling phase C2, and in particular during second sampling phases Cl and fourth sampling phase C3, implemented by means of another pair of integrating capacitors (not shown), typically located on the same other pixel Pj (with j^l) of depth (not shown) having a structure similar to that of pixel Pb

[0108] The polarization reset phases of said PD photodetector are here carried out between a first CO sampling phase and a third C2 sampling phase of the Seql sequence or between a third C2 sampling phase of the Seql sequence and a first CO sampling phase of the following Seq2 sequence.

[0109] According to one embodiment, the polarization reset phases of this other pixel at depth Pj (with j^l) can each be carried out during a first sampling phase C0 conducted by the Cinti capacitance of pixel PI and during a third sampling phase C2 conducted by the Cint2 capacitance of pixel Pp

[0110] Fig. 4 gives an example of a particular embodiment of output stages 51, 61 of the PI depth pixel readout circuit described previously.

[0111] The reading circuit here comprises a first output stage 51 with three transistors coupled to the first storage element and in particular to the first integration capacitance C1Nn via a first reading node NL1, and a second output stage 61 with three transistors coupled to the second storage element and in particular to the second integration capacitance C1NT2 via a second reading node NL2.

[0112] The first output stage 51 consists of a source follower transistor 56, a selection transistor 58 and a reset transistor 54, these transistors being for example of the NMOS type.

[0113] Similarly, the second output stage 61 is formed of a source follower transistor 66, a selector transistor 68 and a reset transistor 64, for example all of the NMOS type.

[0114] The first output stage 51 is connected to a first external reading device DLE1 common to several pixels deep, while the second output stage 61 is connected to a second external reading device DLE2 common to several pixels deep.

[0115] Each external reading device DLE1, DLE2 is in this particular embodiment common to the pixels of the same column (i.e., vertical row) of pixels and may in particular be equipped with a correlated dual sampling (CDS) circuit with Cel and Ce2 sampling capabilities. Another sharing of external DLE1, DLE2 reading devices between depth pixels may be provided as an alternative.

[0116] Each integrating capacitance C^nCresp. is here coupled to the gate of the source follower transistor 56, (resp. 66) which, in this example, has its drain coupled to a high reference potential, in particular Vdd, and its source coupled to an external readout device DLE1 (resp. DLE2) via the selector transistor 58 (resp. 68) which is controlled by an RDZ signal applied to its gate.

[0117] Each first integrating capacitance C1Nn (resp. C1NT2) is also coupled to the high bias potential, in particular Vdd, through transistor 54 (res. 64) which is controlled by an RstZ signal applied to its gate.

[0118] Each external reading device DLE1, DLE2 has a first capacitor C1 which, when a switch 111 controlled by a signal CDS1 is turned on, integrates a current representative of all the charges resulting from the sampling phases performed by the integrating capacitor CiNTi (resp. C1NT2). A second capacitor Ce2 is made (when a switch controlled by a signal CDS1 is turned on) to integrate a current from the output stage 51, 61 after a reset of the reading node NL1, NL2 to which it is associated has been performed. Such a reset is controlled by means of a signal RstZ which activates (i.e., makes conductive) the reset transistor 54.

[0119] As can be seen on the timing diagram in [Fig.5], the RDZ signal is activated (in this example set to high) after an integration period when it is desired to read the charges accumulated by the integration capacitors C^n C1NT2.

[0120] A ResetZ reset signal enabling control of a switch in parallel with the storage capacities is activated (in this example set to high) while the RDZ signal is itself activated.

[0121] In [Fig.6], a depth pixel equipped with two integration capacitors C1Nn, C1NT2 dedicated to distinct sampling phases takes up an arrangement with a CTIA structure with two amplifier stages Al, A2.

[0122] With a reduced number of transistors this structure makes it possible to ensure the biasing of the PD photodetector.

[0123] Since the device here lacks a polarization reset circuit or block to apply a polarization potential between the samplings performed by either of the integration capacities CINT1, CINT2, the stabilization of the photodiode polarization throughout the integration period is not ensured here as in the embodiments described previously.

[0124] An image acquisition device having depth pixels as described above previously can be formed on several levels of circuits and / or superimposed components (also called "tiers" in Anglo-Saxon terminology).

[0125] Thus, in the particular embodiment illustrated in [Fig. 7], the depth pixel photodetector PD is located in a level NI, while the readout circuit with amplification stages A1, A2 and integration capacitors CINT1, CINT2 is arranged in another level, typically higher than N2, i.e., located above level NI. The external readout devices DLE1, DLE2 associated with a row of pixels, for example those equipped with a correlated double sampling (CDS) circuit, are typically found in a third level N3, in particular higher than levels NI and N2. The external biasing block BPE to which the CTIA structure is associated can also be arranged in the third level N3.

[0126] Levels NI, N2, N3 of components or circuits can be superimposed and linked together by an assembly technique commonly called "hybridization".

Claims

Demands

1. A device for acquiring depth images of a scene by detecting a reflected light signal corresponding to the reflection on the scene of an incident light signal, particularly in the near-infrared, the acquisition device having a plurality of depth pixels, at least one first pixel (Pi) among said depth pixels comprising a readout circuit associated with and connected to a photodetector (PD), the photodetector being a non-pinched photodiode, said readout circuit having at least one first storage element having a first integration capacitance (C1NTi) for acquiring first samples of charges from the photodetector (PD) during first sampling phases (Co) carried out during an integration period comprising repeated sequences of several successive sampling phases (Co, Cb, C2, C3) of charges,said image acquisition device being provided with at least one second storage element for acquiring, during other sampling phases (C2) of said sequences shifted relative to the first sampling phases (C0) according to a determined phase shift of sampling phases, other charge samples, wherein the first integrating capacitance (Cn) is located in a feedback branch between an input and an output of a first amplifier stage (AJ) of a transimpedance capacitive amplifier structure, said input being connected to a detection node (ND) coupled to the photodetector (PD) and said output being connected to a readout node (NLi) coupled to an output stage (51) of said readout circuit, and wherein the readout circuit further comprises a polarization reset block (10) for polarizing the photodetector (PD), with a repolarization switch (11) configured to,During polarization reset (RAZ) phases of said photodetector (PD) performed between said first sampling phases, couple the polarization reset block (10) to the photodetector (PD) so as to apply a polarization potential to it; during said first sampling phases, decouple the photodetector from the polarization reset block (10).

2. 2. Device according to claim 1, wherein said sequences include a first sampling phase (CO), a second

3. sampling phase (C1), a third sampling phase (C2), and a fourth sampling phase (C3), and wherein the second storage element is integrated into said first pixel (Pi) and is provided with a second integration capability (CIXI2) to acquire, during said third sampling phases (C2), samples of charges from said photodetector (PD), said polarization reset (RAZ) phases of said photodetector (PD) being carried out each between a first sampling phase (CO) and a third sampling phase (C2) of a given sequence or between a third sampling phase (C2) of a given sequence and a first sampling phase (CO) of a sequence following the given sequence.

3. Device according to claim 1 or 2, wherein each of said sequences comprises at least a first, a second, and a third sampling phase (CO, Cl, C2) and wherein the second storage element is provided with a second integration capacitor (C1NT2) integrated into said first pixel (Pi), the readout circuit further being provided: - a first sampling switch (21) arranged between the first integrating capacitor (Cinti) and the photodetector (PD), the first sampling switch (21) being configured to couple the photodetector (PD) to the first integrating capacitor (C1Nn) during said first sampling phases (CO), said first pixel reading circuit (PI) being further equipped: - a second sampling switch (31) between the second integrating capacitor (C1NT2) and the photodetector (PD), the second sampling switch (31) being configured to couple the photodetector (PD) to the second integrating capacitor during said third sampling phases (C2), the second integrating capacitor (C1NT2) being arranged in another feedback branch of another amplifier stage (A2) of said CTIA amplifier structure, the first sampling switch (21) being provided to decouple the photodetector (PD) from the first integration capacitance (Cinti) during the said third sampling phases (C2), the second sampling switch (31) being provided to decouple the photodetector (PD) from the second integration capacitance (CinT2) during the said first sampling phases (CO).

4. Device according to claim 3, wherein each of said sequences comprises a first sampling phase (CO), a second sampling phase (Cl), a third sampling phase (C2) and a fourth sampling phase (C3), the second sampling phase and the fourth sampling phase being carried out on another photodetector of another depth pixel, said polarization reset phases of said photodetector (PD) being carried out during the second sampling phases and during the fourth sampling phases, the repolarization switch (11) being provided to couple said photodetector (PD) to said polarization reset block (10) during the second sampling phases and during said fourth sampling phases.

5. Device according to claim 1, wherein each of said sequences comprises at least a first sampling phase, a second sampling phase, a third sampling phase and wherein the second storage element provided with said second integration capability (C1NT2) is integrated into another depth pixel (Pj), said other sampling phases (C2) being the second sampling phases, said polarization reset (RAZ) phases of said photodetector (PD) being carried out during said second sampling phase.

6. 6. Device according to any one of claims 1 to 4, wherein said amplifier stage (Al) is formed of: - a first transistor (Ml) having a gate connected to the photodetector (PD) and an electrode, in particular a drain electrode, connected to the first integrating capacitance (C1NTi), - a second transistor (M2) mounted as a current source and having a common electrode with the first transistor (Ml).

7. 7. Device according to claim 6, wherein said depth pixels have a matrix arrangement, the device further comprising an external bias block (EBC) common to the depth pixels of the same row, in particular a horizontal row or line of depth pixels, the external bias block (EBC) comprising a circuit portion mounted in current mirroring with said second transistor (M2).

8. 8. Device according to claim 6 or 7, wherein said The output stage (51) integrated with the first pixel (PI) is provided with: - a follower transistor (66) connected to an output transistor (58) activated, after an integration period, by a selection signal (RDZ) common to several other depth pixels, in particular to other depth pixels located on the same horizontal row or on the same line as the said first depth pixel (PI), - a read node reset transistor (NL1).

9. 9. Device according to any one of claims 6 to 8, wherein the readout circuit is further provided with a reset switch (8) in parallel with said feedback branch, provided that, when closed, it resets the first integration capacity (C^n) prior to said integration period, said reset switch (23) being open during said integration period.

10. 10. Device according to any one of claims 6 or 9, wherein said first pixel (PI) is provided with a second integrating capacitance (Cint2), the CTIA transimpedance capacitive amplifier structure being provided with at least one second amplifier stage (A2), the second integrating capacitance (Cint2) being arranged in another feedback branch between an input (ND) of said second amplifier stage (A2) and an output (NL2) of said second amplifier stage, said input being connected to said detection node (ND) coupled to the photodetector (PD) and said output of said second amplifier stage being connected to a second readout node (NLi) coupled to another output stage (61) of said readout circuit.

11. Device according to claim 10, wherein said second amplifier stage (A2) is formed of: - a transistor (M2i) having a gate connected to the photo-detector (PD) and to a gate of a first transistor of said amplifier stage (Al), - another transistor (Mn) having a gate connected to the gate of a second transistor (MJ) of said amplifier stage (Al).

12. Device according to any one of claims 10 or 11, wherein said other output stage (61) is provided with: - a follower transistor (66) connected to a transistor (58) said to be output activated by a selection signal (RDZ) common to several other depth pixels, in particular to other depth pixels located on the same horizontal row or on the same line as said first depth pixel (PI), - a read node reset transistor (NL1).

13. 13. Device according to any one of claims 10 to 12, wherein the readout circuit is further provided with another reset switch (18) intended to, when closed, reset the second integration capability (C1NT2) prior to said integration period, said other reset switch (18) being open during said integration period.

14. 4 Device according to any one of claims 1 to 13, wherein the repolarization reset block (10) formed of a transistor (M3) mounted as a current source coupled to another transistor whose gate and drain are connected.

15. 15. Device according to any one of claims 1 to 14, the photodiode being based on a III-V material such as InGaAs.

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