METHOD FOR CONTACTLESS COMMUNICATION BETWEEN AN OBJECT AND A READER USING ACTIVE CHARGE MODULATION

The described process and system facilitate rapid communication between NFC objects and readers by initializing and calibrating the oscillator's frequency and phase using an internal clock, addressing the challenge of fast survey readers that do not allow sufficient initialization time.

FR3141304B1Active Publication Date: 2025-02-07STMICROELECTRONICS FRANCE
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Patent Information

Application Number
FR2022010964
Authority / Receiving Office
FR · FR
Patent Type
Patents
Current Assignee / Owner
Filing Date
2022-10-21
Publication Date
2025-02-07
Estimated Expiration
2042-10-21

AI Technical Summary

Technical Problem

Existing NFC readers that quickly survey for the presence of cards do not allow sufficient time for objects in card mode to initialize their phase and frequency locking loops, preventing successful communication.

Method used

A process and system for an object to detect a reader's magnetic survey field, initialize a phase locking loop, calibrate the oscillator's frequency using an internal clock, and adjust the phase to enable rapid communication, even with readers that have short survey periods.

Benefits of technology

Enables objects to communicate effectively with NFC readers that have fast survey times by optimizing the oscillator's frequency and phase calibration within the reader's survey period, allowing for quicker response and successful data exchange.

✦ Generated by Eureka AI based on patent content.

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Patent Text Reader

Abstract

According to one aspect, an object is proposed that is configured to perform contactless communication with a reader (RD) using active load modulation. The object comprises: - means for detecting a reader field, - a phase-locked loop (PLL) including an oscillator (DCO) and configured to lock one phase of the oscillator (DCO) to the reader field, - a calibration system (SYSC) for the frequency of the phase-locked loop's oscillator (DCO), configured to calibrate the oscillator (DCO) frequency from an internal clock (CLKXO) when said detection means detect a stoppage of the reader field before the completion of an initialization of said phase-locked loop, and then to adjust the phase of the oscillator (DCO) when a new reader field is detected. Figure 1
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Description

Title of the invention: METHOD FOR CONTACTLESS COMMUNICATION BETWEEN AN OBJECT AND A READER USING ACTIVE CHARGE MODULATION

[0001] Implementation and realization methods of the invention relate to near field communication, i.e. contactless communication.

[0002] Near field communication (also known by the acronym NFC from the English "Near field communication") is a high-frequency, short-range wireless communication technology that allows data exchange between two devices without contact over a short distance, for example on the order of 10 cm.

[0003] NFC technology is an open technology platform standardized in ISO / IEC 18092 and ISO / IEC 21481 but incorporates many existing standards such as type A and type B protocols defined in ISO-14443 which can be communication protocols usable in NFC technology.

[0004] Near-field communication can be performed between a reader and an object that can be emulated in card mode. The reader is then configured to generate a magnetic field via its antenna, which is generally, according to commonly used standards, a 13.56 MHz sinusoidal wave. The strength of the magnetic field is, for example, between 0.5 and 7.5 amperes / meter in root mean square (RMS).

[0005] Near-field communication can be achieved in an active operating mode. In this operating mode, both the reader and the object generate an electromagnetic field. Generally, this operating mode is used when the object has its own power source, for example a battery, as is the case in a cellular mobile phone which is then emulated in card mode.

[0006] In particular, near-field communication can be achieved using active load modulation (also known by the acronym "ALM"). Active load modulation requires synchronization of signals between the reader and the object.

[0007] The reader is configured to emit an electromagnetic field, and the object is configured to modulate the amplitude of the field without beat. In order to respond to the reader, the object generates a signal synchronized with the reader's field so as to be in phase with the reader's field. It is therefore also important for the reader to generate a sufficiently stable field to be able to detect small variations in its field of view depending on the distance between the reader and the map emulator.

[0008] In reader mode or card emulator mode, it is important that the device generates the cleanest possible clock signal that allows communication with minimal energy consumption. To achieve this, it is necessary to reduce, or even eliminate, the presence of spurious tones in the generated clock signal.

[0009] The object includes a phase-locked loop. The phase-locked loop includes a phase- and frequency-locked oscillator based on a signal having a reference frequency that may be different from 13.56 MHz. The signal having the reference frequency may be a signal from the field generated by the reader. The oscillator is locked so as to obtain at the output of the phase-locked loop a signal having a desired frequency, for example, 13.56 MHz. The oscillator is then locked so as to generate a signal having a frequency that is a multiple of the desired frequency, for example, a frequency of 64 x 13.56 MHz for a desired frequency of 13.56 MHz. The object also includes a circuit for dividing the frequency of the signal generated by the oscillator so as to obtain a signal at the desired frequency, for example, 13.56 MHz.

[0010] In particular, the reader is configured to regularly emit a probing magnetic field to initiate communication with an object. The object is configured to lock the phase-locked loop oscillator to the frequency of the reader's field. Once the oscillator's frequency and phase are calibrated, the object is then configured to respond by generating a magnetic field having the same frequency and phase as the reader's probing magnetic field from the clock signal generated at the output of the phase-locked loop to communicate with the reader.

[0011] Generally, the reader's probing magnetic field is emitted for a sufficient time, for example for a period of 5 milliseconds, for the object to initialize its low-stall regulators and for the phase-locked loop to finish locking its oscillator to the reader's field.

[0012] However, some readers have an operation which does not fully comply with NFC technology.

[0013] In particular, readers are known that are configured to detect the presence of a card very quickly, compared to NFC technology standards. Such a reader is configured to regularly check if a card is present near the reader. To do this, in the same way as described above, the reader emits a magnetic field which it modulates in order to send a response request and then waits for a response if a card is present nearby. However, such a reader is configured to emit its field for a short time before sending its response request. Now, during this short period, an object When emulated in map mode, the device doesn't have time to initialize and lock the phase and frequency of its field to the reader's field. In this case, the reader doesn't receive a response from the device, even if it's nearby. The device is therefore unable to initiate communication with the reader.

[0014] There is therefore a need to propose a method enabling an object to communicate with a reader that quickly probes the presence of a card nearby.

[0015] According to one aspect, a contactless communication method between an object and a reader using active charge modulation is proposed, the method comprising: - emission by the reader of a probing magnetic field, then - detection of a probing magnetic field by said object, - initialization of a phase-locked loop of said object, the method further comprising: - detection of a stoppage of the reader's field before the completion of the initialization of said phase-locked loop of said object, - a calibration of the phase-locked loop oscillator of the object from an internal clock of said object, then - detection of a new magnetic field probing the reader, then - implementation of the phase-locked loop to adjust the phase of the oscillator to allow said object to respond to the reader.

[0016] Such a method allows the frequency of the phase-locked loop oscillator of the object to be initialized when a fast-probing reader is detected. This initialization sets the frequency of the phase-locked loop oscillator based on an internal clock of the object. Thus, the phase-locked loop is prepared to transmit a response to the reader more quickly when the latter emits a new field to probe the presence of the object. Indeed, upon detection of the new field, the object can simply adjust the phase of the generated signal to that of the field generated by the reader, because the frequency of the signal generated by the phase-locked loop oscillator is already the desired one. In particular, the frequency calibration of the oscillator can take between 200 ps (microseconds) and 300 ps, ​​while the phase adjustment of the oscillator can take only between 10 ps and 20 ps.By responding to the reader during the reader survey period, the object can initiate communication with the reader.

[0017] Such a method therefore allows an object to communicate with a reader even if the initialization time of its phase-locked loop is longer than the reader's probing period.

[0018] In an advantageous embodiment, the oscillator calibration is performed by measuring a frequency at the oscillator output, then comparing the measured frequency to a desired frequency, and then calibrating the frequency of the oscillator as a function of a comparison result.

[0019] Alternatively, the calibration of the oscillator is carried out using a frequency-locked loop to lock the frequency of the oscillator to the frequency of the internal clock.

[0020] In particular, the calibration may include an implementation of the frequency-locked loop to calibrate and lock the oscillator frequency from a value stored in a register when a stoppage of the reader's probing magnetic field is detected before the end of an initialization. Preferably, the phase-locked loop is implemented when a new reader probing magnetic field is detected to adjust the oscillator phase. Advantageously, the phase-locked loop is implemented when a new reader probing magnetic field is detected to lock the frequency-locked loop that controls the oscillator.

[0021] According to another aspect, an object is proposed that is configured to perform contactless communication with a reader using active charge modulation, the object comprising: - an internal clock, - detection means configured to detect a magnetic probing field from a reader, - a phase-locked loop comprising an oscillator and configured to lock one phase of the oscillator to the detected magnetic field of the reader, the phase-locked loop being configured to be initialized when a probing magnetic field is detected by said detection means, - a phase-locked loop oscillator frequency calibration system configured to calibrate the oscillator frequency from the internal clock when said sensing means detect a stoppage of the reader's probing magnetic field before the end of an initialization of said phase-locked loop of said object, and then to adjust the oscillator phase when a new reader's probing magnetic field is detected in order to respond to the reader.

[0022] In an advantageous embodiment, the calibration system is configured to measure a frequency at the output of the oscillator and to compare the measured frequency to a desired frequency, and then to calibrate the frequency of the oscillator according to a result of the comparison.

[0023] Alternatively, the calibration system includes a frequency-locked loop configured to lock the oscillator frequency to the internal clock frequency.

[0024] Advantageously, the calibration system is configured to: - implement the frequency-locked loop to calibrate and control the oscillator frequency from a value stored in a register, when said detection means detect a stoppage of the reader's probing magnetic field before the end of an initialization of said phase-locked loop of said object, then - implement the phase-locked loop when a new reader probing magnetic field is detected to adjust the oscillator phase so that it can respond to the reader.

[0025] Preferably, the calibration system is configured to implement the phase-locked loop when a new magnetic field probing the reader is detected to slave the frequency-locked loop that controls the oscillator.

[0026] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments, which are by no means limiting, and the accompanying drawings in which:

[0027] [Fig.1]

[0028] [Fig.2]

[0029] [Fig.3]

[0030] [Fig.4]

[0031] [Fig.5]

[0032] [Fig.6]

[0033] [Fig.7] illustrate embodiments and implementations of the invention.

[0034] Figure 1 illustrates one embodiment of a communication system (SYS) in Near field. The SYS system includes an RD reader and a CE object that can be emulated in card mode for near field communication. The CE object can be a multifunction phone, a smartwatch, etc. The CE object is configured to communicate using active load modulation (also known as ALM). Active load modulation requires signal synchronization between the RD reader and the CE object.

[0035] In particular, the RD reader includes an ANTR antenna configured to generate a magnetic field having a given frequency, in particular of the order of 13.56MHz.

[0036] The CE object includes an ANTC antenna configured to receive the magnetic field emitted by the RD reader and to emit a magnetic field. The object also includes a BAT battery for powering its various components.

[0037] The CE object includes a phase-locked loop (PLL). The phase-locked loop (PLL) includes a digital control oscillator (DCO). This DCO can be a digitally controlled or analog-controlled oscillator. For example, the digitally controlled oscillator can be a square wave generator. "ring oscillator"), specifically a ring oscillator. The phase-locked loop (PLL) is configured to lock the DCO oscillator's phase and frequency to the frequency and phase of the player's field. The PLL thus generates a signal with the same frequency and phase as the player.

[0038] The CE object also includes a TCH transmission chain configured to shape the signals to be transmitted via the antenna to communicate with the reader. The transmission chain uses the clock signal to generate a signal to be transmitted having the same frequency and phase as the reader's field.

[0039] The CE object includes at least one low-dropout regulator (also known as an LDO regulator) configured to supply the phase-locked loop

[0040] The CE object includes a reduced consumption mode in which some of its circuits are not supplied with energy, in particular the LDO regulator supplying the phase-locked loop.

[0041] The CE object is configured to exit reduced power consumption mode when it receives a magnetic field emitted by an RD reader.

[0042] In particular, the CE object is configured to initialize its phase-locked loop (PLL) when it receives a field from the RD reader. If the reader's probing magnetic field is emitted for a sufficient duration for the phase-locked loop (PLL) to be initialized, then the CE object is configured to receive the request from the RD reader and respond to it in order to initiate communication using the clock signal generated by the phase-locked loop (PLL) locked to the RD reader's field.

[0043] Alternatively, the RD reader can be a fast-probing reader. The reader's probing magnetic field is then emitted for an insufficient duration to allow the phase-locked loop (PLL) of the CE object to initialize.

[0044] However, in the illustrated embodiment, the CE object is still configured to communicate with a fast-probing RD reader.

[0045] In particular, the CE object is configured to detect if a received field stops before the completion of the phase-locked loop initialization. In this case, the CE object knows that the RD reader is a fast-probing reader.

[0046] If the CE object detects that the RD reader is a fast-probing reader, the CE object is configured to calibrate the frequency of the PLL phase-locked loop DCO oscillator using a frequency from a signal generated by an internal CLKXO clock. There are different ways to perform the calibration of the PLL phase-locked loop DCO oscillator. Figures 3 to 6 described below illustrate two different ways to perform this calibration.

[0047] Once the oscillator is calibrated, the CE object is configured to await the next emission of a probing magnetic field from the RD reader.

[0048] Once the new probing magnetic field of the RD reader is detected by the CE object, the latter is configured to implement the phase-locked loop (PLL) to calibrate the phase of the PLL oscillator to the phase of the probing magnetic field. When the phase of the DCO oscillator is calibrated, the CE object is configured to initiate communication with the RD reader.

[0049] Fig. 2 illustrates a method implemented by a CE object, such as that described above, to communicate with an RD reader in a contactless communication.

[0050] The process includes a step 20 in which the CE object is in its reduced consumption mode.

[0051] The method also includes a test 21 in which the CE object detects a field from the RD reader.

[0052] Next, if the CE object detects a field from the RD reader during test 21, then the method includes a step 22 for initializing the CE object. During this initialization step, the CE object activates the various elements necessary to initiate communication with the RD reader. For example, the CE object activates an LDO regulator. Activating the LDO regulator powers the PLL phase-locked loop. During the initialization step 22, the CE object performs calibration and locks the PLL phase-locked loop to the frequency and phase of the magnetic field.

[0053] Then, the method includes a test 23 to determine the presence of a field from the RD reader. In this step, the CE object evaluates whether the field from the RD reader is still detected or not.

[0054] If the CE object detects that the RD reader field is still present, then the CE object infers that the RD reader is configured to probe long enough to allow initialization of the CE object.

[0055] Thus, in this case, the method includes a test 24 to determine whether the calibration and locking of the phase-locked loop PLL are complete.

[0056] Once the frequency and phase of the DCO oscillator of the locking loop are locked to the frequency and phase of the magnetic field, and if the field of the RD reader is still present, the method includes a communication step 25 in which the CE object communicates with the RD reader.

[0057] Once the communication is complete, the CE object detects the end of the RD reader's field at test 26, then returns to step 20 in its reduced consumption mode until the next magnetic field detection.

[0058] If at step 22 (initialization of the CE object including the calibration of the loop to phase lock) the field disappears, so the CE object no longer detects the field of the RD reader during test 23. The CE object therefore deduces that the RD reader is a probing reader which is not configured to probe long enough to allow initialization of the CE object.

[0059] In this case, the method includes a step 27 in which the phase-locked loop (PLL) is implemented to lock the DCO oscillator to a desired frequency, for example, on the order of 64*13.56 MHz, from an internal clock of the CE object. In particular, the internal clock can be configured to generate a clock signal with a frequency between 13 MHz and 76 MHz. The method includes a test 28 for verifying that the oscillator is correctly calibrated to the desired frequency.

[0060] Next, once the DCO oscillator is calibrated to the desired frequency, the process includes a step 29 in which the CE object starts a timer while waiting for the next field detection.

[0061] The method then includes a test 30 in which the time counter value is evaluated against a predetermined duration. If the time counter reaches the predetermined duration without the CE object detecting a magnetic field in a test 31, then the CE object considers that the RD reader is no longer nearby. The CE object then returns to its reduced power consumption mode from step 20.

[0062] If the CE object detects a magnetic field in test 31 before the end of said predetermined time, then the method includes a step 32 in which the phase-locked loop PLL locks the frequency and phase of the DCO oscillator to the frequency and phase of the magnetic field.

[0063] Once the frequency and phase of the DCO oscillator are locked, the method includes a communication step in which the CE object communicates with the RD reader.

[0064] Once the communication is complete, the CE object detects the end of the RD reader's field at test 26, then returns to step 20 in its reduced consumption mode until the next magnetic field detection.

[0065] Such a method allows the frequency of the phase-locked loop (PLL) DCO oscillator of the CE object to be initialized when a fast-probing RD reader is detected. This initialization sets the frequency of the PLL phase-locked loop DCO oscillator from an internal CLKXO clock of the object. Thus, the PLL phase-locked loop is prepared so that the CE object can transmit a response to the reader more quickly when the latter sends a new response request to probe for the presence of a card. Indeed, upon detection of the new field, the CE object can only adjust the phase of the generated signal to that of the field generated by the reader, because the frequency of the signal generated by the PLL phase-locked loop DCO oscillator is already the desired one. In particular, the frequency calibration of the oscillator can take between 200 ps (microseconds) and 300 ps, while the oscillator phase adjustment can take only between 10 ps and 20 ps. By responding to the RD reader within the reader's polling period, the object can communicate with the reader.

[0066] Such a method therefore allows the CE object to be able to communicate with an RD reader even if the initialization time of its phase-locked loop PLL is longer than the probing period of the RD reader.

[0067] Figure 3 illustrates a first embodiment of a control system for the DCO oscillator of the PLL phase-locked loop, enabling the DCO oscillator to be controlled by an internal clock when the detected field originates from a high-speed probe reader RD. In particular, the CE object is configured to control the frequency of the PLL phase-locked loop's DCO oscillator with a control value dco_cal. The DCO oscillator has an output connected to a first input of a CDIV1 counter-divider. The CDIV1 counter-divider also has a second input configured to receive a clock signal of frequency Fref. This clock signal is generated by an internal clock of the CE object. The CDIV1 counter-divider is configured to generate a fdco signal. Fref

[0068] The CE object is configured to implement a machine with a finite number of states. This machine with a finite number of states allows the control value dco_cal to be set. In particular, [Fig. 4] illustrates a method that can be implemented by the machine with a finite number of states to control the DCO oscillator of the phase-locked loop (PLL). In particular, the method includes a step 40 in which the control system is in low-power mode and initializes the calibration control of the dco_cal oscillator to its minimum value. The method then includes a test 41 that allows the calibration of the phase-locked loop required in step 22 described previously to be started.

[0069] The method then includes a step 42 of measuring the output frequency of the DCO oscillator of the phase-locked loop PLL.

[0070] The method then includes a test 43 in which the measured frequency at the output of the DCO oscillator is compared to the desired frequency, for example, on the order of 64*13.56 MHz. If the measured frequency is lower than the desired frequency, then the method includes a step 44 in which the control value is incremented to increase the frequency of the DCO oscillator. Following the increment, a frequency measurement is taken again to verify whether the oscillator frequency has reached its value.

[0071] If the oscillator frequency reaches the desired frequency, then the calibration ends at step 45.

[0072] Figure 5 illustrates a second embodiment of a control system for the DCO oscillator of the phase-locked loop PLL allowing the DCO oscillator to be controlled from an internal clock when the detected field comes from a fast-probing RD reader.

[0073] The control system is a frequency-locked loop (FLL) configured to receive an FWW_TYP value as input. This FWW_TYP value can be stored in a register. The FWW_TYP value is a predefined value equal to where FDco_tr^t corresponds to the desired frequency for Fref the oscillator, for example 64*13.56MHz, Fref corresponds to the frequency of the internal clock.

[0074] The control system is implemented by a frequency-locked loop (FLL) controlling the same phase-locked oscillator (DCO) as the phase-locked loop. The frequency-locked loop (FLL) includes a counter-divider CDIV2. The counter-divider CDIV2 has a first input connected to the output of the DCO oscillator, and a second input configured to receive the reference frequency clock signal Fref generated by the internal clock CLKXO. The counter-divider CDIV2 is configured to generate a signal Fpco. The F-locked loop The FLL frequency also includes a CMP2 comparator with a first non-inverting input configured to receive the FWW_TYP value, and a second input configured to receive the Fpço signal. The frequency-locked loop F rej FLL also includes a loop filter FLL_f with an input connected to the comparator output, and an output connected to the DCO oscillator.

[0075] Figure 6 illustrates the frequency-locked loop of the integrated control system with the phase-locked loop for controlling the same DCO oscillator. In this example, the DCO oscillator is configured to output an output oscillator signal having a frequency equal to N * 13.56 MHz. N is preferably an integer equal to or greater than 1, for example, 64. N could also be a fraction, advantageously in conjunction with a delta-sigma converter to recover the average value.

[0076] The phase-locked loop PLL includes a loop filter PLL_f, the controlled oscillator DCO, and a first counter-divider CNT1 receiving on the one hand the output signal of the oscillator and on the other hand the clock signal CLKEX extracted from the field of the reader.

[0077] The output of the first counter-divider CDIV1 is fed back via a first comparator CMP1. In addition, optionally, an adder ADD1 allows adding a phase shift 4>offset, representative of the phase shift caused by the means arranged between the ANTC antenna and the phase-locked loop PLL.

[0078] The frequency-locked loop FLL includes here, as previously described, the loop filter FLL_f, the DCO oscillator, the CDIV2 counter-divider receiving at one end the output signal of the DCO oscillator and at the other end a reference clock signal CLKXO at the reference frequency Fref delivered by the internal clock CLKXO of the CE object.

[0079] The two loop filters PLL_f and FLL_f are here filters with a classic structure (typically incorporating stabilizing filters) and, in order to minimize any stability problems, are preferably designed such that the cutoff frequency of the FLL loop is higher than the cutoff frequency of the PLL loop. Thus, the time responses of both PLL and FLL loops are driven by the PLL loop.

[0080] The output of the CDIV2 counter is looped back to the input of the FLL_f loop filter via a CMP2 comparator.

[0081] In the present case, while the output of the first counter CDIV1 delivers the phase shift between the output signal of the oscillator and the CLEX clock signal extracted from the field of the reader, one of the flip-flops of the counter CDIV1 allows the DVCLK clock signal to be delivered, the frequency of which is divided by N, for example here 64, with respect to the frequency of the DCOS signal so as to obtain the frequency of 13.56 MHz up to said tolerance.

[0082] A switch is further placed between the PLL_f loop filter and the CMP2 comparator. The switch has a first input '0' configured to be connected to the output of the PLL_f loop filter, and a second input '1' configured to receive the FWW_TYP value. The switch also has an input configured to receive the start_on_dfll selection signal. The switch has an output connected to the input of the frequency-locked loop. The signal at the output of the switch thus corresponds to the output value of the PLL_f loop filter when the value of the start_on_dfll selection signal is equal to 0 and to the FWW_TYP value when the value of the start_on_dfll selection signal is equal to 1.

[0083] The switch is configured to allow only frequency-locked loop operation in the absence of a player field (the value of the selection signal is then equal to 1).

[0084] The switch is configured to allow phase-locked loop operation when the new magnetic field probing the reader is detected.

[0085] Figure 7 illustrates a method implemented by the control system to control the DCO oscillator of the phase-locked loop (PLL) using the frequency-locked loop (FLL). In particular, the method includes a step 70 in which the control system is in low-power mode and initializes the The control of the oscillator dco_cal is set to a minimum value. The method then includes a test 71 which initiates the calibration of the phase-locked loop required in step 22 described previously. To calibrate the phase-locked loop, the control system executes the frequency-locked loop in step 72 for a predetermined duration starting from the value FWW_TYP. The method then includes a test 73 in which the control value dco_ctrl of the oscillator is compared to the center frequency value dco_mid, specifically 64*13.56 MHz. Test 73 allows time for the frequency-locked loop to stabilize. If the control value dco_ctrl of the oscillator is less than the value dco_mid, this indicates that the oscillator frequency is lower than the desired frequency.If the oscillator frequency is lower than the desired frequency, then the process includes a step 74 in which the dco_cal value is incremented, before allowing the frequency-locked loop time to attempt to stabilize the oscillator frequency, centering it on the center frequency, specifically 64*13.56 MHz. If the control dco_ctrl value is no longer lower than the dco_mid value in the comparison test 73, this means that the oscillator has reached the desired frequency. The calibration then ends in step 75.

[0086] In this embodiment, the oscillator is controlled by the frequency-locked loop (FLL). However, alternatively, the oscillator can be controlled solely by the phase-locked loop (PLL).

Claims

Claims

1. Method for contactless communication between an object (CE) and a reader (RD) using active charge modulation, the method comprising: - an emission by the reader (RD) of a probing magnetic field, then - a detection of a probing magnetic field by said object (CE), - an initialization of a phase-locked loop (PLL) of said object (CE), the method further comprising: - a detection of a stopping of the field of the reader (RD) before the end of the initialization of said phase-locked loop of said object (CE), - a calibration of the oscillator (DCO) of the phase-locked loop of the object from an internal clock (CLKXO) of said object, then - a detection of a new probing magnetic field of the reader, then - an implementation of the phase-locked loop to adjust the phase of the oscillator (DCO) in order to allow said object to respond to the reader.

2. The method of claim 1, wherein the calibration of the oscillator (DCO) is performed by measuring an output frequency of the oscillator (DCO) and then comparing the measured frequency to a desired frequency, and then calibrating the frequency of the oscillator (DCO) based on a result of the comparison.

3. Method according to claim 1, wherein the calibration of the oscillator (DCO) is carried out using a frequency locked loop (FLL) to lock the frequency of the oscillator (DCO) to the frequency of the internal clock (CLKXO).

4. Method according to claim 3, in which the calibration comprises an implementation of the frequency locked loop (FLL) to calibrate and control the frequency of the oscillator from a value (FWW_TYP) stored in a register, when a stop of the magnetic probing field of the reader is detected before the end of an initialization, and in which the phase locked loop is implemented when a new magnetic probing field of the reader (RD) is detected to adjust the phase of the oscillator (DCO).

5. The method of claim 4, wherein the phase-locked loop is implemented when a new probing magnetic field of the reader (RD) is detected to slave the frequency-locked loop (FLL) which controls the oscillator (DCO).

6. Object configured to be able to carry out contactless communication with a reader using active charge modulation, the object comprising: - an internal clock (CLKXO), - detection means (ANTC) configured to detect a probing magnetic field of a reader, - a phase-locked loop (PLL) comprising an oscillator (DCO) and being configured to slave a phase of the oscillator (DCO) to the detected magnetic field of the reader (RD), the phase-locked loop being configured to be initialized when a probing magnetic field is detected by said detection means (ANTC),- a calibration system (SYSC) of the frequency of the oscillator (DCO) of the phase-locked loop configured to calibrate the frequency of the oscillator (DCO) from the internal clock (CLKXO) when said detection means detect a stoppage of the magnetic probing field of the reader before the end of an initialization of said phase-locked loop of said object, then to adjust the phase of the oscillator (DCO) when a new magnetic probing field of the reader (RD) is detected in order to be able to respond to the reader (RD).,

7. Object according to claim 6, in which the calibration system (SYSC) is configured to measure an output frequency of the oscillator (DCO) and to compare the measured frequency to a desired frequency, then to calibrate the frequency of the oscillator (DCO) according to a result of the comparison.

8. Object according to claim 7, in which the calibration system (SYSC) comprises a frequency locked loop configured to lock the frequency of the oscillator (DCO) to the frequency of the internal clock (CLKXO).

9. Object according to claim 8, in which the calibration system (SYSC) is configured to: - implement the frequency locked loop to calibrate and control the frequency of the oscillator from a value (FWW_TYP) stored in a register, when said detection means detect a stoppage of the reader's probing magnetic field before the end of an initialization of said phase-locked loop of said object, then - implement the phase-locked loop when a new reader probing magnetic field (RD) is detected to adjust the phase of the oscillator (DCO) in order to be able to respond to the reader (RD).

10. Object according to claim 9, in which the calibration system (SYSC) is configured to implement the phase-locked loop when a new probing magnetic field of the reader (RD) is detected to control the frequency-locked loop which controls the oscillator (DCO).