Display device and method for manufacturing such a device

Abstract

Display Device and Method for Manufacturing Such a Device This description relates to a device comprising: - a substrate (200) including electrical connection elements; - a plurality of first monolithic elementary chips (153) fixed and electrically connected to the substrate (200), each first elementary chip (153) including at least one LED and an integrated electronic circuit for controlling said at least one LED, the device further comprising, associated with at least one of the first elementary chips (153), a second elementary chip (223) including a vertical cavity laser diode emitting from the surface, fixed and electrically connected to the substrate (200), the first elementary chip (153) including an integrated electronic circuit for controlling said laser diode. Figure for the abbreviation: Fig. 4

Description

Title of the invention: Display device and method of manufacturing such a device technical field

[0001] This description relates generally to the field of image display devices, and more particularly to an interactive image display device, combining a light emission function and an optical capture function, and a method for manufacturing such a device. Previous technique

[0002] It has already been proposed, for example in patent applications WO2017089676, EP3401958 and WO2018185433 previously filed by the applicant, image display devices comprising a plurality of elementary monolithic electronic chips or microchips arranged in a matrix on the same transfer substrate. The elementary chips are mounted integral with the transfer substrate and connected to electrical connection elements of the transfer substrate for their control. Each chip comprises one or more light-emitting diodes (LEDs) and an integrated circuit for controlling said one or more LEDs, and corresponds to a pixel of the device. The integrated control circuit comprises a connection face opposite said one or more LEDs, comprising a plurality of electrical connection pads intended to be connected to the transfer substrate for controlling the microchip.The transfer substrate comprises a connection face comprising, for each microchip, a plurality of electrical connection pads intended to be connected respectively to the electrical connection pads of the microchip. The chips are attached to the transfer substrate, connection faces facing the connection face of the transfer substrate, and fixed to the transfer substrate so as to connect the electrical connection pads of each microchip to the corresponding electrical connection pads of the transfer substrate.

[0003] This type of display device is particularly suitable for producing large-area display screens, for example computer screens, television screens, tablet screens, etc.

[0004] The subject of interest here is more particularly the production of an interactive image display device combining a light emission function and an optical capture function. More particularly, the subject of interest here is the production of an interactive image display device combining a visible light emission function for displaying images, and a light emission-reception function, for example infrared, for detection applications. Summary of the invention

[0005] One embodiment provides a device comprising: - a carrying substrate comprising electrical connection elements; - a plurality of first monolithic elementary chips fixed and electrically connected to the substrate, each first elementary chip comprising at least one LED and an integrated electronic circuit for controlling said at least one LED, the device further comprising, associated with at least one of the first elementary chips, a second elementary chip comprising a vertical cavity laser diode emitting by the surface, fixed and electrically connected to the transfer substrate, the first elementary chip comprising an integrated electronic circuit for controlling said laser diode.

[0006] According to one embodiment, the device further comprises a plurality of photosensitive detectors, and, associated with each photosensitive detector, an integrated electronic circuit for reading the photosensitive detector electrically connected to the transfer substrate.

[0007] According to one embodiment, each photosensitive detector is associated with a first elementary chip, the electronic reading circuit of the photosensitive detector being integrated into said first elementary chip.

[0008] According to one embodiment, each photodetector comprises a photosensitive organic layer.

[0009] According to one embodiment, each photodetector comprises an inorganic photodiode, for example based on III-V type semiconductor materials, for example based on indium-gallium arsenide, or based on amorphous silicon.

[0010] According to one embodiment, each photodetector comprises a matrix layer, for example made of resin, in which quantum dots are incorporated.

[0011] According to one embodiment, each photodetector comprises a silicon photodiode in CMOS technology, an avalanche photodiode, or a detection device making it possible to acquire information regarding the distance between the device and the scene observed by direct or indirect measurement of the time of flight of the light.

[0012] According to one embodiment, the laser diode is adapted to emit in a range of wavelengths of sensitivity of the photodetectors, for example in the infrared.

[0013] According to one embodiment, in each first elementary chip, the electronic control circuit of said at least one LED and the electronic control circuit of the laser diode comprise MOS transistors formed in and on a layer of monocrystalline silicon.

[0014] According to one embodiment, in each first elementary chip, said at least one LED is an inorganic LED, for example gallium nitride.

[0015] According to one embodiment, in each first elementary chip, said at least one LED is adapted to emit visible light.

[0016] According to one embodiment, each first elementary chip comprises an integrated electronic circuit adapted to control a laser diode of a second elementary chip, and in which the number of second elementary chips is less than the number of first elementary chips, so that certain first elementary chips have their laser diode control circuit not connected to a laser diode.

[0017] According to one embodiment, the second elementary chip comprises two metal connection pads connected respectively to an anode region and to a cathode region of the laser diode, said two metal connection pads being connected respectively to two metal connection pads of the first elementary chip via conductive interconnection elements of the transfer substrate. Brief description of the drawings

[0018] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0019] [Fig.1A], [Fig.1B], [Fig.1C], [Fig.1D], [Fig.1E], [Fig.1F], [Fig.1G], [Fig.1H], [Fig.II] and [Fig.U] are cross-sectional views illustrating successive stages of an example of a process for manufacturing elementary pixel chips of an interactive display device according to an embodiment;

[0020] [Fig.2] is a top view schematically and partially illustrating an example of a transfer substrate of an interactive display device according to one embodiment;

[0021] [Fig. 3A], [Fig. 3B] and [Fig. 3C] are cross-sectional views illustrating successive stages of an example of a manufacturing process for an interactive display device according to one embodiment; and

[0022] [Fig.4] is a schematic top view of an example of an interactive display device according to one embodiment. Description of the embodiments

[0023] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0024] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the various applications that the described interactive display devices may have have not been detailed, the described embodiments being compatible with all or most of the known applications of an emissive display device integrating a light emission-reception function, for example applications for motion detection, face recognition, identification, etc.

[0025] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0026] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0027] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0028] According to one aspect of an embodiment, an image display device is provided comprising a plurality of elementary monolithic electronic chips arranged in an array on the same substrate. As in the examples described in the applicant's previously filed patent applications WO2017089676, EP3401958, and WO2018185433, the elementary chips are mounted securely to the substrate and connected to electrical connection elements of the substrate. Each chip comprises one or more LEDs and a control circuit for said one or more LEDs and corresponds to a pixel of the display device. The control circuit includes a connection face opposite said one or more LEDs, comprising a plurality of electrical connection areas (also called terminals or pads) intended to be connected to the substrate for controlling the microchip.The transfer substrate comprises a connection face comprising, for each microchip, a plurality of electrical connection pads (also called terminals or pads) intended to be connected respectively to the electrical connection pads of the microchip. The chips are attached to the transfer substrate, connection faces facing the connection face of the transfer substrate, and fixed to the transfer substrate so as to connect the electrical connection pads of each microchip to the corresponding electrical connection pads of the transfer substrate.

[0029] According to one aspect of an embodiment, the image display device further comprises a function for transmitting-receiving light radiation, for example infrared, allowing the detection of elements or variations in the device's environment.

[0030] For this purpose, the device includes a plurality of photosensitive detectors, for example organic photodetectors, for example arranged in a matrix according to rows and columns, defining an image sensor.

[0031] The display device further includes one or more vertical-cavity surface-emitting laser diodes, also called VCSELs (from the English "Vertical-cavity surface-emitting laser", adapted to emit in a wavelength range of sensitivity of photosensitive detectors.

[0032] The VCSELs are, for example, external to the pixel chips of the display device and are arranged on the device's carrier substrate, on the same side of the carrier substrate as the pixel chips. The VCSELs are, for example, connected to electrical connection terminals on the carrier substrate for control.

[0033] By way of example, the device comprises one VCSEL diode per elementary pixel chip of the device, arranged in the vicinity of said elementary pixel chip. In other words, the matrix of elementary pixel chips of the display device and the matrix of VCSEL diodes are interleaved matrices of the same dimensions and the same pitch.

[0034] The photodetectors are for example also external to the elementary pixel chips of the display device, and are arranged on the transfer substrate of the device, on the same side of the transfer substrate as the elementary pixel chips. The photodetectors are for example connected to electrical connection terminals of the transfer substrate for their reading.

[0035] By way of example, the device comprises one photodetector per elementary pixel chip of the device, arranged in the vicinity of said elementary pixel chip. In other words, the matrix of elementary pixel chips of the display device and the matrix of photodetectors are interlaced matrices of the same dimensions and the same pitch.

[0036] According to one aspect of an embodiment, each pixel chip of the display device incorporates an electronic control circuit for the corresponding VCSEL diode, i.e., the diode in the same position within the pixel matrix of the device. Each pixel chip of the device comprises two connection terminals linked, for example, respectively to the two electrodes of the VCSEL diode via conductive tracks of the substrate.

[0037] Each elementary pixel chip of the display device may further integrate an electronic circuit for reading an electrical signal representative of a light intensity received by the corresponding photodetector, i.e., one in the same position in the pixel matrix of the device. In this case, each elementary pixel chip The device includes for this purpose a connection terminal individually connected to an electrode of the associated photodetector via a conductive track of the carrying substrate.

[0038] Examples of embodiments of such an interactive display device will be described in more detail below in relation to the figures.

[0039] Figures 1A to 1J are sectional views illustrating an example of a method of manufacturing the elementary pixel chips of the device.

[0040] [Fig.1A] comprises a view (a) schematically representing a control structure comprising a first substrate 101 in and on which a plurality of elementary control integrated circuits 103 have been formed, for example identical or similar, corresponding respectively to the control integrated circuits of the future elementary pixel chips of the device.

[0041] In the example shown, the substrate 101 is a SOI (Semiconductor On Insulator) type substrate, comprising a support semiconductor substrate 101a, for example made of silicon, an insulating layer 101b, for example made of silicon oxide, arranged on and in contact with the upper face of the support substrate 101a, and an upper semiconductor layer 101c, for example made of monocrystalline silicon, arranged on and in contact with the upper face of the insulating layer 101b.

[0042] In this example, the elementary control circuits 103 are formed in and on the upper semiconductor layer 101c of the substrate 101. Each elementary control circuit 103 comprises, for example, a plurality of MOS transistors (not detailed in FIGS. 1A to II). The elementary control circuits 103 are, for example, produced in CMOS (Complementary Metal Oxide Semiconductor) technology. Each elementary control circuit 103 may comprise a circuit adapted to control the emission of light by the LED(s) of the future elementary pixel chip of the device, and a control circuit adapted to control the emission of light by the VCSEL diode associated with the future elementary pixel chip of the device. Each elementary control circuit 103 may further comprise a circuit for reading the photodetector associated with the future elementary pixel chip of the device.

[0043] In this example, each elementary control circuit 103 comprises, on its upper face side, one or more metal connection pads 105a, 105b. By way of example, the pads 105a, 105b are flush with the upper face side of an upper insulating layer, for example made of silicon oxide, of an interconnection stack (not detailed in the figures) covering the upper face of the upper semiconductor layer 103c of the substrate 101. Thus, in this example, the upper surface of the view control structure (a) is a flat surface comprising an alternation of metallic regions (the pads 105a, 105b) and insulating regions.

[0044] By way of example, each elementary control circuit 103 comprises a specific metal pad 105a for each LED of the future elementary pixel chip of the device, intended to be connected to an anode region of the LED and making it possible to individually control the emission of light by said LED. Each elementary control circuit 103 may further comprise a metal pad 105b intended to be connected to a cathode region of each LED of the future elementary pixel chip of the device. In the case where the elementary chip comprises several LEDs, the cathode contact may be common to all the LEDs of the chip. Thus, the elementary control circuit 103 may comprise a single metal pad 105b.

[0045] By way of example, each elementary pixel chip of the device comprises three individually controllable LEDs adapted to emit blue light, green light and red light respectively. In this case, each elementary control circuit 103 may comprise three separate metal pads 105a intended to be connected respectively to the anode regions of the three LEDs, and a single metal pad 105b intended to be collectively connected to the cathode regions of the three LEDs. In [Fig.lA], only two metal pads 105a and one metal pad 105b per electronic circuit have been shown.

[0046] [Fig.1A] further comprises a view (b) very schematically representing a structure comprising a second substrate 111, on the upper face of which rests an active stack of LEDs 113. The active stack of LEDs 113 is for example an inorganic stack of LEDs, for example based on one or more III-V type semiconductor materials, for example based on gallium nitride. The substrate 111 is for example made of sapphire or silicon.

[0047] The active LED stack 113 comprises, for example, in order starting from the upper face of the substrate 111, an N-type doped semiconductor layer forming a cathode layer, an active layer, and a P-type doped semiconductor layer forming an anode layer (layers not detailed in the figure). The active layer comprises, for example, an alternation of quantum well layers made of a first semiconductor material and barrier layers made of a second semiconductor material defining a stack of multiple quantum wells.

[0048] The active stack 113 can be formed by epitaxy on the upper face of the substrate 111. As an alternative, the active stack 113 is formed by epitaxy on a growth substrate, not shown, and then transferred to the upper face of the substrate 111.

[0049] At this stage, the stack 113 is not yet structured into individual LEDs. In other words, the layers of the stack 113 each extend continuously and with a substantially uniform thickness over the entire upper surface of the substrate 111.

[0050] [Fig.lB] comprises a view (a) illustrating a step of depositing a metal layer 107 on and in contact with the upper face of the control structure of view (a) of [Fig.lA]. In this example, the layer 107 extends continuously and with a substantially uniform thickness over the entire upper surface of the interconnection stack of the control structure of view (a) of [Fig.lA]. Thus, the layer 107 connects all the metal pads 105a, 105b of the control structure to each other.

[0051] [Fig. 1B] further comprises a view (b) illustrating a step of depositing a metal layer 115 on and in contact with the upper face of the active LED stack 113 of the structure of view (b) of [Fig. 1A]. The metal layer 115 may be a single layer or a stack of several metal layers. Preferably, the metal layer 115 comprises, on its upper face side, a layer made of the same material as the layer 107.

[0052] [Fig. 1C] illustrates the structure obtained at the end of a step of transferring and fixing the active stack of LEDs 113 and the metal layer 115 on the structure of view (a) of [Fig. 1B].

[0053] In [Fig.lC], the orientation of the structure of view (a) of [Fig.lB] remains unchanged. On the other hand, the elements of the structure of view (b) of [Fig.lB] are reversed with respect to the orientation of [Fig.lB].

[0054] During this step, the structure of view (b) of [Fig. 1B] is attached to the upper face of the structure of view (a) of [Fig. 1B], using the substrate 111 as a handle. The lower face (in the orientation of [Fig. 1C], corresponding to the upper face in the orientation of [Fig. 1B]) of the metal layer 115 is fixed to the upper face of the metal layer 107. The fixing is for example obtained by direct bonding or molecular bonding of the lower face of the layer 115 to the upper face of the layer 107, that is to say without adding material between the two layers.

[0055] The substrate 111 is then removed, for example by grinding and / or chemical etching, so as to free access to the upper face of the active LED stack 113, that is to say, in this example, the upper face of the cathode semiconductor layer of the active LED stack 113.

[0056] Figure 1D illustrates a trench formation step 121 extending vertically in the active LED stack from its upper face and laterally delimiting, in the stack 113, a plurality of islands 123 corresponding to the individual LEDs of the future elementary chips of the device. The trenches 121 are formed, for example, by plasma etching. In the example of Figure 1D, the trenches 121 are interrupted on the upper face of the metal layer 115. In a top view (not shown), the trenches 121 form a grid laterally separating the diodes. elementary 123 from each other.

[0057] [Fig. 1E] illustrates a subsequent step of vertical extension of the trenches 121 through the metal layers 107 and 115, for example using the same etching mask (not shown) as that used in the previous step. At the end of this step, the trenches 121 open onto the upper face of the interconnection stack covering the upper face of the substrate 101.

[0058] The portion of the stack of layers 107 and 115 remaining under each LED 123 at the end of this step constitutes an anode electrode of the LED. Said anode electrode is in contact, by its lower face, with the upper face of a metal connection pad 105a of the underlying elementary control circuit 103. Thus, each LED has its anode electrode individually connected to a metal connection pad 105a of an elementary control circuit 103.

[0059] In this example, a trench 121 is further formed opposite each metal connecting stud 105b so as to free access to the upper face of the studs 105b.

[0060] [Fig. 1E] further illustrates a subsequent step of passivation of the sides of the LEDs 123. For this, a layer 125 of an electrically insulating material, for example silicon oxide or silicon nitride, is deposited by a conformal deposition method on the upper face of the structure. The layer 125 then coats the upper face and the sides of the LEDs 123, as well as the sides of the portions of the metal layers 107 and 115 located under the LEDs 123, and, at the bottom of the trenches 121, the upper face of the interconnection stack coating the substrate 101. A vertical anisotropic etching step is then implemented to remove the horizontal portions of the layer 125, and to keep only the vertical portions of this layer, coating the sides of the LEDs 123 and the sides of the portions of the metal layers 107 and 115 located under the LEDs 123.

[0061] [Fig. 1F] illustrates a subsequent step of filling the trenches 121 with metal 127. For example, the metal 127 is initially deposited over the entire upper surface of the structure with a thickness greater than the depth of the trenches 121, so as to completely fill the trenches 121. A planarization step, for example by chemical-mechanical polishing, is then implemented to free access to the upper face of the LEDs 123. This gives a substantially flat upper surface on which the cathode semiconductor regions of the LEDs 123, the vertical insulation regions 125 of the LEDs, and the metal regions 127 filling the trenches 121 are flush. In top view (not shown), the metal regions 127 form a conductive grid laterally separating the LEDs 123 from each other.The metal regions 127 are electrically connected to the metal pads 105b at the bottom of the trenches 121, and define a contact metallization. common cathode to all 123 LEDs in the structure.

[0062] [Fig. 1G] illustrates a subsequent step of depositing a conductive layer 129, transparent to the emission wavelengths of the LEDs of the display device, on the upper face of the structure. The layer 129 extends for example continuously and with a substantially uniform thickness over the entire upper surface of the structure of [Fig. 1F]. The layer 129 is for example made of a transparent conductive oxide, for example indium-tin oxide (ITO). As a variant, the layer 129 may be a metal layer sufficiently thin to be transparent, for example a silver layer with a thickness of less than 80 nm.

[0063] The layer 129 is in contact, by its lower face, with the upper face of the cathode semiconductor regions of the LEDs 123, and defines a common cathode electrode of the LEDs 123. The layer 129 is also in contact, by its lower face, with the upper face of the metallic region 127. Thus, the layer 129 electrically connects the cathode semiconductor region of each LED 123 to the common cathode contact metallization 127 of the structure.

[0064] [Fig. 1H] illustrates a subsequent step of transferring the structure of [Fig. 1G] onto a temporary support substrate 140. In [Fig. 1H], the orientation of the structure is reversed with respect to the orientation of [Fig. 1G]. The temporary support substrate is fixed to the face of the conductive layer 129 opposite the substrate 101, i.e. its lower face in the orientation of [Fig. 1H] (corresponding to its upper face in the orientation of [Fig. 1G]). The temporary support substrate 140 is for example a silicon substrate. The fixing of the temporary support substrate 140 onto the conductive layer 129 can be obtained by means of an adhesive bonding layer, or by direct bonding.

[0065] [Fig. 1H] further illustrates a subsequent step of removing the support substrate 101a from the initial SOI structure, for example by grinding and / or chemical etching, so as to free access to the upper face of the insulating layer 101b of the SOL structure.

[0066] It will be noted that the embodiments described are not limited to the example described above in which the substrate 101 is an SOI type substrate. As a variant, the substrate 101 may be a bulk semiconductor substrate, for example made of silicon. In this case, in the step of [Fig. 1A], the substrate 101 may be thinned by its rear face (upper face in the orientation of [Fig. 1H]), for example by grinding. An insulating passivation layer, for example made of silicon oxide, may then be deposited on the upper face of the thinned substrate, replacing the layer 101b of the SOL substrate. As a variant, the layer 101b may be omitted.

[0067] Figure II illustrates the structure obtained after the formation of contact openings in layers 101b and 101c, and the formation of metallizations of Contact resumption 131 in and on said openings. The contact metallizations 131 allow electrical contact to be re-established on metallic levels (not detailed in the figures) of the interconnect stack located on the underside of the semiconductor layer 101c. The metallizations 131 are, for example, electrically connected to transistors of the control circuit, these transistors being themselves connected or electrically linked to connection metallizations 105a, 105b of the LEDs.

[0068] The metallizations 131 form connection terminals of the future elementary pixel chips of the device, intended to be connected to corresponding connection terminals of the transfer substrate of the device.

[0069] [Fig.U] illustrates the structure obtained at the end of a step of singularizing the elementary pixel chips of the device. For this, trenches 151 extending vertically through the layers 101b, 101c, 127 and 129 are formed from the upper face of the structure, along cutting lines. In this example, the trenches open onto the upper face of the temporary support substrate 140. In top view, the trenches 151 form a continuous grid laterally delimiting a plurality of elementary pixel chips 153, for example identical or similar, each comprising an elementary control circuit 103 and one or more LEDs 123. The trenches 151 are for example produced by plasma etching.

[0070] It will be noted that in the example described in relation to Figures 1A to 1J, the elementary LEDs 123 are formed from the same active stack of LEDs and all emit at the same wavelength. In the case where the elementary chips 153 each comprise several LEDs 123, steps of forming differentiated light conversion elements on the different LEDs 123 of each chip can be provided, for example after the deposition of the cathode conductive layer 129 and before the fixing of the temporary support substrate 140. For the sake of simplification, the production of the conversion elements has not been detailed in the figures. The production of these elements is within the abilities of the person skilled in the art upon reading the present description.Alternatively, each elementary chip may comprise LEDs 123 of distinct natures adapted to emit respectively in distinct wavelength ranges, in which case the conversion elements may be omitted.

[0071] The elementary pixel chips 153 are intended to be transferred onto a transfer substrate 200 of the display device, as will be described in more detail below in relation to FIGS. 3A to 3C.

[0072] [Fig.2] is a schematic and partial top view of an exemplary embodiment of the transfer substrate 200 of the display device.

[0073] The transfer substrate 200 comprises, for example, a support plate or sheet 201 made of an insulating material, for example glass or plastic. As a variant, the The substrate plate or sheet 201 comprises a conductive substrate, for example metallic, covered by a layer of insulating material. The substrate further comprises electrical connection elements, and in particular conductive tracks and conductive areas, formed on the upper surface of the substrate plate 201. These electrical connection elements are formed, for example, by printing a succession of conductive and insulating layers on the upper surface of the substrate plate 201. The electrical connection elements are formed, for example, by a deposition or printing process such as inkjet printing, screen printing, rotogravure, vacuum deposition, or any other suitable method.

[0074] In the example shown, the transfer substrate 200 comprises two conductive metal levels M1 and M2 separated by an insulating level (not visible in the figure), and metal vias V connecting the two metal levels through the insulating level. In this example, the transfer substrate 200 further comprises metal connection pads formed on the upper metal level M2, intended to be connected to corresponding connection pads 131 of the elementary pixel chips 153 of the device.

[0075] Active control circuits for the display device (not shown), adapted to power and control the elementary chips of the device via the electrical connection elements of the carrier substrate, are for example connected to the electrical connection elements of the carrier substrate at the periphery of the carrier substrate 200.

[0076] In the example shown, the manufacture of the transfer substrate comprises the following three successive deposition steps.

[0077] During a first deposition step, a plurality of conductive tracks substantially parallel to the direction of the columns of the display device (vertical direction in the orientation of [Fig. 2]) are formed on the upper face of the support plate 201. More particularly, in this example, during the first deposition step, four conductive tracks C1, C2, C3 and C4 are formed for each column of the display device, extending over substantially the entire length of the columns of the display device. The tracks C1 are intended to carry a DATA-L signal for adjusting the light intensity emitted by the LEDs 123 of the elementary chips 153 of the column.It will be noted that in this example - non-limiting - the intensity adjustment signals of the different colors (red, green, blue) are transmitted sequentially via the track CL. As a variant, not shown, several separate tracks can be provided to transmit in parallel, on separate terminals of each elementary chip, the intensity adjustment signals of the different colors. The tracks C2 are intended to carry a DATA-V signal for adjusting the light intensity emitted by the VCSEL diodes of the pixels of the column. The tracks C3 are intended to carry a signal. DATA-S representative of the light intensity received by the photodetectors of the pixels in the column. The C4 tracks are intended to distribute a high VDD supply potential to the various elementary pixel chips 153.

[0078] The conductive elements formed during this first deposition step define the first conductive level Ml of the transfer substrate.

[0079] During a second deposition step, the first conductor is covered with an insulating material (not visible in the figure), so as to allow the subsequent deposition of conductive tracks extending above the tracks C1, C2, C3 and C4, without creating a short circuit with the tracks C1, C2, C3 and C4.

[0080] During a third deposition step, a plurality of conductive tracks substantially parallel to the direction of the lines of the display device are formed on the upper face of the support plate 201. More particularly, in this example, during the third deposition step, three conductive tracks L1, L2 and L3 are printed for each line of the display device, extending over substantially the entire length of the lines of the display device. The tracks L1 are intended to carry a signal SEL-L for selecting the corresponding line of pixels. The tracks L2 are intended to carry a signal SEL-V for selecting the corresponding line of VCSEL diodes. The tracks L3 are intended to carry a signal SEL-S for selecting the corresponding line of photodetectors.

[0081] In this example, during the third deposition step, a metallic ELI region defining a lower electrode of the photodetector of the display device is further printed for each pixel of the device.

[0082] The conductive elements printed during this third deposition step define the second conductive level M2 of the transfer substrate.

[0083] After the third deposition step, for each pixel, ten metal pads PI, P2, P3, P4, P5, P6, P7, P8, P9 and P10 are formed on conductive areas of the metal level M2, intended to receive respectively ten connection pads 131 distinct from the elementary chip 153 of the pixel. In addition, for each pixel, two metal pads PI 1 and P12 are formed on conductive areas of the metal level M2, intended to receive respectively two connection pads distinct from the VCSEL diode of the pixel. Pads P6, P7 and P8 are connected respectively to the conductive tracks L1, L2 and L3 of the pixel. Pad P9 is connected to the electrode ELI of the pixel. Pads P5 and P10 are connected respectively to pads P1 and P12 of the pixel.The above-mentioned connections are made by conductive elements formed in the metal level M2, and, possibly, by vias V (open between the second and third deposition steps) and conductive elements formed in the metal level ML.

[0084] Figures 3A to 3C are sectional views illustrating successive steps of a example of a method of manufacturing an interactive display device according to one embodiment.

[0085] [Fig.4] is a schematic top view of the device obtained at the end of the method of Figures 3A to 3C.

[0086] Figures 3A and 3B illustrate more particularly a step of collective transfer of elementary pixel chips 153 onto the transfer substrate 200.

[0087] The individual chips 153 are initially attached to one face of the temporary support substrate 140. The structure comprising the temporary support substrate 140 and the individual chips 153 is, for example, produced by a method of the type described in relation to Figures IA to IJ. In the example shown, the structure is reversed with respect to the orientation of [Fig. U], i.e., the individual chips 153 are arranged on the underside of the temporary support substrate 140.

[0088] For the sake of simplification, in FIGS. 3A to 3C, the elementary chips 153 and the transfer substrate 200 have been shown schematically, and numerous elements have been omitted compared to the representations of FIGS. 1J and 2.

[0089] The elementary chips 153 are collectively attached opposite the connection face of the transfer substrate 200, namely its upper face in the orientation of FIGS. 3A and 3B, using the temporary support substrate 140 as a handle ([Fig.3A]).

[0090] The connection terminals 131 of elementary chips 153, located on the lower face side of said chips, are then brought into contact with the corresponding connection pads PI, P2, P3, P4, P5, P6, P7, P8, P9 and P10 of the transfer substrate 200, and fixed to said connection pads PI, P2, P3, P4, P5, P6, P7, P8, P9 and P10. The fixing of the connection terminals 131 of the elementary chips 153 to the connection pads of the transfer substrate is for example carried out by direct bonding, by thermocompression, by soldering, by means of metallic microstructures (for example micro-pillars) previously formed on the terminals 131, or by any other suitable fixing and connection method.

[0091] Once fixed, by their connection terminals 131, to the transfer substrate 200, the elementary chips 153 are detached from the temporary support substrate 140 and the latter is removed ([Fig.3B]), freeing access to the emission face of the LEDs 123 (not detailed in FIGS. 3A to 3C).

[0092] The spacing of the elementary chips 153 on the transfer substrate 200 may be greater than the spacing of the elementary microchips 153 on the temporary support substrate 140. Preferably, the spacing of the elementary chips 153 on the transfer substrate 200 is a multiple of the spacing of the elementary microchips 153 on the temporary support substrate 140. In this case, only a portion of the chips 153 are taken from the support substrate 140 with each transfer, as illustrated in Figures 3A and 3B. The remaining chips 153 remain attached to the temporary support substrate 140 and can be used during another collective transfer stage to populate another part of the transfer substrate 200 or another transfer substrate.

[0093] The method further comprises, before or after the step of transferring and fixing the elementary chips 153 onto the transfer substrate 200, a step of transferring and fixing, onto the same transfer substrate 200, elementary VCSEL diode chips 223 ([Fig. 4] - not visible in Figures 3A to 3C), distinct from the elementary chips 153. Each elementary VCSEL diode chip 223 comprises, for example, a single VCSEL diode. Each elementary VCSEL diode chip 223 comprises, for example, two metallic electrical connection areas arranged on the side of its face facing the transfer substrate, called the connection face, and intended to be fixed and electrically connected to the corresponding metallic connection areas PI1 and P12 of the transfer substrate 200.Each elementary VCSEL diode chip 223 comprises, for example, only two metal pads for connection to the transfer substrate 200, connected respectively to an anode region and to a cathode region of the VCSEL diode.

[0094] Each elementary VCSEL diode chip includes a light-emitting face disposed on the side of the chip opposite its connection face. The connection face and the emission face are, for example, parallel to the connection face of the substrate 200. By way of example, each VCSEL diode includes an active emissive layer disposed between two reflective structures, for example Bragg mirrors. The VCSEL diodes of the chips 223 are, for example, of the type described in the article entitled "Vertical-cavity surface-emitting lasers for optical interconnects" by Hui Li et al.

[0095] The elementary VCSEL diode chips 223 are for example transferred and fixed on the transfer substrate 200 by a collective transfer method, for example similar to the collective transfer method of the elementary pixel chips 153 described in relation to FIGS. 3A and 3B.

[0096] As a variant, the elementary VCSEL diode chips 223 are transferred and fixed on the transfer substrate 200 individually, for example by an automated pick and place process.

[0097] [Fig.3C] illustrates the device after fixing all of the elementary chips 153 and the elementary VCSEL diode chips 223 (not visible in the figure) on the transfer substrate 200.

[0098] [Fig. 3C] further illustrates a subsequent step of depositing, in each pixel, a portion of photosensitive organic layer 203, for example sensitive in the infrared or in the near infrared, on and in contact with the upper face of the ELI electrode of the pixel. The portions of layer 203 are for example deposited by a method localized printing, for example by screen printing or by a slot-die coating process. In each pixel, the organic layer portion 203 extends for example over the entire upper surface of the ELI electrode of the pixel.

[0099] [Fig.3C] further illustrates a subsequent step of depositing, in each pixel, an upper electrode EL2 on and in contact with the upper face of the photosensitive organic layer portion 203 of the pixel. The electrode EL2 extends for example over the entire upper surface of the photosensitive organic layer portion 203 of the pixel. The electrode EL2 is transparent to the sensitivity wavelengths of the layer 203. For example, the electrode EL2 is made of a transparent conductive oxide, for example ITO. In this example, in each pixel, the stack of the layers ELI, 203 and EL2 forms a photodetector 211. The electrodes ELI and EL2 correspond for example respectively to the cathode electrode and the anode electrode of the photodetector.

[0100] The electrodes EL2 can be deposited in a localized manner through a stencil. For example, the upper electrode EL2 is common to all the pixels of the device. The electrode EL2 forms, for example, in top view, a continuous grid covering the portions of photosensitive layer 203 of all the pixels of the device, for example as illustrated in the schematic top view of [Fig.4]. The common electrode EL2 can then be connected to a node for applying a fixed bias potential at the periphery of the pixel matrix.

[0101] As a variant, the photodetectors 211 can be formed before the steps of transferring and fixing the elementary chips 153 and 223 on the transfer substrate 200, or between the step of transferring and fixing the elementary chips 153 and the step of fixing the elementary chips 223 on the transfer substrate 200.

[0102] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the described embodiments are not limited to the particular examples of embodiments of the pixel element chips and the transfer substrate described in connection with FIGS. 1A to 1J, 2, 3A to 3C and 4.

[0103] Furthermore, the described embodiments are not limited to the particular case described above in which the photodetectors of the device are organic photodiodes. As a variant, the organic photodetectors of the described device may be replaced by inorganic photodetectors, for example based on IILV type semiconductor materials, for example based on indium-gallium arsenide, or based on amorphous silicon. In another variant, the photodetectors 211 may consist of a matrix layer, for example made of resin, in which are in incorporated quantum dots. Alternatively, the photodetectors may be silicon photodiodes in CMOS technology, avalanche photodiodes, for example SPAD (Single Photon Avalanche Diode) type, or any other detection device making it possible to detect a light signal backscattered by the scene, for example making it possible to acquire information on the distance between the device and the observed scene, for example by direct or indirect measurement of the time of flight of the light.

[0104] Furthermore, the embodiments described are not limited to the particular example described above in which the electronic reading circuit of each photodetector 211 is integrated into the elementary chip 153 of the corresponding pixel. As a variant, the electronic reading circuit of the photodetector may be integrated into a separate chip. In this case, the photodetector 211 may not be connected to the elementary chip 153 of the pixel. For example, the photodetector 211 and the electronic reading circuit of the photodetector 211 may be integrated into the same monolithic chip separate from the chips 153 and 223, fixed and electrically connected to corresponding electrical connection pads of the transfer substrate 200. In another variant, each photodetector 211 may be integrated into the elementary chip 153 of the corresponding pixel.

[0105] Furthermore, the described embodiments are not limited to the particular examples described above in which the device comprises one VCSEL diode elementary chip 223 and one photodetector 211 per visible pixel elementary chip 153. Alternatively, the number of VCSEL diode elementary chips 223 may be less than the number of elementary chips 153. In this case, in certain elementary chips 153, the VCSEL diode control circuit is not used. Similarly, the number of photodetectors 211 may be less than the number of elementary chips 153.

[0106] Furthermore, the described embodiments are not limited to the examples described above of application to interactive display devices, but may apply more generally to other LED emissive devices that can benefit from the use of VCSEL type emissive cells.

[0107] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Claims

1. Image display device, comprising: - a transfer substrate (200) comprising electrical connection elements; - a plurality of first monolithic elementary chips (153) fixed and electrically connected to the transfer substrate (200), each first elementary chip (153) comprising at least one LED (123) and an integrated electronic circuit for controlling said at least one LED (123), the device further comprising, associated with at least one of the first elementary chips (153), a second elementary chip (223) comprising a vertical cavity laser diode emitting by the surface, fixed and electrically connected to the transfer substrate (200), the first elementary chip (153) comprising an integrated electronic circuit for controlling said laser diode.

2. Device according to claim 1, further comprising a plurality of photosensitive detectors (211), and, associated with each photosensitive detector, an integrated electronic circuit for reading the photosensitive detector electrically connected to the transfer substrate (200).

3. Device according to claim 2, in which each photosensitive detector (211) is associated with a first elementary chip, the electronic circuit for reading the photosensitive detector (211) being integrated into said first elementary chip.

4. A device according to claim 2 or 3, wherein each photodetector (211) comprises a photosensitive organic layer.

5. Device according to claim 2 or 3, in which each photodetector comprises an inorganic photodiode, for example based on III-V type semiconductor materials, for example based on indium-gallium arsenide, or based on amorphous silicon.

6. Device according to claim 2 or 3, in which each photodetector comprises a matrix layer, for example made of resin, in which quantum dots are incorporated.

7. Device according to claim 2 or 3, in which each photodetector comprises a silicon photodiode in CMOS technology, an avalanche photodiode, or a detection device making it possible to acquire information as to the distance between the device and the scene observed by direct or indirect measurement of the time of flight of the light.

8. Device according to any one of claims 2 to 7, in which said laser diode is adapted to emit in a range of wavelengths of sensitivity of the photodetectors (211), for example in the infrared.

9. Device according to any one of claims 1 to 8, in which, in each first elementary chip (153), the electronic circuit for controlling said at least one LED and the electronic circuit for controlling the laser diode comprise MOS transistors formed in and on a layer (103c) of monocrystalline silicon.

10. Device according to any one of claims 1 to 9, wherein, in each first elementary chip (153), said at least one LED (123) is an inorganic LED, for example gallium nitride.

11. Device according to any one of claims 1 to 10, wherein, in each first elementary chip (153), said at least one LED (123) is adapted to emit visible light.

12. Device according to any one of claims 1 to 11, in which each first elementary chip (153) comprises an integrated electronic circuit adapted to control a laser diode of a second elementary chip (223), and in which the number of second elementary chips (223) is less than the number of first elementary chips (153), so that certain first elementary chips (153) have their laser diode control circuit not connected to a laser diode.

13. Device according to any one of claims 1 to 12, in which said second elementary chip (223) comprises two metal connection pads connected respectively to an anode region and to a cathode region of the laser diode, said two metal connection pads being connected respectively to two metal connection pads of the first elementary chip (153) via conductive interconnection elements of the transfer substrate (200).

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