Integrated circuit comprising a passive component in an interconnection part, corresponding manufacturing process.
By integrating a dielectric structure that increases substrate resistivity through vertical extension, the quality factor of passive components in integrated circuits is enhanced, addressing the performance degradation caused by thermal budgets.
Patent Information
- Application Number
- FR2022012439
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-11-28
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2042-11-28
AI Technical Summary
The quality factor of passive components in integrated circuits is adversely affected by the decrease in resistivity of the semiconductor substrate due to thermal budgets during manufacturing, leading to decreased performance.
Incorporating a dielectric structure that extends vertically into the substrate from the front face to a second depth greater than a first depth, increasing the resistivity of the substrate and aligning with the position of the passive component, using materials like silicon dioxide or low-k materials to form a monolithic block.
The increased resistivity of the substrate enhances the quality factor of passive components, reducing leakage and improving performance.
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Abstract
Description
Title of the invention: Integrated circuit comprising a passive component in an interconnection part, corresponding manufacturing method.
[0001] Embodiments and implementations relate to integrated circuits, in particular integrated circuits comprising a passive component in a part of interconnections, and to manufacturing processes for such integrated circuits.
[0002] The interconnecting part conventionally comprises metal levels, including interconnecting tracks and vias vertically connecting the tracks from one level to another.
[0003] The interconnection part is typically made on top of a semiconductor substrate of the integrated circuit.
[0004] Passive components, such as in particular coils or inductive elements, can typically be made in one of the last metal levels of the interconnecting part.
[0005] They conventionally exhibit a quality factor which depends on the resistivity of the semiconductor substrate located opposite their positions in the metal level.
[0006] In particular, due to losses in the substrate, the quality factor of passive components decreases when the resistivity of the substrate is lower, and increases when the resistivity of the substrate is higher.
[0007] That being said, an increase in the resistivity of the semiconductor substrate does not classically improve the quality factor of passive components.
[0008] Indeed, the resistivity of the substrate near the front face decreases greatly due to "thermal budgets" or "annealing", typically applied in the semiconductor substrate during the manufacture of the integrated circuit.
[0009] Thus, there is a need to improve the performance, in particular to increase the quality factor, of the passive components of integrated circuits.
[0010] According to one aspect, an integrated circuit is proposed in this regard comprising a semiconductor substrate having a front face comprising insulation structures extending vertically into the substrate from the front face to a first depth.
[0011] The integrated circuit also includes an interconnecting portion comprising metal layers incorporating at least one passive component, above the front face of the substrate.
[0012] The integrated circuit further comprises a dielectric structure aligned vertically with the position of said at least one passive component, and extending vertically into the substrate from the front face to a second depth greater than the first depth.
[0013] Indeed, depending on the nominal resistivity (i.e. for example before annealing) of the semiconductor substrate, the resistivity of the substrate increases vertically in depth in an advantageous way, compared to the resistivity at the front face level, from the order of magnitude of the depth of conventional insulation structures.
[0014] For example, the insulation structures may be shallow insulation trenches (usually "STI" for "Shallow Trench Isolation" in English).
[0015] These insulation structures, such as shallow insulation trenches, can have a first depth on the order of a few hundred nanometers "nm", for example 300 nm, or between 100 nm and 500 nm.
[0016] A second depth, for example on the order of 500 nm to 1 micrometer “pm”, can allow the resistivity of the semiconductor substrate to be increased by a factor of 2 to 10, depending on the nominal resistivity of the semiconductor substrate, relative to the resistivity taken at the front face level.
[0017] Thus, according to one embodiment, the second depth can be chosen so that the resistivity of the semiconductor substrate at the level of the second depth is at least one and a half times greater than the resistivity of the substrate at the level of the first depth, or even at least twice greater, or even four to five times greater.
[0018] For example in this respect, the first depth is between 0.1 pm (micrometer) and 0.5 pm (micrometer) and the second depth is between 0.3 pm (micrometer) and 1.5 pm (micrometer).
[0019] According to one embodiment, said dielectric structure comprises a monolithic block of a dielectric material.
[0020] Such a monolithic block can occupy a volume located vertically from the metal level of the passive component of the interconnecting part up to said second depth of the substrate.
[0021] According to another embodiment, said dielectric structure comprises a monolithic block of a dielectric material, which can occupy a volume located vertically from one of the metal levels of the interconnecting part, between the front face of the substrate and the metal level of the passive component, up to said second depth of the substrate.
[0022] For example, the monolithic block of dielectric material can be made of silicon dioxide or of a material with a low relative dielectric constant.
[0023] Materials with a low relative dielectric constant are usually called "low-k" or "1ow-k" ("low-kappa") according to the usual English term and are perfectly known to those skilled in the art.
[0024] According to another aspect, a method for manufacturing an integrated circuit comprising is also proposed: - the formation of insulating structures in a semiconductor substrate extending vertically from a front face of the substrate to a first depth, - a formation, above the front face of the substrate, of an interconnecting part comprising metal levels incorporating at least one passive component, comprising, prior to the formation of said passive component, a formation of a dielectric structure extending vertically in the substrate from the front face to a second depth greater than the first depth, and aligned vertically with the position of the future passive component.
[0025] According to an embodiment that can be considered independently, the second depth is chosen so that the resistivity of the semiconductor substrate at the level of the second depth is at least one and a half times greater than the resistivity of the substrate at the level of the first depth, or even at least twice greater, or even four to five times greater.
[0026] For example, the first depth is between 0.1 pm (micrometer) and 0.5 pm (micrometer) and the second depth is between 0.3 pm (micrometer) and 1.5 pm (micrometer).
[0027] According to one embodiment, said formation of the dielectric structure comprises the formation of a monolithic block of a dielectric material.
[0028] This monolithic block can occupy a volume located vertically from the metal level of the passive component of the interconnecting part up to said second depth of the substrate.
[0029] For example, the formation of the monolithic block includes -an etching step removing said volume from all metal levels of the interconnecting portion below the metal level of the passive component, and down to the second depth of the substrate, -filling the volume with the dielectric material, and - a removal of excess flattened dielectric material at said metal level of the passive component.
[0030] According to one embodiment, said formation of the dielectric structure comprises the formation of a monolithic block of a dielectric material.
[0031] In this embodiment, this monolithic block can occupy a volume located vertically from one of the metal levels of the interconnecting part, between the front face of the substrate and the metal level of the passive component, up to said second depth of the substrate.
[0032] For example, the formation of the monolithic block includes -an engraving of said volume in all metal levels of the part interconnection below said metal level of the interconnecting part, and down to the second depth of the substrate, -filling the volume with the dielectric material, and -a removal of excess flattened dielectric material at said metal level of the interconnecting part.
[0033] For example, said monolithic block of dielectric material is silicon dioxide.
[0034] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiment and implementation, which is in no way limiting, and the accompanying drawings, in which:
[0035] [Fig. 1], and
[0036] [Fig.2], and
[0037] [Fig.3], and
[0038] [Fig.4], and
[0039] [Fig.5], and
[0040] [Fig.6], and
[0041] [Fig.7], and
[0042] [Fig.8] schematically illustrate embodiments and implementations of the invention.
[0043] Figures 1 to 4 illustrate steps in an example implementation of a manufacturing process for an integrated circuit IC comprising a passive LHQ element, in particular a high quality factor inductive element.
[0044] Fig. 1 schematically illustrates a cross-sectional view of the integrated circuit IC after a step 100 of the formation of the interconnecting part BE.
[0045] The BE interconnection part is usually referred to by extension by the acronym "BEOL" from the English terms "Back End Of Line" (literally "end of line (of production)").
[0046] This acronym "BEOL" designates the manufacturing steps of the BE interconnection part, comprising a network of conductive metal tracks for carrying the signals from the integrated circuit CL
[0047] Prior to the interconnection part BE, a semiconductor part FE of the integrated circuit CI was formed, from a front face FA of a semiconductor substrate SUB.
[0048] The FE semiconductor part is usually referred to by extension by the acronym "FEOL" from the English terms "Front End Of Line" (literally "start of (production) line").
[0049] This acronym “FEOL” designates the manufacturing steps of the FE semiconductor part, carried out in the SUB substrate on the front face side FA and on the front face before FA.
[0050] The semiconductor part FE includes in particular active elements, such as TM transistors of the metal oxide semiconductor type “MOS” and / or bipolar transistors TB.
[0051] In addition, the FE semiconductor part includes STI insulation structures, the formation of which is usually implemented during the very first stages of manufacturing the integrated circuit IC.
[0052] STI isolation structures are typically designed to laterally isolate active components at the front face FA, and thus delimit "active regions" in the SUB substrate.
[0053] The STI insulation structures extend vertically in this respect into the SUB substrate from the front face FA to a first depth PL
[0054] For example, STI insulation structures can be shallow insulation trenches (usually in English "Shallow Trench Isolation").
[0055] The formation of these shallow insulation trenches includes etching open trenches from the front face FA, then filling these open trenches with a dielectric material such as silicon dioxide.
[0056] Furthermore, the steps in forming the FE semiconductor part typically include annealing steps, requiring "thermal budgets", including high-temperature treatments of varying durations.
[0057] The different annealing stages tend to lower the resistivity of the SUB substrate at the front face FA, in particular due to the migration phenomenon of dopants from the SUB substrate.
[0058] The pattern of the reduction of the resistivity R according to the depth P of the substrate SUB is illustrated for example in [Fig.8].
[0059] The formation steps of the semiconductor part FE are completed by the formation of a pre-metal oxide layer PMD covering the front face FA and encompassing the elements (for example transistors TM, TB) formed on the front face FA.
[0060] Vertical metallic contacts are provided to electrically connect the elements of the FE semiconductor part.
[0061] The interconnecting part BE is formed above the front face FA of the substrate SUB, on the pre-metal oxide layer PMD thus formed.
[0062] The PMD pre-metal dielectric layer can be considered to belong to the BE interconnection part.
[0063] In the vertical direction Z perpendicular to the front face FA of the substrate SUB, the top of the front face FA is defined in the direction directed outwards from the substrate SUB, and the bottom in the direction directed from the front face FA inwards from the substrate SUB. SUB substrate.
[0064] The interconnecting part BE comprises levels of metals M1, ..M5, comprising PM5 metal tracks located in intermetal dielectric layers IMD, usually made of silicon oxide.
[0065] The PM5 metallic tracks of each level are typically made by a Damascus process comprising an overfilling of openings etched in the inter-metal dielectric layer IMD, with molten metal.
[0066] The excess metal above the IMD dielectric layer is removed by flattening, typically by chemo-mechanical polishing "CMP" (for "Chemical-Mechanical Polishing" in English), stopped by an AR stop layer, typically silicon nitride.
[0067] The metal tracks of successive metal levels can be connected by vertical vias V5, made in via levels MV5.
[0068] The levels of via MV5 are a particular designation for levels of metals of the same nature as those which contain PM5 metallic tracks.
[0069] In step 100, the structure of the integrated circuit IC is thus classically ready for the formation of the metal level M6 which will contain a passive component LHQ, at a known position.
[0070] Figures 2 and 3 illustrate steps 200, 300 of a formation of a dielectric structure BLMN, before the formation 400 of said metal level M6 which will contain a passive component LHQ.
[0071] The BLMN dielectric structure extends vertically into the substrate from the front face FA to a second depth P2 greater than the first depth PI, and is aligned vertically with the position of the future passive component LHQ.
[0072] Fig. 2 illustrates a 200 etching step removing a volume in all metal levels MV5, M5, ..., M1 of the interconnecting part BE below the metal level M6 of the passive component, and in the pre-metal dielectric layer PMD as well as the shallow insulation trenches STI down into the substrate SUB at the second depth P2.
[0073] For example the vertical height h of the engraving can be on the order of ten micrometers "pm", for example between 5 pm and 15 pm.
[0074] The width w of the engraving corresponds to the width of the metallic track of the passive component LHQ, for example a track forming a loop of an inductive element, can be between 1 pm and 25 pm.
[0075] Of course, the values of the height h and the width w are not limited, and depend on the choice of embodiment of the passive component, including the thickness of the etched metal levels.
[0076] The etching technique, for example of the deep reactive ion etching type (usually "DRIE" for "Deep Reactive Ion Etching" in English), can be chosen and adapted so as to be able to etch a given width w to a given depth h.
[0077] Figure 3 illustrates a step 300 of the formation of the BLMN dielectric structure of the Damascus type, comprising -a filling of the engraved volume with a dielectric material, and -a removal of excess flattened dielectric material at the level of the M6 metal level of the passive component.
[0078] For example, the filling of the etched volume with the BLMN dielectric material can be done by a high-density plasma dielectric deposition technique “HDPD” (for “High Density Plasma Deposition” in English), for example a chemical vapor deposition of silicon dioxide.
[0079] The excess of the BLMN dielectric material above the last inter-metal dielectric layer IMD_MV5 is also removed by chemical-mechanical polishing (CMP) type flattening, stopped by the AR_MV5 silicon nitride stop layer.
[0080] For example, the BLMN dielectric material is silicon dioxide, or a material with a low relative dielectric constant, usually called "low-k" or "1ow-k" ("low-kappa") according to common English terminology, and are perfectly known to those skilled in the art.
[0081] "Low-k" materials refer to all dielectric materials that can be used in the microelectronics industry and that have a relative dielectric constant "k" or "K" (kappa) lower than the relative dielectric constant of silicon dioxide.
[0082] Thus, a monolithic block of BLMN dielectric material was formed.
[0083] This monolithic block of BLMN dielectric material occupies the volume located vertically from the metal level M6 of the passive component LHQ of the BE interconnection part up to the second depth P2 of the substrate.
[0084] Indeed, these Damascene-type steps 200-300, -result in the formation of a single, homogeneous dielectric material, thus constituting a monolithic BLMN block of the dielectric material; -unlike, for example, the structure of the surrounding BE interconnection part, which comprises a succession of IMD silicon oxide and AR silicon nitride layers (and, moreover, metallic traces and vias)
[0085] Figure 4 illustrates a device after a 400 step of metal level formation. M6 including the passive component LHQ.
[0086] This metal level M6 comprises metal tracks PM6 produced by Damascus processes identical to the process described in relation to [Fig. 1] for the PM5 metallic track formation.
[0087] For example, among the PM6 metallic tracks, a structure such as a winding of at least one loop, makes it possible to realize the passive component LHQ of the inductive element type.
[0088] Figures 5 to 7 illustrate an example of an alternative to the manufacturing process described in relation to Figures 1 to 4.
[0089] The elements of the example in Figures 5 to 7 that are common with the example in Figures 1 to 4 support the same references and will not all be detailed again.
[0090] Figure 5 illustrates a device after step 500 of this alternative, in which the opening of the volume receiving the monolithic block is engraved just before the formation of the first layer of metal ML
[0091] Thus, the opening is etched in the pre-metal dielectric IMD, in the shallow insulation trenches STI and in the semiconductor substrate SUB, up to the second depth P2 (greater than the first depth PI of the shallow insulation trenches STI).
[0092] The opening of the 500 stage can also be engraved in all metal levels, from any of the metal levels of the interconnecting part BE located between the front face FA of the SUB substrate and the metal level M6 comprising the passive component LHQ, up to the second depth P2 in the SUB substrate.
[0093] Fig. 6 illustrates a device after step 600 of filling the volume of the opening engraved in step 500 with the dielectric material BLMN2, and a removal of excess dielectric material flattened at said level of metal Ml of the interconnecting part.
[0094] Thus, a monolithic block of BLMN dielectric material was formed.
[0095] This monolithic block of dielectric material BLMN occupies the volume located vertically from one of the metal levels (for example from the first metal level M1) of the interconnecting part BE, between the front face FA of the substrate SUB and the metal level M6 of the passive component LHQ, up to the second depth P2 of the substrate.
[0096] Figure 7 illustrates a device after a step 700 in which all levels of subsequent metals, up to the level of metal M6 containing the passive component LHQ, were formed.
[0097] The passive component LHQ is as described previously in relation to [Fig.4].
[0098] The alternative described in relation to Figures 5 to 7 presents in particular the advantage of engraving a smaller height h2, and therefore implementation in a shorter time.
[0099] However, this alternative has the disadvantage, compared to the process described in relation to Figures 1 to 4, that the SUB substrate may have to endure annealing steps subsequent to the formation of the monolithic dielectric block BLMN, during the formation of the interconnecting part BE.
[0100] That being said, the annealing of the BE interconnecting part is typically less important than that of the FE semiconductor part.
[0101] They also generate a lesser reduction in the resistivity of the surface substrate.
[0102] In a third alternative, the etching to form the monolithic dielectric block BLMN can be done before the formation of the transistors TB, TM, for example at the time when the shallow insulation trenches STI are made.
[0103] Fig. 8 schematically illustrates the integrated circuit IC obtained by the processes described above in relation to figures 1 to 4 and 5 to 7.
[0104] The integrated circuit IC particularly comprises the dielectric structure BLMN aligned vertically with the position of said passive component LHQ, and extending vertically in the substrate SUB from the front face FA to a second depth P2 greater than the first depth PL
[0105] Fig. 8 further shows, on the right, a graph representing the resistivity R of two examples of substrate SUB 125, SUBlk, in ohm-centimeters “ohm*cm”, as a function of the depth P in the substrate, in micrometers “pm”.
[0106] The two examples of substrate SUB 125, SUBlk correspond to substrates having nominal resistivities, that is to say summarily the resistivity at any point of the substrate before the annealing phases, respectively of 125 ohm*cm for a substrate of "medium resistivity" SUB 125, and of 1000 ohm*cm for a substrate of "high resistivity" SUB 1k.
[0107] In practice, after the annealing phases, the resistivity R of the SUB 125, SUBlk substrates increases when going vertically into the depth P, in a way that is advantageous compared to the resistivity at the front face FA, from approximately 1 pm, or even from 0.5 pm.
[0108] The depth axis P is aligned on the schematic of the integrated circuit IC, in particular at the origin point P=0 pm at the front face FA of the substrate SUB.
[0109] The first PI depth of the STI lateral isolation structures can be on the order of a few tenths of a micrometer, for example 0.3 pm, or between 0.1 pm and 0.5 pm.
[0110] At the first depth P1, -the resistivity of the substrate with average resistivity SUB 125 is, for example, 20 to 25 ohm*cm; and -The resistivity of the high resistivity substrate SUBlk is, for example, 50 ohm*cm.
[0111] The second depth P2 is greater than the first depth PL This second depth P2 is advantageously chosen so that the resistivity of the semiconductor substrate SUB at the level of the second depth P2 is at least twice greater than the resistivity of the substrate at the level of the front face FA, for "P=0".
[0112] At a second depth P2 of 1 pm, -the resistivity of the SUB 125 substrate can for example be on the order of 40 ohm*cm; and -the resistivity of the high resistivity substrate SUBlk is for example 250 ohm*cm.
[0113] Thus, by etching the silicon of the SUB substrate in depth, the resistivity seen by the passive component LHQ, in particular an inductive element, is higher and the leakages are lower, so that the quality factor of the passive component has been increased.
Claims
Demands
1. Integrated circuit comprising a semiconductor substrate (SUB) having a front face (FA) comprising insulation structures (STI) extending vertically in the substrate from the front face to a first depth (PI), and an interconnect portion (BE) comprising metal levels incorporating at least one passive component (LHQ), above the front face (FA) of the substrate, the integrated circuit further comprising a dielectric structure (BLMN) aligned vertically with the position of said at least one passive component (LHQ), the dielectric structure extending vertically in the substrate from the front face to a second depth (P2) greater than the first depth (PI);in which said dielectric structure comprises a monolithic block (BLMN) of a dielectric material, occupying a volume located vertically from the metal level (M6) of the passive component of the interconnecting part up to said second depth (P2) of the substrate.;
2. Integrated circuit according to claim 1, wherein the second depth (P2) is chosen such that the resistivity of the semiconductor substrate (SUB) at the level of the second depth is at least one and a half times greater than the resistivity of the substrate at the level of the first depth (PI).
3. Integrated circuit according to any one of claims 1 or 2, wherein the first depth (PI) is between 0.1 pm and 0.5 pm and the second depth (P2) is between 0.3 pm and 1.5 pm.
4. Integrated circuit according to any one of claims 1 to 3, wherein said monolithic block (BLMN) of dielectric material is made of silicon dioxide or of a material with a low relative dielectric constant.
5. A method for manufacturing an integrated circuit comprising: - the formation of insulation structures (STI) in a semiconductor substrate (SUB) extending vertically from a front face (FA) of the substrate to a first depth (PI), - the formation, above the front face (FA) of the substrate, of an interconnecting portion (BE) comprising metal layers incorporating at least one passive component (LHQ), comprising, prior to the formation of said passive component (LHQ), the formation of a dielectric structure (BLMN) extending vertically in the substrate from the front face up to a second depth (P2) greater than the first depth (PI), and aligned vertically with the position of the future passive component (LHQ); wherein said dielectric structure formation comprises a monolithic block formation (BLMN) of a dielectric material, occupying a volume located vertically from the metal level (M6) of the passive component of the interconnecting part up to said second depth (P2) of the substrate.
6. A method according to claim 5, wherein the second depth (P2) is chosen such that the resistivity of the semiconductor substrate at the second depth is at least one and a half times greater than the resistivity of the substrate at the first depth (PD-
7. A method according to any one of claims 5 or 6, wherein the first depth (PI) is between 0.1 pm and 0.5 pm and the second depth (P2) is between 0.3 pm and 1.5 pm.
8. A method according to any one of claims 5 to 7, wherein the formation of the monolithic block (BLMN) comprises an etching step removing said volume in all metal levels of the interconnecting part (BE) below the metal level (M6) of the passive component, and down to the second depth (P2) of the substrate, filling the volume with the dielectric material, and removing excess flattened dielectric material at said metal level (M6) of the passive component.
9. Integrated circuit according to any one of claims 5 to 8, wherein said monolithic block (BLMN) of dielectric material is made of silicon dioxide or of a material with a low relative dielectric constant.