Power detector
Patent Information
- Application Number
- FR2022014192
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-12-22
- Publication Date
- 2025-03-14
- Estimated Expiration
- 2042-12-22
Smart Images
Figure 00000012_0000 
Figure 00000012_0001 
Figure 00000013_0000
Abstract
Description
Title of the invention: Power detector Technical field
[0001] The present description relates to a power detector for determining the power of an alternating signal. Prior art
[0002] Root mean square power detectors, also called rms power detectors, are based on average power measurement, and are particularly suitable for accurate power measurements of radio frequency modulated signals which have a high peak-to-average ratio or noise-like property.
[0003] An rms power detector may for example be used in a radio frequency receiver comprising amplifiers and an automatic gain control circuit which can control the gains of the amplifiers based on the rms power measured by the rms power detector. A disadvantage of an rms power detector is that it may have a high power consumption. Another disadvantage of an rms power detector is that it may have a low sensitivity. Summary of the Invention
[0004] An object of an embodiment is to provide an rms power detector which overcomes all or part of the disadvantages of existing rms power detectors.
[0005] Another object is that the rms power detector has reduced power consumption.
[0006] Another object is that the rms power detector has improved sensitivity.
[0007] One embodiment provides a power detector for detecting power rms of an alternating voltage, comprising a transconductor configured to receive the voltage and to provide a first current to a node with a non-linear relationship between the first current and the voltage, a current-output digital-to-analog converter configured to receive a digital signal and to provide a second current to the node, a low-pass filter connected to the node, and an inverter connected to the node and configured to provide a binary signal.
[0008] According to one embodiment, the transconductor comprises a first MOS transistor.
[0009] According to one embodiment, the low-pass filter comprises a first capacitor having an electrode connected to the node.
[0010] According to one embodiment, the current output digital to analog converter comprises second MOS transistors and switches com- controllable, each second MOS transistor being in series with one of the controllable switches, each controllable switch being controlled by a bit of the digital signal.
[0011] According to one embodiment, the power detector comprises a current source configured to provide a reference constant current and first current mirrors configured to copy the reference constant current multiplied by different multiplicative coefficients, each first current mirror comprising one of the second MOS transistors.
[0012] According to one embodiment, the power detector comprises a third MOS transistor mounted as a diode, the gate of the third MOS transistor being connected to the gate of the first MOS transistor via a resistor and a second current mirror configured to copy the constant reference current to power the third MOS transistor.
[0013] An embodiment also provides an electronic circuit comprising the power detector described above and an electronic unit configured to receive the binary signal and to modify the digital signal until the binary signal is toggled.
[0014] According to one embodiment, the electronic circuit is a radiofrequency receiver or a radiofrequency transmitter.
[0015] According to one embodiment, the electronic circuit comprises an amplifier configured to receive a radio frequency alternating voltage and to amplify the radio frequency alternating voltage, the amplifier being a transconductance amplifier comprising a fourth MOS transistor, and the first MOS transistor is a scale replica of the fourth MOS transistor.
[0016] An embodiment also provides a method for determining the rms power of an alternating voltage using the power detector described above, comprising modifying the digital signal until the binary signal switches.
[0017] According to one embodiment, the method comprises setting the alternating voltage to a constant value and modifying the digital signal until the binary signal is toggled and storing the digital signal for which the binary signal has toggled. Brief description of the drawings
[0018] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0019] [Fig.l] partially and schematically represents an embodiment of a power detector;
[0020] [Fig.2] is a block diagram of an embodiment of a method for calibrating the power detector shown in [Fig.l];
[0021] [Fig.3] partially and schematically represents an embodiment of a digital to analog converter with current output;
[0022] [Fig.4] partially and schematically represents another embodiment of a power detector;
[0023] [Fig.5] partially and schematically represents another embodiment of a power detector; and
[0024] [Fig.6] partially and schematically represents an embodiment of a radiofrequency receiver circuit. Description of the embodiments
[0025] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed.
[0026] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be linked by means of one or more other elements. In addition, a signal which alternates between a first constant state, for example, a low state, noted "0", and a second constant state, for example, a high state, noted "1", is called a "binary signal". The high and low states of the different binary signals of the same electronic circuit can be different. In practice, binary signals can correspond to voltages or currents which may not be perfectly constant in the high or low state.
[0027] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%. In addition, the expression "substantially constant" means that it varies by less than 10% over time compared to a reference value.
[0028] The rms value of an alternating signal is defined as the amount of direct current signal required to produce an equivalent amount of heat in the same load. Therefore, the rms voltage Vrms of an alternating voltage V is given by the following relationship: [Math 1] V rms ^avg[v 2 (t)]
[0029] The power P(dBm) of an alternating signal V, expressed in dBm, is given by the following relation: [Math 2] y-„ àvg[y2(t)] PWBmMOlog.^MOlog^^
[0030] According to one embodiment, the rms power detector comprises, in order to perform the power detection of the input alternating voltage, a transconductor receiving the input alternating voltage and providing an output current and having a non-linear characteristic between the output current and the input voltage. The transconductor may be a metal-oxide-semiconductor field effect transistor, hereinafter referred to as a MOS transistor.
[0031] [Fig. 1] partially and schematically represents an embodiment of a power detector 10 configured to determine the rms power of a signal Vrf, for example a radiofrequency alternating voltage. The power detector 10 is connected between a source of a high reference potential Vdd and a source of a low reference potential Gnd, for example the ground considered to be equal to 0 V.
[0032] The power detector 10 comprises: - an IN input receiving the Vrf voltage; - an OUT output providing a binary voltage VOut; - a MOS MO transistor, for example an N-channel MOS transistor, the source of the MOS MO transistor being connected, preferably connected, to the source of the low reference potential Gnd, the drain of the MO transistor being connected, preferably connected, to a node D; - a digital to analog converter with current output C-DAC controlled by a digital control signal S and connected, preferably connected, between node D and the high reference potential source Vdd; - a resistor R connected, preferably connected, between the gate of the MO transistor and a source of a bias voltage Vbias; - a first capacitor CRF connected, preferably connected, between the input IN and the gate of the transistor MO; - a second capacitor Cfiit connected, preferably connected, between node D and the low reference potential source Gnd; and - an inverter INV, the input of the inverter INV being connected, preferably connected, to node D, and the output of the inverter INV being connected, preferably connected, to the output OUT.
[0033] The power detector 10 is controlled by an electronic control circuit P, for example a microcontroller, receiving a binary voltage VOut and providing a control signal S.
[0034] The operation of the detector 10 is described below. The C-DAC converter provides a current iDAC at the node D which depends on the control signal S. The control signal S is a digital signal having N+1 bits So to SN, N being an integer for example greater than or equal to 3. The bit So is for example the least significant bit of the control signal S. The current at the drain of the transistor MO is called ioui and the gate-source voltage of the transistor MO is called Vgs. The first derivative of the current i0UT with respect to the voltage Vgs is called gm and the second derivative of the current i0UT with respect to the voltage Vgs is called gm'. When the voltage VRF is equal to 0 V, the current i0UT is equal to a constant current ibias. The voltage across the capacitor Cfiit is called Vfiit.
[0035] Without taking into account the filtering action of the capacitor Cfiit, the current i0UT is given by the following relation, neglecting the terms higher than the second order terms: [Math 3] yes^Wgmv RF +gm^
[0036] When the VRF voltage is a sinusoidal voltage having a pulsation co and a maximum amplitude VRb, the input voltage VRF is given by the relation:
[0037] vRF=VRF-cos(œt)
[0038] The Math 3 relation then becomes: [0°39] iOUT=ib.as+gnrVRF-cos^^ wt ) )2
[0040] The current i0UT is averaged by the filtering action of the capacitor Cfiit, so that the actual current i0UT is given by the following relation: [Math 6] [Math.5] ioUT=Îbias+Sm' 'VRF
[0041] In the Math 6 relation of the current i0UT, the second term is proportional to the rms power of the VRF voltage. The detector 10 detects the continuous amplitude of the second-order distortion product generated by the nonlinear characteristics of the MOS transistor MO by comparing the current i0UT with the current iDAC generated by the C-DAC converter and detecting when the current iDAC is equal to the current i OUT*
[0042] According to one embodiment, the C-DAC converter is controlled so that the current iDAC is increased from 0 A. Therefore, initially the current iDAC is lower than the maximum current i0UT that can be conducted by the MO transistor. The voltage VfiH is therefore substantially at the low reference voltage Gnd. The voltage V out is at logic value "1". The command S is modified to increase the current iDAc* As soon as the current iDAC becomes greater than the maximum current i0UT that can be driven by the transistor MO, the voltage Vfiit is driven by the transistor MO and increases to be approximately equal to the high reference voltage Vdd minus the voltage across the converter C-DAC and is greater than the threshold of the inverter INV. The voltage Vfiit consequently decreases instantly above the threshold of the inverter INV so that the voltage VOut is at a low logic value "0". Therefore, the voltage VOut switches from a high logic value "1" to a low logic value "0" when the current iDAC is equal to the current i0UT- The switching of the voltage VOut is detected by the control circuit P and the value Stog of the control signal S for which the voltage VOut switches from a high logic value "1" to a low logic value "0" is stored.
[0043] Since the ibias current is known, the second term of the Math 6 relation can be determined.
[0044] The detector 10 compares in a single branch the drain current i0UT of the MO transistor to a calibrated current iDAC using the voltage Vfiit at the node D which is a high gain rail-to-rail node, so that the comparison can be carried out by a simple inverter INV.
[0045] The MO transistor can be driven in the active region, the triode region or the low inversion region. In the active region and the triode region, the ids / Vgs relationship is quadratic. In the low inversion region, the ids / Vgs relationship is exponential. In the active region, the triode region or the low inversion region, the current i0UT has a term linearly proportional to the rms RF input power, so that the detection method described above can be implemented.
[0046] Due to the detuning of the components of the detector 10, there may be an additional continuous term ioff that appears in the Math 6 relation of the current i0UT, which becomes as follows: [Math 7] ÎOUT—ibias+gm' RF+Cff
[0047] [Fig.2] is a block diagram showing one embodiment of a method for calibrating the detector 10 to take into account the additional term ioff.
[0048] At a step 20, the VRF voltage is set to 0 V.
[0049] In a step 22, the C-DAC converter is controlled so that the iDAC current is equal to 0 A.
[0050] At a step 24, the voltage VOut is observed. In the case where the voltage VOut is equal to the high logic value "1" (Y), the process continues with a step 26. In the case where the voltage VOut is equal to the low logic value "0" (N), the process continues with a step 28.
[0051] In step 26, the control signal S is increased, for example, by one bit. This leads to an increase in the current iDAC. The method returns to step 24 in which the voltage VOut is observed.
[0052] In step 28, the switching of the voltage VOut is detected by the control circuit P and the value Soff of the control value S is stored. As soon as the voltage VOut has just switched from the high logic value "1" to the low logic value "0", the current iDAC corresponding to the stored control value Soff is equal to the sum of ibias and ioff.
[0053] According to another embodiment, the determination of the value Soff of the control signal S can be carried out by a dichotomy algorithm.
[0054] When the value Stog of the control signal S for which the voltage VOut switches from a high logic value "1" to a low logic value "0" is detected, the difference between the values Stog and Soff can be determined.
[0055] The method for determining the control value Soff can be implemented at the start-up of the electronic device comprising the detector 10. The values Soff and Stog of the control signal S can be used to determine the second term of the relation Math 6 which is proportional to the rms power of the voltage Vrf.
[0056] The method for determining the control value Soff described above advantageously does not require the implementation of additional analog hardware. Furthermore, it advantageously does not require the voltage Vrf.
[0057] [Fig.3] represents an embodiment of a current output digital to analog converter C-DAC.
[0058] The digital to analog converter with current output C-DAC comprises: - a current source CS providing a constant current Iref and having a first terminal connected, preferably connected, to the source of the low reference potential Gnd; - a MOS transistor Ml, for example a P-channel MOS transistor, the source of the transistor Ml being connected, preferably connected, to the source of the high reference potential Vdd, the drain of the transistor Ml being connected, preferably connected, to a second terminal of the current source CS, and the gate of the transistor Ml being connected, preferably connected, to the second terminal of the current source CS; - N+1 MOS transistors MC;, i being an integer varying from 0 to N, each transistor MC; being for example a P-channel MOS transistor, the source of the transistor MC; being connected, preferably connected, to the source of the high reference potential Vdd, and the gate of the transistor MC; being connected, preferably connected, to the gate of the transistor Ml; and - N+1 controllable switches SWi, i being an integer varying from 0 to N, each switch SW; having a first terminal connected, preferably connected, to the drain of the transistor MC; and a second terminal connected, preferably connected, to the node D, each switch SW; being controlled by a bit Si of the control signal S.
[0059] Each transistor MC has a size coefficient relative to transistor Ml equal to 2'. This means that transistor MC0 has the same size as transistor Ml and that transistor MCN is 2N times larger than transistor Ml. Each transistor MC constitutes a current mirror with transistor Ml and reproduces the current Iref multiplied by a coefficient equal to 2'.
[0060] In one embodiment, the switch SW; is closed when the bit Si is at a high logic value "1" and is open when the bit Si is at a low logic value "0". For example, the switch SW; is a MOS transistor, for example an N-channel MOS transistor, the drain of the transistor being connected, preferably connected, to the drain of the transistor MC;, the source of the transistor being connected, preferably connected, to the node D, and the gate of the transistor receiving the bit Si.
[0061] [Fig.4] partially and schematically represents another embodiment of a power detector 30. The power detector 30 shown in [Fig.4] comprises all the elements of the power detector 10 shown in [Fig.l] except that the transistor MO is replaced by a transconductor T which receives the input voltage Vrf, and possibly the bias voltage Vbias, and which supplies the current iour- The transconductor has a non-linear relationship between the current i0UT and the input voltage Vrf. For example, the transconductor T comprises a bipolar junction transistor.
[0062] [Fig. 5] partially and schematically represents another embodiment of a power detector 40. The power detector 40 shown in [Fig. 5] comprises all the elements of the power detector 10 with the C-DAC converter which has the structure shown in [Fig. 3]. The power detector 40 further comprises: - a MOS transistor M2, for example a P-channel MOS transistor, the source of the transistor M2 being connected, preferably connected, to the source of the high reference potential Vdd, and the gate of the transistor M2 being connected, preferably connected, to the gate of the transistor M1; and - a MOS transistor M3, for example an N-channel MOS transistor, the source of the transistor M3 being connected, preferably connected, to the source of the low reference potential Gnd, the gate of the transistor M3 being connected, preferably connected, to the resistor R and the drain of the transistor M3 being connected, preferably connected, to the drain of the transistor M2 and to the gate of the transistor M3.
[0063] In the embodiment shown in [Fig.5], the same current source CS is used to bias the C-DAC converter and to bias the MO transistor. This advantageously makes it possible to monitor drift variations that depend on temperature.
[0064] One application of a power detector relates to a radio frequency receiver or a radio frequency transmitter.
[0065] [Fig.6] is a block diagram of a radio frequency receiver 50 which receives an alternating voltage RFIN which may correspond to an alternating voltage obtained from an antenna.
[0066] The receiver 50 comprises: - a low noise amplifier 52 (LNA) which receives the RFIN voltage and amplifies the RFIN voltage; - a downconversion unit 54 which receives the amplified voltage supplied by the low noise amplifier 52 and downconverts it to the baseband frequency; - a variable gain amplifier 56 (VGA) which amplifies the downconverted signal; - an analog to digital converter 58 (ADC) which converts the down-converted and amplified signal into a digital signal VD; - a power detector 60, which corresponds to any one of the detectors 10, 30 or 40, which receives the voltage RFIN and which provides digital control values S off and Stog of the control signal S at the time of detection of the rms power of the voltage RFIN; and - an automatic gain control circuit 62 (AGC), which may correspond to the control circuit P described previously, which sends the control signal S to the power detector 60, and which sends gain control signals Gl, G2, G3 to the low noise amplifier 52, to the variable gain amplifier 56, and / or to the analog to digital converter 58, which depend on the detected rms power of the RFIN voltage.
[0067] Alternatively, instead of determining the rms power of the RFIN voltage, the power detector 60 may determine the rms power of the amplified voltage provided by the low noise amplifier 52.
[0068] According to one embodiment, the low noise amplifier 52 comprises at least one MOS transistor.
[0069] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.
[0070] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
Claims
1. Power detector (10; 30; 40) for detecting the rms power of an alternating voltage (VRF), comprising a transconductor (MO; T) configured to receive the voltage (Vrf) and to provide a first current (iOur) to a node (D) with a non-linear relationship between the first current and the voltage, a current-output digital-to-analog converter (C-DAC) configured to receive a digital signal and to provide a second current (iDAc) to the node, a low-pass filter (Cfiit) connected to the node, and an inverter (INV) connected to the node and configured to provide a binary signal (VOut)-
2. The power detector of claim 1, wherein the transconductor comprises a first MOS transistor (MO).
3. A power detector according to claim 1 or 2, wherein the low-pass filter (Cfiit) comprises a first capacitor (Cfiit) having an electrode connected to the node (D).
4. A power detector according to any one of claims 1 to 3, wherein the current output digital to analog converter (C-DAC) comprises second MOS transistors (MC0, MCi, MCn) and controllable switches (SW0, SWb SWN), each second MOS transistor being in series with one of the controllable switches, each controllable switch being controlled by a bit (So, Si, SN) of the digital signal (S).
5. Power detector according to claim 4, comprising a current source (CS) configured to provide a reference constant current (Iref) and first current mirrors (Ml, MC0, MCi, MCN) configured to copy the reference constant current multiplied by different multiplicative coefficients, each first current mirror comprising one of the second MOS transistors (MC0, MCi, MCN).
6. Power detector according to claims 2 and 5, comprising a third diode-mounted MOS transistor (M3), the gate of the third MOS transistor being connected to the gate of the first MOS transistor (MO) via a resistor (R) and a second current mirror (Ml, M2) configured to copy the constant reference current (Iref) to power the third MOS transistor.
7. Electronic circuit (50) comprising the power detector (10; 30; 40) according to any one of claims 1 to 6 and an electronic unit (P) configured to receive the binary signal (VOut) and to change the digital signal (S) until the binary signal switches.
8. An electronic circuit according to claim 7, wherein the electronic circuit is a radio frequency receiver (50) or a radio frequency transmitter.
9. An electronic circuit according to claim 8, wherein the power detector (10; 40) is according to claim 2, comprising an amplifier (52) configured to receive a radio frequency alternating voltage (RFIN) and to amplify the radio frequency alternating voltage, the amplifier being a transconductance amplifier comprising a fourth MOS transistor, and wherein the first MOS transistor (MO) is a scaled replica of the fourth MOS transistor.
10. Method for determining the rms power of an alternating voltage (Vrf) using the power detector (10; 30; 40) according to any one of claims 1 to 6, comprising modifying the digital signal (S) until the binary signal (VOut) switches over.
11. A method according to claim 10, comprising setting the alternating voltage (Vrf) to a constant value and modifying the digital signal (S) until the binary signal (VOut) switches and storing the digital signal (S) for which the binary signal (VOut) has switched.