Method for manufacturing a phase-change memory device

Abstract

Title: Method for manufacturing a phase-change memory device. The invention relates to a phase-change memory device (1) comprising a stack (100) including a memory point (200). The memory point comprises, stacked in a vertical direction (Z), a lower electrode (110), a chalcogenide section (120) disposed on the lower electrode, and an upper electrode (130) disposed on the chalcogenide section. The memory point has a lateral surface (203) and a top face (201), and includes an encapsulation layer (300) disposed in contact with the lateral surface and the top face, and a doped portion (125) extending from the lateral surface and inside the chalcogenide section, along its entire height.The chalcogenide section also has an undoped portion (126) with no or less doping than the doped portion, extending from the doped portion to the center of the chalcogenide section. Figure for the abstract: Fig. 3H.

Description

Title of the invention: Method for manufacturing a phase-change memory device. Technical field

[0001] The present invention relates to the field of phase-change memory devices. It finds a particularly advantageous application in the field of memory devices based on at least one chalcogenide layer, for example based on germanium, selenium and tellurium (GeSbTe, also referred to as GST material). STATE OF THE ART

[0002] Memory devices are crucial in many applications, for example, for the type of memory commonly referred to as Storage Class Memory (SCM), embedded memories for automobiles, or neuromorphic applications. In this context, resistive memories are excellent candidates to support or replace Flash memory. Resistive memories offer significant advantages in terms of speed and scalability, i.e., the reduction in the dimensions of the individual memory cell and the distance between two memory points, which increases the density of memory points in memory arrays.Among resistive memories, phase change memories (commonly abbreviated PCM, from the English Phase Change Memory) represent one of the most mature non-volatile resistive memory technologies and are at an advanced stage of development and production.

[0003] Phase-change memories typically comprise two programming states obtained from a layer based on a chalcogenide material forming a so-called "memory" layer and exhibiting an amorphous state and a crystalline state: - "reset" programming, or equivalently HRS (High Resistive State), which is based on the melting of all or part of the chalcogenide layer during an electrical pulse that raises the material's melting temperature by Joule heating. The molten portion of the chalcogenide material is then frozen in an amorphous state by sudden cooling, achieved by rapidly reducing the current. The amorphous state of the chalcogenide material is very poorly electrically conductive. The reset programming allows the "0" information to be stored, resulting in a high resistance within the PCM device. - "Set" programming, or equivalently LRS (Low Resistivity State), which... This process is based on the partial or total melting of the chalcogenide material during an electrical pulse. The chalcogenide material then crystallizes through gradual cooling achieved by progressively reducing the current. The crystalline state of the chalcogenide material is a better electrical conductor than the amorphous state. The programming set allows the information "1" to be stored, along with a low resistance in the PCM device.

[0004] The memory layer can be further supplemented by a second chalcogenide layer, called the "selector" layer, incorporated into a selector module or switch of the PCM device (commonly referred to in English as an ovonic threshold switch, OTS). The second chalcogenide layer, in its amorphous state, exhibits different electrical conductivity states when a threshold voltage and an initialization voltage are applied. Above the threshold voltage, the second chalcogenide layer exhibits low resistivity, allowing the passage of a high current flow. This current enables the programming and reading of the PCM device selected in a network, without undesirable programming of adjacent devices. The threshold voltage is the switching voltage of the selector layer that allows the current to flow.The threshold voltage can be used to differentiate between the set and reset states. The initialization voltage is the threshold voltage required for the first switching operation, typically higher than subsequent threshold voltages.

[0005] Among the specifications required, depending on the applications, we will seek stability of the amorphous phase at high temperature, reliability with a programming error rate typically less than ppm (106), endurance typically greater than 109 cycles and / or fast crystallization rates.

[0006] However, certain manufacturing steps of a PCM device have a negative impact on its performance. In particular, the etching or structuring (commonly referred to as "patterning") of the PCM device affects the composition of the chalcogenide layers and can lead to undesired recrystallization of these layers, an acceleration of segregation phenomena, and poor functionality of the PCM device for critical dimensions that are too small.

[0007] Even when encapsulating the PCM device, its performance is degraded. In particular, an oxygen peak is frequently observed at the sides of the device.

[0008] The known solutions therefore do not offer a satisfactory solution for reducing the size of a memory point without significantly degrading its performance.

[0009] An object of the present invention is therefore to propose a solution improving the properties of a phase-change memory device.

[0010] The other objects, features and advantages of the present invention will become apparent at The following description and accompanying drawings will be examined. It is understood that other benefits may be incorporated. SUMMARY

[0011] To achieve this objective, a first aspect of the invention relates to a phase-change memory device comprising a stack including a memory point, the memory point comprising, stacked in a so-called vertical direction: i. a lower electrode formed in a lower layer, ii. at least one so-called chalcogenide section formed in at least one chalcogenide layer, disposed on the lower electrode, iii. a top electrode formed in a top layer and disposed on at least one chalcogenide section, the memory spot having a lateral surface and a top face.

[0012] The memory point also includes an encapsulation layer encapsulating the memory point and disposed in contact with the lateral surface and the upper face. The memory point has at least one portion, called the doped portion, extending from the lateral surface and into the chalcogenide segment, and having a doping of at least one species, called the doping species, selected from the following species: carbon, fluorine, nitrogen, indium, arsenic, aluminum, germanium, silicon, chlorine, and boron. The doped portion extends, in the so-called vertical direction, along the entire height of the chalcogenide segment. The chalcogenide segment has a portion, called the undoped portion, having a doping level that is zero or lower than the doping level of the doped portion with said doping species, the undoped portion extending from the doped portion to a center of the chalcogenide segment.

[0013] A second aspect of the invention relates to a method for manufacturing a phase-change memory device comprising the following steps: - supplying a stack having a top face, the stack comprising, stacked in a so-called vertical direction: i. a bottom layer, ii. at least one so-called chalcogenide layer based on at least one chemical element from the chalcogen family, iii. a top layer, - a substrate structuring etching from its upper face, the structuring etching extending into at least part of the lower layer and enabling the formation of a memory point comprising: i. a lower electrode formed in the lower layer, ii. at least one so-called chalcogenide section formed in the at least one chalcogenide layer, disposed on the lower electrode, iii. an upper electrode formed in the upper layer and disposed on at least one chalcogenide segment, the memory point having a lateral surface and a top face, - a formation of an encapsulation layer encapsulating the memory point and disposed in contact with the lateral surface and the top face of the memory point, - an ionic implantation of a so-called doping species in at least one chalcogenide segment through the encapsulation layer, the ionic implantation being carried out in an implantation direction forming an angle called implantation angle 0impi with the vertical direction, with 0impi >25°, the ionic implantation being configured so as to dope at least a portion of the chalcogenide segment, the portion extending from the lateral surface.

[0014] Following the etching of the stack to form the memory cell and its subsequent encapsulation, the memory cell, and in particular the chalcogenide section, exhibits numerous defects. These include structural defects caused by the etching process and oxidation of the chalcogenide species due to the inevitable exposure of the memory cell to air before encapsulation. These etching and encapsulation steps are, however, extremely common, even unavoidable, in the production of memory devices.

[0015] The implantation as described above makes it possible to eliminate, or at least reduce, the quantity of these defects and, in particular, to improve the reliability of the interface between the chalcogenide segment and the encapsulation layer. Specifically, it makes it possible to break the oxide bonds formed with the chalcogenide species and to form instead bonds between the chalcogenide species and the doping species, for example, Ge-C bonds.

[0016] The proposed implantation from the lateral surface of the memory point also makes it possible to improve the cleanliness of the interface between the chalcogenide section and the encapsulation layer, making it possible to avoid the parasitic effects of degeneration of the chalcogenide species at the level of said interface, and to improve the adhesion between the memory point and the encapsulation layer.

[0017] Thanks to the inclination of the implantation, the process allows the treatment of the interface between the memory point and the encapsulation layer without modification of the chalcogenide material, which is not possible with a vertical implantation.

[0018] The proposed implantation also has the advantage of reducing stress on the amorphous chalcogenide section at the interface with the encapsulation layer. This directly benefits from stress relaxation and therefore a limitation of the number of structural defects that can appear, as well as improved robustness of the device. This also has a positive impact on the device's lifespan, particularly in terms of endurance.

[0019] In the context of the present invention, the doping of the chalcogenide layer is This is achieved by ion implantation onto a pre-formed chalcogenide layer. Ion implantation allows for better control of the location of the doping agent within the chalcogenide layer, particularly at lower concentrations than with co-spraying.

[0020] During the development of the invention, it was further highlighted that, surprisingly, ion implantation induces a structural redistribution of the chalcogenide layer (by the passage of ions and their implantation), which makes it possible to improve its properties.

[0021] The performance of the PCM device is thus improved. In particular, the programming of the SET state and the endurance of the PCM device can be improved.

[0022] This solution clearly stands out from solutions implementing co-spray deposition, which instead encourage adapting the spray deposition parameters to improve the properties of a carbon-doped PCM device.

[0023] The advantages described for the manufacturing process of the device extend to the device itself, which notably features a good quality interface between the memory point and the encapsulation layer. BRIEF DESCRIPTION OF THE FIGURES

[0024] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0025] [Fig.1] Fig.1 represents a cross-sectional scanning electron microscopy view illustrating by way of example the location of a PCM device between the metal levels at the end of the manufacturing line (commonly referred to in English as back-end of line, or simply back-end).

[0026] [Fig.2] Fig.2 represents a perspective diagram of a memory point according to a example of a project.

[0027] [Fig. 3A] Figures 3A to 31 represent a first embodiment of the process according to the invention. [Fig. 3A] illustrates the provision of a stack comprising a bottom layer, a chalcogenide layer and a top layer.

[0028] [Fig.3B] Fig.3B illustrates the formation of an etching mask on the upper face of the stack.

[0029] [Fig.3C] Fig.3C represents the formation of openings in the engraving mask.

[0030] [Fig.3D] The [Fig.3D] illustrates the structuring etching of the stack through the etching mask, making it possible to obtain a memory point comprising a lower electrode, a chalcogenide section and an upper electrode.

[0031] [Fig.3E] Fig.3E illustrates the removal of the engraving mask.

[0032] [Fig.3F] The [Fig.3F] represents a step of encapsulating the memory point by an encapsulation layer.

[0033] [Fig.3G] Fig.3G illustrates a step in the implantation of the memory point and in particular of the chalcogenide section through the encapsulation layer.

[0034] [Fig.3H] Fig.3H represents the memory device after implantation.

[0035] [Fig.31] Fig.31 represents a detail of Fig.3F, including the chalcogenide section, including its doped portion.

[0036] [Fig. 4A] Figures 4A to 4E represent a second embodiment of the process according to the invention. [Fig. 4A] illustrates the provision of a stack comprising a bottom layer, a first chalcogenide layer, an intermediate layer, a second chalcogenide layer and a top layer.

[0037] [Fig.4B] [Fig.4B] illustrates the memory point obtained after a structuring etching of the stack illustrated in [Fig.4A]. The memory point comprises a lower electrode, a first chalcogenide section, an intermediate electrode, a second chalcogenide section and a top electrode.

[0038] [Fig.4C] The [Fig.4C] represents a step of encapsulating the memory point by an encapsulation layer.

[0039] [Fig.4D] Fig.4D illustrates a step in the implantation of the memory point and in particular of the chalcogenide segments through the encapsulation layer.

[0040] [Fig.4E] Fig.4E represents the memory device after implantation.

[0041] [Fig.5A] Figures 5A, 5B and 5C represent diagrams, respectively in perspective, front view and top view, of a PCM device according to an example embodiment.

[0042] [Fig.5B]

[0043] [Fig.5C]

[0044] [Fig.6] Fig.6 is a graph illustrating the evolution of the concentration of different species in a slice of the PCM device comprising a portion of the memory layer and the encapsulation layer.

[0045] [Fig.7] The [Fig.7] is a graph illustrating the implantation profiles obtained for two different implantation energies in a slice of the PCM device comprising a portion of the memory layer and the encapsulation layer.

[0046] [Fig.8] Fig.8 is a graph illustrating the evolution of the resistivity of the memory layer of the memory device as a function of temperature, for different values ​​of implantation energy and implanted dose.

[0047] [Fig.9] The [Fig.9] is a graph illustrating the density within the memory layer of the memory device and the thickness of the impacted memory layer for different implantation energies and implanted doses.

[0048] The drawings are given by way of example and are not limiting of the invention. They These are schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality. DETAILED DESCRIPTION

[0049] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0050] Advantageously, 20<0impi<60°.

[0051] Preferably, the portion has, along all directions of a transverse plane perpendicular to the vertical direction, a radial dimension 1125 with 1125 < 20 nm, preferably 1125 < 10 nm. This prevents the performance of the chalcogenide material from being altered, or at least altered to an excessive degree.

[0052] Advantageously, 1125 > 2 nm, preferably 1125 > 5 nm.

[0053] According to one embodiment, the at least one chalcogenide section comprises a first chalcogenide section and a second chalcogenide section: - the first chalcogenide section is disposed on the lower electrode, and is intended to form a so-called memory layer, and - the second chalcogenide section is intended to form a so-called selective layer, the second chalcogenide section being separated from the first chalcogenide section by an intermediate electrode, and - the ionic implantation is configured so that the portion of the chalcogenide section extends into the first chalcogenide section and the second chalcogenide section.

[0054] According to one example, the implanted doping species is at least one of carbon, fluorine, nitrogen, indium, arsenic, aluminum, germanium, silicon, chlorine and boron.

[0055] According to one example, during ion implantation, the implantation energy is greater than or equal to 1 keV, preferably greater than or equal to 4 keV, preferably greater than or equal to 10 keV, for example greater than or equal to 30 keV.

[0056] According to one example, during ion implantation, a dose of implanted doping species Dimpi greater than 1015 atoms / cm2 is implanted.

[0057] According to one example, the encapsulation layer is based on at least one material taken from: SiN, SiC and SiCN.

[0058] According to one example, the chalcogenide section comprises at least one chemical element among germanium Ge, antimony Sb and tellurium Te.

[0059] According to one example, the first chalcogenide segment, or memory layer, perhaps at base or made of any material belonging to the ternary diagram of germanium Ge, antimony Sb and tellurium Te. For example this material is chosen from GelSb2Te4, GeTe, Sb2Te3, Ge7SblTe2.

[0060] According to one example, the second chalcogenide stretch, or selective layer, comprises at least one chemical element among selenium, arsenic, sulfur, silicon and aluminum.

[0061] According to one example, the second chalcogenide section, or selector layer, is based on or made of a material chosen from the alloy families GeSbSe, GeSe, AsSeSiGe, AsSe, SbSe, SiSe, AsTe, SiGeSe, AlTe, possibly doped with nitrogen N. Note that the stoichiometric coefficients between the chemical elements of these alloys can vary, for example according to the intended applications.

[0062] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0063] A parameter "approximately equal to / greater than / less than" a given value means that this parameter is equal to / greater than / less than the given value, to within ±10% of that value. A parameter "approximately between" two given values ​​means that this parameter is at least equal to the smaller of the given values, to within ±10% of that value, and at most equal to the larger of the given values, to within ±10% of that value.

[0064] A substrate, layer, zone or portion "based on" a material A means a substrate, layer, zone or portion comprising this material A, for example at least 50%, and possibly other materials, for example doping elements.

[0065] Within the framework of the invention, energies are given in electronvolts, for which 1 eV ~ 1.602.10-19 J, in the international system of units.

[0066] As is well known in the field, the chalcogen family refers to the chemical elements in the 16th column of the periodic table of chemical elements, or equivalently the column preceding those of the halogens and the noble gases.

[0067] In the detailed description that follows, terms such as "horizontal", "vertical", "longitudinal", "transverse", "upper", and "lower" may be used. These terms should be interpreted in a relative manner with respect to the position normal of the PCM device during its manufacture. For example, the notions "horizontal" and "longitudinal" correspond to the main extension direction of the layers and sections, and in particular of the chalcogenide layer(s) and section(s), of the PCM device.

[0068] A reference frame will also be used whose longitudinal or back / front direction corresponds to the Y axis, the transverse or right / left direction corresponds to the X axis and the vertical or bottom / top direction corresponds to the Z axis.

[0069] The manufacturing process of the PCM 1 device will now be described with reference to the figures according to several embodiment examples.

[0070] A PCM 1 device is typically manufactured at the end of the production line (commonly referred to as the back-end of the line, or simply the back-end). The PCM 1 device and its substrate can be arranged between two metal layers M of the back-end, in particular between the last two layers, for example between MN and MN-1 as illustrated in [Fig. 1]. The position of the part of the device manufactured at the beginning of the production line (usually referred to as the front-end) is indicated by dashed lines in [Fig. 1]. Integrations can more generally include up to ten or more metal layers. The term substrate does not necessarily mean a single layer and can include a stack of layers, particularly in the context of a back-end embodiment.

[0071] An example of implementation of the method according to the invention will now be described with reference to Figures 3A to 31.

[0072] As illustrated in [Fig. 3A], a first step consists of providing a stack 100 comprising, stacked along a stacking direction Z: a ​​bottom layer 110a, a chalcogenide layer 120a, and a top layer 130a. The chalcogenide layer 120a is positioned above an upper face 11la of the bottom layer 110a. Preferably, the bottom face 122a of the chalcogenide layer 120a is in direct contact with the top face 11la of the bottom layer 110a. The top layer 130a is positioned above an upper face 121a of the chalcogenide layer 120a. Preferably, the bottom face 132a of the top layer 130a is in direct contact with the top face 121a of the chalcogenide layer 120a. Preferably, the upper faces 111a, 121a, 131a and lower faces 112a, 122a, 132a of the lower 110a, chalcogenide 120a and upper 130a layers extend along planes parallel to a transverse plane XY perpendicular to the stacking direction Z.

[0073] According to the stacking direction Z, the lower 110a, chalcogenide 120a and upper 130a layers have thicknesses enOa, e^oa and ei30a respectively.

[0074] The stack 100 has a top face 101. Preferably, the top face 101 of the stack 100 coincides with the top face 131a of the top layer 130a.

[0075] The chalcogenide layer 120a is based on at least one chemical element from the chalcogen family.

[0076] A second step of the process consists of a structuring engraving of the stack 100 so as to form a memory point 200 as illustrated in [Fig.3E].

[0077] The structuring etching can be carried out according to the steps shown in Figures 3B to 3E. Typically, an etching mask 50 is deposited on the upper face 101 of the stack 100 ([Fig. 3B]). Openings 55 are then formed in the etching mask 50. An etch is then made in the upper layer 130a, the chalcogenide layer 120a, and the lower layer 110a, through the openings 55 of the etching mask 50. This etch passes through the upper layer 130a and the chalcogenide layer 120a to their respective thicknesses enoa and ei20a. The structuring etch can stop in the lower layer 110a, or it can pass completely through the latter.

[0078] Following the structuring etching, a memory point 200 is obtained comprising a lower electrode 110 formed in at least a part of the lower layer 110a, a chalcogenide section 120 formed in the chalcogenide layer 120a and an upper electrode 130 formed in the upper layer 130a.

[0079] The thicknesses en0, e^o, and eno along the stacking direction Z of these electrodes and section are each substantially equal to the thickness enOa, ei20a, enoa and e^oa' of the layer from which they were formed.

[0080] The memory point 200 has an upper face 201 extending substantially in the same plane as the upper face 101 of the stack 100 from which the memory point 200 was formed. The upper face 201 thus preferably extends in a plane substantially parallel to the transverse plane XY. The memory point 200 also has a lateral surface 203 extending from its upper face 201 along its entire height H200. The geometry of the lateral surface of the memory point 200 depends, in particular, on the intended applications. If the memory point 200 is cylindrical, its lateral surface 203 corresponds to the surface defined by the generating lines of said cylinder and extending along its height H200. This is particularly the case when the different sections 110, 120, 130 composing the memory point 200 have the same projection in the transverse plane XY.The lateral surface 203 of the memory point 200 can also be more complex, particularly when, as in the example illustrated in [Fig. 2], the different segments 110, 120, 130 composing the memory point 200 do not have the same projection in the transverse XY plane. The lateral surface 203 then typically comprises a plurality of flanks, each extending mainly in a plane parallel to a plane generated by two of the three axes X, Y, and Z.

[0081] The memory point also presents, in any direction of the transverse plane XY a radial dimension l2Oo- boo is typically greater than 10 nm and / or less than 100 nm.

[0082] All or part of the chalcogenide 120 section is configured to change phase when the device 1 is used. It may be capable of transitioning from an amorphous state to a crystalline state or vice versa. In particular, the chalcogenide 120 section may be capable of transitioning from an amorphous state to a crystalline state or vice versa when the chalcogenide 120 section is a so-called "memory" layer. The transition between the amorphous and crystalline states allows a reset state of high resistivity to be stored in the amorphous state or a set state of low resistivity to the crystalline state in a so-called "memory" layer. The resistivity in the reset state is higher than the resistivity in the set state.

[0083] As illustrated in Figures 3D to 31, the chalcogenide section 120 can comprise a single layer, the memory layer; that is, there are not two chalcogenide sections separated by a layer other than a chalcogenide section, for example, an electrode. For example, in this case, the device 1 does not include a selector layer described later. In this case, preferably, the entire chalcogenide section 120 is configured to change phase when the device is in use. It is also possible that only a portion of the chalcogenide section 120 is configured to change phase, for example, in the case of programming in an intermediate state.

[0084] By way of example, the lower electrode 110 can be configured to provide the electrical impulse to the chalcogenide section 120 for its transition from one state to the other. The lower electrode 110 can be an electrode designated by the term "heater." Typically, a "heater" electrode has a smaller contact area with the chalcogenide section 120 compared to the contact area between the chalcogenide section 120 and the upper electrode 130. Note that the lower electrode 110 can be expected to have a given geometry, and the upper electrode 130 can have a given geometry, not necessarily distinct from each other.

[0085] The upper electrode 130 is generally referred to as the "top electrode".

[0086] Preferably, the engraving mask 50 is removed after the structuring engraving, as illustrated by the transition from [Fig.3D] to [Fig.3E].

[0087] Following the structuring etching, the memory point 200 is encapsulated by an encapsulation layer 300. The encapsulation layer 300 is in contact with the upper face 201 of the memory point 200 and with at least a part of its lateral surface 203 extending from the upper face 201. The encapsulation layer 300 is in contact with the upper face 201 and the lateral surface 203 of the memory point 200. Preferably, the encapsulation layer 300 covers the entire lateral surface 203 of the memory point 200.

[0088] The encapsulation layer 300 has a thickness e300 deposited conformally on the lateral surface 203 and the upper face 201 of the memory point 200. The thickness e300 of the encapsulation layer 300 is advantageously between 10 and 30 nm, it can for example be substantially equal to 20 nm.

[0089] The manufacturing process according to the invention of the PCM 1 device provides, after the encapsulation of the memory point 200, a step, illustrated in [Fig.3G], of implanting a so-called doping species into the memory point 200 through the encapsulation layer 300. The doping species can be chosen from carbon, fluorine, nitrogen, indium, arsenic, aluminum, germanium, silicon, chlorine or boron.

[0090] Ion implantation is for example carried out in the reaction chamber of an implantation reactor, for example an ion beam ion implanter.

[0091] The implantation of the doping species is carried out along an implantation direction 10 located in space by a first angle 0 measured with respect to the stacking direction Z and by a second angle <e>measured with respect to the X axis, as illustrated in Figures 5B and 5C respectively.

[0092] A particular feature of the invention is that the implantation direction 10 forms a non-zero implantation angle θimpi with the stacking direction Z. Preferably, the implantation angle θimpi is greater than or equal to 20°, advantageously greater than or equal to 40°. In this way, the doping agents are implanted in the memory spot 200 not only from its upper face 201 but also from its lateral surface 203.

[0093] The inclination of the implantation direction 10 relative to the vertical allows, in particular, targeting the interface between the memory point 200 and the encapsulation layer 300 at the lateral surface 203 of the memory point 200. Some existing solutions implementing chalcogenide layer doping involve co-spraying of the chalcogenide species and the dopant element. However, such co-spraying does not allow the dopant element to be introduced at the interface between the memory point 200 and the encapsulation layer 300.

[0094] The angle <e>The angle formed by the implantation direction 10 with the X-axis is arbitrary. It is possible, in particular, for this angle to vary during the implantation step, or for the implantation step to be performed for several values ​​of ¢. This allows for better distribution of the implantation within the memory point 200. This can, in particular, allow for implantation using the entire lateral surface 203 of the memory point 200.

[0095] The implantation allows for the doping of at least one portion 125, referred to as the doped portion, extending at least into the chalcogenide section 120 from the lateral face 203. The doped portion 125 is defined as the region of the memory point 200 having, after the implantation step, an atomic concentration of the doping species greater than or equal to 0.5%. Preferably, this atomic concentration is between 0.5% and 5%. The chalcogenide section also includes a portion 126, referred to as the undoped portion, extending from the doped portion 125 to the center of the chalcogenide section 120. The undoped portion 126 has a concentration of the doping species lower than that of the doped portion 125, or even zero.

[0096] The doped portion 125 of the chalcogenide section 120 preferably extends along the stacking direction Z over at least 50%, and advantageously at least 75%, of the thickness ei20 of the chalcogenide section 120. Preferably, the doped portion 125 extends over the entire thickness eno of the chalcogenide section 120. As illustrated in [Fig. 31], the doped portion 125 has, in projection along any direction of the transverse plane XY, a radial dimension 1125. The radial dimension 1125 is advantageously greater than or equal to 2 nm, preferably greater than or equal to 5 nm, over the entire height of the doped portion 125. Preferably, the doped portion 125 extends over at least 20% of l2Oo. Furthermore, the radial dimension li25 is advantageously less than or equal to 20 nm, preferably less than or equal to 10 nm, over the entire height of the doped portion 125. Preferably, the doped portion 125 extends over 80% or less of the radial dimension l200 of the memory point 200.

[0097] As illustrated in [Fig. 3H], the implantation is typically configured so that the doped portion 125 extends not only into the chalcogenide section 120 but also into the lower electrode 110 and / or the upper electrode 130. The doped portion 125 typically extends from the lateral surface 203 and the upper face 201. Advantageously, it extends along the stacking direction Z over at least 50%, and advantageously at least 75%, of the height H200 of the memory point 200. Preferably, the doped portion 125 extends over the entire height H200 of the memory point 200.

[0098] Different radial implantation profiles can be obtained in the chalcogenide section 120 and more generally in the memory point 200 by adjusting the implantation parameters, in particular the dose and implantation energy. These parameters notably allow control of the radial dimension 1125.

[0099] According to one example, the concentration profile of the doping species in the doped portion 125 is homogeneous in the transverse XY plane over its entire radial dimension li25. Such a profile can notably be obtained by high-energy implantation, for example at 30 keV for carbon implantation. According to an alternative example, the ion implantation step can be configured to form a profile of The concentration of the doping species is not uniform in the transverse plane. For this reason, the ion implantation step may, for example, include several successive ion implantations.

[0100] The doping profile in doping species can be determined by several methods such as Raman spectroscopy or X-ray spectroscopy, in particular associated with transmission electron microscopy (commonly called TEM, from the English "Transmission Electron Microscopy").

[0101] Another example of implementation of the method according to the invention will now be described with reference to Figures 4A to 4E.

[0102] In this embodiment, as illustrated in [Fig.4B], the chalcogenide section 120 comprises a first chalcogenide section 120' and a second chalcogenide section 120” separated in the stacking direction Z by an intermediate electrode 140.

[0103] To obtain a memory point 200 presenting these layers, it is possible to implement the steps described below.

[0104] The stack 100 initially provided comprises, according to this example, stacked along a stacking direction Z: a ​​bottom layer 110a, a first chalcogenide layer 120a', an intermediate layer 140a, a second chalcogenide layer 120a” and a top layer 130a. The chalcogenide layer 120a described in the first embodiment thus comprises two layers 120a', 120a” separated by the intermediate layer 140a.

[0105] A structuring etch then allows the memory point 200 to be obtained. As described in the first embodiment, this etch is advantageously made through openings in an etching mask 50 deposited on the upper face 101 of the stack 100. The structuring etch this time passes through the upper layer 130a, the first chalcogenide layer 120a', the intermediate layer 140a, and the second chalcogenide layer 120a' through all their respective thicknesses ei30a, e^oa', ei40a, and e^oa'. The structuring etch may stop in the lower layer 110a, or it may pass entirely through this layer.

[0106] Following the structuring etching, a memory point 200 is obtained comprising, stacked according to the stacking direction Z: - a lower electrode 110 formed in at least a part of the lower layer 110a, - a first chalcogenide 120' segment formed in the first chalcogenide 120a' layer, - an intermediate electrode 140 formed in the intermediate layer 140a, - a second chalcogenide section 120” formed in the second chalcogenide layer 120a”, and - a top electrode 130 formed in the top layer 130a.

[0107] The thicknesses eno, e^”, ei40 and e^ according to the stacking direction Z of these electrodes and sections are each substantially equal to the thickness enoa, ei20a”, ei4oa and ei20a” of the layer from which they were formed. The thickness en0 of the lower electrode 110 depends on the depth of the etch in the lower layer 110a.

[0108] The second chalcogenide 120" section is commonly referred to as the selector layer. The selector layer is preferably intended to remain amorphous.

[0109] A layer may be disposed between the second chalcogenide section 120”, or selector layer, and the intermediate electrode 140 and / or the upper electrode 130, for example a carbon-based layer, configured to block the interdiffusion of chemical elements between these layers.

[0110] As in the first embodiment, the memory point 200 has a top face 201 and a lateral surface 203, the characteristics of which described in the first embodiment are transposed here mutatis mutandis.

[0111] Similar to what has been described for the first embodiment, the memory spot 200 is then encapsulated by an encapsulation layer 300 ([Fig. 4C]), and subsequently subjected to the implantation of a doping species ([Fig. 4D]). The features and advantages described in the first embodiment extend mutatis mutandis to the case where the memory spot 200 comprises two chalcogenide sections 120 separated by an intermediate electrode.

[0112] Advantageously, in this embodiment, the doped portion 125 extends into both the first chalcogenide section 120' and the second chalcogenide section 120”. The doped portion 125 then comprises a first doped portion 125', extending into the first chalcogenide section 120', and a second doped portion 125”, extending into the second chalcogenide section 120”.

[0113] The first doped portion 125' of the first chalcogenide section 120' extends preferably along the stacking direction Z over at least 50%, and advantageously at least 75%, of the thickness e^' of the first chalcogenide section 120. Preferably, the first doped portion 125' extends over the entire thickness ei20” of the first chalcogenide section 120'.

[0114] Similarly, the second doped portion 125” of the second chalcogenide section 120” preferably extends along the stacking direction Z over at least 50%, and advantageously at least 75%, of the thickness ei20” of the second chalcogenide section 120”. Preferably, the second doped portion 125” extends over the entire thickness ei20” of the second chalcogenide section 120’.

[0115] The remarks developed on the implantation profile apply perfectly to this embodiment.

[0116] The advantages of the implantation according to the invention are presented below. The The advantages described with reference to the chalcogenide section apply both to cases where the latter includes a memory layer and to cases where it includes both a memory layer and a selector layer. The specific advantages of each of these two scenarios are mentioned.

[0117] The implantation step results in the introduction of a peak in the concentration of the doping species at the interface between the encapsulation layer 300 and the memory dot 200. For example, the atomic concentration of the doping species at this interface can reach 5 at.%. The implantation also introduces a lateral gradient or other concentration profile of the doping species from the lateral surface 203 towards the interior of the memory dot 200. This helps to limit the depletion of chalcogenide species that can be observed in [Fig. 6], which illustrates the evolution of the concentration of different species in a slice of a prior art PCM device comprising a portion of the memory layer and the encapsulation layer. This figure shows a Ge depletion induced by oxidation occurring upon exposure to air after etching.An implantation, for example of carbon, makes it possible to reduce or even prevent the segregation of Ge (or any other chalcogenide species), which is linked to the heterogeneous nucleation occurring at the interface between the germanium oxide (GeOx) layer and the chalcogenide material itself. This results in a reduction of the phase separation phenomenon, which can itself lead to a reduction of possible elemental depletion phenomena.

[0118] This implantation at the interface between memory dot 200 and encapsulation layer 300, and on the doped portion 125, has the effect of breaking the bonds forming between the chalcogenide species and oxygen atoms, due in particular to the exposure of the memory dot to air between the structuring etching and encapsulation. Instead of chalcogenide-oxygen bonds (Ge-O, TeO2, Sb2O3...), bonds are formed between the chalcogenide species and the doping species (Ge-C, Ge-As...). These bonds, unlike oxide bonds, are beneficial to the functioning of device 1. In particular, they allow for a passivation of the doped portion 125. This has the advantage of delaying the crystallization of regions poor in chalcogenide species, typically coinciding with the doped portion 125.Delayed crystallization ensures better uniformity and less variability in chalcogenide material crystals, whereas larger and non-homogeneously oriented crystals, typical of non-implanted devices, induce intrinsic variability.

[0119] The implantation also allows a structural relaxation of the material at the base of the chalcogenide section 120. This has the effect of a decrease in the density of the PCM 1 device, in particular at the interface between the memory point 200 and the encapsulation layer 300.

[0120] The presence of the doping species also makes the chalcogenide section less affected by crystalline segregation between its component chemical elements. This has the advantage of improving the reliability of the SET state programming.

[0121] The implantation step from the upper face 101 and the lateral surface 203 of the memory dot also improves the cleanliness of the interface between the memory dot 200 and the encapsulation layer 300. This reduces or even avoids potential parasitic degeneration effects of the material constituting the chalcogenide section at the interfaces with the encapsulation layer 300. It also improves the adhesion between the memory dot 200 and the encapsulation layer 300.

[0122] The implantation also causes a reduction of the internal stress of the chalcogenide section in its amorphous state, particularly at its interface with the encapsulation layer 300. This allows a relaxation of the stresses in this region, which in turn has the benefit of reducing the structural defects created in this region, and this until the end of the integration of the PCM 1 device.

[0123] The presence of the doping species in the chalcogenide section 120, or memory layer, particularly near the interface with the encapsulation layer 300, improves its thermal performance, notably through a reduction in thermal conductivity. Furthermore, the crystallization of the chalcogenide species is made more uniform by this reduction in thermal conductivity. Indeed, following the emission of an electrical pulse for programming the SET state, heat is dissipated more slowly. The crystallization process of the memory layer is thus improved and made more homogeneous. For the memory layer, the variability of the SET state is thereby reduced. For the selector layer, the variability of the threshold voltage and the initialization voltage is reduced.

[0124] The various advantages of the implantation described above have general positive consequences on the PCM device: - An improvement in the number of cycles during which the PCM 1 device can operate with performance exceeding given specifications. This is equivalent to an improvement in the endurance of device 1. - Achieving performance equivalent to that obtained in the prior art for large dimensions (typically a width taken along the Y axis between 50 and 300 nm), this time for reduced dimensions of the memory point 200 (in particular a width of the memory point taken along the Y axis less than or equal to 50 nm).

[0125] It is understood that the advantages described above with respect to the implementation step of the process according to the invention naturally extend to the presence of the doped portion 125 in the device according to the invention.

[0126] Dimensions of the PCM 1 device are now given by way of non-limiting example, with reference to Figures 2, 3F, and 4C. The PCM 1 device may have a width Li along the y-direction of substantially between 5 nm and 100 nm. The lower electrode 110 may have a thickness en0 of substantially between 30 nm and 200 nm, for example, 100 nm. If applicable ([Fig. 4C]), the intermediate electrode 140 may have a thickness ei40 of substantially between 2 and 50 nm, for example, 20 nm. The upper electrode 130 may have a thickness eno of substantially between 10 nm and 100 nm, for example, 50 nm. The chalcogenide section ([Fig. 3F]) can have a thickness approximately between 10 nm and 100 nm, for example approximately 50 nm. If applicable ([Fig.4C]), the first chalcogenide 120' segment may have a thickness of approximately between 10 nm and 100 nm, for example approximately 50 nm. Where applicable, the first chalcogenide 120” segment may have a thickness of approximately between 5 nm and 50 nm, for example approximately 25 nm.

[0127] Specific examples of implementation

[0128] Results obtained for PCM devices 1 comprising a lower electrode 110, a chalcogenide section or memory layer 110, an upper electrode 120, and an encapsulation layer 300, as illustrated for example in [Fig. 3F], will now be described. The dimensions of this device 1 correspond to the dimensions described previously. In these examples, the memory layer 110 is made of Ge2Sb2Te5, the encapsulation layer of SiN, and the doping species is carbon.

[0129] Figure 7 shows the implantation profiles (concentration in at / cm³) obtained by TRIM simulation for a carbon dose of 10¹⁶ at / cm² and two distinct implantation energy values ​​(4 keV 701 and 5 keV 702), as a function of depth in a slice of device 1 extending from the outer edge of the encapsulation layer 300 into the memory layer. For both implantation energies, a high carbon density is observed at the interface between the SiN encapsulation layer 300 and the chalcogenide section 120, and the carbon concentration in the chalcogenide section 120 decreases with distance from the PCM / encapsulation interface over approximately 15 nanometers. At the interface, the carbon density is approximately 5 at.%.

[0130] Figure 8 illustrates resistivity measurements (in Ω·cm) as a function of temperature (in °C) of amorphous memory layers implanted with a uniform carbon profile for different implantation energies (8 keV or 30 keV) and implanted doses (10¹⁵ or 10¹⁶ at / cm²). An increase in crystallization temperature is observed for the examples implanted at higher doses and higher energies. This confirms an improvement in the stability of the amorphous phase with respect to crystallization thanks to the presence of carbon.

[0131] Figure 9 illustrates density measurements (in g / cm³) and doped or implanted thickness (corresponding to the radial dimension 1125) (in Å) of amorphous memory layers implanted with carbon for different implantation energies (8 keV or 30 keV) and implanted doses (10¹⁵ or 10¹⁶ at / cm²), as well as a density measurement (in g / cm³) of an unimplanted amorphous memory layer (reference). It can be seen that carbon implantation reduces the density of the memory layer by more than one unit, regardless of the implanted dose and implantation energy, over a thickness between 2 nm and 6 nm from the interface with the encapsulation layer 300. Increasing the implanted dose particularly reduces the density. These elements confirm that the implantation allows for structural relaxation and thus a reduction in the density of the chalcogenide section.

[0132] Through the different embodiments described above, it is clear that the invention proposes a method for manufacturing a memory device by improving the properties.

[0133] The invention is not limited to the embodiments described above and extends to all embodiments covered by the invention. In particular, the PCM device may have any characteristic resulting from the implementation of the method, and conversely, the method may include any step configured to obtain a characteristic of the device.< / e> < / e>

Claims

Demands

1. Phase-change memory device (1) comprising a stack (100) comprising a memory point (200), the memory point (200) comprising, stacked in a so-called vertical direction (Z): i. a lower electrode (110) formed in a lower layer (110a), ii. at least one so-called chalcogenide section (120) formed in at least one chalcogenide layer (120a), disposed on the lower electrode (110), iii. an upper electrode (130) formed in an upper layer (130a) and disposed on at least one chalcogenide section (120), the memory point (200) having a lateral surface (203) and a superior face (201), the memory point also includes: - an encapsulation layer (300) encapsulating the memory point (200) and disposed in contact with the lateral surface (203) and the upper face (201), - at least one portion (125), referred to as the doped portion, extending from the lateral surface (203) and into the interior of the chalcogenide section (120), and having doping based on at least one species, referred to as the doping species, selected from the following species: carbon, fluorine, nitrogen, indium, arsenic, aluminum, germanium, silicon, chlorine, and boron, the doped portion (125) extending, in the vertical direction (Z), along the entire height of the chalcogenide section (120), the chalcogenide section (120) having an undoped portion (126) having no doping or less doping than the doped portion (125) in the doping species, the undoped portion (126) extending from the doped portion (125) to a center of the chalcogenide section (120).

2. Device (1) according to the preceding claim, wherein the doping species of at least one doped portion (125) has an atomic percentage greater than 0.5%.

3. Device (1) according to any one of the preceding claims, wherein the doped portion (125) has in all directions of a transverse plane (XY) perpendicular to the vertical direction (Z) a radial dimension 1125 with 1125 < 20 nm, preferably 1125 < 10 nm.

4. Device (1) according to any one of the preceding claims, wherein the doped portion (125) has in all directions of a transverse plane (XY) perpendicular to the vertical direction (Z) a radial dimension 1125 with 1125 > 2 nm, preferably 1125 > 5 nm.

5. Device (1) according to any one of the preceding claims, wherein the memory point (200) has a height H200 along the stacking direction (Z), the doped portion (125) extending along the stacking direction (Z) over at least 50%, preferably at least 75%, of the height H200 of the memory point (200).

6. Device (1) according to any one of the preceding claims, wherein the encapsulation layer (300) has a thickness e3Oo of between 10 nm and 30 nm.

7. Method of manufacturing a phase-change memory device (1) comprising the following steps: • supplying a stack (100) having an upper face (101), the stack (100) comprising, stacked in a so-called vertical direction (Z): i. a lower layer (110a), ii. at least one so-called chalcogenide layer (120a) based on at least one chemical element from the chalcogen family, iii. an upper layer (130a), • a structuring etching of the stack (100) from its upper face (101), the structuring etching extending into at least a part of the lower layer (110a) and enabling the formation of a memory point (200) comprising: i. a lower electrode (110) formed in the lower layer (110a), ii. at least one chalcogenide section (120) formed in at least one chalcogenide layer (120a), disposed on the lower electrode (110), iii.an upper electrode (130) formed in the upper layer (130a) and disposed on at least one. chalcogenide section (120), the memory point (200) having a lateral surface (203) and a superior face (201), • the formation of an encapsulation layer (300) encapsulating the memory point (200) and disposed in contact with the lateral surface (203) and the upper face (201) of the memory point (200), • an ionic implantation of a so-called doping species, chosen from among the following species: carbon, fluorine, nitrogen, indium, arsenic, aluminum, germanium, silicon, chlorine, and boron, in at least one chalcogenide segment (120) through the encapsulation layer (300), the ionic implantation being carried out along an implantation direction (10) forming an angle called the implantation angle θimpi with the vertical direction (Z), with θimpi > 25°, the ionic implantation being configured so as to dope at least one portion (125) called the doped portion of the chalcogenide segment (120), the doped portion (125) extending from the lateral surface (203), and to not dope or to dope with a doping level lower than the doping level of the doped portion (125) a portion (126) called the undoped portion extending from the doped portion (125) and up to a center of the chalcogenide section (120).

8. Method according to the preceding claim in which 2O<0impi<6O°.

9. A method according to any one of claims 7 and 8 wherein at least one chalcogenide section (120) comprises a first chalcogenide section (120') and a second chalcogenide section (120”): • the first chalcogenide segment (120') is placed on the lower electrode (100), and is intended to form a so-called memory layer, and • the second chalcogenide section (120”) is intended to form a so-called selective layer, the second chalcogenide section (120”) being separated from the first chalcogenide section (120') by an intermediate electrode (140), and • The ion implantation is configured so that the portion (125) of the chalcogenide section (120) extends into the first chalcogenide section (120') and the second chalcogenide section (120”).

10. A method according to any one of claims 7 to 9 wherein, during ion implantation, the implantation energy is greater than or equal to 1 keV, preferably greater than or equal to 4 keV, preferably greater than or equal to 10 keV, for example greater than or equal to 30 keV.

11. A method according to any one of claims 7 to 10 wherein, during ion implantation, a dose of doping species Dimp greater than 1015 atoms / cm2 is implanted.

12. A method according to any one of claims 7 to 11 wherein the encapsulation layer is based on at least one material taken from: SiN, SiC and SiCN.

13. A method according to any one of claims 7 to 12, wherein the chalcogenide section (120) comprises at least one chemical element among germanium, antimony and tellurium.

14. A process according to any one of claims 7 to 13 in combination with claim 9 wherein the second chalcogenide section (120”) comprises at least one chemical element among selenium, arsenic, sulfur, silicon and aluminum.

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