Electronic image acquisition circuit

Abstract

Image Acquisition Electronic Circuit This description concerns an electronic circuit comprising image acquisition cells (210), each cell having: - a photodetector (PD) connected to a first node (SN) of the cell; - an amplifier transistor (SF) having: its gate connected to the first node, a conduction node connected to an output (250) of the cell, and a back-gate control node, the amplifier transistor (SF) being configured so that its threshold voltage varies according to the back-gate voltage of the amplifier transistor (SF); the circuit comprising at least one feedback control circuit configured to adjust a voltage applied to the back-gate control node of the amplifier transistor (SF) of one of the cells as a function of a voltage (VX) present at the output of the cell and a reference voltage (VREF). Figure for the abbreviation: Fig. 2

Description

Title of the invention: Electronic image acquisition circuit

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[0007] technical field This description relates generally to electronic circuits and in particular to image sensors. Previous technique The electronic circuits of image sensors sometimes include image acquisition cells, called pixels, containing a photodiode used in reverse. For certain types of pixels, determining the illumination level received by a pixel involves measuring the voltage across the photodiode at specific times. During an acquisition period, the voltage across the photodiode varies due to the integration of the photogenerated current into the diode's capacitance. The voltage measurement is performed after the pixel has been reset. This reset introduces random noise with a standard deviation of μkr, where k is the Boltzmann constant, T is the temperature, and C is the capacitance of the photodiode. However, some new organic photosensitive materials expected to replace conventionally used semiconductors do not allow the use of a pinched diode, and therefore different pixel architectures must be used. There is a renewed interest in image sensors without a transfer gate. These pixel architectures include, for example, the "3T" type with three transistors, or the Capacitive Transimpedance Amplifier (CTIA) type. However, these pixel architectures are susceptible to noise induced by photodiode reset, which is generally ten times greater than all other noise sources. Summary of the invention There is a need to obtain electronic circuits including pixels where the impact of noise ^7" is reduced. One embodiment overcomes all or part of the drawbacks of known electronic circuits. One embodiment provides an electronic circuit comprising image acquisition cells, each cell comprising: - a photodetector connected to a first node of the cell; - an amplifying transistor having: its gate connected to the first node, a conduction node connected to a cell output, and a control node for a back-grid voltage, the amplifier transistor being configured so that its threshold voltage varies according to the back gate voltage of the amplifier transistor; the circuit comprising at least one control circuit configured to adjust a voltage applied to the back gate voltage control node of the amplifier transistor of one of the cells as a function of a voltage present at the output of the cell and a reference voltage.

[0008] One embodiment provides a method for controlling an electronic circuit, the method comprising: - to adjust, by means of a control circuit, as a function of a voltage present at an output of an image acquisition cell and a reference voltage, a voltage applied to a control node of a back-gate voltage of an amplifier transistor of the image acquisition cell of the electronic circuit, said amplifier transistor being configured so that its threshold voltage varies as a function of said back-gate voltage, each cell containing: - a photodetector connected to a first node of the cell, and - said amplifier transistor, one conduction node of which is connected to the output of the cell and the gate of which is connected to the first node.

[0009] In one embodiment, the amplifier transistor is formed in a technology using a semiconductor substrate stripped on insulator.

[0010] In one embodiment, each cell includes a sampling capacitor and a sampling transistor, the back-gate voltage control node of the amplifier transistor of each cell being connected to the sampling capacitor and connected to an output of the servo circuit via the sampling transistor.

[0011] In one embodiment, the sampling capacitor stores a sampled correction value of the output of the servo circuit on the rear gate voltage control node of the amplifier transistor.

[0012] In one embodiment, the size of the sampling capacitor is independent of the sensitivity of the image acquisition cell.

[0013] In one embodiment, the control circuit includes a differential amplifier, a first input of which is connected to said output of the cell, and a second input of which is configured to receive the reference voltage, an output of the differential amplifier providing an output voltage, applied to the sampling transistor, and a function of a difference between the voltage present at the output of the cell and the reference voltage.

[0014] In one embodiment, the first node of each cell is a detection node and each cell comprises: - a readout transistor connected in series with the amplifier transistor; and - a reset transistor configured to connect the detection node to a reset voltage rail, the amplifier transistor being mounted as a source follower and having said conduction node connected to the output of the cell via the readout transistor.

[0015] In one embodiment, each cell being of the capacitive transimpedance amplifier type and comprising: - a readout transistor connected in series with the amplifier transistor; - a reset transistor configured to connect an integration node, common to the read transistor, the amplifier transistor, and the reset transistor, to the first node; and - an integration capacity linking the integration node and the first node; the amplifier transistor having said conduction node connected to the output of the cell via the readout transistor.

[0016] In one embodiment, at least some of the cells are arranged in at least one column of cells, in which the outputs of the cells are interconnected by at least one first column conductor connected to a current source and to a first servo circuit configured to sequentially adjust a voltage applied to the back gate voltage control node of the amplifier transistor of each of the cells in the column.

[0017] In one embodiment, the amplifying transistor is isolated by trenches.

[0018] In one embodiment, the sampling capacitor has a capacitance su greater than that of the first associated node or capacity.

[0019] In one embodiment, the photodetectors comprise an organic material and / or nanoparticles. Brief description of the drawings

[0020] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0021] [Fig.1A] is a block diagram of an example of an electronic image acquisition circuit;

[0022] [Fig.1B] is a schematic view of a "3T" type pixel;

[0023] [Fig.1C] is a timing diagram illustrating an example of circuit operation beyond [Fig.lB];

[0024] [Fig.2] is a schematic view of an image acquisition cell matrix of an electronic circuit according to an embodiment of the present description;

[0025] [Fig.3] is a timing diagram illustrating the operation of the circuit of [Fig.2]; And

[0026] Figure 4 is a schematic view of an image acquisition cell array of an electronic circuit according to an embodiment of the present description. Description of embodiments

[0027] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0029] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0030] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0031] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0032] Figure 1A is a block diagram of an example of an image acquisition electronic circuit 100. This circuit includes an image acquisition matrix 140 (PIXEL ARRAY) comprising a matrix network of image acquisition cells or pixels at the intersection of row conductors and column conductors. The acquisition device also includes a control unit 120 (CTRL) driving, among other things, a row decoding circuit 130 (ROW DEC) and an output amplifier circuit 150 (OUTPUT-AMP ADC) or analog-to-digital converter circuit, generally one per column, providing digital OUT signals representative of the illumination of the different cells. These digital signals are used by a device (not shown) associated with the image acquisition electronic circuit and comprising, for example, circuits for storing the values ​​assigned to the different cells and for image processing.

[0033] Fig. 1B is a schematic view of a 201 pixel of type "3T" (meaning "3 transistors"). The pixel 201 actually contains three transistors, a first RST transistor, a second SF transistor and a third RD transistor.

[0034] In the example of [Fig. 1B], pixel 201 has a ground-referenced photodiode PD connected to a detection node SN of pixel 201. The sum of all the capacitances connected to this detection node SN—that is, the junction capacitance of the photodiode, the capacitances of the connected transistors, and the parasitic capacitances—is represented by reference 230. The photodiode PD is used in reverse, and capacitance 230 is, after a reset, discharged by a photocurrent that varies according to the received light intensity. The cathode of the photodiode is connected to the SN node.

[0035] In the example of [Fig. IB], the first transistor RST is configured to connect the sensing node SN to a reset voltage rail, for example powered by a VRST voltage.

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[0041] In the example in [Fig. 1B], the second SF transistor is configured as a source follower, with its gate connected to the SN detection node and its source connected to a 250 output of the pixel. The drain of the second SF transistor is, for example, connected to a supply rail with a positive potential VSF. In some cases, the VRST and VSF voltages are equal, although in other examples, these voltages may be different from each other. The first transistor RST receives, on its gate, a two-state RESET signal that resets the voltage at the detection node SN. When the RESET signal is in its first state, the first transistor RST is conducting. In the second state of the RESET signal, the transistor RST is blocked. In the example in [Fig. 1B], the third transistor RD is connected in series with the second transistor SF. In an example not shown, the drain of the second transistor SF is connected, via the third transistor RD, to the supply voltage rail VSF. The third transistor RD is controlled by a row or row select READ signal. The third transistor RD acts as a switch, allowing the SF transistor to be biased, for example, by a column current source connected to output 250 of pixel 201. When biased, the SF transistor is a follower that traces the signal from node SN to a node VX of output 250 of pixel 201. The transition from a conducting to a non-conducting state of the third transistor RD induces random noise with a standard deviation ^kT~ at the SN node, which the SF transistor then passes on at the output of the pixel VX. Figure [Fig.1C] is a timing diagram illustrating an example of the operation of the circuit beyond [Fig.1B]. At a time tl, the READ and RESET signals are set to a state, for example high, to make transistors RD and RST conduct. The detection node SN is thus activated. at the VRST voltage and the VX voltage stabilizes at a level 302 dependent on an offset due to the sizing of the SF transistor and the value of the corresponding column current.

[0042] At time t2, the RESET signal is, for example, set to a low state to make the RST transistor inactive. The capacitance at the SN detection node is on the order of a femtofarad, which means that at time t2, broadband noise ^kr~ is generated in the channel of the RST transistor and then sampled at the SN detection node. This noise is then integrated into VX in baseband as a random voltage shift, illustrated in curve 292, relative to the noise-free case 290. An integration phase starts at time t2, which causes the voltage VX to decrease (in the case where the charges are electrons) as the charges are photogenerated until time t5.

[0043] At a time t'3 between times t2 and t5, the READ signal goes, for example, to a low state, to make the RD transistor non-conducting and to allow access to other lines of the matrix.

[0044] At a time t4 between times t'3 and t5, the READ signal goes high, for example, to make transistor RD conduct until time t7. Between times t4 and t5, the voltage VX is converted, for example, by an analog-to-digital converter, not shown in [Fig. 1C], which is connected to the VX output of the pixel. In [Fig. 1C], the time scales between times t1 and t'3 and between t4 and t7 are not the same as between t'3 and t4, so that the relatively long time between t'3 and t4 can be represented. Therefore, although the slopes of curves 290 and 292 between t'3 and t4 appear steeper than between times t4 and t5, they are actually similar.

[0045] In the example in Figure IC, a second correlated double sampling phase takes place between time t6 and time t7 to determine the value of VX in the absence of photogenerated charges. To do this, the RESET signal goes high at time t5 until time t6, when it returns to a low level. Between times t5 and t6, the voltage VX stabilizes again at the same level as between times t1 and t2, within the limits of random noise ^kT~. At time t6 and until time t7, the pixel is read without a signal, which corresponds to a first digitization of the voltage level VX. The charges integrated between t6 and t7 can be neglected because the integration time is short.Between times t6 and t7, the voltage VX is, for example, converted during a second digitization by the analog-to-digital converter used for the first integration phase, and the comparison between the values ​​obtained during the two digitizations provides access to the amount of photogenerated charge. However, the random noise ^kT~ sampled on the voltage SN when the . The RST transistor switching state from high to low is statistically different between the first and second digitizations. The standard deviation of this difference becomes SïkT V c, and this noise is dominant compared to all other noise sources, given the generally very low value of the capacitance C of the SN detection node. It is therefore desirable to propose a solution to reduce the impact of this noise.

[0046] Figure 2 is a schematic view of a 140-cell acquisition matrix of 210 cells images of the electronic circuit according to an embodiment of the present description. In the example in [Fig. 2], only one cell 210 is shown for clarity. In one example, at least some of the cells 210 are arranged in at least one column of cells, in which the cells are interconnected by at least one first column conductor COL connected to a current source 245. In an example not shown, at least some of the cells 210 are arranged in several columns of cells, and the cells in the same column are interconnected by at least one column conductor, for example, isolated from the first column conductor, and connected to another current source or to the same current source 245.

[0047] In the example of [Fig. 2], each cell 210 comprises a "3T" type pixel as described in [Fig. 1B]. Unlike [Fig. 1B], in [Fig. 2], the second SF transistor of each cell further comprises a control node 262 for a back-gate voltage VBB of the second SF transistor. The second SF transistor is, for example, configured so that its threshold voltage varies according to this back-gate voltage.

[0048] The control node 262 corresponds, for example, to a back gate of the second SF transistor. In this case, the gate connected to the sensing node SN is a so-called "front" gate. The back and front gates can act separately, and with different associated transconductances, on the same channel of the second SF transistor. The back gates can be formed, for example, by technology using a fully depleted silicon-on-insulator (FDSOI) semiconductor substrate, preferably fully depleted silicon on insulator. When the substrate of the second SF transistor is of the FDSOI type, the back gate is, for example, formed under an insulating layer placed between the channel and the substrate. In this example, the front gate is, for example, formed on the surface above the insulator and the channel.

[0049] In another example, the control node 262 corresponds to an electrode influencing the threshold voltage of the channel made in the semiconductor material of the substrate of the second SF transistor. For example, portions of the semiconductor material containing said electrode are isolated from the rest of the substrate by insulating trenches, for example polarized.

[0050] In the example of [Fig. 2], the source of the second SF transistor of each cell The third transistor RD of the same column is connected, via the third transistor, to the column conductor COL of matrix 140. The third transistor RD is controlled by a row or row selection READ signal, supplied, for example, on a control line 280 common to all cells 210 of the same row. The transistor RD forwards the voltage information from node SN, which arrives at the output 250 of cell 210, to the column conductor COL of the same column with a value VX.

[0051] In the example of [Fig.2], the outputs 250 of the cells in the same column are, for example, interconnected by the same column conductor COL.

[0052] In the example of [Fig.2], the circuit includes at least a first control circuit 295 having an input connected to the output 250 of the cells 210 of the same column and having an output connected to the control node 262 of the back gate voltage of the second SF transistor of the cells 210 of the same column via another column conductor 285 and via a CORR sampling transistor included in each pixel.

[0053] The servo circuit 295 is, for example, configured to adjust a voltage VBB applied to the rear gate voltage control node of the second SF transistor as a function of a servo control of the voltage VX present at the output 250 of the cell selected on the READ signal so that it tends towards a reference voltage VREF.

[0054] In the example of [Fig. 2], the control circuit 295 includes a differential amplifier 290, a first input 292 of which is connected to said output 250 of the cell, and a second input 294 of which is configured to receive the reference voltage VREF. The differential amplifier 290 has, for example, an output configured to provide an output voltage VCORR, which is a function of the level of control applied to the voltage VX so that the voltage VX tends towards the reference voltage VREF. In one example, the voltage VREF is chosen to be at an average level of the voltages present at the storage nodes SN of the cells 210 of the column, less the gate-source voltage of the second transistor SF.

[0055] The servo circuit 295 applies the VCORR correction to the cell selected by the transistor RD via the CORR sampling transistor of the same cell.

[0056] In the example of [Fig. 2], each cell 210 comprises a ground-referenced storage capacitor 255 and the sampling transistor CORR. The back-gate control node 262 of the second SF transistor in the cell is connected to the storage capacitor 255 and to the output of the differential amplifier 290 via the sampling transistor CORR. One of the main conduction nodes of the sampling transistor CORR in each cell of the same column is connected to the output of the servo circuit 295. In For example, the 255 storage capacitor has a capacitance greater than the capacitance of the SN detection node, which allows, for example, the reduction of charge injection during sampling by the CORR transistor and promotes the retention of the VBB servo voltage without impacting the conversion factor (in Volt / electron) of the pixel.

[0057] The sampling transistor CORR receives, at its gate, a two-state SMP control signal defining time ranges in which, respectively, 1) the output of amplifier 290 is connected to the control node 262 of the rear gate voltage of the SF transistor, and 2) in which the sampling transistor CORR is cut off and the VCORR voltage is therefore sampled and stored by capacitor 255. The retention of the VCORR voltage is all the better when the storage capacitor 255 is connected to the rear gate of the CORR transistor, because the gain between the rear gate and the source is approximately 10%, compared to approximately 90% for the front gate. Having a large capacitance thus limits the voltage drift due to leakage currents, and furthermore, this voltage drift is greatly attenuated by the low gain between the rear gate 262 and the source of the SF transistor.The VBB control voltage of node 262 corresponds to the VCORR output voltage of amplifier 290, sampled by the CORR sampling transistor and stored by capacitor 255.

[0058] The control value found in the VBB voltage sampled on capacitor 255 also samples noise in / 77" where "Cl" is here the value of Vci Sampling capacity 255. However, since the sampling capacity 255 is greater than the capacity of the detection node SN, the generated noise is lower. Furthermore, as the sampled VBB voltage is stored on the back gate 262, its associated noise is multiplied by the back gate amplification (approximately 10%), given that the main noise to be corrected at the detection node SN undergoes approximately 90% amplification by the front gate. Comparing these two contributions to the VX node, the contribution to the total noise at output 250 resulting from the correction on the back gate 262 is significantly lower than that of the noise to be corrected at the detection node SN, for example, by a factor of 1 / 10.

[0059] The SMP signal is, for example, common to all cells in the same row and is provided, for example, on a row 270.

[0060] In operation, the amplifier 290 provides the VCORR voltage to make the output voltage VX of the selected cell equal to the reference voltage VREF.

[0061] The [Fig.3] is a timing diagram illustrating the operation of the circuit of the [Fig.2].

[0062] At a time t1, similar to time t2 in [Fig. 1C], the READ, RESET and SMP signals are set to a state, for example high, to make the transistors RD, RST and CORR passers. The 210 cells of the row to be read are then selected. The SN detection node is thus brought to the VRST voltage and the VX voltage stabilizes at a level dependent on a 302, 304 offset due to SF transistor sizing disparities between cells.

[0063] At a time t2, the RESET signal is, for example, set to a low state to make the RST transistor not conducting. At time t2, the noise ^kr~ generated in the channel of the transistor RST is sampled at the pixel output and is integrated into VX as a voltage shift.

[0064] At time t3, the amplifier 290, which was for example activated beforehand at time t2, provides at its output the voltage VCORR generated on the basis of a comparison between the initially noisy voltage VX and the voltage VREF. The noise is sampled At time t2, the amplifier input is set, and it then requires some time (until t3) to stabilize. The resulting VCORR voltage level depends on the voltage across the SN detection node, which includes both offsets due to differences in the sizing of the SF transistors and noise IkT. The VC voltage VCORR will modify the threshold voltage of the second SF transistor of the selected cell which, in turn, will modify the output voltage of the VX cell by forming a feedback loop so that VX tends towards VREF.

[0065] At time t3, with the amplifier output stabilized at the correction value, the SMP signal is, for example, set to a low level to make the CORR sampling transistor inactive, and the amplifier 290 is, for example, deactivated. The correction sampling capacitor 255 then takes over, storing the feedback voltage for the entire duration of the integration, which begins after sampling.

[0066] As shown in the example in [Fig. 3], at time t3, a charge injection can occur at the control node 262, resulting in a variation of the VCORR voltage. Furthermore, there is another, much larger charge injection occurring at the falling edge of the RESET signal. Those skilled in the art will implement precautions to limit these charge injections and may, for this purpose, implement a correlated double sampling (CDS) method.

[0067] The output level VX obtained during the establishment and sampling of the correction is mainly deterministic since the random part corresponding to the noise has been corrected.

[0068] At time t'3, similar to time t'3 of [Fig.lC], the READ signal passes, for example to a low state, to make the selection transistor RD non-conducting.

[0069] Similar to [Fig. IC], the first integration phase starts from time t2 which causes the voltage VX to fall (in the case where the charges are electrons) as the charges are photogenerated until time t5 similar to [Fig. IC].

[0070] At time t4, which is between times t'3 and t5 and similar to time t4 in [Fig. 1C], the READ signal goes, for example, high to make the transistor RD conduct until time t8, similar to time t8 in [Fig. 1C]. Between times t4 and t5, the voltage VX is, for example, converted by an analog-to-digital converter, not shown in [Fig. 3], which is connected to the VX output of the pixel.

[0071] In [Fig. 3], the time scales between times t1 and t'3 and between t4 and t8 are not the same as between t'3 and t4, so that the relatively long time between t'3 and t4 can be represented. Therefore, although the slope of the voltage curve VX between t'3 and t4 appears steeper than between t4 and t5, it is actually similar.

[0072] The electronic circuit and its operation, as described in the example in [Fig. 2] and 3, make it possible to correct, while maintaining a certain speed, by aligning the output voltage VX of the cell with the reference voltage VREF, the random thermal noise intrinsic to the "3T" configurations. A similar problem can be applied to the "CTIA" configurations.

[0073] Similar to [Fig. IC], the second correlated sampling phase takes place between times t7 and t8 to apply the reset value, before the integration phase, and taking into account the noise correction kT / C.

[0074] At time t5, after the signal conversion with the analog-to-digital converter, the RESET and SMP signals return to a high level to make the RST and CORR transistors conduct respectively, and perform a new noise control operation with the control circuit 295.

[0075] At time t6, similar to time t6 in Figure IC, the RESET signal goes, for example, low to make the RST transistor inactive. A new noise value [kT~] is then sampled at the detection node. Before time At t6 or at t6 the amplifier is, for example, reactivated to control the output voltage VX of the cell to the voltage VREF as between t2 and t3. The output level VX obtained at the end of establishment, at a time t7, and the sampling of the correction is then deterministic and equal to that obtained at time t3 due to the elimination of the random part ^kT.

[0076] At the end of the establishment time, at time t7, between times t6 and t8, the SMP signal goes, for example, to a low level to make the transistor non-passing CORR sampling, which allows the VBB correction to be stored at apply to capacitor 255. Between times t7 and t8, an analog conversion digital measurement of the voltage VX, not shown, is then performed, which allows measurement VX in the absence of photogenerated loads and with noise correction / TF. By V”

[0077] The difference between the first conversion (between t4 and t5) and the second conversion (between t7 and t8) means that the correlated double sampling (CDS) function only provides the result of integrating photogenerated charges, the random part ^kT~ having been corrected. By comparison, during the same transition to the high state of the READ signal between the value of VX, obtained between t7 and t8, and the value of VX, obtained between t4 and t5, That is to say, after the integration phase, it is possible to measure a more precise quantity of the accumulated charges without memory storage. Since the same elements (cell 210, amplifier 295, control voltages, etc.) are used between times t2 and t3, and then between times t6 and t7, the disparities involved are the same, so their effects will exactly cancel each other out through the correlated double sampling operation.

[0078] The phase of operation of the electronic circuit between times t5 and t8 makes it possible to overcome the sizing variations of the transistors between the cells (Fixed Pattern Noise), particularly with regard to the disparities between the CORR transistors and / or second SF transistors of the different cells 210

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[0082] of the different columns. In summary, before the first digitization, the feedback loop divides the sum of the deterministic offset due to manufacturing differences and the first generated random noise ^kT by the loop gain. Similarly, before the second digitization, the feedback loop 295 corrects the sum of the deterministic offset due to manufacturing differences and the second generated random noise ^ÿ~. The difference between the two digitizations corresponds to the signal due to the photogenerated charges. Correlated double sampling (CDS) allows us to differentiate between the two scans to obtain the photogenerated charges. The expert can nevertheless implement a measurement of photogenerated charges without correlated double sampling, albeit at the cost of lower accuracy. Indeed, correlated double sampling allows for correction of factors such as the amplifier offset 290 and charge injection during sampling at the VBB level.

[0083] Figure 4 is a schematic view of a matrix 140 of image acquisition cells 410 of an electronic circuit according to an embodiment of the present description. In the example of Figure 4, only one cell 410 is shown for clarity, but several cells 410 are, for example, arranged in columns and rows in a similar manner to the cells 210 of Figure 2.

[0084] The 410 cells of [Fig.4] incorporate similar elements to those of the 210 cells of [Fig.2] except that the 410 cells each include a CTIA type pixel and not a “3T” type transistor.

[0085] In the example of [Fig. 4], the CTIA pixel of cell 410 comprises a ground-referenced PD photodiode connected to an NCTIA input node of the CTIA. The sum of all the capacitances connected to the NCTIA input node—that is, the junction capacitance of the photodiode, the capacitances of the connected transistors, and the parasitic capacitances—is represented by reference 230. The PD photodiode is used in reverse, and the generated photocurrent integrates into an integrating capacitance Cint connecting the SN node to the NCTIA node. The cathode of the photodiode is connected to the NCTIA node.

[0086] In the example of [Fig. 4], the CTIA pixel of cell 410 includes a first transistor RST configured to connect the NCTIA input node to a detection node SN common to transistors RD and DRV. The RST transistor receives, on its gate, a two-state RESET control signal that resets the voltage at the NCTIA input node. When the RESET signal is in its first state, the RST transistor conducts, which resets the charge of Cint. In the second state of the RESET signal, the RST transistor is off, which allows the integration of the photogenerated charges into Cint.

[0087] In the example of [Fig.4], the DRV transistor, mounted in common source, has its gate connected to the input node NCTIA and its drain connected to the integration node NINT.

[0088] In the example of [Fig. 4], cell 410 includes a transistor RD connected in series with the drain of transistor DRV at the common node NCTIA. The drain of transistor DRV is connected, via the third transistor RD, to the column conductor COL, which is connected to a current source 245. Transistor RD is controlled by a row or row selection READ signal.

[0089] When cell 410 is biased, i.e., when the READ signal is high, the potential of the NCTIA node is equal to the gate-source voltage of the DRV transistor biased by the current from the current source 245. When the RESET signal is high, the voltage across Cint is 0V. When the RESET signal is low, the photogenerated charges integrate into the feedback capacitor Cint. The signal is therefore detected at the integration node NINT.

[0090] In the example of [Fig. 4], and similarly to [Fig. 2], the DRV transistor of each cell 410 further includes a control node 262 for a back-gate voltage VBB of the DRV transistor. The DRV transistor is configured, as in [Fig. 2], so that its threshold voltage varies according to this back-gate voltage.

[0091] In the example of [Fig. 4], the circuit comprises at least one first control circuit 295, similar to the control circuit 295 of [Fig. 2], and having an input connected to the output 250 of the cells 410 of the same column and having an output connected to the control node 262 of the back gate voltage of the second SF transistor of the cells 410 of the same column via another column conductor 285. The correction is applied to a given cell when the corresponding sampling transistor CORR is conducting, and the cell row is selected with READ=1. Since the control circuit 295 of [Fig. 4] is similar to that of [Fig. 2], only the input 292 and the output VCORR are shown. The control circuit 295 of [Fig. 4] is similar to that of [Fig. 2].4] is configured to adjust a VBB voltage, which is the VCORR voltage that will be sampled, applied to the control node 262 of the back gate voltage of the DRV transistor based on a comparison between the VX voltage present at the output 250 of the selected cell with the READ signal and the VREF reference voltage.

[0092] The example in [Fig. 4], similarly to the example in [Fig. 2], allows a threshold voltage correction to be stored on the rear gate of the DRV transistor connected in common-source configuration, in order to correct the offset seen on the VX rail. A person skilled in the art will be able to implement the control of the rear gate voltage VBB in a manner similar to that shown in detail in the example in [Fig. 2].

[0093] The operation of the example in [Fig.4] is similar to the example in [Fig.3] except that the voltage VX between t2 and t6 increases instead of decreasing during the integration of the signal.

[0094] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0095] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

[0096] In particular, in the examples in Figures 2 or 4, the capacitance of capacitor 255 can be chosen to be large, for example, compared to that of the SN detection node or the Cint capacitance, to promote retention independently of the capacitance of the SN detection node for [Fig. 2] or the Cint capacitance of [Fig. 4]. In other words, the size of the sampling capacitor 255 is independent of the sensitivity of the image acquisition cell 210, 410.

[0097] In particular, even though the embodiments presented are based on the photo generation of electrons, a person skilled in the art will be able to use their knowledge to modify the circuits presented in the case where holes are generated at the level of the SN detection node.

[0098] On the other hand, even though the case of photodiodes has been described in the different embodiments, a person skilled in the art may replace them with photodetectors comprising an organic material and / or nanoparticles.

Claims

Demands

1. Electronic circuit comprising image acquisition cells (210, 410), each cell comprising: - a photodetector (PD) connected to a first node (SN,NCTIA) of the cell; - an amplifier transistor (SF,DRV) having: its gate connected to the first node, a conduction node connected to an output (250) of the cell, and a back-gate voltage control node, the amplifier transistor (SF,DRV) being configured so that its threshold voltage varies according to the back-gate voltage of the amplifier transistor (SF,DRV); the circuit comprising at least one control circuit configured to adjust a voltage applied to the back-gate voltage control node of the amplifier transistor (SF,DRV) of one of the cells as a function of a voltage (VX) present at the output of the cell and a reference voltage (VREF).

2. Circuit according to claim 1, wherein the amplifier transistor (SF,DRV) is formed in a technology using a semiconductor substrate stripped on insulator.

3. Circuit according to claim 1 or 2, wherein each cell (210, 410) comprises a sampling capacitor (255) and a sampling transistor (CORR), the back-gate voltage control node (262) of the amplifier transistor (SF,DRV) of each cell being connected to the sampling capacitor (255) and connected to an output of the servo circuit (295) via the sampling transistor (CORR).

4. Circuit according to claim 3, wherein the sampling capacitor (255) stores a sampled correction value (VBB) of the output of the servo circuit (295) on the rear gate voltage control node of the amplifier transistor (SF,DRV).

5. Circuit according to claim 3 or 4, wherein the size of the sampling capacitor (255) is independent of the sensitivity of the image acquisition cell (210, 410).

6. Circuit according to any one of claims 3 to 5, wherein the The control circuit (295) includes a differential amplifier (290) having a first input (292) connected to said output (250) of the cell, and having a second input configured to receive the reference voltage (VREF), an output of the differential amplifier (290) providing an output voltage (VCORR), applied to the sampling transistor (CORR), and a function of a difference between the voltage (VX) present at the output of the cell and the reference voltage (VREF).

7. Electronic circuit according to any one of claims 1 to 6, the first node of each cell being a sensing node (SN) and each cell comprising: - a readout transistor (RD) connected in series with the amplifier transistor (SF); and - a reset transistor (RST) configured to connect the sensing node (SN) to a reset voltage rail, the amplifier transistor (SF) being mounted as a source follower and having said conduction node connected to the output (250) of the cell via the readout transistor (RD).

8. Electronic circuit according to any one of claims 1 to 6, each cell being of the capacitive transimpedance amplifier (CTIA) type and comprising: - a readout transistor (RD) connected in series with the amplifier transistor (DRV); - a reset transistor (RST) configured to connect an integration node (NINT), common to the readout transistor (RD), the amplifier transistor (DRV) and the reset transistor (RST), to the first node (NCTIA); and - an integration capacitor (Cint) connecting the integration node (NINT) and the first node (NCTIA); the amplifier transistor (DRV) having said conduction node connected to the output (250) of the cell via the readout transistor (RD).

9. A circuit according to any one of claims 1 to 8, wherein at least some of the cells are arranged in at least one column of cells, wherein the outputs (250) of the cells are interconnected by at least one first column conductor (COL) connected to a current source (245) and to a first servo circuit configured to sequentially adjust a voltage applied to the node

10.

11.

12.

13. control of the rear grid voltage of the amplifier transistor (SF, DRV) of each of the cells in the column. Circuit according to any one of claims 1 to 9, wherein the amplifier transistor (SF,DRV) is isolated by trenches. Electronic circuit according to any one of claims 8 to 10 in their dependence on claim 3, wherein the sampling capacitor (255) has a capacitance greater than that of the first associated node (SN) or capacitance (Cint). Circuit according to any one of claims 1 to 11, wherein the photodetectors comprise an organic material and / or nanoparticles. A method for controlling an electronic circuit according to any one of claims 1 to 12, the method comprising adjusting, by a control circuit, as a function of a voltage (VX) present at an output (250) of an image acquisition cell (210, 410) and a reference voltage (VREF), a voltage applied to a control node of a back-gate voltage of an amplifier transistor (SF, DRV) of the image acquisition cell (210, 410) of the electronic circuit, said amplifier transistor being configured so that its threshold voltage varies as a function of said back-gate voltage, each cell comprising: - a photodetector (PD) connected to a first node (SN,NCTIA) of the cell, and - said amplifier transistor (SF,DRV) of which a conduction node is connected to the output (250) of the cell and whose gate is connected to the first node.

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