Method for determining computing hardware architectures

Abstract

A method for determining a hardware architecture of an integrated circuit is proposed, comprising a plurality of iterative steps: - applying (130) an optimization algorithm to an architecture exploration space to determine at least one candidate architecture configuration, said space comprising functions evaluating optimization criteria; - applying said configuration (140) to evaluation tools; - determining (150) at least two main optimization criteria chosen from among the computational performance, energy consumption and / or the area of ​​said circuit, one main criterion being determined from the results of the evaluation tools and a technology database; - determining whether (160) a stopping criterion is met; At each iteration, the determination of said configuration is optimized via the evaluation of the functions relating to the main criteria.The iterations are stopped in response to the verification of the stopping criterion and the generation of at least one optimized configuration. Figure for the abbreviation: [Fig.1].

Description

Title of the invention: Method for determining computing hardware architectures Technical field

[0001] The present invention relates generally to electronic systems, and in particular to a method for determining computing hardware architectures by exploring the design space.

[0002] Computing hardware architectures are conventionally used as basic elements for the design of systems on chip.

[0003] A system-on-chip, also called SoC (or System-on-Chip according to the corresponding English expression) corresponds to a complete system embedded on an integrated circuit which comprises a multitude of electrical or electronic components. Such an integrated circuit implements characteristic functionalities associated with a specific application or application domain, as well as generic elements, such as processor cores, storage elements or even inputs / outputs. An integrated circuit comprises a hardware device (or hardware device) which is generally associated with software configured to control the hardware device and in particular to implement the characteristic functionalities. The hardware device comprises, in particular for so-called high-performance SoCs, a multi-core hardware architecture (i.e. composed of several computing cores) and is produced from assembled hardware bricks.Hardware device design involves developing the hardware architecture of the various building blocks and configuring them using known Computer Aided Design (CAD) tools, according to a design flow. A design flow comprises a set of steps implemented using a variety of tools. Such tools enable the actual design (e.g., transforming a high-level architecture description into a lower-level one) as well as evaluating possible architecture configuration cases. Such tools are also used to validate the complete design of an SoC circuit.

[0004] With the increase in complexity of integrated circuits, such a design flow leads to an increase in the design space for exploration, which can lead to multiple iterations at each step in the design flow, an increase in the complexity of the tools and difficulties in linking the different tools, as well as an increase in the cost of the necessary resources.

[0005] Various design methods and tools have been proposed to attempt to improve the design flow of computing hardware architectures. Known methods use manual or dynamic design flows using different simulators to perform an exploration of the design space and defined architecture configurations by applying an optimization algorithm, as described for example in the article “An Automatic Design Space Exploration Framework for Multicore Architecture Opthnizations” by H. Calborean et al., 9th RoEduNet, vol. 14, 2010, or as described for example in the article “Multilevel simulation-based codesign of next generation HPC microprocessors” by L. Zaourar et al., International Workshop PMPBS (PMBS), Super Computing, St. Louis, United States, 2021.

[0006] However, such methods do not allow for a dynamic design flow capable of determining the best configurations by optimally taking into account all the different results delivered by the available evaluation and design tools, for the exploitation of a wide choice of evaluation parameters. These methods also do not allow for supporting a multi-level vision of the design of an integrated circuit in which the results of one design level could be reused to improve the results of a previous level.

[0007] There is thus a need for a method capable of optimizing the determination of the computing hardware architectures to be used for the design of an integrated circuit. Summary of the invention

[0008] The present invention improves the situation by providing a computer-implemented method for determining a hardware architecture of an integrated circuit. The method comprises at least a plurality of iterations of the following steps:

[0009] - apply an optimization algorithm A to an architecture exploration space E, so as to determine at least one candidate architecture configuration G, the candidate architecture configuration G belonging to the architecture exploration space E, the architecture exploration space E comprising a set of objective functions F evaluating optimization criteria Cq associated with the candidate architecture configuration G;

[0010] - apply the candidate architecture configuration G to a plurality of tools Om evaluation, which provides evaluation results of candidate architecture configurations G;

[0011] - determine a value of at least two optimization criteria Cq, the at least two so-called main optimization criteria being chosen from among the calculation performance, the energy consumption and / or the surface area of ​​the integrated circuit to be designed, the value of one of the main optimization criteria being determined by applying an analytical function T taking as arguments at least one piece of circuit information and at least one piece of circuit information. at least one technological information, the at least one circuit information being determined from the evaluation results provided by at least one evaluation tool Om among the evaluation tools Om, the at least one technological information coming from at least one technological database; and

[0012] - determine whether a stopping criterion is verified.

[0013] At each iteration, the determination of the candidate architecture configuration G is optimized from the evaluation of the objective functions F relating to the determined values ​​of the at least two main optimization criteria Cq.

[0014] The method further comprising stopping the iterations in response to the verification of the stopping criterion and generating at least one optimized Gopt computation architecture configuration from the at least one G architecture configuration.

[0015] In embodiments, the stopping criterion can be defined as a function of an evaluation of at least one objective function Fh relating to a main optimization criterion Cq, from the determined value of the main optimization criterion.

[0016] Alternatively, the stopping criterion may be defined based on a predefined execution time of the plurality of iterations of optimization steps.

[0017] Advantageously, each evaluation tool Om can be configured to generate a set of evaluation results Rmg associated with the at least one architecture configuration G. The method can further comprise a step consisting of applying the candidate architecture configuration G to a first evaluation tool O m among the evaluation tools Om, from at least one evaluation result Rmg resulting from a prior step of applying the candidate architecture configuration G to a second evaluation tool Om among the evaluation tools Om.

[0018] The generation of the at least one architecture configuration G can be carried out according to said plurality of usable evaluation tools Om.

[0019] According to embodiments, the method may further comprise a prior step of receiving an architecture descriptor D and a step of generating the architecture exploration space E from the architecture descriptor D and the optimization algorithm A.

[0020] Advantageously, an evaluation tool Om of the plurality of evaluation tools Om may be an evaluation tool chosen from an architecture configuration simulator, an architecture compilation tool, a consumption evaluation tool, a tool based on exploitation of a database and a tool based on exploitation of a candidate configuration data memory. The candidate configuration data memory may be used to save evaluation results from the step of applying candidate architecture configurations G and / or from the step of determining the value of optimization criteria Cq of candidate architecture configurations G.

[0021] Another object of the invention is an integrated circuit hardware architecture obtained by implementing the determination method.

[0022] The invention further provides a method of designing an integrated circuit comprising an implementation of an integrated circuit from the integrated circuit hardware architecture.

[0023] The invention also provides a computer program product comprising programming code instructions capable of being implemented by a computer, the computer being capable of implementing the method for determining a hardware architecture of an integrated circuit.

[0024] The method for determining computing hardware architectures according to the embodiments of the invention allows optimization of the exploration of the design space and the architecture configurations to be analyzed to design an optimized integrated circuit.

[0025] The embodiments of the invention thus provide a fast, flexible and efficient solution for determining a complex system-on-chip architecture. Such a solution has the advantage of being not only 'multi-level', in that it is applicable at different levels in the integrated circuit architecture (i.e. to the complete system, to the system architecture including the interconnections between the basic elements, or to the microarchitecture of the basic elements of the integrated circuit), while ensuring a broad exploration, but also 'single-objective' or 'multi-objective'. The exploration of the design space can be carried out from executions and different combinations of these various and varied evaluation tools, functional or extra-functional for example.

[0026] This results in a non-intrusive solution adapted to different existing methods of conventional circuit design flows (for example for the generation of RTL code, logic synthesis, routing placement, etc.). In particular, the method for determining computing hardware architectures according to the embodiments is adaptable to any design flow. Such a method does not require modifying steps usually implemented in a conventional circuit design flow and simply allows the addition of steps. Furthermore, such a method requires little so-called confidential information from a conventional design flow such as information from the RTL code. Description of figures

[0027] Other characteristics, details and advantages of the invention will emerge from reading the description given with reference to the appended drawings given by way of example.

[0028] [Fig. 1] [Fig. 1] is a flowchart representing the steps of the method of designing integrated circuit hardware architectures, according to embodiments of the invention.

[0029] [Fig.2] [Fig.2] is a diagram showing an overall structure of an integrated circuit hardware architecture design flow, according to embodiments of the invention. Detailed description

[0030] [Fig.l] represents a method for determining a hardware architecture of an integrated circuit, according to certain embodiments of the invention.

[0031] The integrated circuit hardware architecture determined by such a method makes it possible to generate a hardware description file of an integrated circuit (SoC for example). The hardware description file of the integrated circuit can be written in hardware description language, for example and without limitation, in VHDL or Verilog language. Such a hardware description file will then be used to design the integrated circuit according to an existing integrated circuit design method. The integrated circuit is potentially capable of performing all types of calculations, and in particular complex calculations.

[0032] The integrated circuit can be used or defined for many different applications and technical fields. The integrated circuit can be used for example and without limitation in telecommunication systems, in imaging systems, industrial systems (such as cybersecurity systems, in systems associated with manufacturing processes for example), in systems specific to the banking or tax field, or in systems for scientific calculations, such as high-performance computing systems of the HPC type, etc.

[0033] The method for determining the hardware architecture of an integrated circuit according to the embodiments of the invention makes it possible to determine the hardware architecture of an integrated circuit from a descriptor D of the architecture and / or from an exploration space E of the architecture. The hardware architecture determined by the method according to the embodiments of the invention is advantageously optimized according to various optimization criteria to allow efficient execution of complex or specific calculations by the integrated circuit.

[0034] The architecture descriptor D corresponds to a first representation (also called 'internal representation' or 'architectural representation') of a hardware architecture design optimization problem. The architecture exploration space E corresponds to a second representation (also called 'mathematical representation') of this hardware architecture design optimization problem. The exploration space E can thus be a translation of the internal representation into a mathematical representation.

[0035] The architecture descriptor D and / or the architecture exploration space E comprise a set of elements making it possible to define (or describe or model) a integrated circuit hardware architecture, such as parameters of the integrated circuit to be designed (for example, structural parameters related to the components and / or resources of the circuit), circuit optimization objectives (related for example to performance and / or consumption and / or sizing of the circuit) and / or constraints of the integrated circuit to be designed.

[0036] The integrated circuit may be, for example, a heterogeneous high-performance computing processor comprising a plurality of computing cores and different constituent elements (or integrated circuit components such as memories. In such an example, the parameters of the integrated circuit to be designed may include the types of computing cores, the number of computing cores for each type of core, the hierarchy of the memories, the bandwidth and the pre-fetching (or pre-charging) of the memories, and / or the interconnection between the different computing resources (for example a network on chip NoC, or Network on Chip according to the corresponding English expression), etc.

[0037] In embodiments, the objectives of the integrated circuit to be designed may include, for example, maximizing the computational performance of the integrated circuit, minimizing the power consumption of the integrated circuit, and / or minimizing the area (or size) of the integrated circuit. In particular, the computational performance may be associated, for example, with a temporal datum such as the latency or the frequency of execution of computations, the performance also being able to be linked to the peak computational power, for example the number of computational elements of the integrated circuit and their size, and / or to the memory footprint of the hardware architecture, for example the number of storage elements of the integrated circuit and their size.

[0038] The constraints of the integrated circuit to be designed may be, for example, design constraints relating to the predetermined parameters of the circuit and / or to the objectives, or even known physical constraints.

[0039] In embodiments, the architecture descriptor D may be represented according to a format specific to a design flow to be implemented by the method according to the embodiments of the invention to produce the integrated circuit. For example, the architecture descriptor D may be implemented in the form of a computer file of the 'computational architecture template' type (i.e. of the computational architecture pattern type). The architecture descriptor D may comprise a so-called high-level description of the parameters, objectives and / or constraints of the integrated circuit to be designed. For example and without limitation, the architecture descriptor D may be a text file and / or an XML file comprising a number of cores, their type, their size, a number of memories, a number of interconnection networks, a number of buses, a number of NoCs, the position of the routers, the topology, etc.

[0040] The exploration space E may comprise one or more data structures. In particular, a data structure may comprise a set P of N parameters to be optimized Pn (also called parameters to be explored or decision variables) of the integrated circuit to be designed. The index 'n' associated with different parameters to be optimized is thus an integer between 1 and N. The set P may be defined according to the following expression (01):

[0041] (Ph ..., PN} andPeE(Ol)

[0042] For each parameter Pn, a data structure of the exploration space E can also comprise one or more sets Ln of sub-parameters associated with the parameter Pn. Thus, each set Ln can comprise Kn sub-parameters to be optimized fnk of the integrated circuit to be designed. The integer Kn is a variable integer depending on the parameter Pn considered. The index 'k' associated with different sub-parameters of the set Ln is thus an integer between 1 and Kn. The set Ln can be defined according to the following expression (02):

[0043] Ln={f„}, ..., CnKn}

[0044] In embodiments, a set L may also be associated with a sub-parameter fnk. Thus, a set Lnk may be defined according to the following expression (03):

[0045] = {4,,« l(..... j and L„ke E (03)

[0046] Thus, the data structure(s) of the exploration space E comprising the different sets P and L can be structured hierarchically according to the dependencies between parameters and sub-parameters.

[0047] Furthermore, a data structure of the exploration space E may comprise a set F of H objective functions and / or constraints Fh of the integrated circuit to be designed, and may be defined according to the following expression (04):

[0048] F = {F], ..., Fh} and F e E (04)

[0049] The set P and / or the set(s) L and / or the set F may for example be implemented in the form of matrices, tables, lists or vectors. The values ​​N, K and H are integers greater than or equal to 2.

[0050] For example and without limitation, a set (or list) P of parameters Pn to be optimized for an integrated circuit comprising a plurality of computing cores can be defined according to the following enumeration (05):

[0051] P = {'Pp number of cores', 'P2: type of each core', 'P3: memory hierarchy parameters', 'P4: memory bandwidth', 'P5: NoC / Interconnection', 'P6: presence of a memory prefetching mechanism'} (05)

[0052] The list P can thus include, according to the preceding enumeration (05), the number of cores of the integrated circuit, the type of each core of the integrated circuit, the parameters of the cache hierarchy of the integrated circuit, the bandwidth of the memory of the circuit integrated circuit (or memory bandwidth in English), the type of NoC interconnect network of the integrated circuit, and / or the presence or absence of a memory prefetching mechanism of the integrated circuit, etc. It should be noted that if the presence of a memory prefetching mechanism of the integrated circuit is confirmed, sub-parameters may include the type and / or size of the memory prefetching mechanism.

[0053] A set Ln of sub-parameters fnk may for example correspond to a plurality of possible values, magnitudes or metrics associated with each parameter Pn of the previous set P. For example and without limitation, a set (or list) Ln may be defined according to the following enumerations (06) and (07):

[0054] - for parameter 'P5: NoC / Interconnection' of list P, list L5 can be:

[0055] L5 = {'Gu NoC interconnection network topology', 'G2: routing algorithm', ' G3: number of routers', 'G4: position of routers', 'G5: type of routers'} (06)

[0056] - for parameter 'P3: memory hierarchy parameters' of list P, list L3 maybe :

[0057] L3 = {'Gu cache instruction #1', 'G2: cache data #1', 'G3: cache instruction #2', ' / 34: cache data #1', 'G5: level 3 cache size', 'Ge: last level cache size'} (07)

[0058] A list Ln (and in particular the preceding list L3) can thus comprise, according to the preceding enumeration (06), cache instructions (or cache instruction in English), cache data (or data cache in English), the size of the level 3 cache (or SLC meaning System Level Cache according to the Anglo-Saxon expression), and / or the size of the last level cache (or LLC meaning Last Level Cache according to the Anglo-Saxon expression), etc.

[0059] Furthermore, for example for the parameter 'P3: memory hierarchy parameters' of the list P, a set (or list) Lnk can be defined according to the following enumerations (08), (09), (10) and (11):

[0060] - for sub-parameter '3i: cache instruction no. T of list L3, list L3i can be :

[0061] L3i = {'Gi(U cache line size', 'Gw associativity', 'Gi(3>- instruction cache size', 'Gw exclusivity', 'Gi(5f replacement policy', 'Gi(6>- write buffer size', 'Giof prefetch'} (08)

[0062] - for sub-parameter 'G2: cache data n°T of list L3, list L32 can be :

[0063] L32 = {' / ”32(U cache line size' , '^32(2): associativity', ' / 32(3): cache size for data', exclusivity', 'G2(5h replacement policy', 'Gw write buffer size', prefetch'} (09)

[0064] - for sub-parameter 'G3: cache instruction #2' of list L3, list L33 can be :

[0065] L33 = {'^(i): cache line size' , ' / "33(2); associativity', cache size for instructions', exclusivity', '^33(5): replacement policy', '^33(6): write buffer size', '^33<7): prefetch'} (10)

[0066] - for sub-parameter 'f35: the size of the level 3 cache' of the L3 list, the L35 list maybe :

[0067] L35 = {cache line size', '^35(2): associativity', '^35(3): #system_level_cache_slice' ', 'f35(4): exclusivity', ' / -35(5): SLC slice', latency, ' / 35(7): replacement policy', ' / 35(8): write buffer size', prefetch', SLC bandwidth'} (11)

[0068] A Lnk list (and in particular a previous L3k list) can thus include, according to the preceding enumerations (08), (09) and (10) and (11), the size of the cache line (or cache line size in English), the associativity (or associativity in English), the size of the cache for the data or the instructions (or cache size in English), the exclusivity (or clusivity in English), the replacement policy (or replacement in English), the size of the write buffer memory (or write buffer size in English), and / or the prefetching (or prefetcher in English), etc. It should be noted that the data replacement policy refers to one or more rules for defining data retention or abandonment.

[0069] A Lnk list (and in particular the preceding L35 list) may also comprise, according to the preceding enumeration (11), a cache slice at the system level (or #SLC slice in English), SLC slice parameters (or SLC slice in English), the latency (or latency in English), and / or the SLC bandwidth (or SLC bandwidth in English), etc. It should be noted that the sub-parameters or lists of values ​​associated with the latency or with sizes may for example be discrete values.

[0070] An objective and / or constraint function Fh of a set (or list) F is defined to evaluate one or more optimization criteria of the circuit associated with an integrated circuit configuration to be designed. The objective and / or constraint function Fh then corresponds to a mathematical formulation associated with one or more objectives and / or constraints of the integrated circuit to be designed.

[0071] It is noted that there are a plurality Q of circuit optimization criteria Cq. The value Q is an integer greater than or equal to 3. In embodiments, the optimization criteria may comprise the following three main optimization criteria:

[0072] - a first main optimization criterion of the circuit Ci corresponding to the per calculation formance of the integrated circuit which can be defined for example by a number of floating-point operations per second expressed in FLOPS (or Floating-point Operations Per Second according to the Anglo-Saxon expression), a temporal data of the circuit integrated such as latency (in seconds) or operating frequency (in Hz), or a measurement of memory size (in number of bits or bytes);

[0073] - a second main optimization criterion of the circuit C2 corresponding to the integrated circuit power consumption; and

[0074] - a third main optimization criterion of the circuit C3 corresponding to the surface of the integrated circuit.

[0075] Advantageously, other optimization criteria Cq of the circuit can be defined, such as the price of the circuit, the environmental footprint of the circuit, the manufacturing time of the circuit, the security level of the circuit, etc.

[0076] For example and without limitation, the set F of objective and / or constraint functions Fh may comprise a first objective function Fi associated with the first main optimization criterion Ci corresponding to the calculation performance of the integrated circuit. The first objective function Fi may then be a maximum argument function (or Argmax) of the calculation performance of the integrated circuit Ci, as defined according to the following equation (12):

[0077] Fi = Argmax (Ci) (12)

[0078] The list F may also comprise a second and a third objective function, F2 and F3, associated respectively with the second and third main optimization criterion of the circuit, C2 and C3, corresponding to the energy consumption of the integrated circuit and to the surface area of ​​the integrated circuit. The second objective function F2 and the third objective function F3 may then be a minimum argument function (or Argmin) of the energy consumption of the integrated circuit C2 and a minimum argument function of the surface area of ​​the integrated circuit C3, as defined according to the following equations (13) and (14):

[0079] F2 = Argmin (C2) (13)

[0080] F3 = Argmin (C3) (14)

[0081] As used herein, particularly in the preceding equations (12), (13) and (14), the maximum and minimum argument functions refer to the functions for determining the minimum and maximum possible value(s) of a variable represented by a data set.

[0082] In particular, it should be noted that an objective function of the list F is a function seeking to minimize or maximize a criterion expressed as an optimization objective of the circuit. A constraint function of the list F is a function seeking to respect a constraint of the integrated circuit to be designed. For example and without limitation, a constraint function Fh can then be an inequality function between several parameters of the list P and / or sub-parameters of a list Ln. If the constraint corresponds to cache size relationships for the data or the instructions of levels 1, 2 and 3, constraint functions Fh can be defined according to the following expression (15):

[0083] ^31(3) - ^32(3), and ^32(3) - ^33(3) (15)

[0084] Furthermore, the exploration space E can be adapted to be used by one or more optimization algorithms A.

[0085] As used herein, the expression “optimization algorithm” refers to an algorithm performing an operational search RO (also called “combinatorial optimization” or “decision support”) to analyze complex situations and in particular to develop one or more solutions to the problem of designing a hardware architecture to be optimized. An optimization algorithm may be any algorithm or mathematical model capable of determining different decision variables (i.e. parameters and sub-parameters) and different objective and / or constraint functions of an exploration space E related to the search for optimized solutions of an internal representation of an architecture design descriptor D.

[0086] For example and without limitation, the hardware architecture design problem defined by the architecture design descriptor D may be equivalent or close to a known combinatorial optimization problem so that the mathematical representation of the problem, i.e. the exploration space E, may be transcribed and enriched on this known problem (Linear Problem, Integer Linear Problem, graph, genome, etc.). In this case, an algorithm A known to be effective for solving this known combinatorial optimization problem may be applied (Simplex, separation and evaluation algorithm, shortest path search algorithm, genetic algorithm, etc.).Thus, depending on the identification of the design problem of a hardware architecture to be optimized, an optimization algorithm A can be adapted, and therefore the exploration space E (of architecture, micro-architecture or even system) induced can be generated automatically.

[0087] As shown in [Fig.l], the architecture determination method comprises a step 110 of receiving the descriptor D of the calculation architecture.

[0088] In step 120, the architecture exploration space E can be generated from the descriptor D of the calculation architecture.

[0089] As shown in [Fig.l], the method for designing integrated circuit hardware architectures comprises a plurality of iterations of optimization steps 130 to 150 associated with a multi-criteria hardware architecture design exploration.

[0090] In step 130, the operational search optimization algorithm A is applied to the architecture exploration space E, so as to generate, at each iteration 'i' of the design method, one or more candidate architecture configurations Gÿ of the integrated circuit. The index 'j' is associated with different configurations generated at an iteration i. The number of candidate architecture configurations generated may be different at each iteration i.

[0091] A candidate architecture configuration Gÿ comprises a subset of the elements P for which certain parameters or decision variables are fixed. A candidate architecture configuration Gÿ may also comprise subsets of the elements L for which certain sub-parameters are fixed. The candidate architecture configuration Gÿ then corresponds to a subset (i.e. an instance) of the architecture exploration space E. Each candidate architecture configuration Gÿ of the set of generated configurations is a unique architecture configuration, and is therefore different from each of the configurations generated during the same iteration i and during the previous iterations [1, i-1].

[0092] Advantageously, operational research can be applied hierarchically to the architecture exploration space E.

[0093] For example and without limitation, the first iteration(s) (generally designated by the index i) of the design method may be adapted so as to generate one or more candidate architecture configurations Gÿ associated with the optimization of the parameters Pn of the list P. Similarly, for one or more configurations Gÿ selected to optimize all of the parameters Pn of the list P, one or more subsequent iterations may be adapted so as to generate, for each parameter Pn, one or more candidate architecture configurations Gÿ associated with the optimization of one or more sub-parameters of the list Ln.And so on, for one or more configurations Gÿ selected to optimize the set of parameters Pn of the list P and the set of sub-parameters of a list Ln, one or more subsequent iterations can be adapted so as to generate, for each sub-parameter Znk, one or more candidate architecture configurations Gÿ associated with the optimization of one or more sub-parameters of the list Lnk.

[0094] The optimization algorithm A applied to the optimization step 130 of the method may be an optimization algorithm A selected from a set of optimization algorithms, which may for example be stored in an algorithm register RA

[0095] Advantageously, the optimization algorithm A can be selected in step 120 from among the algorithms of the set of algorithms stored in the register RA. The elements P, L and F of the architecture exploration space E can thus be generated from the architecture descriptor D and the selected optimization algorithm A. The architecture exploration space E can then be used in step 130 by the selected optimization algorithm A.

[0096] In particular, the optimization algorithm A may be selected from the objectives and / or constraints of the integrated circuit to be designed. For example and without limitation, a design objective may be the minimization of the latency of an integrated circuit. The integrated circuit may consist of several cores comprising a number X of routers. Each router is characterized by a spatial position on the circuit and can be connected to one or more routers by a connection. Such an objective of minimizing the latency of the circuit may correspond to the search for a topology of an optimized interconnection network between the routers in the circuit, that is, to the search for the shortest connection path from an input (a first router) and to an output (an Xth router) to distribute (or transmit) data as quickly as possible between routers through the circuit. In this case, the selected optimization algorithm A may advantageously be derived from graph theory. In particular, the optimization algorithm A may comprise the determination of a Graph comprising a certain number of points, such that each point corresponds to (or represents) the spatial position of a router in the integrated circuit.The optimization thus consists of determining the shortest path between each router two by two to obtain a minimized overall path between a first and an Xth router. Each path between two routers (i.e. an edge of the Graph) corresponds to (or represents) a possible connection between two routers of the integrated circuit.

[0097] In embodiments, the optimization algorithm A may be selected from one or more objective functions Fh. For example, an optimization criterion C4 may correspond to the latency of an integrated circuit, i.e., for example, to the measurement of the number of “hops” or connections (and / or the measurement of the connection time) between the different elements of the circuit. An objective function F4 may then be a minimum argument function of the latency of the integrated circuit, as defined according to the following equation (16):

[0098] F4 = Argmin (C4) (16)

[0099] In this case, the selected optimization algorithm A can be defined from the detection of a minimum argument function associated with the optimization criterion of the circuit C4.

[0100] The generation of candidate architecture configurations Gÿ in the first optimization step 130 is performed using a set of characteristic parameters associated with one or more architecture configuration evaluation tools Om given among M architecture configuration evaluation tools. The index 'm' associated with different evaluation tool parameters Om is thus an integer between 1 and M.

[0101] An evaluation tool Om can be any computer tool suitable for analyzing (or evaluating) an architecture configuration. An evaluation tool Om has predefined input quantities Vmg, corresponding to the elements to be supplied to this evaluation tool, and delivers as output one or more output quantities Rmg corresponding to evaluation results. For a given architecture configuration Gÿ that one wishes to evaluate by means of an evaluation tool Om, it is appropriate therefore to provide this tool with values ​​of the input quantities Vmg associated with a given architecture configuration Gÿ. The evaluation tool Om will output one or more values ​​of the output quantities Rmg corresponding to evaluation results after analysis of the given architecture configuration Gÿ.

[0102] A set of characteristic parameters associated with an evaluation tool Om may comprise, for example, the type of predefined input quantities Vmg and / or output quantities Rmg.

[0103] For example and without limitation, an Om evaluation tool can be a functional instruction set simulator, a memory hierarchy simulator, an architecture simulator at the RTL level (from the English Register Transfer Level), such as: VPSim, GEM5, Virtualizer or Vista, ModelSim or Questa, the Open source computing tool DRAMSys or even DRAMPower, etc.

[0104] An Om evaluation tool can also be an architecture compilation tool such as the Synopsys “Design Compiler” tool, or a memory and input / output oriented evaluation tool such as the Open source computing tool CACTI.

[0105] In the example of an Om evaluation tool of the VPSim simulator type, possible input quantities Vmg of the VPSim simulator may be parameters related to the hardware architecture of the integrated circuit, such as the 'number of cores' or the 'type of cores'. In the example of an Om evaluation tool of the GEM5 simulator type, possible input quantities Vmg of the GEM5 simulator may be parameters related to the micro-architecture of the integrated circuit, such as sub-parameters associated with the micro-architecture of the cores such as the sub-parameters 'data prefetching', 'size and number of registers', etc.

[0106] An example of output quantity Rmg can be an estimate of the calculation performance of the integrated circuit, or even evaluations of access to interconnections or memory, for example in number, time or energy consumption.

[0107] In the example of an evaluation tool Om of the VPSim simulator type, an output quantity Rmg of the VPSim simulator can be the execution time of an application on a Gÿ architecture configuration or more generally another metric linked to the architecture such as the number of cache accesses (or cache hits in English), or the number of cache faults (or cache misses in English) for example.

[0108] In embodiments, an evaluation tool Om may also be associated with one or more operating quantities tm. An operating quantity tm may for example be associated with the analysis time (or exploration time limit) of an architecture configuration Gÿ by the evaluation tool Om. The definition of the operating quantities tm may impact the value of the output quantities Rmg of the evaluation tool. The set of characteristic parameters associated with a tool Om evaluation can also include, for example, operating quantities tm.

[0109] In embodiments, several evaluation tools Om may be provided to evaluate the same output quantity Rmg, but deliver after simulation / evaluation different values ​​of these output quantities Rmg and each output quantity Rmg may further be associated with distinct operating quantities tm. For example, a VPSim simulator and a GEM5 simulator may each deliver an estimate of the computational performance of the integrated circuit. For the GEM5 simulator, the performance estimate may be obtained according to a very high analysis time, thus slowing down the overall exploration of a Gÿ architecture configuration. For an Om evaluation tool of the VPSim simulator type, the performance estimate may be obtained according to a very short analysis time, thus accelerating the overall exploration of a Gÿ architecture configuration.A performance estimate delivered by the VPSim simulator can be described as less precise (or more approximate) compared to an estimate delivered by the GEM5 simulator, which is then described as more detailed. Other Rmg output quantities can be derived from a VPSim simulator and / or a GEM5 simulator, such as the number of accesses to certain resources, the type of access, etc.

[0110] The Om evaluation tools may be pre-selected from a set of available tools based on tool selection conditions.

[0111] An architecture configuration Gÿ may be represented by a data structure, such as a matrix, comprising parameters selected and / or determined and / or calculated from the architecture exploration space E. The remainder of the description will be made with reference to an architecture configuration data structure Gÿ of parameter matrix type as a non-limiting example.

[0112] According to certain embodiments, the parameter matrix of an architecture configuration Gÿ can be determined in step 130 by taking into account one or more selected evaluation tools Om. In particular, the parameter matrix of an architecture configuration Gÿ can be determined by taking into account at least a portion of the possible input quantities Vmg of the selected evaluation tool(s) Om.

[0113] For example and without limitation, assuming that the selected evaluation tools include a first evaluation tool Oi (e.g., the VPSim simulator) and a second evaluation tool O2 (e.g., the GEM5 simulator), an architecture configuration Gÿ may be generated so as to include elements associated with possible input quantities Vig of the first evaluation tool Oi (VPSim simulator) and possible input quantities V2g of the second evaluation tool O2 (GEM5 simulator). In other words, if an evaluation tool does not allow to evaluate differences between several values ​​of a given parameter (or sub-parameter) of the exploration space E, then this parameter is not considered in the operation of generating an architecture configuration Gÿ to be evaluated. Thus, the operation of generating an architecture configuration Gÿ to be explored considers a subset of the exploration space E to choose a new configuration to simulate / evaluate taking into account the evaluation tool(s) used (or selected / chosen).

[0114] In embodiments, execution links between a first selected evaluation tool Om and a second selected or available evaluation tool O(m+i) may be determined prior to step 130. For example and without limitation, the execution of a given selected evaluation tool O3 may depend on certain values ​​of input quantities V3g not available in an architecture configuration Gÿ to be determined. On the other hand, these values ​​of input quantities V3g of the selected evaluation tool O3 may correspond or be associated with values ​​of output quantities R4g accessible via the execution of another available evaluation tool O4.In such an embodiment, in addition to selecting the assessment tool O3, the other assessment tool O4 may also be selected from the set of available assessment tools Om, in response to determining this execution link between the assessment tool O3 and the other assessment tool O4.

[0115] In such an embodiment, the parameter matrix of an architecture configuration Gÿ can then comprise elements associated with possible input quantities V4g of the evaluation tool O4.

[0116] In step 140, the candidate architecture configurations Gÿ determined in step 130 are evaluated by a plurality of chosen evaluation tools Om.

[0117] For each architecture configuration Gÿ to be evaluated, step 140 thus comprises the selection of elements included in the architecture configuration Gÿ required for the determination of the values ​​of the input quantities Vmg of an evaluation tool Om of the chosen plurality of tools for the evaluation of the candidate configurations Gÿ.

[0118] Furthermore, in step 140, at least two evaluation tools of the selected plurality of tools may be executed in parallel.

[0119] In embodiments, the evaluation tools Om used in step 140 may be the evaluation tools Om selected in step 130 and considered for the generation of the parameter matrix of an architecture configuration G.

[0120] In embodiments, the method may comprise, before the execution of the evaluation tools in step 140, a prior step of transformation (or transcription, translation) of at least part of the candidate architecture configurations Gÿ into input files that are understandable (i.e. readable or decipherable) by the evaluation tools Om. In particular, an input file of an evaluation tool Om may be generated from the transcription of the selection of elements of a confi candidate architecture guration Gÿ in values ​​of the input quantities Vmg of an evaluation tool Om.

[0121] In embodiments, the prior configuration transformation step may be performed from a first translation register Rn associated with one or more evaluation tools Om. The first translation register RT may comprise transcription elements such as python scripts for example. The transcription elements associated with the evaluation tools Om selected to be executed are then applied to a candidate architecture configuration Gÿ to generate input files of the evaluation tools Om. The selection of the transcription elements associated with the evaluation tools Om may be performed based on the determination of the candidate architecture configurations Gÿ in step 130 and / or the selection of the evaluation tools Om in step 140.For an evaluation tool like VPSim simulator for example, the input files can be determined from a python script generating a hardware platform suitable for the VPSim simulator (e.g. in terms of number of cores, type, memory parameters, NoC parameters, etc.).

[0122] Step 140, the execution of the evaluation tools thus provides evaluation result values ​​of each candidate architecture configuration Gÿ.

[0123] Advantageously, the method may comprise, after step 140 of evaluating the candidate configurations by the plurality of evaluation tools Om chosen, a step of receiving all of the values ​​of output quantities Rmg. The set of values ​​of output quantities Rmg thus corresponds to the evaluation results, after analysis, of each architecture configuration G.

[0124] In embodiments where at least some of the values ​​of input quantities Vmg of the evaluation tools Om chosen in step 130 depend on one or more possible output quantities Rmg of the evaluation tools Om, step 140 may comprise, for each candidate configuration:

[0125] - the evaluation of the candidate configuration Gÿ by a first part of the plurality of Om assessment tools chosen,

[0126] - the reception of the set of values ​​of output quantities Rmgcorresponding to the evaluation results after analysis of the architecture configuration Gÿ by first part of the plurality of evaluation tools Om chosen, then

[0127] - the evaluation of the candidate configuration Gÿ by a second part of the plurality of selected Om assessment tools, the second part of the plurality of Om assessment tools having a dependency link with the first part of the plurality of selected Om assessment tools.

[0128] In embodiments, the method for determining hardware architecture may comprise a step of transforming (or transcribing, translating) the evaluation results of the candidate architecture configurations G, obtained in step 140, into input files of the evaluation tools Om and / or into a mathematical representation usable for the implementation of operational research. The step of transforming the evaluation results can be carried out from the first translation register Rn. For example and without limitation, transcription elements associated with the evaluation tools Om can be selected from the elements of the register Rn, and applied to at least part of the evaluation results of evaluation tools Om.

[0129] Applying a transcription element to at least part of the evaluation results may, for example, generate one or more input files for other Om evaluation tools to be executed.

[0130] The application of a transcription element to at least part of the evaluation results can also make it possible to generate, for example, one or more matrices associated with a mathematical representation that can be used in the context of operational research 130. For example, the transformation of the evaluation results into a mathematical representation can correspond to their transformation into a format (for example integer, binary, etc.) that can be used via the execution of an optimization algorithm A.

[0131] The selection of the elements associated with the evaluation tools Om can be carried out at the stage of transforming the evaluation results according to the determination of the candidate architecture configurations Gÿ and / or the choice of the evaluation tools Om.

[0132] In step 150, two or more circuit optimization criterion values ​​Cq are determined from evaluation results of the candidate configurations Gÿ obtained in step 140.

[0133] Two optimization criteria of the set of optimization criteria of the circuit to be determined in step 150 can be chosen from among antagonistic optimization criteria characterizing the integrated circuit to be designed, that is to say chosen from among at least one main optimization criterion of calculation performance, one main optimization criterion of energy consumption and one main optimization criterion of surface area of ​​an integrated circuit.

[0134] For example and without limitation, an optimization criterion of the circuit Cq may be the computational performance Ci (in terms of computational execution time) associated with a candidate architecture configuration Gÿ. The value of the computational performance Ci may be calculated from the performance estimate determined by a first evaluation tool (for example the VPSim simulator) or by a second evaluation tool (for example the GEM5 simulator).

[0135] Furthermore, in step 150, at least one value of a circuit optimization criterion Cq defined among the set of circuit optimization criteria to be determined is calculated. by means of one or more analytical formulas (or analytical functions) noted 7, An analytical formula 7, used in the calculation of the value of a circuit optimization criterion Cq, takes as input parameters at least one piece of circuit information (generically noted Ic) and at least one piece of technological information (generically noted It).

[0136] An optimization criterion Cq of the circuit to be calculated from an analytical function can be the calculation performance Ci, the energy consumption C2 (static and / or dynamic) of an integrated circuit to be designed and / or the surface area of ​​this circuit C3 associated with a candidate architecture configuration Gÿ.

[0137] Circuit information may be information related to the structure of the integrated circuit to be designed and / or information related to the operating activity of the integrated circuit to be designed. For example and without limitation, information related to the structure may correspond to a number or type of constituent elements of an integrated circuit, such as a number or type of cores in the circuit. Information related to the operating activity may correspond to a number or type of memory accesses, a number or type of access to a constituent element of the integrated circuit, a number or type of solicitation of a constituent element of the integrated circuit or a chain of constituent elements of the integrated circuit, a number or type of operations performed by the integrated circuit, etc. The type of information related to the operating activity available may depend on the design level of the integrated circuit.For example, the calculation latency of a constituent element of the circuit can be information linked to the operating activity and makes it possible to calculate a more global latency or a quantity linked to energy consumption by an analytical formulation.

[0138] Circuit information can be determined from one or more evaluation results obtained in step 140, i.e. from one or more values ​​of output quantities Rmg from at least one of the evaluation tools Om.

[0139] Technological information is determined from one or more technological databases. A technological database includes data for circuit building blocks that can be manufactured according to a given integrated circuit design technology. For example and without limitation, technological information may correspond to performance, consumption or area information of a building block of an integrated circuit. An element of an integrated circuit may be any “circuit brick” used to design the functionalities of the integrated circuit. Examples of elements of an integrated circuit are, for example, logic gates, memories, processors, circuits dedicated to a specific functionality such as imagers, displays, signal transmission / reception circuits, coprocessors, routers, computers, control circuits, test circuits, power management circuits, etc. These circuit elements can correspond to elementary bricks, for example an OR logic gate, or on the contrary to higher level bricks such as a processor, a memory or a logic circuit that can be made from elementary bricks.

[0140] For each of these circuit elements, information relating to their performance, their consumption, their surface area, and / or other information associated with these elements, such as their cost, their environmental impact, etc., can be extracted from one or more technological databases.

[0141] The surface of a circuit element may thus correspond to a surface dimension in 2D, in top view (conventionally defined from a view called "layout" in English and visible from a GDS II type file). The energy consumption information of an element is generally of two types. The first type corresponds to dynamic energy consumption information linked to an activity of the element, that is to say to the energy consumption linked to the loading of state of the elements (for example to a memory access, to the creation of an image by an imager, to the performance of a calculation by a coprocessor, etc.). The second type corresponds to static energy consumption information of an element, that is to say any energy consumption information which is not relative to the dynamic energy consumption (such as for example the permanent energy consumption independent of the activity).It should be noted, however, that the static energy consumption may be dependent on the activity of the element depending on the consideration of certain consumption management techniques such as the DVFS technique, or the management of "body bias" on FDSOI. The performance information may correspond to information linked to a temporal notion, such as for example a propagation time through a circuit element for the performance of a task, an operating frequency of a circuit element, a latency time of a processing chain including at least one circuit element, etc.

[0142] Such technological databases may be constructed and / or determined and / or obtained from suppliers (or supplier catalogs) and / or from integrated circuit manufacturers. These databases may also be constructed, for example, prior to or during the design process, using simulation / evaluation / synthesis tools from lower-level supplier and / or manufacturer data, for example from design kits provided by the manufacturers. To construct these technological databases for obtaining technological information, an architectural model resulting from pre-execution of a computer tool may be used. Such a tool This information technology database can be, for example, an architecture compilation tool such as the Synopsys "Design Compiler" tool, surface (or size) models of available constituent elements, or even high-level simulations pre-performed using dedicated simulators such as, for example, a consumption evaluation tool such as the Open source CACTI IT tool associated with information on cache memories or the Synopsys "PrimePower" IT tool. In addition, during the design process, these technological databases can be enriched by at least part of the circuit information determined and / or refined at each iteration i.

[0143] Furthermore, a technological database can be adapted to search and retrieve (via the application of queries for example) one or more technological information from one or more values ​​of output quantities Rmg from at least one of the evaluation tools Om executed, and / or from elements of the associated candidate configuration Gÿ.

[0144] In embodiments, the step of determining the optimization criterion value of the circuit Cq may be performed using a function register R^r. The function register Ry is associated with the analytical formulas to be applied to the circuit and technological information to calculate an optimization criterion value of the circuit Cq.

[0145] In particular, an analytical function may be any function enabling the processing of circuit and technological information. For example, an analytical function may comprise a sum of parameters, a division, a subtraction, and / or a multiplication, etc.

[0146] For example and without limitation, for determining a value of the third main optimization criterion C3 of the circuit, corresponding to the surface area of ​​the integrated circuit, an analytical function ? may be a sum taking as arguments the sum of the surfaces of the elements of the circuit. For determining a value of the second main optimization criterion C2 of the circuit, corresponding to the energy consumption of a calculation element of the integrated circuit, an analytical function may be a multiplication taking as arguments the number of activations of each operation and their average energy consumption.

[0147] It should be noted that a value of a circuit optimization criterion Cq defined among the set of circuit optimization criteria to be determined can be obtained directly from values ​​of output quantities Rmg after analysis of an architecture configuration Gÿ by a chosen evaluation tool Om. The evaluation tool Om can then use technological databases for its internal operation. In this case, the value of the circuit optimization criterion Cq is not obtained by an analytical function 7 executed after analysis by the evaluation tool.

[0148] For example and without limitation, the value of the calculation performance Ci or the energy consumption C2 can be calculated from the combination of results obtained by evaluation tool (for example VPSim simulator and / or GEM5 simulator) with information obtained via the exploitation of technological databases. In particular, such an evaluation tool delivering a so-called functional result such as a number of operations, accesses, cycles, can be configured from a technological database, for example to generate maximum frequencies achievable by components of the circuit.

[0149] In step 150, the selection in the function register R2 of the analytical formula(s) to be applied is carried out from the optimization criterion of the circuit Cq to be determined.

[0150] In embodiments, the selection of the analytical formula(s) to be applied may further be performed from the circuit information Ic available after the evaluation of the candidate architecture configurations Gÿ..

[0151] The value of at least one optimization criterion of the circuit Cq can be determined from a selected analytical function taking as arguments:

[0152] - one or more circuit information L obtained from at least one result of an evaluation tool (and possibly information from the candidate architecture configuration Gÿ), and

[0153] - one or more technological information It obtained from at least one technology database.

[0154] Thus, the value of an optimization criterion of the circuit Cq can be defined according to the following equation (17):

[0155] Cq = (Ic, It) (17)

[0156] For example and without limitation, the evaluation of a candidate architecture configuration Gÿ by a first evaluation tool Oi can generate output quantity values ​​Rig. Circuit information Ici can then be derived from the output quantity values ​​Rig. The value of a circuit optimization criterion Cq can thus be determined from a selected analytical function 7 taking as arguments the circuit information Ici and technological information Iü according to the following equation (18):

[0157] Cq = ^(Icl,Itl)(18)

[0158] The evaluation of a candidate configuration Gÿ by a second evaluation tool O2 can generate output quantity values ​​R2g. Circuit information L2 can then be derived from the output quantity values ​​R2g. The value of a circuit optimization criterion Cq can thus be determined from the selected analytical function taking as arguments the circuit information Li, the technological information Itb and the circuit information IC2 according to the following equation (19):

[0159] Cq = (IcI, ItI, Ic2) (19)

[0160] In embodiments, the value of a circuit optimization criterion Cq may be determined from output quantity values ​​Rmg resulting from the combined execution of two or more evaluation tools Om. For example and without limitation, the evaluation of a candidate configuration Gÿ by an evaluation tool O4 may provide the output quantity values ​​Rg4, themselves used for the evaluation of the candidate configuration Gÿ by an evaluation tool O3 providing as output the output quantity values ​​Rg3. Circuit information Ic3 may then be derived from the output quantity values ​​Rg3. Technological information It3 may also be derived from the output quantity values ​​Rg3 and / or Rg4, and / or from the elements of the candidate architecture configuration Gÿ.The value of a circuit optimization criterion Cq can thus be determined from a selected analytical function 7 taking as arguments the circuit information Ic3 and the technological information It3, according to the following equation (20): .

[0161] Cq = (Ic3, It3) (20)

[0162] It should be noted that the different embodiments for determining the value of an optimization criterion of the circuit Cq can be implemented separately or be combined.

[0163] The value of the first main optimization criterion for the calculation performance Ci of the circuit (for example the overall latency of a processing chain) can be for example calculated by applying a selected analytical function 7 taking as arguments a plurality of latency information obtained via the execution of simulators (for example VPSim and / or GEM5) and the exploitation of the technological database.

[0164] The value of the second main optimization criterion C2 of energy consumption of the circuit can be calculated for example by applying a selected analytical function taking as arguments a list of elements of the integrated circuit and the associated energy consumptions of these different elements accessible from an existing database or, if they are not accessible from an existing database, by generating / feeding such a database from results of consumption simulations making it possible to obtain this technological information.It is generally possible to have an analytical function 7 which takes as argument the number of accesses to the interconnection between the constituent elements of the circuit or one of these parts or the number of memory accesses (obtained via for example the VPSim simulator), with the energy consumption per access obtained via the exploitation of the technological database (base constructed for example with the CACTI tool).

[0165] The value of the third main optimization criterion C3 of circuit surface can be calculated for example by applying a selected analytical function. Such an analytical function takes as arguments parameters from the architecture configuration to be evaluated (for example, the number and configuration of processor cores, cache memories), as well as results from evaluation tools (for example, the surface area of ​​a cache memory obtained for example via the CACTI tool), and results obtained via the exploitation of technological databases (for example, a base determined from a model to obtain the size of microprocessors, often expressed in mm2). It should be noted that the CACTI tool itself relies on technological databases. Such an analytical function 7 can also take as arguments results from a summary report (for example from the “Design Compiler” tool for a low-level description of the architecture).

[0166] Thus, the value of the third main optimization criterion C3 of the circuit surface can be calculated, for example, by applying an analytical function ? defined according to the following expression:

[0167] -T = ('Number of cores' x 'area of ​​a core') + ('number of cache memories' x 'area of ​​a cache memory') + 'area of ​​the remainder'.

[0168] In the preceding expression, the arguments associated with the term "numbers of" refer to parameters originating from the architecture configuration to be evaluated obtained by the application of algorithm A. Also in the preceding expression, the argument "surface of the remainder" refers to the result of the addition of the surfaces of the elementary components of the integrated circuit other than the cores or cache memories (i.e. the interconnections, the peripherals, etc.).

[0169] In embodiments, the evaluation results generated by the plurality of evaluation tools Om and / or the circuit optimization criteria values ​​Cq associated with each candidate architecture configuration Gÿ may be stored in a candidate configuration data store. For example and without limitation, if in a current iteration of the optimization steps of the method, it is determined that a candidate architecture configuration Gÿ is identical to an architecture configuration Gÿ previously determined in a previous iteration, the optimization step 140 of the method may be implemented using the data stored in the candidate configuration data store, in relation to the architecture configuration Gÿ previously determined in the previous iteration (and in particular circuit optimization criteria values ​​Cq previously calculated in association with the configuration).

[0170] In step 160, it is determined whether a stopping criterion for the plurality of iterations of optimization steps is satisfied.

[0171] In embodiments, the stopping criterion may relate to the evaluation of a or several objective functions Fh defined in the architecture exploration space E with respect to the determined circuit optimization criteria values ​​Cq.

[0172] In embodiments, the stopping criterion may be defined based on a predefined execution time of the plurality of iterations of optimization steps and / or a number of iterations executed. For example, it may be determined that the stopping criterion is satisfied if the predefined execution time has expired.

[0173] If it is determined that the stopping criterion is not satisfied in step 160, a further iteration of optimization steps 130 to 150 is implemented.

[0174] If it is determined that the stopping criterion is satisfied in step 160, the iterations of optimization steps 130 to 150 are stopped and step 170 is executed.

[0175] In step 170, one or more optimized computational architecture configurations G opt are generated. An optimized configuration Gopt is generated in step 170, from the candidate architecture configurations Gÿ determined in step 130 of at least one of the executed iterations i of the optimization steps of the method and the values ​​of optimization criteria of the circuit Cq determined in step 150 of the last iteration of the optimization steps 130 to 150.

[0176] Advantageously, in the first iteration of the optimization steps 130 to 150, a candidate architecture configuration Gÿ determined in the optimization step 130 may be an architecture configuration G; called 'initialization architecture configuration'. In the second iteration of the optimization steps 130 to 150, in step 130, the optimization algorithm A is applied so as to generate one or more candidate architecture configurations Gÿ from the architecture exploration space E, the initialization architecture configuration G; and the determined circuit optimization criterion values ​​Cq (i.e. for example as a function of the evaluation results of the initial architecture configuration generated by the plurality of evaluation tools Om).In subsequent iterations of optimization steps 130 to 150, at the first optimization step 130, the optimization algorithm A is applied to generate one or more candidate architecture configurations Gÿ from the architecture exploration space E, architecture configurations Gÿ generated at a previous iteration of optimization steps 130 to 150 (e.g., the initialization architecture configuration G;) and the determined circuit optimization criteria values ​​Cq.

[0177] For example and without limitation, step 130 of a current iteration of the optimization steps may comprise operations of modifications of the elements of the parameter matrix (for example 'number of cores', sub-parameters of the NoC, etc.) of the initialization architecture configuration G; and / or of the architecture configuration Gÿ of the previous iteration. These modification operations may be applied in a variable and / or predefined neighborhood of the elements of the parameter matrix parameters. These modification operations can be determined from the evaluation of one or more optimization criteria Ch defined in the architecture exploration space E with respect to the determined values ​​of circuit optimization criteria Cq. In addition, since the design exploration of hardware architectures is generally a multi-criteria exploration, the modification operations can be determined using a comparison between different evaluations of optimization criteria Ch, which allows for a dynamic generation of Pareto front (also called Pareto optimum) generally used in the field of operations research.

[0178] In an exemplary embodiment, a circuit optimization criterion may be the computational performance Ci and an objective function may be the maximum argument function of the computational performance of the integrated circuit Fi = Argmax (Ci). In one embodiment, the optimization step 130 may comprise comparing the value of the circuit optimization criterion Ci over a number of successive iterations associated with modified architecture configurations Gÿ, so as to evaluate whether the computational performance increases and therefore whether the objective function Fi associated with the maximum argument function of the computational performance is verified.

[0179] In embodiments, the method for designing integrated circuit hardware architectures according to the embodiments may comprise a step of sorting and / or ranking candidate architecture configurations Gÿ (determined in one or more iterations of the optimization steps 130 to 150). The sorting step may be performed (or executed) based on the determined circuit optimization criterion value(s) Cq and / or the evaluation of one or more objective functions and / or constraints Fh defined in the architecture exploration space E with respect to the determined circuit optimization criterion values ​​Cq.

[0180] Furthermore, the sorting step can be performed so as to keep the so-called 'dominant' architecture configurations Gÿ. A dominant architecture configuration Gd refers to an architecture configuration defined with respect to at least one ancillary architecture configuration Ga. The dominant architecture configurations G d and the ancillary architecture configurations Ga are evaluated during the same optimization iteration or two different optimization iterations. A dominant architecture configuration Gd has configuration evaluation results inducing a better evaluation on the set of objective and / or constraint functions Fh compared to the evaluation on the set of objective and / or constraint functions Fh induced by the configuration evaluation results from an ancillary architecture configuration Ga.

[0181] The ranking step can be performed so as to order the architecture configurations Gÿ according to the evaluation of one or more objective functions and / or constraints Fh defined in the architecture exploration space E with respect to the values ​​of circuit optimization criteria Cq determined associated with these configurations.

[0182] [Fig.2] represents an example of system 1 for designing the hardware architecture of an integrated circuit in which the method for designing integrated circuit hardware architectures can be implemented.

[0183] The system 1 for designing the hardware architecture of an integrated circuit comprises a device 20 for determining the hardware architecture and a memory 40. The device 20 may comprise an initialization module 202 configured to generate an architecture exploration space E, for example from the architecture descriptor D, and an optimization module 204 configured to implement the method for designing integrated circuit hardware architectures.

[0184] In embodiments, the memory 40 may comprise the algorithm register RA associated with the optimization algorithms used to select an algorithm A in step 130.

[0185] As shown in [Fig.2], the system 1 may comprise an assembly 60 of available Om evaluation tools. The optimization module 204 may be configured to select one or more Om evaluation tools from the set of available Om evaluation tools to generate the architecture configuration parameter matrix Gÿ in step 140.

[0186] In embodiments, the optimization module 204 may also be configured to determine execution links between a selected Om assessment tool and another selected or available Om assessment tool.

[0187] In embodiments, the memory 40 may also include the first translation register Rn associated with one or more evaluation tools Om which may be used by the optimization module 204 to select the transcription elements associated with the evaluation tools Om at step 140.

[0188] In embodiments, the optimization module 204 may also comprise a combination unit 2042 configured to calculate optimization criteria values ​​of the circuit Cq in step 150.

[0189] According to some embodiments, the memory 40 may also include the set of technological databases 402 and the RF function register used by the combining unit 2042 to calculate values ​​of optimization criteria of the circuit Cq in step 150.

[0190] In particular, a technological database may comprise a plurality of databases of different natures. Such databases may comprise textual or digital data. Such databases may be so-called design databases usable by different tools of design of a digital circuit and presenting different formats associated with these tools. Such databases can also include, for different circuit bricks (memory, processor, logic gates, logic functions) associated with a design database, TLM (or Transaction Level Model) type files, RTL files, layout files providing mask representations for manufacturing according to a given technology, a process design kit (or PDK for Process Design Kit in English) including files providing propagation time delays, files providing a physical behavior model, etc. Such files can be in “.db” format or “.lib” format for example.

[0191] The memory 40 may further comprise the candidate configuration data memory configured to record the evaluation results generated by the plurality of evaluation tools Om executed and / or the circuit optimization criteria values ​​Cq associated with each candidate architecture configuration G.

[0192] The use of a candidate configuration data memory makes it possible to accelerate the exploration of the different established Gÿ architecture configurations (to be evaluated) to generate an optimized integrated circuit.

[0193] In embodiments, the system 1 may comprise one or more data input / output interfaces, such as human-machine interfaces 80 (HMIs). These human-machine interfaces may comprise one or more information acquisition means or transmission means, such as input and control devices (e.g. microphone, speaker, keyboard) and / or one or more display devices (e.g. video screen, touch screen, etc.). For example and without limitation, the system 1 may comprise a human-machine interface 80 configured to acquire an architecture descriptor D provided by a user of the system 1 in the form of a computational architecture model Çtemplate').

[0194] In embodiments, the memory 40 may comprise a second translation register RT2 associated with one or more computational architecture models (templates) and the initialization module 202 may be configured to select a computational architecture model from the templates in the register RT2. The selection of the computational architecture template may be performed as a function of the architecture descriptor D. The initialization module 202 may thus be configured to generate the elements P, L and F of the architecture exploration space E from the architecture descriptor D and the selected template of the second translation register RT2.

[0195] In embodiments, the system 1 may comprise a transformation tool 80' configured to transform the optimized Gopt configuration into a hardware architecture description file (also called 'hardware description file') at the RTL level defining the behavior of a circuit and directly convertible into combinational logic gates and sequential elements (flip-flops, etc.). A description of a hardware architecture at the RTL level, called low level, can for example be defined in a hardware description language HDL (Hardware Description Language) such as Verilog or VHDL.

[0196] In embodiments, the initialization module 202 may be configured to receive one or more optimized configurations Gopt and generate an architecture exploration space E from the one or more optimized configurations Gopt similarly to generating the architecture exploration space E from the architecture descriptor D.

[0197] In embodiments, the memory 40 may comprise a data register RD associated with parameters to be optimized of the integrated circuit to be designed and the initialization module 202 may thus be configured to generate the elements P, L and F of the architecture exploration space E from the architecture descriptor D or optimized configurations Gopt, and from some or all of the parameters of the data register RD.

[0198] The exploitation of pre-generated Gopt optimized configurations by series of iterations of optimization steps by implementing the hardware architecture determination method, according to the embodiments of the invention, allows multi-level management of the design of integrated circuit hardware architectures. In this case, the assembly 60 of the design system 1 may comprise evaluation tools that can be used according to different levels of description of architecture configurations or one or more constituent elements of an architecture configuration. In such an embodiment, the set of translation registers, data and optimization algorithms can be adapted to the evaluation tools and to each of the different levels of description of architecture configurations that can be used by the evaluation tools.In the same way, the set of technological databases 402 can comprise databases adapted to the different levels of description of architectural configurations. Advantageously, certain evaluation tools and certain technological databases can be respectively exploitable and used on a multitude of levels of design of hardware architectures.

[0199] Those skilled in the art will understand that the invention may be computer-implemented, particularly as a computer program comprising instructions for its execution. The computer program may be recorded on a processor-readable recording medium. Reference to a computer program that, when executed, performs any of the functions described above, is not limited to an application program running on a single host computer. Rather, the terms computer program and software are used herein in a general sense to refer to any type of computer code (e.g., application software, firmware, microcode, or any other form of computer instruction) that can be used to program one or more processors to implement aspects of the techniques described herein. The computing means or resources may in particular be distributed ("Cloud computing"), possibly using peer-to-peer technologies.

[0200] The software code may be executed on any suitable processor (e.g., a microprocessor) or processor core or a set of processors, whether provided in a single computing device or distributed among several computing devices (e.g., as may be accessible in the device environment). The executable code of each program enabling the programmable device to implement the processes according to the invention may be stored, for example, in the hard disk or in read-only memory. Generally, the program(s) may be loaded into one of the storage means of the device before being executed. The central unit may control and direct the execution of the instructions or portions of software code of the program(s) according to the invention, instructions which are stored in the hard disk or in read-only memory or in the other aforementioned storage elements.

[0201] The method for determining hardware architectures can be implemented on a distributed computing unit comprising a plurality of physical cores. The embodiments of the invention are particularly suitable for such a distributed implementation as well as for porting to multi-core hardware technologies. The method for determining hardware architectures according to the embodiments of the invention can be implemented in computer code (which may in particular consist of a hardware abstraction language) in different languages, such as C++, Python, Chisel, pyMTL, spinal-HDL, etc.

[0202] The invention is not limited to the embodiments and examples described above as a non-limiting example. The invention encompasses all the variant embodiments which may be envisaged by those skilled in the art.

Claims

1. Claims A computer-implemented method for determining a hardware architecture of an integrated circuit, characterized in that the method comprises at least a plurality of iterations of the following steps: - applying (130) an optimization algorithm A to an architecture exploration space E, so as to determine at least one candidate architecture configuration G, said candidate architecture configuration G belonging to said architecture exploration space E, said architecture exploration space E comprising a set of objective functions F evaluating optimization criteria Cq associated with said candidate architecture configuration G; - applying said candidate architecture configuration G (140) to a plurality of evaluation tools Om, which provides evaluation results of the candidate architecture configurations G, an evaluation tool being a computer tool adapted to analyze an architecture configuration in response to values of input quantities associated with the architecture configuration; - determining (150) a value of at least two optimization criteria Cq of said optimization criteria Cq, said at least two so-called main optimization criteria being chosen from the calculation performance, the energy consumption and / or the surface area of said integrated circuit to be designed, the value of one of said main optimization criteria being determined by applying an analytical function taking as arguments at least one piece of circuit information and at least one piece of technological information, a piece of circuit information being information related to the structure of the integrated circuit and / or information related to the operating activity of the integrated circuit, and a piece of technological information being determined from one or more technological databases, said at least one piece of circuit information being determined from the evaluation results provided by at least one evaluation tool Om among said evaluation tools Om,said at least one technological information being derived from at least, a technological database; and - determining whether (160) a stopping criterion is verified; and in that, at each iteration, the determination of said candidate architecture configuration G is optimized from the evaluation of the objective functions F relating to said determined values of said at least two main optimization criteria Cq; the method further comprising a stopping of said iterations in response to the verification of said stopping criterion and a generation of at least one optimized calculation architecture configuration Gopt from said at least one architecture configuration G, said method being applicable at different levels in the architecture of the integrated circuit.

2. Method according to claim 1, wherein said stopping criterion is defined as a function of an evaluation of at least one objective function Fh relating to a main optimization criterion Cq, from the determined value of said main optimization criterion.

3. The method of claim 1, wherein said stopping criterion is defined based on a predefined time of execution of said plurality of iterations of optimization steps.

4. Method according to one of claims 1 to 3, in which each evaluation tool Om is configured to generate a set of evaluation results Rmg associated with said at least one architecture configuration G, and in which the method further comprises a step of applying said candidate architecture configuration G (140) to a first evaluation tool Om among said evaluation tools Om, from at least one evaluation result Rmg resulting from a prior step of applying said candidate architecture configuration G (140) to a second evaluation tool Om among said evaluation tools Om.

5. Method according to one of claims 1 to 4, wherein the generation of said at least one architecture configuration G is carried out as a function of said plurality of usable evaluation tools Om.

6. Method according to one of claims 1 to 5, in which the method further comprises a prior step of receiving (110) an architecture descriptor D and a step of generating (120) said architecture exploration space E from said architecture descriptor D and said optimization algorithm A.

7. Method according to one of claims 1 to 6, wherein an evaluation tool Om of said plurality of evaluation tools Om is an evaluation tool chosen from an architecture configuration simulator, an architecture compilation tool, a consumption evaluation tool, a tool based on exploitation of a database and a tool based on exploitation of a candidate configuration data memory, said candidate configuration data memory being used to save evaluation results from the step (140) of applying candidate architecture configurations G and / or the step (150) of determining the value of optimization criteria Cq of candidate architecture configurations G.

8. Method according to one of the preceding claims, wherein said plurality of evaluation tools comprises evaluation tools operable according to different levels of description of architectural configurations or of one or more constituent elements of an architectural configuration.

9. Integrated circuit hardware architecture obtained by implementing the method according to one of claims 1 to 8.

10. A method of designing an integrated circuit comprising an implementation of an integrated circuit from the integrated circuit hardware architecture of claim 9.

11. A computer program product comprising programming code instructions capable of being implemented by a computer, the computer being capable of implementing the method according to any one of claims 1 to 8.

Images