Memory circuit

Abstract

Memory Circuit This description relates to a memory circuit comprising a plurality of elementary cells, each having a resistive element of variable resistance, said element comprising first and second electrodes separated by a layer of a ferroelectric material, and a control circuit configured to perform read (303-1, 303-2, 303-p) and / or write (301-1, 301-2, 301-n) operations. The control circuit is further configured to, after each write operation of an elementary cell and before the next write operation of said elementary cell, apply to the cell a refresh sequence (305-1, 305-2, 305-n) comprising the application, between the first and second electrodes of the resistive element of the cell, of a succession of voltage pulses (V) of alternating polarities. Figure for the abstract: Fig. 3

Description

Title of the invention: Memory circuit technical field

[0001] This description relates generally to electronic devices, more particularly to memory circuits comprising several elementary memory cells, each comprising a resistive element of variable resistance. Previous technique

[0002] Memory circuits comprising several elementary memory cells, each having a resistive element of variable resistance, have been proposed. In these memory circuits, the resistive element of each cell comprises, for example, a ferroelectric tunnel junction (FTJ) having a layer of ferroelectric material interposed between two electrodes.

[0003] Each elementary memory cell is typically capable of alternating between at least two different resistance levels, corresponding respectively to opposite polarizations of the ferroelectric material layer. During a write operation in a memory cell, the transition between the two resistance levels is achieved, for example, by applying a voltage between the two electrodes located on either side of the layer.

[0004] Existing memory circuits comprising elementary memory cells, each with a resistive element of variable resistance, suffer from various drawbacks. Reliability problems are particularly observed when using existing memory circuits, manifesting themselves notably as drifts in the various resistance levels after several successive programming operations. These problems can also affect read operations. Summary of the invention

[0005] There is a need to improve existing memory circuits comprising elementary memory cells, each containing a resistive element of variable resistance. In particular, it would be desirable to increase the reliability of programming and / or reading operations on these memory circuits.

[0006] To this end, one embodiment provides a memory circuit comprising a plurality of elementary cells, each having a resistive element of variable resistance, said element comprising first and second electrodes separated by a layer of a ferroelectric material, and a control circuit configured to implement read and / or write operations, the control circuit being further configured to, after each write operation of a elementary cell and before the next writing operation of said elementary cell, apply to the cell a refresh sequence comprising the application, between the first and second electrodes of the resistive element of the cell, of a succession of voltage pulses of alternating polarities.

[0007] According to one embodiment, the first electrode is connected to a first conductive track and the second electrode is connected to a second conductive track.

[0008] According to one embodiment, the second electrode is connected, by means of a selector or a selection transistor, to the second conductive track.

[0009] According to one embodiment, the control circuit is further configured to, during each refresh sequence, alternately apply a positive potential to the first conductive track and to the second conductive track.

[0010] According to one embodiment, the memory circuit further comprises biasing circuits connected to the first conductive tracks, each biasing circuit comprising at least one first charge pump intended to provide a positive potential and at least one second charge pump intended to provide a negative potential.

[0011] According to one embodiment, the control circuit is configured to, during each refresh sequence, alternately apply positive and negative potentials to the first conductive track.

[0012] According to one embodiment, the memory circuit further comprises a filtering circuit connected to the first conductive track, the filtering circuit comprising a capacitive element and a switch associated in parallel between first and second nodes, the second node being connected to the first conductive track.

[0013] According to one embodiment, the control circuit is further configured to, during each refresh sequence, apply a voltage signal having alternations of the same sign to the second node of the filtering circuit.

[0014] According to one embodiment, each refresh sequence comprises between ten and one hundred voltage pulses.

[0015] According to one embodiment, the voltage pulses during each refresh sequence have an amplitude equal, in absolute value, approximately twice that of a voltage such that an electric field applied to the layer is equal to the coercive field of the ferroelectric material.

[0016] According to one embodiment, each refresh sequence begins with a first voltage pulse and ends with a last voltage pulse, the first and last voltage pulses having polarities opposite and identical to those of a voltage pulse applied by the control circuit, between the first and second electrodes of the resistive element of the cell, during the previous write operation.

[0017] According to one embodiment, the voltage pulses applied during each refresh sequence have, in absolute value, an amplitude strictly greater than that of the voltage pulses applied during the writing operations.

[0018] According to one embodiment, the ferroelectric material of the layer is based on doped hafnium oxide, hafnium oxide and zirconium, aluminum nitride and scandium, or germanium telluride.

[0019] According to one embodiment, the ferroelectric material of the layer is based on doped hafnium oxide or hafnium and zirconium oxide and is crystallized at least partially in an orthorhombic system.

[0020] According to one embodiment, said variable resistance resistive element further comprises a dielectric layer interposed between the layer of the ferroelectric material and the first electrode.

[0021] One embodiment provides a method for controlling a memory circuit comprising a plurality of elementary cells, each comprising a resistive element of variable resistance, said element comprising first and second electrodes separated by a layer of a ferroelectric material, and a control circuit configured to perform read and write operations, the method comprising the following steps: a) perform, using the control circuit, at least one operation to write an elementary cell; and b) after each write operation and before the next write operation of said elementary cell, apply to the cell, by means of the control circuit, a refresh sequence comprising the application, between the first and second electrodes of the resistive element of the cell, of a succession of voltage pulses of alternating polarities. Brief description of the drawings

[0022] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0023] [Fig.1] is a schematic and partial cross-sectional view of an example of a memory cell of the type to which, by way of example, described embodiments apply;

[0024] [Fig.2] is an example of a hysteresis loop illustrating variations in the polarization of a layer of ferroelectric material as a function of an electric field applied to the layer;

[0025] [Fig. 3] is a chronogram illustrating, schematically and partially, a example of the evolution, as a function of time, of a voltage applied between electrodes of a resistive element of an elementary memory cell according to an embodiment;

[0026] [Fig. 4] is a schematic and partial top view illustrating a memory circuit according to one embodiment; and

[0027] [Fig.5] is a schematic and partial top view illustrating a memory circuit according to one embodiment. Description of the implementation methods

[0028] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the control circuits for the memory circuits and the applications in which such memory circuits may be used have not been detailed, as the described embodiments and variants are compatible with the control circuits for conventional memory circuits and with conventional applications implementing memory circuits.

[0030] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "approximately", "about", "substantially", and "in the order of" mean within 10%, preferably within 5%.

[0033] In the following description, the terms "insulating" and "conducting" mean, unless otherwise specified, electrically insulating and electrically conductive respectively.

[0034] Fig. 1 is a schematic and partial cross-sectional view of an example of a memory cell 100 of the type to which, by way of example, described embodiments apply.

[0035] In the example shown, the memory cell 100 comprises a layer of ferroelectric material 101, or ferroelectric layer 101, interposed between two electrodes 103A and 103B. More specifically, in the illustrated example, electrode 103B covers one face of the ferroelectric layer 101 (the lower face of layer 101, in the orientation of [Fig. 1]). Furthermore, in this example, a dielectric layer 105 covers one face of the ferroelectric layer 101 opposite electrode 103B (the upper face of layer 101, in the orientation of [Fig. 1]), while electrode 103A covers one face of the dielectric layer 105 opposite the ferroelectric layer 101 (the upper face of layer 105, in the orientation of [Fig. 1]).As an example, the ferroelectric layer 101 is based on hafnium dioxide (HfO2), for example doped with silicon or aluminum atoms, on hafnium zirconium oxide (HZO), for example of the type HfxZr(i X)O2 where x is approximately 0.5, or on germanium telluride (GeTe). The material of the ferroelectric layer 101 is, for example, crystallized, at least partially, in a non-centrosymmetric system, for example the orthorhombic system. As an alternative, the material of the layer 101 can be based on aluminum scandium nitride (AIScN), for example, crystallized at least partially in a hexagonal phase. As an example, the layer 101 has a thickness of approximately 10 nm.

[0036] The dielectric layer 105 is, for example, made of a material and has a thickness such that a current can flow between the ferroelectric layer 101 and the electrode 103B, by tunneling through the layer 105, when a voltage on the order of a few volts is applied between the electrodes 103A and 103B. By way of example, the dielectric layer 105 is made of alumina (Al₂O₃) or silicon dioxide (SiO₂) and has a thickness of between 0.5 and 3.5 nm.

[0037] The electrodes 103A and 103B may be made of the same material. The electrodes 103A and 103B are made of a conductive material, for example, a material based on a metal, a metal alloy, or a doped semiconductor material. By way of example, each electrode 103A, 103B is made of tungsten or titanium nitride.

[0038] Alternatively, the dielectric layer 105 may be omitted. In this case, the electrode 103B is made of a different material than the electrode 103A, so that there is a difference in output working capacity between the electrodes 103A and 103B. Furthermore, the ferroelectric layer 101 is, for example, thinner than in the case illustrated in [Fig. 1] where the memory cell 100 includes the layer 105 interposed between the ferroelectric layer 101 and the electrode 103A. In the case where the memory cell 100 lacks the dielectric layer 105, the ferroelectric layer 101 has, for example, a thickness of approximately 5 nm.

[0039] Figure 2 is an example of a hysteresis loop 200 illustrating polarization variations P of a layer of ferroelectric material, for example layer 101 of the memory cell 100 of [Fig.l], as a function of an electric field E applied to the ferroelectric layer.

[0040] In a case where the material of the ferroelectric layer 101 is crystallized in a non-centrosymmetric phase, the layer 101 comprises a plurality of electric dipoles, each formed by an elementary unit cell of the crystal lattice. Each electric dipole of the layer 101 exhibits a substantially vertical polarization oriented either from electrode 103A to electrode 103B, the negative charge of the dipole then being closer to electrode 103A than its positive charge, or from electrode 103B to electrode 103A, the positive charge of the dipole then being closer to electrode 103A than its negative charge.By applying a voltage between electrodes 103A and 103B of the memory cell 100, it is possible to modify, in the ferroelectric layer 101, the proportions of dipoles oriented from electrode 103A to electrode 103B, exhibiting a polarization denoted Pdown, and of dipoles oriented from electrode 103B to electrode 103A, exhibiting a polarization denoted Pup. This makes it possible to obtain at least two opposing polarization states of the ferroelectric material layer 101, corresponding respectively to two different resistance levels: . - a highly resistive level, corresponding to a case in which the dipoles of layer 101 are predominantly in the Pdown polarization state; and - a low resistivity level, exhibiting for example a lower electrical resistance, for example between ten and ten thousand times lower, than that of the high resistivity level, corresponding to a case in which the dipoles of the 101 layer are predominantly in the Pup polarization state.

[0041] At an initial instant, for example after the manufacturing operations of the memory cell 100 and before any writing operation in the memory cell 100, the electric dipoles of layer 101 are, for example, predominantly in the Pup bias state (point 201). A bias voltage Vbias is then, for example, applied between electrode 103A and electrode 103B of the memory cell 100. The bias voltage Vbias is, for example, positive and has a value strictly greater than a voltage Vc such that the electric field E applied to the ferroelectric layer 101 is equal to a coercive field Ec of the material. The coercive field Ec corresponds to the minimum value of the field E to be applied to layer 101 so that its bias P changes direction and opposes the bias P of layer 101 prior to the application of the field E.In other words, the coercive field Ec corresponds to the field E to be applied so that the bias P of the ferroelectric layer 101 is zero, that is, so that layer 101 contains approximately as many dipoles in the Pup bias state as dipoles in the Pdown bias state. Applying the bias voltage Vbias causes a transition (arrow 203) from layer 101 to the level. strongly resistive (point 205), in which the electric dipoles of layer 101 are predominantly in the Pdown bias state. After ceasing to apply the Vbias voltage (arrow 207), the P bias of layer 101 is equal to a Pr remanent bias (point 209).

[0042] A bias voltage -Vbias is then applied, for example, between electrode 103A and electrode 103B of the memory cell 100. The bias voltage -Vbias is, for example, negative and has a value strictly less than a bias voltage -Vc such that the electric field E applied to the ferroelectric layer 101 is equal to a coercive field -Ec of the material. By way of example, the bias voltage -Vbias and the coercive field -Ec are substantially equal, in absolute value, to the bias voltage Vbias and the coercive field Ec, respectively. In practice, the coercive field -Ec may be different from the coercive field Ec, the difference between the fields Ec and -Ec corresponding to a compensation field (or "offset"). The application of the voltage -Vbias causes a transition (arrow 211) from layer 101 to the low resistivity level (point 213), in which the electric dipoles of layer 101 are predominantly in the Pup bias state.After the bias voltage -Vbias (arrow 215) has been removed, the bias P of layer 101 is equal to a remanent bias -Pr (point 201). The bias -Pr is, for example, approximately equal in absolute value to the bias Pr.

[0043] For the sake of simplification, [Fig. 2] illustrates an example in which the polarization P of layer 101 is, at point 205, substantially equal to Pr and, at point 213, substantially equal to -Pr. This example is not, however, limiting, as the polarization P may, in practice, be equal, at point 205, to a saturation polarization Psat greater than Pr and, at point 213, to a saturation polarization -Psat less than -Pr.

[0044] The bias voltages Vbias and -Vbias are, for example, each applied in the form of a voltage pulse with a duration on the order of a few nanoseconds, for example greater than or equal to 10 ns. By way of example, each voltage Vbias, -Vbias is, in absolute value, less than 5 V, for example equal to approximately 2.5 V, in a case where the ferroelectric layer 101 has a thickness on the order of 10 nm.

[0045] At a later time, the bias voltage Vbias is, for example, reapplied between electrodes 103A and 103B of the memory cell 100. The application of the bias voltage Vbias then causes a transition (arrow 203) of layer 101 to the highly resistive level (point 205), in which the electrical dipoles of layer 101 are predominantly in the Pdown bias state. After the bias voltage Vbias is no longer applied (arrow 207), the P bias of layer 101 is again equal to the remanent bias Pr (point 209).

[0046] In the example shown, the application of the positive bias voltage Vbias between the Applying electrodes 103A and 103B corresponds to writing a first resistance state, for example a high resistance or highly resistive state, to memory cell 100, while applying the negative voltage -Vbias between electrodes 103A and 103B corresponds to writing a second resistance state different from the first resistance state, for example a low resistance or weakly resistive state, exhibiting a resistance lower than that of the first resistance state, to memory cell 100. Although not detailed in this description, other intermediate resistance states can also be obtained, for example by acting on the duration of application of the bias voltages Vbias and -Vbias and / or on the values ​​of these voltages.

[0047] Figure 3 is a chronogram 300 illustrating, schematically and partially, a example of evolution, as a function of time t, of a voltage V applied between electrodes of a resistive element of an elementary memory cell, for example between electrodes 103A and 103B of cell 100, according to an embodiment.

[0048] In the example shown, a write operation 301-1 is first implemented. The write operation 301-1 comprises the application of the negative voltage -Vbias between electrodes 103A and 103B. This leads, for example, to the storage of the highly resistive state in memory cell 100.

[0049] In this example, a read operation 303-1, following the write operation 301-1, is then implemented. The read operation 303-1 comprises the application of a read voltage Vr between the electrodes 103A and 103B of the memory cell 100. In the illustrated example, the read voltage Vr is negative and, for example, between -1 and -2 V, for example, approximately -1.5 V. Alternatively, in the case of a stacking configuration different from that of the cell 100 previously described in relation to [Fig. 1], the read voltage Vr may be positive.

[0050] In the example illustrated in [Fig. 3], a refresh sequence 305-1, comprising the application of a succession of alternating polarity voltage pulses V between electrodes 103A and 103B, is then implemented. In this example, the refresh sequence 305-1 is implemented after the write operation 301-1 and before any subsequent write operation.

[0051] In the example shown, a write operation 301-2, for example analogous to the write operation 301-1, is implemented after the refresh sequence 305-1. The write operation 301-2 differs, for example, from the write operation 301-1 in that the write operation 301-2 includes the application of the positive bias voltage Vbias between electrodes 103A and 103B. This leads, for example, to the storage of the low-resistance state in the memory cell 100.

[0052] In this example, a read operation 303-2, following the write operation 301-2 and analogous or identical to the read operation 303-1, is then implemented. In the illustrated example, the read operation 303-2 comprises the application of the read voltage -Vr between the electrodes 103A and 103B of the memory cell 100.

[0053] Figure 3 illustrates an example in which each write operation 301-1, 301-2 is followed by a read operation 303-1, 303-2 preceding the next write operation. This example is not, however, limiting; at least one of the read operations may, as an alternative, be omitted.

[0054] In the example illustrated in [Fig.3], a refresh sequence 305-2 analogous to the refresh sequence 305-1 and comprising the application, between electrodes 103A and 103B, of a succession of voltage pulses V of alternating polarities, is implemented after the reading operation 303-2.

[0055] Subsequently, other write operations and / or other read operations (not detailed), for example operations analogous or identical respectively to write operations 301-1 and 301-2 and to read operations 303-1 and 303-2, may be implemented, a refresh sequence analogous or identical to refresh sequence 305-1 or 305-2 being applied after each write operation and before the next write operation in cell 100.

[0056] In the example illustrated in [Fig.3], an nth write operation 301-n, for example identical to the write operation 301-1, is then implemented, followed by a pth write operation 303-p, with p less than or equal to n, and an nth refresh sequence 305-n.

[0057] In the example shown, each refresh sequence 305-1, 305-2, ... 305-n begins with a voltage pulse V of opposite polarity to the voltage applied during the preceding write operation 301-1, 301-2, ... 301-n and ends with a pulse of the same polarity as the voltage applied during the preceding write operation 301-1, 301-2, ... 301-n. Thus, in a case where the refresh sequence follows a write operation during which the positive bias voltage Vbias is applied between electrodes 103A and 103B of cell 100, for example, the refresh sequence 305-2 following the write operation 301-2, the refresh sequence begins with a negative pulse and ends with a positive pulse.Otherwise, that is, if the refresh sequence follows a write operation during which the negative voltage -Vbias is applied between electrodes 103A and 103B of cell 100, for example the refresh sequences 305-1 and 305-n following respectively the write operations 301-1 and 301-n, the refresh sequence begins with a positive pulse and ends with a negative pulse.

[0058] In the illustrated example, during the refresh sequences 305-1, 305-2, ... 305-n, the voltage pulses V applied between the electrodes 103A and 103B reach extreme values ​​(minimum and maximum) strictly greater, in absolute value, than the extreme values ​​Vbias and -Vbias of the voltage pulses applied between the electrodes 103A and 103B during the write operations 301-1, 301-2, ... 301-n. Put another way, the voltage signals V applied between the electrodes 103A and 103B of the memory cell 100 during the refresh sequences 305-1, 305-2, ... 305-n have a greater amplitude than the signals applied between these electrodes during the read operations 301-1, 301-2, ... 301-n.

[0059] The extreme values ​​reached by the voltage pulses V during the refresh sequences 305-1, 305-2, ... 305-n are, for example, equal in absolute value to about twice the voltage Vc corresponding to the coercive field Ec of layer 101. As an example, the extreme values ​​of the voltage V are equal, in absolute value, to about 6 V.

[0060] By way of example, each refresh sequence 305-1, 305-2, ... 305-n comprises between ten and one hundred voltage pulses V, for example about one hundred voltage pulses V. The frequency of the pulses is for example on the order of 100 kHz.

[0061] Figure 3 illustrates a case in which the voltage signal V applied between electrodes 103A and 103B during each refresh sequence 305-1, 305-2, ... 305-n has a triangular shape. This example is not limiting, however; the voltage signal V applied during each refresh sequence 305-1, 305-2, ... 305-n could, alternatively, have any shape, for example, a trapezoidal shape, a crenellated shape, etc.

[0062] Applying refresh sequences 305-1, 305-2, ... 305-n to memory cell 100 prevents the resistance of the ferroelectric layer 101 from drifting, for example increasing, after several successive write operations 301-1, 301-2, ... 301-n, for example when the number n of successive writes is on the order of several tens, for example approximately 50. Applying refresh sequences 305-1, 305-2, ... 305-n thus advantageously makes it possible to obtain reliable and repeatable memory states, which tends to increase the lifetime of memory cell 100.Moreover, these advantages are not limited to the case of two memory states, for example the highly and weakly resistive states described previously, but are also obtained regardless of the number of memory states, for example in the case where cell 100 includes at least one intermediate resistance state between the highly and weakly resistive states.

[0063] Fig. 4 is a schematic and partial top view illustrating a 400 memory circuit according to one embodiment.

[0064] In the example shown, the memory circuit 400 comprises a plurality of elementary memory cells 100, one of whose electrodes, for example electrode 103A, is connected to a conductive track 401 (SL), and the other electrode, electrode 103B in this example, is connected, via a selection transistor T, to another conductive track 403 (BL). In the example shown, each memory cell 100 is connected to a first conduction terminal (source or drain) of transistor T, the other conduction terminal of transistor T being connected to the conductive track 403. Furthermore, in this example, each transistor T has a control terminal (gate) connected to another conductive track 405 (WL). As an alternative, the T transistors can be omitted, with each elementary memory cell 100 connecting the conductive track 401 to the conductive track 403.In this case, the electrodes 103A and 103B of each cell 100 are, for example, respectively connected to the conductive tracks 401 and 403.

[0065] By way of example, the conductive tracks 401, 403 and 405 correspond respectively to source lines, bit lines and word lines of the memory circuit 400.

[0066] In the example illustrated in [Fig. 4], the memory circuit 400 further includes a control circuit 407 (CMD), comprising, for example, a microcontroller. The control circuit 407 is configured, for example, to implement read operations, write operations, and refresh sequences for each elementary memory cell 100 of the memory circuit 400, as previously described in relation to [Fig. 3]. The connections between the control circuit 407 and the conductive tracks 401, 403, and 405 have not been shown in [Fig. 4] in order to avoid cluttering the drawing. Alternatively, several circuits may be provided to implement the read, write, and refresh operations.

[0067] By way of example, the write operations are implemented by applying, between conductive track 401 and conductive track 403, the bias voltage Vbias, for writing a highly resistive state, or -Vbias, for writing a low-resistive state, as previously explained. In practice, for writing a highly resistive state in a memory cell 100, track 401 is, for example, brought to a positive potential V1 referenced to a reference potential Vref, for example ground, applied to track 403, the bias voltage Vbias between electrodes 103A and 103B of the memory cell 100 being in this case equal to the potential difference V1 - Vref.For example, the polarities are reversed for writing a weakly resistive state, that is to say that track 401 is brought to the reference potential Vref while track 403 is brought to the potential VI, the voltage - Vbias between electrodes 103A and 103B of memory cell 100 being in this case equal to the potential difference Vref-VL.

[0068] Refresh sequences are implemented, for example, by the control circuit 407, in a manner analogous to write operations. More precisely, during a refresh sequence of a memory cell 100, a triangular or trapezoidal voltage signal V is applied to the memory cell 100, alternating between phases of applying a potential V2 to track 401, with track 403 then, for example, being grounded, and phases of applying the potential V2 to track 403, with track 401 then, for example, being grounded. The potential V2 is, for example, strictly greater than the potential VL

[0069] By way of alternative, the memory circuit 400 further comprises biasing circuits 409 (PCs), for example, as many circuits 409 as conductive traces 401, each circuit 409 being connected to a trace 401 different from those to which the other circuits 409 are connected. By way of example, each circuit 409 comprises at least one charge pump, for example, two charge pump stages, for providing a positive potential, for example, the potential V2, and at least one other charge pump, for example, two other charge pump stages, for providing a negative potential, for example, a potential equal to about -V2. In this alternative, each refresh sequence is, for example, implemented by alternating between phases of applying the potential V2 and phases of applying the potential -V2 to the trace 401, the trace 403 then being, for example, held at the Vref potential during these phases.

[0070] During write operations, read operations and refresh sequences in the memory cell 100, the corresponding selection transistor T is controlled to the conducting state by a control voltage applied, for example by the control circuit 407, on the conductive track 405 to which the control terminal of the transistor T is connected. The control of the transistors T is within the capabilities of a person skilled in the art from the indications in this description.

[0071] Fig. 5 is a schematic and partial top view illustrating a 500 memory circuit according to one embodiment.

[0072] The memory circuit 500 of [Fig. 5] includes elements common to the memory circuit 400 of [Fig. 4]. These common elements will not be detailed again below. The memory circuit 500 of [Fig. 5] differs from the memory circuit 400 of [Fig. 4] in that the memory circuit 500 further includes filtering circuits 501, each comprising a capacitive element 503 and a switch 505 connected in parallel between nodes 507 and 509.

[0073] In the example shown, the memory circuit 500 comprises as many circuits 501 as there are tracks 401 (SL), each circuit 501 being connected, via its node 507, to a track 401 different from those to which the other circuits 501 are connected. The switch 505 of each circuit 501 is, for example, controlled by a control signal SIG, for example, is a signal with two states that respectively control the opening and closing of switch 505. The SIG signal is generated, for example, by the control circuit 407. The capacitive elements 503 are, for example, manufactured using CMOS technology (Complementary Metal-Oxide-Semiconductor). As an example, the capacitive element 503 in each circuit 501 has a capacitance on the order of picofarads, for example, between 0.1 and 10 pF.

[0074] The switch 505 is for example a transistor, for example a MOS transistor (from the English "Metal-Oxide-Semiconductor") on the gate of which the SIG signal is applied.

[0075] The memory circuit 500 of [Fig. 5] takes advantage of the fact that the tunnel junction of each memory cell 100 has a high resistance, for example on the order of 10 GQ, and that this resistance varies according to the absolute value of the voltage V applied across its terminals. Each circuit 501 makes it possible to form a high-pass filter of the "CR" type, whose resistive element R is mainly composed of the tunnel junction of the memory cell 100 and whose capacitive element C is mainly composed of the capacitive element 503.This high-pass filter advantageously allows, when switch 505 is open, the removal of the DC component from a half-wave signal—that is, a signal with alternations of the same sign, for example, a signal with only positive alternations—applied to node 509 of circuit 501 by circuit 407, transforming it into a full-wave signal comprising both positive and negative alternations. Thus, during refresh sequences, a voltage signal V with positive alternations and a maximum value approximately twice the voltage V2 is applied to node 509, resulting in the application, on track 401, of a voltage signal V with positive and negative alternations whose absolute values ​​are approximately equal to V2. Put another way, the half-wave signal applied to node 509 has an amplitude approximately twice that of the full-wave signal present at node 507.

[0076] For example, switch 505 is closed outside of refresh sequences.

[0077] One advantage of the 500 memory circuit is that it allows refresh sequences to be implemented using only a positive half-cycle signal, making it possible to generate a positive and negative half-cycle signal on the same track 401, with track 403, for example, being held at the reference potential Vref during the sequences. This reduces the driving complexity and power consumption of the memory circuit, for example, compared to the 400 memory circuit of [Fig. 4] in which the refresh sequences are implemented by the control logic or by means of the charging pumps of circuits 409.

[0078] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0079] Finally, the practical implementation of the described embodiments and variants is within the grasp of a person skilled in the art, based on the functional specifications given above. In particular, a person skilled in the art is able to determine the capacitance of the capacitive elements 503 of the circuits 501 and the number of alternations of voltage pulses applied to each refresh sequence, depending on the application.

Claims

Claims

1. Memory circuit (400; 500) comprising a plurality of elementary cells (100) each comprising a resistive element of variable resistance, said element comprising first and second electrodes (103A, 103B) separated by a layer of a ferroelectric material (101), and a control circuit (407) configured to implement read operations (303-1, 303-2, 303-p) and / or write operations (301-1, 301-2, 301-n), the control circuit being further configured to, after each write operation of an elementary cell and before the following write operation of said elementary cell, apply to the cell a refresh sequence (305-1, 305-2, 305-n) comprising the application, between the first and second electrodes of the resistive element of the cell, of a succession of voltage pulses (V) of alternating polarities.

2. The memory circuit (400; 500) of claim 1, wherein the first electrode (103A) is connected to a first conductive track (401) and the second electrode (103B) is connected or joined to a second conductive track (403).

3. Memory circuit (400; 500) according to claim 2, in which the second electrode (103B) is connected, by means of a selector or a selection transistor (T), to the second conductive track.

4. Memory circuit (400) according to claim 2 or 3, wherein the control circuit (407) is further configured to, during each refresh sequence (305-1, 305-2, 305-n), alternately apply a positive potential to the first conductive track (401) and to the second conductive track (403).

5. A memory circuit (400) according to claim 2 or 3, further comprising bias circuits (409) connected to the first conductive tracks (401), each bias circuit comprising at least one first charge pump for providing a positive potential and at least one second charge pump for providing a negative potential.

6. Memory circuit (400) according to claim 5, wherein the control circuit (407) is configured to, during each refresh sequence (305-1, 305-2, 305-n), alternately apply the positive and negative potentials to the first conductive track (401).

7. A memory circuit (500) according to claim 2 or 3, comprising in furthermore a filtering circuit (501) connected to the first conductive track (401), the filtering circuit comprising a capacitive element (503) and a switch (505) associated in parallel between first and second nodes (507, 509), the second node being connected to the first conductive track.

8. Memory circuit (500) according to claim 7, wherein the control circuit (407) is further configured to, during each refresh sequence (305-1, 305-2, 305-n), apply a voltage signal having alternations of the same sign to the second node (509) of the filtering circuit (501).

9. Memory circuit (400; 500) according to any one of claims 1 to 8, wherein each refresh sequence (305-1, 305-2, 305-n) comprises between ten and one hundred voltage pulses.

10. Memory circuit (400; 500) according to any one of claims 1 to 9, in which the voltage pulses (V) during each refresh sequence (305-1, 305-2, 305-n) have an amplitude equal, in absolute value, to approximately twice a voltage such that an electric field (E) applied to the layer (101) is equal to the coercive field (Ec) of the ferroelectric material.

11. Memory circuit (400; 500) according to any one of claims 1 to 10, wherein each refresh sequence (305-1, 305-2, 305-n) begins with a first voltage pulse (V) and ends with a last voltage pulse, the first and last voltage pulses respectively having polarities opposite and identical to those of a voltage pulse applied by the control circuit (407), between the first and second electrodes (103A, 103B) of the resistive element of the cell (100), during the previous write operation (301-1, 301-2, 301-n).

12. Memory circuit (400; 500) according to any one of claims 1 to 11, in which the voltage pulses applied during each refresh sequence (305-1, 305-2, 305-n) have, in absolute value, an amplitude strictly greater than that of the voltage pulses applied during the write operations (301-1, 301-2, 301-n).

13. Memory circuit (400; 500) according to any one of claims 1 to 12, wherein the ferroelectric material of the layer (101) is based on doped hafnium oxide, hafnium and zirconium oxide, aluminum and scandium nitride, or germanium telluride.

14. Memory circuit (400; 500) according to claim 13, wherein the ferroelectric material of the layer (101) is based on doped hafnium oxide or an oxide of hafnium and zirconium and is crystallized at least partially in an orthorhombic system.

15. A memory circuit according to any one of claims 1 to 14, wherein said variable resistance resistive element further comprises a dielectric layer (105) interposed between the layer of ferroelectric material (101) and the first electrode (103A).

16. Method for controlling a memory circuit (400; 500) comprising a plurality of elementary cells (100) each comprising a resistive element of variable resistance, said element comprising first and second electrodes (103A, 103B) separated by a layer of a ferroelectric material (101), and a control circuit (407) configured to implement read operations (303-1, 303-2, 303-p) and write operations (301-1, 301-2, 301-n), the method comprising the following steps: a) performing, by means of the control circuit (407), at least one write operation (301-1, 301-2, 301-n) of an elementary cell;and b) after each write operation and before the following write operation of said elementary cell, applying to the cell, by means of the control circuit (407), a refresh sequence (305-1, 305-2, 305-n) comprising the application, between the first and second electrodes of the resistive element of the cell, of a succession of voltage pulses (V) of alternating polarities.;

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