Voltage regulator

Abstract

Voltage regulator The present description relates to a voltage regulator (3) comprising: a first output (300) intended to be connected to a capacitive element (C); a current source (304) coupling the first output (300) to a first node (306) configured to receive a supply voltage (VDD), the current source being configured to provide a first direct current (I) only when a first binary signal (sig2) is in its first binary state; a comparator (308) configured to compare a first voltage (Vout) on the first output (300) with a setpoint voltage (Vref); and a first circuit (310) configured, when the comparator (308) indicates that the first voltage (Vout) is lower than the setpoint voltage (Vref), to put the first signal (sig2) in its first binary state for a first fixed duration (Tload) determined by the supply voltage or independent of the supply voltage. Figure for abstract: Fig.3.

Description

Title of the invention: Voltage regulator Technical field

[0001] The present description relates generally to electronic circuits, for example integrated electronic circuits, and, more particularly, to voltage regulators. Prior art

[0002] Voltage regulators are devices or circuits configured to provide, from a direct current (DC) supply voltage, a regulated continuous voltage having a value determined by a voltage or setpoint value. Many voltage regulators are known.

[0003] For example, known linear voltage regulators comprise a MOS (Metal Oxide Semiconductor) transistor coupling a node for applying the supply voltage to a node for supplying the regulated voltage, and a comparator providing a signal representative of the comparison of the value of the regulated voltage with that of the setpoint voltage or an error amplifier providing an error signal representative of the error between the value of the regulated voltage and the setpoint value. The gate of the MOS transistor is then controlled from the signal provided by the comparator or the amplifier, so that the regulated voltage is equal to the setpoint voltage. The transistor can be P-channel (PMOS) or N-channel (NMOS). Compared to a PMOS transistor, an NMOS transistor has a better power supply rejection ratio (PSRR).However, implementing the control of such an NMOS transistor requires prior knowledge of the static consumption of the load. However, this static consumption depends on the PVT parameters (from the English "Process Voltage Temperature"), which poses a problem.

[0004] Furthermore, the bandwidth of known linear voltage regulators decreases when one seeks to reduce the static consumption of the regulator, for example so that the regulator has a static consumption less than 5% of the average consumption of the load which is, for example, less than or equal to approximately 10 pA at 27°C, or for example so that the regulator has a static consumption less than 200 nA, or even 100 nA for a load having a static consumption of the order of 3 pA. This reduction in the bandwidth of the regulator is not desirable because it results in an increase in the variations of the regulated voltage around its setpoint value.

[0005] As an alternative example, known charge pump voltage regulators include switched capacitors. However, providing the charge pump capacitors makes these regulators bulky. In addition, the capacitors are typically mounted external to the chip including the charge pump switches, which complicates the charge pump. This also requires increasing the number of input / output pads on the chip, which is not always possible.

[0006] As another alternative example, known voltage regulators include a Switched Mode Power Supply (SMPS). However, a Switched Mode Power Supply requires the provision of an inductance ("coil" in English), which makes the regulator bulky. In addition, Switched Mode Power Supply type regulators are sources of noise for the electronic systems to which they belong, which poses a problem when these systems include circuits (or applications) sensitive to noise.

[0007] The three examples above of known voltage regulators all have disadvantages with regard to their consumption and / or their size and / or their regulation speeds.

[0008] More generally, known voltage regulators have drawbacks. Summary of the invention

[0009] There is a need to overcome all or part of the disadvantages of known voltage regulators.

[0010] For example, there is a need for a voltage regulator having low static consumption that is compact and exhibits rapid response.

[0011] One embodiment overcomes all or part of the drawbacks of known voltage regulators.

[0012] For example, one embodiment provides a voltage regulator having low static consumption, for example less than 200 nA, or even 100 nA, when the load it supplies is at rest and has a static consumption of the order of 3 pA, and which is also compact and has a rapid response.

[0013] One embodiment provides a voltage regulator comprising: a first output for connection to a capacitive element; a current source coupling the first output to a first node configured to receive a supply voltage, the current source being configured to provide a first direct current only when a first binary signal is in its first binary state; a comparator configured to compare a first voltage on the first output with a set voltage; and a first circuit configured, when the comparator indicates that the first voltage is lower than the set voltage, to set the first signal to its first binary state for a first duration.

[0014] According to one embodiment, the first duration is fixed and independent of the supply voltage or fixed and determined by the supply voltage.

[0015] According to one embodiment, the direct current has a fixed value independent of the temperature.

[0016] According to one embodiment, the direct current has a value proportional to the absolute value of the temperature.

[0017] According to one embodiment, the first duration and the current source are configured so that a quantity of charges supplied to the first output during each first duration is fixed for a given temperature value and a given supply voltage value.

[0018] According to one embodiment, the first circuit comprises a second circuit adapted to supply two control signals respectively to two switches of a switching converter of the pulse frequency modulation type, each first duration being determined from at least one of the two control signals, preferably from the two control signals.

[0019] According to one embodiment: the first output is further intended to be connected to a first terminal of an inductive element; the regulator comprises a second output intended to be connected to a second terminal of the inductive element, a first switch connected between the first node and the second output, and a second switch connected between the second output and a second node configured to receive a reference potential; the first circuit is configured, when the comparator indicates that the first voltage is lower than the set voltage, to set a second signal to its first binary state for a second duration, then, at the end of the second duration, to set a third signal to its first binary state for a third duration; the first circuit is further configured, in a first operating mode, to control an on state of the first switch when the second signal is in its first binary state and an on state of the second switch when the third signal is in its first binary state, and, in a second operating mode, to put the first signal in its first binary state as soon as one of the second and third signals is in its first binary state.

[0020] According to one embodiment, the second duration is fixed and determined by the supply voltage, or fixed and independent of the supply voltage, and the third duration is fixed and determined by the supply voltage, or fixed and independent of the supply voltage.

[0021] According to one embodiment, the first operating mode is of the pulse frequency modulation type.

[0022] According to one embodiment, when the comparator indicates that the first voltage is lower than the setpoint voltage, the first circuit is configured to: generate a first voltage ramp, compare the first ramp with a first threshold voltage (Vref), and set the second signal to its first binary state from the start of the first ramp until the first ramp crosses the first threshold voltage; and generate a second voltage ramp when the first ramp crosses the setpoint voltage, compare the second ramp with a second threshold voltage, and set the third signal to its first binary state from the start of the second ramp until the second ramp crosses the second threshold voltage.

[0023] One embodiment provides a device comprising the regulator as described, and a load connected to the first output of the regulator.

[0024] One embodiment provides a device comprising the regulator as described, a load connected to the first output of the regulator, and an inductive element connected between the first and second outputs of the regulator.

[0025] According to one embodiment, the device comprises an integrated circuit chip comprising the regulator, the inductive element being arranged outside the chip.

[0026] According to one embodiment, the device further comprises a capacitive element connected to the first output of the regulator. Brief description of the drawings

[0027] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0028] [Fig.l] represents an example of a linear type voltage regulator;

[0029] [Fig.2] shows an example of a power supply type voltage regulator cutting operating in pulse frequency modulation;

[0030] [Fig.3] represents an embodiment of a voltage regulator;

[0031] [Fig.4] represents an alternative embodiment of the regulator of [Fig.3]; and

[0032] [Fig.5] illustrates, by means of timing diagrams, a mode of operation of the regulator of [Fig.4]. Description of the embodiments

[0033] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular,...

[0035] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0036] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0037] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0038] In the remainder of the description, for simplicity, when two nodes are at the same potential, these two nodes have the same reference and are described as if they corresponded to one and the same node, it being understood that, in practice, these two nodes may be distinct.

[0039] [Fig. 1] shows an example of a linear voltage regulator 1.

[0040] The regulator 1 comprises a MOS transistor T1, in this example with N channel, coupling a node 100 configured to receive a supply voltage VDD, to an output 102 of the regulator 1. The source of the transistor T1 is connected to the output 102, the drain of the transistor T1 being connected to the node 100. The regulator 1 is configured to provide, on its output 102, a regulated voltage Vout having a value determined by a setpoint voltage Vref, for example a voltage Vout equal to the voltage Vref.

[0041] For this, in this example where the transistor T1 is N-channel, the regulator 1 comprises a comparator 104 configured to receive the voltage Vref on its non-inverting input + and the voltage Vout on its inverting input, and to provide an err signal representative of the comparison of these two voltages with each other. Note that, in an example where the transistor T1 would be P-channel, the comparator 104 is preferably replaced by an error amplifier 104 configured to receive the voltage Vref on its non-inverting input + and the voltage Vout on its inverting input, and to provide an err signal representative of the comparison of these two voltages.

[0042] The gate of transistor Tl is controlled from the err signal, so that the voltage Vout is equal to the voltage Vref.

[0043] A load 106 (block "LOAD" in [Fig.l]) is connected between the output 102 and a node 108 configured to receive a reference potential GND, for example ground. The load 106 is powered by the voltage Vout. A capacitive element C is connected to the output 102. This capacitive element C makes it possible, for example, to smooth out variations in the voltage Vout.

[0044] For example, this capacitive element C is a capacitance connected in parallel with the load 106 between the nodes 102 and 108 as shown in the example of [Fig.l]. As another example not shown, this capacitive element C corresponds to the capacitance of the load 106.

[0045] The use of an N-channel transistor Tl makes it possible to eliminate the voltage drop between node 100 and output 102 which would result from the use of a PMOS type transistor Tl having its source connected to node 100 and its drain connected to output 102. The use of an N-channel transistor Tl also allows a better PSRR than with a P-channel transistor Tl.

[0046] However, as illustrated in [Fig.l], the use of an NMOS type transistor Tl involves providing a charge pump CP in the regulator 1, between the output of the error amplifier 104 and the gate of the transistor TL. This further involves providing in the regulator 1, a start-up circuit SU configured to precharge the charge pump, i.e. to precharge the gate of the transistor Tl to a value allowing the start-up of the regulator 1. This precharge value of the gate of the transistor Tl is in practice determined from the static consumption of the load 106 which is connected to the output 102. However, as mentioned previously, the static consumption of the load depends on the PVT parameters, from which it follows that the configuration of the circuit SU also depends on the PVT parameters, which is not desirable.

[0047] [Fig.2] represents an example of a voltage regulator 2 of the switching power supply type operating in pulse frequency modulation (PFM).

[0048] The switching power supply 2 comprises a high side switch ITH, for example a PMOS transistor, connected between a node 200 configured to receive a supply voltage VDD and an output 202 of the regulator 2. The switching power supply 2 further comprises a low side switch ITL, for example an NMOS transistor, connected between the output 202 and a node 204 configured to receive a reference potential GND, for example ground.

[0049] An inductance ("coil" in English) L is connected between the output 202 and an output 206 of the regulator 2, the inductance L having a terminal connected to the output 202 and a terminal connected to the output 206.

[0050] The switching power supply 2 is configured to provide, on its output 206, a regulated voltage Vout to a load 208 (block "LOAD" in [Fig.2]) connected to the output 206 to be powered by the voltage Vout. The load 208 is, for example, connected between the output 206 and the node 204 to the reference potential GND. A capacitive element C is connected to the output 206. This capacitive element C makes it possible, for example, to smooth out the variations in the voltage Vout.

[0051] For example, this capacitive element C is a capacitance connected in parallel with the load 208 between the nodes 206 and 204 as shown in the example of [Fig.2]. As another example not shown, this capacitive element C corresponds to the capacitance of the load 106.

[0052] The regulator 2 is configured to supply, on its output 206, the voltage Vout regulated to a value determined by a reference voltage Vref, for example to a value equal to that of the voltage Vref.

[0053] For this, in this example where the switching power supply 2 operates in pulse frequency modulation, the regulator 2 comprises a comparator 210 and a circuit 212 (block "CTRL" in [Fig.2]).

[0054] Comparator 210 is configured to compare voltage Vout to voltage Vref. For example, comparator 210 receives voltage Vout on its inverting input - and voltage Vref on its non-inverting input +, and provides an output signal sigl in a first low binary state when voltage Vout is less than voltage Vref, and in a second high binary state when voltage Vout is greater than voltage Vref. As an alternative example, comparator 210 receives voltage Vref on its inverting input - and voltage Vout on its non-inverting input +, and provides an output signal sigl in a first high binary state when voltage Vout is less than voltage Vref, and in a second low binary state when voltage Vout is greater than voltage Vref.

[0055] The circuit 212 is configured to provide two control signals sigH and sigL of the respective switches ITH and ITL. More particularly, when the comparator 210 indicates that the voltage Vout is lower than the voltage Vref (signal sigl in its first binary state), the circuit 212 is configured to put the signal sigH in its first binary state for a duration Ton, then, at the end of the duration Ton, to put the signal sigL in its first binary state for a duration Toff. Outside of the durations Ton and Toff, the circuit 212 is configured so that the signal sigH is in its second binary state and the signal sigL is in its second binary state. The circuit 212 is further configured so that the signal sigL is in its second binary state during each duration Ton, and the signal sigH is in its first binary state during each duration Toff.

[0056] The regulator 2 is configured so that the switch ITH is on when the signal sigH is in its first binary state, and so that the switch ITL is on when the sigL signal is in its first binary state. Thus, the switches ITH and ITL are respectively on and off during each Ton duration, respectively off and on during each Toff duration, and both off outside the Ton and Toff durations.

[0057] Each of the durations Ton and Toff is, for example, fixed and determined by the supply voltage, for example so that a maximum current in the inductance L at the end of each duration Ton, also called peak current, has the same value regardless of the value of the voltage VDD.

[0058] As an alternative example, each of the durations Ton and Toff is fixed and independent of the voltage VDD.

[0059] A disadvantage of regulator 2 is that it requires inductance L, which makes it bulky. Furthermore, regulator 2 is a source of noise, this noise resulting for example from voltage variations across inductance L occurring at the end of each duration Ton.

[0060] To overcome the drawbacks of known voltage regulators, a voltage regulator is proposed here in which, when a regulated voltage Vout is lower than a setpoint voltage Vref, the regulator is configured to supply a direct current I to an output of the regulator on which the regulated voltage Vout is available, for a duration Tload, the duration Tload being fixed and independent of the supply voltage or fixed and determined by the supply voltage, i.e. fixed for a given supply voltage value. A capacitive element is connected to the output of the regulator on which the regulated voltage Vout is available, this capacitive element corresponding to a capacitance connected to the output and / or to the capacitance of a load connected to the output.

[0061] Such a voltage regulator does not require an inductor, a PVT parameter-dependent starting circuit, and bulky capacitive elements such as the capacitive elements of a charge pump.

[0062] Advantageously, to control the controllable current source delivering the direct current I only during each duration Tload, the voltage regulator can reuse known circuits for controlling high-side and low-side switches of a switching power supply operating in pulse frequency modulation. Indeed, the proposed regulator has a similar operation to that of a switching power supply operating in pulse frequency modulation, with the difference that it does not require an inductance L. Of course, the present description is not limited to the case where the control circuit of the current source reuses high-side and low-side switch control circuits of a PFM type switching power supply. Indeed, the fixed duration Tload (depending or not on the supply voltage) can be generated by dedicated circuits not reusing circuits of control of high and low switches of a PFM type switching power supply, for example by any circuits configured to generate pulses of duration Tload.

[0063] According to one embodiment, the value of the current I delivered during each duration Tload is fixed.

[0064] According to an alternative embodiment, the current I delivered during each duration Tload has a value proportional to the absolute value of the temperature, or, in other words, is a PTAT current (from the English "Proportional To Absolute Temperature" - proportional to the absolute value of the temperature). Thus, in the same way that the current leaks of the load, therefore the static consumption of the latter, increase when the temperature increases, the value of the current I increases with the temperature. This results in better regulation of the voltage Vout.

[0065] According to one embodiment, the duration Tload and the value of the current I are determined so that, for a given temperature value and a given value of the supply voltage, at each duration Tload, the same quantity of charge is supplied by the regulator on its output on which the regulated voltage Vout is available. In other words, the quantity of charge that the regulator supplies on its output at each duration Tload determines the current I and the duration Tload.

[0066] This amount of charge supplied at each duration Tload determines the maximum current that the load can draw from the regulator while maintaining the regulation of the regulator's output voltage at its setpoint value. Said symmetrically, the load that will be connected to the regulator and, in particular, the consumption of this load, determine the amount of charge that the regulator must supply at each duration Tload to maintain the regulation of the output voltage at its setpoint value, the duration Tload and the current I then being chosen to obtain this amount of charge.

[0067] For example, when the regulator can operate in continuous injection and it is actually operating in continuous injection, that is to say when a new duration Tload begins at the end of each duration Tload, the regulator is then at its maximum current regulation limit. In other words, the regulator operates for example in continuous injection when the load that it supplies consumes a current equal to the maximum regulated current that the regulator can deliver.

[0068] The voltage regulator proposed here is advantageously suitable for implementation in low-power applications. For example, the voltage regulator proposed here has a static consumption of less than 5% of the static consumption of the load that it supplies. For example, the voltage regulator proposed here has a static consumption of less than 200 nA, or even 100 nA, when it is sized to supply a load having a static consumption of the order of 3 pA.

[0069] [Fig.3] represents an exemplary embodiment of such a voltage regulator, referenced 3 in this figure.

[0070] The device 3 comprises an output 300 configured to provide a regulated voltage Vout equal to a setpoint voltage Vref. A load 301 ("LOAD" block in [Fig.3]) is intended to be connected to the output 300 of the regulator 3, so as to be powered by the voltage Vout. In the example [Fig.3], the load 301 is shown connected to the output 300. For example, the load 301 is connected between the output 300 and a node 302 configured to receive a reference potential GND, for example ground.

[0071] A capacitive element C is intended to be connected to the output 300. As an example, this capacitive element C is a capacitance connected in parallel with the load 301, between the output 300 and the node 302. As another example, this capacitive element C corresponds to the capacitance of the load 302. As another example, this capacitive element corresponds to the capacitance equivalent to a capacitance connected in parallel with the load 301 and to the capacitance of the load 301.

[0072] Circuit 3 further includes a current source 304. Current source 304 couples output 300 to a node 306. For example, current source 304 has a terminal coupled, preferably connected, to node 306 and a terminal coupled, preferably connected, to output 300.

[0073] The node 306 is configured to receive a supply voltage VDD from the regulator 3. The voltage VDD is referenced to the potential GND. The voltage VDD is, for example, positive.

[0074] The current source 304 is configured to provide a direct current I, only when a binary signal sig2 is in its first binary state. Thus, when the signal sig2 is in its second binary state, the current source 304 does not provide the current I, or, in other words, provides a zero current.

[0075] According to one embodiment, the current I has a fixed value independent of the temperature. According to another embodiment, the current I has a value proportional to the absolute value of the temperature (PTAT).

[0076] Similar to the regulator 2 described in relation to [Fig.2], the regulator 3 of [Fig.3] comprises a comparator 308 configured to compare the voltage Vout available on the output 300 with the reference voltage Vref.

[0077] For example, comparator 308 receives voltage Vout on its inverting input - and voltage Vref on its non-inverting input +, and provides an output signal sigl in a first low binary state when voltage Vout is lower than voltage Vref, and in a second high binary state when voltage Vout is higher than voltage Vref. As an alternative example, comparator 308 receives voltage Vref on its inverting input - and voltage Vout on its non-inverting input +, and provides an output signal sigl in a first high binary state when voltage Vout is lower than voltage Vref, and in a second low binary state when voltage Vout is higher than voltage Vref.

[0078] The regulator 3 further comprises a circuit 310 (block "CIRC" in [Fig.3]). When the comparator 308 indicates that the voltage Vout is lower than the voltage Vref, or, in other words, when the signal sigl is in its first binary state, the circuit 310 is configured to put the signal sig2 in its first binary state for the duration Tload.

[0079] As a result, when the voltage Vout becomes lower than the voltage Vref, the signal sigl switches to its first binary state, which causes the signal sig2 to be set to the first binary state for the duration Tload by the circuit 310. The supply of the current I for the duration Tload to the element C tends to increase the voltage Vout which approaches, or even exceeds, its setpoint value, i.e. the value of the voltage Vref.

[0080] According to one embodiment, the circuit 310 comprises a circuit similar or identical to the CTRL circuit described previously in relation to [Fig. 2]. In other words, the circuit 310 comprises a circuit configured to provide two control signals sigH and sigL respectively to two switches ITH and ITL of a switching power supply operating in pulse frequency modulation, although the switches ITH and ITL and the inductance L of such a switching power supply are not present in the regulator 3 of FIG. 3, and, more broadly, in the device illustrated in [Fig. 3].

[0081] In such an embodiment, the duration Tload can then be determined by the duration Ton of the on state of the ITH switch and / or the duration Toff of the on state of the ITL switch.

[0082] For example, each duration Tload is then equal to (or coincident with) a corresponding duration Ton. However, in this example, if the voltage Vout is still lower than the voltage Vref at the end of the duration Tload, it is necessary to wait until the end of the following duration Toff to implement a new duration Tload, which may harm the effectiveness of the regulation of the voltage Vout by the regulator 3.

[0083] As an alternative example, each duration Tload is then equal to (or coincident with) a corresponding duration Toff. However, in this example, the supply of current I to output 300 after voltage Vout has become lower than voltage Vref will only occur after the end of the duration Ton preceding this duration Toff, which reduces the response time of regulator 3.

[0084] As another alternative example, each duration Tload corresponds to the total duration of a corresponding duration Ton and the following duration Toff. Compared to the two examples above, this allows the regulator 3 to supply the current I for a duration Tload starting immediately after the voltage Vout has become lower than the voltage Vref, and, furthermore, that a new duration Tload can start immediately after the end of a current duration Tload if the voltage Vout is lower to the voltage Vref at the end of the current duration Tload. In other words, the regulator can then operate by continuous current injection.

[0085] Other implementations of the circuit 310 are within the reach of those skilled in the art from the indications given in the present description, for example from the functional indications given in the present application.

[0086] In particular, according to one embodiment, the circuit 310 does not comprise a circuit similar or identical to the CTRL circuit described previously in relation to [Fig.2]. In this case, the circuit 310 is configured to provide the signal sig2 in its first binary state for the duration Tload if the voltage Vout is lower than the voltage Vref, i.e. if the signal sigl is in its first binary state. By way of example, the circuit 310 may then comprise a pulse generator of duration Tload controlled by the signal sigl, for example a pulse generator comprising a Schmitt trigger.

[0087] According to one embodiment, the regulator 3 is part of an integrated circuit chip and the capacitive element C is arranged outside the chip, the assembly of the regulator 3 and the element C forming an electronic device. In this case, the output 300 of the regulator 3 corresponds, for example, to an output terminal of the integrated circuit chip. Furthermore, the load 301 may be part of the same integrated circuit chip as the regulator, or, conversely, be arranged outside the chip, the assembly of the regulator, the element C and the load 301 forming an electronic device.

[0088] [Fig.4] represents an example of an alternative embodiment of the regulator 3 described in relation to [Fig.3].

[0089] In this variant embodiment, the regulator 3 is configured to operate selectively according to a first operating mode or a second operating mode. In other words, the regulator 3 alternates between operating phases where it operates according to the first operating mode, and operating phases where the regulator 3 operates according to the second operating mode.

[0090] In the second operating mode, the regulator 3 operates in the manner described in relation to [Fig.3]. In other words, in the second operating mode, when the voltage Vout is lower than the voltage Vref, the regulator 3 supplies the current I to its output I for a duration Tload.

[0091] In the first operating mode, the regulator 3 operates as a switching power supply operating in pulse frequency modulation.

[0092] The alternative embodiment of [Fig.4] takes advantage of the fact that parts (or circuits) of the regulator 3 can then be used in each of the first and second operating modes. As an example, this makes it possible to have a compact regulator 3 which can operate alternately according to the first and second operating modes. As an alternative example, this makes it possible for this same regulator 3 can be put into an application where it operates only in the first mode, or, conversely, into an application where it operates only in the second mode.

[0093] The regulator 3 described here in relation to [Fig.4] comprises many elements in common with the regulator 3 described in relation to [Fig.4], and only the differences between these two regulators are highlighted here.

[0094] More particularly, with respect to the regulator 3 described in relation to [Fig.3], the regulator 3 of [Fig.4] further comprises, in a similar manner to the regulator 2 of [Fig.2], a high-side ITH switch, for example a PMOS transistor, and a low-side ITL switch, for example an NMOS transistor.

[0095] The switch ITH couples the node 306 receiving the voltage VDD to an output 400 of the regulator 3, and the switch ITL couples the output 400 to the node 302 receiving the reference potential GND.

[0096] Furthermore, in [Fig.4], similarly to regulator 2 of [Fig.2], output 300 of regulator 3 is intended to be connected to one terminal of an inductor or inductive element L, output 400 of regulator 3 being intended to be connected to the other terminal of inductive element L. In the example of [Fig.4], element L is shown connected between outputs 300 and 400 of regulator 3. The presence of element L allows regulator 3 to operate according to the first operating mode.

[0097] In the embodiment of [Fig.4], the circuit 310 (block "CIRC" in [Fig.4]), is configured, when the comparator 308 indicates that the voltage Vout (output 300) is lower than the voltage Vref, to put a signal sigH in its first binary state for a duration Ton, then, at the end of the duration Ton, to put a signal sigL in its first binary state for a duration Toff. The durations Ton and Toff are for example determined in the same way as in [Fig.2].

[0098] In the first operating mode, that is to say when the regulator 3 operates as a pulse frequency modulation switching power supply, the regulator 3, and more particularly its circuit 310, are configured to put the switch ITH in the on state when the signal sigH is in its first binary state, and to put the switch ITL in the on state when the signal sigL is in its first binary state.

[0099] In the second operating mode, that is to say when the regulator 3 operates in the manner described in relation to [Fig. 3], the regulator 3, and more particularly its circuit 310, are configured to put the signal sig2 for controlling the current source 304 to its first binary state only when the signal sigH is in its first binary state, or, in a variant, only when the signal sigL is in its first binary state, or in some other variant, only when either of the signals sigH and sigL is in its first binary state.

[0100] According to one embodiment, a binary signal M of the regulator 3, for example a signal M supplied to the regulator 3 by another circuit, for example a microcontroller, determines the operating mode of the regulator 3. For example, a first binary state of the signal M corresponds to the first operating mode, and a second binary state of the signal M corresponds to the second operating mode.

[0101] According to one embodiment, the circuit 310 comprises the circuit 212 (block "CTRL" in [Fig.4]) described in relation to [Fig.2]. This circuit 212 provides the signals sigH and sigL on the basis of the signal sig2 in [Fig.4], in the same way as it provided the signals sigH and sigL on the basis of the signal sigl in [Fig.2]. In this embodiment, from the signals sigH and sigL, the circuit 310 is configured to control the switches ITH and ITL in the manner described in relation to [Fig.2] and to maintain the signal sig2 in its second binary state when the regulator 3 operates according to the first mode of operation, and, to control the source 304 in the manner described in relation to [Fig.3] and to maintain the switches ITH and ITL blocked when the regulator 3 operates according to the second mode of operation.

[0102] For example, as shown in [Fig.4], the circuit 310 comprises two routing circuits 402 and 403, for example two demultiplexers 402 and 404. The circuit 402, respectively 404, receives the signals M and sigH, respectively M and sigL.

[0103] When the signal M is in its first binary state (first operating mode), the circuit 402, respectively 404, provides the signal sigH, respectively sigL, on its output 408, respectively 410, the switch ITH, respectively ITL, being controlled from the output 408, respectively 410. The output 408 of the circuit 402, respectively the output 410 of the circuit 404, is coupled, preferably connected, to the gate of the transistor ITH, respectively ITL. When the signal M is in its second binary state (second operating mode), the outputs 408 and 410 are such that the switches ITH and ITL are blocked.

[0104] When the signal M is in its second binary state (second operating mode), the circuit 402, respectively 404, provides the signal sigH, respectively sigL, on its output 412, respectively 414. The outputs 412 and 414 are coupled, preferably connected, to inputs of a logic gate 416. The logic gate 416 and the circuits 402 and 404 are configured to provide the signal sig2 from the signals sigH and sigL so that: the signal sig2 is in its first binary state when the signal M is in its second binary state and that, in this example, one or the other of the signals sigH and sigL is in its first binary state, the signal sig2 is in its second binary state when the signal M is in its second binary state and both signals sigH and sigL are simultaneously in their second binary states, and the signal sig2 is in its second binary state when the signal M is in its first binary state.

[0105] In the example above, when in the second operating mode each duration Tload is equal to the total duration of a corresponding duration Ton and a duration Toff following this duration Ton, and the circuit 310 determines the signal sig2 from the signals sigH and sigL.

[0106] In other examples not illustrated, in the second mode of operation, each duration Tload is equal to the duration of a corresponding duration Ton and the circuit 310 determines the signal sig2 only from the signal sigH. As an example, in this case, the circuit 310 can be that illustrated in [Fig.4] in which the gate 416 is omitted and the signal sig2 is available directly on the output 412 of the circuit 402.

[0107] In still other examples not illustrated, in the second mode of operation each duration Tload is equal to the duration of a corresponding duration Toff and the circuit 310 determines the signal sig2 solely from the signal sigL. As an example, in this case, the circuit 310 can be that illustrated in [Fig.4] in which the gate 416 is omitted and the signal sig2 is available directly on the output 414 of the circuit 404.

[0108] For example, circuit 310 of regulator 3 of [Fig.3] may correspond to circuit 310 of regulator 3 of [Fig.4] in which circuits 402 and 404 are omitted.

[0109] Although a particular mode of implementation of the circuit 310 has been described in relation to [Fig.4], the person skilled in the art is able to provide other implementations of the circuit 410 from the indications given in the present description, for example from the functional indications given in the present application.

[0110] According to one embodiment, the regulator 3 of [Fig.4] is part of an integrated circuit chip, and the element L is arranged outside the chip. In this case, the outputs 300 and 400 of the regulator 3 correspond, for example, to two input / output terminals of the integrated circuit chip. Furthermore, the load 301 may be part of the same integrated circuit chip as the regulator, or, conversely, be arranged outside the chip.

[0111] The assembly of the regulator 3, the elements C and L, and the load 301 forms an electronic device.

[0112] Although element C (Figures 3 and 4) and element L ([Fig.4]) have been described above as not being part of the regulator 3, in embodiments, this or these elements may be part of the regulator 3.

[0113] [Fig.5] illustrates, by means of timing diagrams, an example of operation of the regulator of [Fig.4]. In this example, each duration Tload corresponds to the sum of a corresponding duration Ton and the duration Toff following this duration Ton, or, in other words, the signal sig2 for controlling the source 304 is determined from the two signals sigH and sigL. In this example, the circuit 310 is implemented in the manner illustrated in [Fig.4]. In this example, the first binary state of each of the signals sigl, sigH, sigL and sig2 corresponds to the high state of this signal, the second binary state corresponding to the low state of the signal.

[0114] In this embodiment, the circuit 310 is configured, when the signal sigl indicates that the voltage Vout is lower than the voltage Vref, to: generate a voltage ramp Vp, compare the ramp Vp with a first threshold voltage (in this example the voltage Vref although in other examples not illustrated the first threshold voltage may be different from the voltage Vref), and set the signal sigH to its first state from the start of the ramp Vp until the first ramp crosses the first threshold voltage;and generating a voltage ramp Vn when the ramp Vp crosses a second threshold voltage (in this example the voltage Vref although in other examples not shown the first threshold voltage may be different from the voltage Vref and, for example, be different from the first threshold voltage), comparing the ramp Vn with the voltage Vref, and setting the signal sigL to its first state from the start of the ramp Vn until the ramp Vn crosses the second threshold voltage. ;

[0115] In this example, the ramp Vp is an increasing ramp and the ramp Vn is a decreasing ramp. However, in other examples, the ramp Vp may be decreasing and / or the ramp Vn may be increasing.

[0116] Thus, in [Fig.5], at a time tl, the voltage Vout (not shown) becomes lower than the voltage Vref (not shown), from which it follows that the signal sigl switches to its first binary state (high state in this example). The circuit 212 then generates a ramp Vp starting at time tl, and, at the same time, switches the signal sigH to its first binary state (high state in this example). Time tl therefore marks the start of a corresponding duration Ton.

[0117] In [Fig.4], the signal M (not shown) is in its second binary state, from which it follows that the regulator 3 operates according to the second mode. Thus, the switching of the signal sigH to its first binary state at time t1 causes the switching of the signal sig2 to its first binary state (high state in this example) at time t1.

[0118] From time tl, the ramp Vp increases until it crosses the first threshold voltage (the voltage Vref in this example) at a time t2 following time tl. Thus, at time tl, the circuit 212 switches the signal sigH to its second binary state (low state in this example). In addition, the circuit 212 then generates a ramp Vn starting at time t2, and, at the same time, switches the sigL signal to its first binary state (high state in this example).

[0119] The instant t2 therefore marks the end of the duration Ton having started at the instant tl, and the start of a following duration Toff.

[0120] From time t2, the ramp Vn decreases until it crosses the second threshold voltage (in this example the voltage Vref) at a time t3 following time t2. Thus, at time t3, the circuit 212 switches the signal sigL to its second binary state (low state in this example).

[0121] Time t3 therefore marks the end of the duration Toff which began at time t2.

[0122] Between times t1 and t3, one or the other of the signals sigL and sigH is in its first binary state, these two signals sigL and sigH being in their second binary states before time t1 and after time t3. Thus, in this example, the signal sig2 switches to its first binary state at time t1 and remains in its first binary state from time t1 until time t3 where it switches to its second binary state. In other words, the duration Tload begins at time t1 and ends at time t3, and is equal to the sum of the duration Ton (between times t1 and t2) and the duration Toff (between times t2 and t3). Throughout the duration Tload, the source 304 delivers the current I to the output 300 of the regulator.

[0123] In the example of [Fig.4], although this is not illustrated, the voltage Vout increases from time tl and becomes higher than the voltage Vref again at a time between times tl and t2, from which it follows that the signal sigl switches to its second binary state at this same time.

[0124] In another example not illustrated, the operation described in relation to the instants t1, t2 and t3 is repeated from the instant t3 because the voltage Vout is always lower than the voltage Vref at this instant t3, or, in other words, because the signal sigl is always in its first binary state at this instant t3 (voltage Vout lower than the voltage Vref).

[0125] According to one embodiment, the slope of each of the ramps Vp and Vn is fixed throughout the operation of the regulator 3, and, in particular, is independent of the voltage VDD. In this case, each of the durations Ton, Toff and Tload is fixed and independent of the voltage VDD.

[0126] According to another embodiment, the slope of the ramp Vp is proportional to 1 / (VDD-Vout) so that the duration Ton depends on the voltage VDD and the peak current in the inductive element L when the regulator 3 operates according to the first operating mode is constant and independent of the voltage VDD.

[0127] Although examples of operation of the regulator 3 corresponding to the second mode of operation of the regulator 3 have been described in relation to [Fig. 5], the person skilled in the art will be able from the description made in relation to Figures 2 and 5, to deduce the operation of the regulator 3 in the first operating mode. For example, taking [Fig.5], in the first operating mode, the switch ITH would have been put in the on state for the duration Ton, then the switch ITL would have been put in the on state for the duration Toff. In addition, the signal sig2 would have remained in its second binary state as long as the regulator 3 operates according to the first operating mode.

[0128] Furthermore, although examples of operation of the regulator 3 have been described in relation to [Fig.5] where each duration Tload corresponds to the sum (or succession) of a duration Ton and a corresponding duration Toff, in other examples, each duration Tload corresponds to a duration Toff only, or to a duration Ton only.

[0129] Furthermore, the person skilled in the art will be able to adapt the example of [Fig.5] where each of the signals sigl, sigH, sigL and sig2 is in the high state in its first binary state, to examples in which one or more of these signals sigl, sigH, sigL and sig2 is in the low state in its first binary state.

[0130] Simulations have shown that the regulator 3 of [Fig.3] and the regulator 3 of [Fig.4] when operating according to the second mode made it possible to obtain very low static consumption values, for example between two consecutive durations Tload. For example, the static consumptions measured in simulations are less than 5% of the average static consumption of the load 301. For example, for a load 301 having low consumption, that is to say an average static consumption less than or equal to 3 pA, the static consumptions measured for the regulator 3 are less than 200 nA, or even less than 100 nA. By way of example, the regulator 3 according to the embodiment variant of [Fig.4] is implemented in an electronic system comprising circuits or applications sensitive to noise.In this case, when the noise-sensitive circuit(s) or application(s) are not active, the first operating mode makes it possible to take advantage of the high efficiency of the regulator 3 operating in a PFM type switching power supply, and, conversely, when the noise-sensitive circuit(s) or application(s) are active, the second operating mode makes it possible to take advantage of the low noise of the regulator 3 operating by injecting current I into the load 301.

[0131] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0132] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, as regards the implementation of the circuit 310, this does not not limited to an implementation comprising the circuit 212, and the person skilled in the art is able to provide other implementations of this circuit 310 from the functional indications given above. For example, the durations Ton and Toff can be generated other than from the respective ramps Vp and Vn. More generally, the present description is not limited to the case of a circuit 310 implemented from a circuit 212 configured to control high-side and low-side switches in a switching power supply operating in PFM.

Claims

Claims

1. Voltage regulator (3) comprising: a first output (300) intended to be connected to a capacitive element (C); a current source (304) coupling the first output (300) to a first node (306) configured to receive a supply voltage (VDD), the current source being configured to provide a first direct current (I) only when a first binary signal (sig2) is in its first binary state; a comparator (308) configured to compare a first voltage (Vout) on the first output (300) with a setpoint voltage (Vref);and a first circuit (310) configured, when the comparator (308) indicates that the first voltage (Vout) is lower than the set voltage (Vref), to set the first signal (sig2) to its first binary state for a first duration (Tload), in which the first duration (Tload) and the current source (304) are configured so that a quantity of charges supplied to the first output (300) during each first duration (Tload) is fixed for a given temperature value and a given supply voltage value (VDD).;

2. A voltage regulator according to claim 1, wherein the direct current (I) has a fixed value independent of temperature.

3. A voltage regulator according to claim 1, wherein the direct current (I) has a value proportional to the absolute value of the temperature.

4. Voltage regulator according to any one of claims 1 to 3, wherein the first circuit (310) comprises a second circuit (CTRL) adapted to supply two control signals (sigH, sigL) respectively to two switches (ITH, ITL) of a switching converter of the pulse frequency modulation type, each first duration (Tload) being determined from at least one of the two control signals, preferably from the two control signals.

5. A voltage regulator according to any one of claims 1 to 3, wherein:

6.

7. the first output (300) is further intended to be connected to a first terminal of an inductive element (L); the regulator (3) comprises a second output (400) intended to be connected to a second terminal of the inductive element (L), a first switch (ITH) connected between the first node (306) and the second output (400), and a second switch (ITL) connected between the second output (400) and a second node (302) configured to receive a reference potential (GND); the first circuit (310) is configured, when the comparator (308) indicates that the first voltage (Vout) is lower than the set voltage (Vref), to set a second signal (sigH) to its first binary state for a second duration (Ton), then, at the end of the second duration (Ton), set a third signal (sigL) to its first binary state for a third duration (Toff); the first circuit (310) is further configured, in a first operating mode, to control a passing state of the first switch (ITH) when the second signal (sigH) is in its first binary state and a passing state of the second switch (ITL) when the third signal (sigL) is in its first binary state, and, in a second operating mode, to put the first signal (sig2) in its first binary state as soon as one of the second and third signals (sigH, sigL) is in its first binary state. Voltage regulator according to claim 5, wherein the first mode of operation is of the pulse frequency modulation type. Voltage regulator according to claim 5 or 6, wherein, when the comparator (308) indicates that the first voltage (Vout) is lower than the set voltage (Vref), the first circuit (310, 212) is configured to: generating a first voltage ramp (Vp), comparing the first ramp (Vp) with a first threshold voltage (Vref), and setting the second signal (sigH) to its first binary state from the start (tl) of the first ramp (Vp) until the first ramp (Vp) crosses the first threshold voltage (Vref); and generate a second voltage ramp (Vn) when the first ramp (Vp) crosses the setpoint voltage (Vref), compare the second ramp (Vn) with a second threshold voltage (Vref), and set the third signal (sigL) to its first binary state from the start (t2) of the second ramp (Vn) until the second ramp (Vn) crosses the second threshold voltage (Vref).

8. Device comprising the voltage regulator (3) according to any one of claims 1 to 4, and a load (310) connected to the first output (300) of the regulator (3).

9. Device comprising the regulator (3) according to any one of claims 5 to 7, a load (310) connected to the first output (300) of the regulator (3), and an inductive element (L) connected between the first and second outputs (300; 400) of the regulator.

10. A device according to claim 9, wherein the device comprises an integrated circuit chip comprising the regulator (3), the inductive element (L) being arranged outside the chip.

11. Device according to any one of claims 8 to 10, wherein the device further comprises a capacitive element (C) connected to the first output (300) of the regulator (3).

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