Method for producing a microelectronic device comprising a wrapping grid

Abstract

Title: Method for producing a microelectronic device comprising a wrapping gate The invention relates to a method for producing a device comprising transistors (T1, T2). Advantageously, the channels (41) of the transistors (T1, T2) are produced by depositing a semiconductor material, preferably a 2D material, after selective removal of certain layers of the initial stack. The wrapping gates (50) are produced after selective removal of the other layers of the initial stack. The initial stack does not include the semiconductor material or the material of the gates (50). The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material. Figure for the abstract: Fig.16A

Description

Title of the invention: Method for producing a microelectronic device comprising a covering grid Technical field

[0001] The invention relates to the field of microelectronic technologies. It finds a particularly advantageous application in the manufacture of advanced FET (Field-Effect Transistor) type devices with a conformal gate and channel based on semiconductor materials, in particular based on two-dimensional (2D) materials or semiconductor oxides. STATE OF THE ART

[0002] The constant increase in transistor performance was first made possible by the reduction in transistor dimensions, for a classic MOSFET (“Metal-Oxide-Semiconductor Field-Effect Transistor”) architecture based on silicon.

[0003] This classic architecture then gave way to other types of architectures better suited to the performances specified in technological nodes below 12 nm. The so-called "finFET" architecture, for example, makes it possible to meet the performances set by the 7 nm and 5 nm technological nodes.

[0004] For the next technological nodes, particularly from 3 nm and below, other architectures offering better electrostatic control are necessary. An architecture envisaged to address the problems of these next technological nodes includes gate-enveloping transistors called GAA transistors (acronym for Gate Around), stacked on top of each other.

[0005] In parallel with the development of new architectures, materials other than silicon are being considered for the manufacture of transistor channels. Recently, 2D materials, which can be made up of a single layer of atoms, have emerged as promising candidates for use in electronic and optoelectronic devices comprising one or more elements of very low thickness.

[0006] The document “Challenges of Wafer-Scale Integration of 2D Semiconductors for High-Performance Transistor Circuits, Tom Schram et al., Adv. Mater., 2109796 (2022)” discloses a method for manufacturing stacked GAA transistors comprising a channel based on 2D material. In this method, the 2D materials considered are transition metal dichalcogenides in the form of monolayers. These 2D materials degrade easily when subjected to an average thermal budget. However, the different steps of the method disclosed by this document involve a substantial thermal budget, likely to degrade ther- only 2D material monolayers. It also appears that the steps of forming the internal spacers and replacing the sacrificial gate imply that parts of the 2D material monolayers are freely suspended. The mechanical stresses undergone by the 2D material monolayers are also likely to degrade the final structure and / or the targeted performances. The thermal and / or mechanical aspects of this manufacturing process are not completely appropriate for 2D material monolayers. Consequently, the development of such a process requires significant modifications and adaptations of existing technological processes. The modifications and adaptations proposed to date impose additional costs and / or limitations for the industrial manufacturing of GAA transistors based on 2D materials.

[0007] Controlled industrial manufacturing, satisfying the required quality requirements, is an important issue for the development of GAA transistor technologies based on 2D materials.

[0008] There is therefore a need for a method of manufacturing GAA transistors based on 2D materials having improved reproducibility and limited manufacturing cost.

[0009] One objective of the invention is to propose such a reproducible, controlled manufacturing method that limits the manufacturing cost. Another objective of the invention is to at least partially overcome the drawbacks of known methods. SUMMARY

[0010] To achieve these objectives, according to one embodiment, a method is provided for manufacturing a microelectronic device comprising at least one transistor comprising at least two channels based on a semiconductor material, a gate surrounding said channels, a source and a drain, said channels being stacked in a main direction z, said method comprising the following steps: - Providing on a substrate a stack in the main direction z comprising a plurality of first layers in a first material alternating with a plurality of second layers in a second material, the first and second materials being different from said semiconductor material forming each channel, - Form in this stack the first openings defining the first patterns, - Form a sacrificial grid straddling the first patterns and partly in the first openings, - Form the first spacers on the first patterns and bordering the sacrificial grid, - Form in the first patterns second openings defining second patterns, - Partially remove, from the second openings, the first material of the first layers selectively to the second material of the second layers, so as to form first spaces in line with the first spacers, - Fill the first spaces with a dielectric material to form internal spacers, - Completely removing, from the second openings, the second material of the second layers selectively to the first material of the first layers, so as to form second spaces and to expose parts of the sacrificial grid, - Forming a dielectric layer, called the gate dielectric layer, in the second spaces, on the exposed parts of the sacrificial gate and the remaining parts of the first layers, directly above the sacrificial gate, - Deposit a layer based on a semiconductor material in the second spaces, on the gate dielectric layer, directly above the sacrificial gate and the first spacers, so as to form: • channels based on the semiconductor material directly above the sacrificial gate, and • a source and a drain based on the semiconductor material directly above the first spacers, - Preferably form source and drain contacts in the second openings, - Remove the sacrificial grid so as to form third openings, - Completely remove, from the third openings, the first material from the remaining parts of the first layers, so as to form third spaces surrounding the channels based on the semiconductor material, - Fill the third spaces with a material, called gate material, so as to form a so-called wrapping gate completely surrounding the channels of the at least one transistor.

[0011] A principle of the method according to the invention consists in selectively replacing certain layers of the initial stack with a semiconductor material in order to form the channels of the transistor. The initial stack does not include the semiconductor material. The subsequent deposition of the semiconductor material aims to better preserve the semiconductor material. According to a preferred possibility, the semiconductor material is a two-dimensional (2D) material chosen from transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S) or selenium (Se).

[0012] Thus, unlike known methods which envisage the formation of layers at 2D material base in the initial stack, from the start of the process, the process according to the invention makes it possible to introduce layers of 2D material at the end of the process, after structuring the stack and in particular after the formation of the internal spacers. This advantageously makes it possible to limit the risk of degradation of the 2D material during the process. The 2D material is not exposed at all stages of the manufacturing process. The 2D material is thus preserved.

[0013] Furthermore, the 2D material layers are not freely suspended during the method according to the invention. The gate dielectric layer coats and holds the 2D material portions around which the encapsulating gate is formed. The mechanical strength is improved. The integrity of the structure is thus preserved.

[0014] Furthermore, the late introduction of the 2D material during the manufacturing process makes it possible to use standard microelectronics technologies for the formation and structuring of the stack. There is no need to modify or adapt the standard technological structuring steps to the constraints of using the 2D material. The costs of the process are thus advantageously limited. The process can also be more easily implemented in existing production lines.

[0015] Other objects, features and advantages of the present invention will become apparent from a consideration of the following description and accompanying drawings. It is understood that other advantages may be incorporated. BRIEF DESCRIPTION OF THE FIGURES

[0016] [Fig. 1 A] [Fig.2A] [Fig.3A] [Fig.4A] [Fig.5A] [Fig.6A] [Fig.7A] [Fig.8A] [Fig.9A] [Fig. 10 A][Fig.llA][Fig.l2A][Fig.l3A][Fig.l4A][Fig.l5A][Fig.l6A] Figures nA (n=l... 16) schematically illustrate, along xz cross sections, steps in manufacturing a device with superimposed transistors, according to embodiments of the present invention.

[0017] [Fig.lB][Fig.2B][Fig.3B][Fig.4B][Fig.5B][Fig.6B][Fig.7B][Fig.8B][Fig.9B][Fig.l0 B][Fig.llB][Fig.l2B][Fig.l3B][Fig.l4B][Fig.l5B][Fig.l6B] Figures nB (n=l... 16) schematically illustrate, according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device, according to embodiments of the present invention.

[0018] Figures 11A, 12A and 11B, 12B illustrate in particular alternative steps to the step illustrated in Figures 10A, 10B.

[0019] In the cross-sectional figures, section planes are indicated (A-A', B-B', ..., P-P') with cross-references to the section planes of the corresponding figures. The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily to the scale of the applications practices. In particular, on the schematic diagrams, the thicknesses and / or dimensions of the different layers, patterns and reliefs are not representative of reality. For reasons of clarity, not all alphanumeric references are systematically repeated from one figure to another. It is understood that the elements already described and referenced, when reproduced in another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned. A person skilled in the art will easily identify the same element reproduced in different figures. DETAILED DESCRIPTION

[0020] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0021] According to one example, the stack comprises an alternation of a first layer with a second layer. Preferably, said first layer and said second layer are in contact. According to one example, the final device comprises transistor channels formed after selective removal of the second layers of the initial stack. According to one example, the final device comprises conformal gates formed after selective removal of the first layers of the initial stack. The initial stack typically comprises neither the semiconductor material of the transistor channels nor the material of the conformal gates. According to an alternative possibility, the transistor channels are formed after selective removal of the first layers of the initial stack and the conformal gates are formed after selective removal of the second layers of the initial stack.

[0022] According to one example, the internal spacers are based on silicon nitride. The internal spacers are preferably in contact with the remaining portions of the first layers. Before forming the internal spacers, the partial removal of the first material of the first layers is configured to retain portions of the first layers between the first spaces. These portions are called remaining portions. The remaining portions of the first layers are thus located between the first spaces, in a direction of the xy plane.

[0023] The deposition of the layer based on the semiconductor material is done in the second spaces, between the remaining parts of the first layers and the sacrificial gate, along the main direction z. According to one example, the deposition of the layer based on the semiconductor material is also done on sides of the second pattern substantially parallel to the main direction z, in particular on sides of the first spacers and on sides of the internal spacers. This makes it easier to reconnect the source and drain contacts in the device.

[0024] According to one example, the deposition of the layer based on the semiconductor material is configured to form lateral portions of the layer based on the semiconductor material on sides of the second pattern substantially parallel to the main direction z, and horizontal portions of the layer based on the semiconductor material in the second spaces, such that the lateral portions are thicker than the horizontal portions. Thicker lateral portions make it possible to reduce the contact resistance of the source and drain contacts. The channels of the transistor are formed in the horizontal portions.

[0025] According to one example, the deposition of the layer based on the semiconductor material is configured to form lateral portions of the layer based on the semiconductor material on the first spacers and on the internal spacers.

[0026] According to one example, the method comprises forming source and drain contacts in the second openings.

[0027] According to one example, the formation of the wrapping gates is carried out after the deposition of the layer based on the semiconductor material. This type of process, typically called "gate last" where the functional gate is formed at the end of the process, replacing a sacrificial gate, makes it possible to preserve the dimensional characteristics of the gate. This makes it possible to obtain better control of the threshold voltage of the MOSFET transistors. The thermal budget linked to the deposition of the semiconductor material does not impact the equivalent thickness of gate oxide at the interface with the gate. The structural and electrical characteristics of the functional gate are better controlled.

[0028] According to one example, the deposition of the layer based on the semiconductor material is carried out by chemical vapor deposition or by atomic layer deposition. Chemical vapor depositions are easy to implement. Atomic layer depositions make it possible to precisely control the thickness of the layer based on the semiconductor material. These deposits make it possible to obtain very good conformity for the layer based on the semiconductor material.

[0029] According to one example, the semiconductor material is chosen from transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

[0030] According to another example, the semiconductor material is chosen based on a semiconductor oxide, for example based on IGZO (Zinc-indium-gallium oxide), In2O3, IWO (Tungsten-doped indium oxide), ITO (Indium-tin oxide), IAZO (Zinc-indium-aluminium oxide), InGaZnO, InGaO, InZnO or an amorphous semiconductor oxide.

[0031] According to one example, the first material is chosen from SiGe and the second material is chosen from Si, or vice versa. These materials can be easily epitaxied by conventional technological processes of microelectronics. This makes it possible to benefit existing technological pathways. The cost of the process is reduced.

[0032] According to one example, the formation of the sacrificial gate is carried out in such a way that the sacrificial gate extends over an entire height of the first openings. According to one example, the first openings extend over the entire height of the stack of the first and second layers. The sacrificial gate extends over the entire height of the stack. The sacrificial gate typically rests on the substrate. This makes it possible to provide access to all the layers of the stack via the third openings.

[0033] According to one example, the second patterns each comprise a central portion directly above the sacrificial grid and first and second peripheral portions on either side of the central portion, directly above the first spacers.

[0034] According to one example, the deposition of the layer based on the semiconductor material is configured so that the layer based on the semiconductor material completely fills the second spaces.

[0035] According to another example, the deposition of the layer based on the semiconductor material is configured so that the layer based on the semiconductor material partially fills the second spaces. According to one example, the method further comprises, after deposition of the layer based on the semiconductor material, a deposition of a dielectric layer configured to fill the second spaces. This makes it possible to form a layer based on the semiconductor material of low thickness, without constraint on the thickness of the second layers of the stack. The layer based on the semiconductor material may have a thickness less than that of the second layers of the initial stack.

[0036] According to one example, the substrate is a solid silicon-based substrate.

[0037] According to one example, the stack comprises at least three first layers of the first material alternating with three second layers of the second material.

[0038] According to one example, the stack comprises as many first layers of the first material as second layers of the second material.

[0039] According to one example, the first openings are formed along a longitudinal direction x and the second openings are formed along a transverse direction y perpendicular to the longitudinal direction x, said first and second openings extending to the substrate.

[0040] According to one example, the removal of the first material of the first layers selectively to the second material of the second layers is carried out by a first selective etching having a SiO:2O selectivity of at least 5:1, preferably at least 10:1. This first selective etching is typically stopped at time.

[0041] According to one example, the removal of the second material of the second layers selectively to the first material of the first layers is carried out by a second selective etching having an S2o:io selectivity of at least 5:1, preferably at least 10:1.

[0042] According to one example, the deposition of the layer based on the semiconductor material is configured to form lateral portions of the layer based on the semiconductor material on flanks of the second pattern in the second openings. According to one example, the method further comprises forming source and drain contacts in said second openings and on the lateral portions of the layer based on the semiconductor material, before removing the sacrificial gate.

[0043] Unless incompatibility exists, it is understood that all of the above optional features may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention. The features and advantages of one aspect of the invention, for example the device or the method, may be adapted mutatis mutandis to the other aspect of the invention.

[0044] The invention relates generally to a method for manufacturing a microelectronic device with GAA transistors. Such a microelectronic device may have a "GAA stacked nanosheet" type architecture, i.e. with stacked nanosheets and a fully encapsulating gate. An architecture with stacked nanowires and a fully encapsulating gate is also possible.

[0045] The nanowires or nanosheets typically each comprise a conduction channel of a transistor. These channels are stacked in a z direction. This means that they each occupy a level of given altitude in the z direction. A level can be defined between two planes perpendicular to the z direction.

[0046] Advantageously, the method according to the invention can be implemented for the production of GAA MOS transistors for the 5 nm and sub-5 nm technological nodes.

[0047] A microelectronic device comprising superimposed GAA transistors can be advantageously integrated into logic systems having 3D architectures. These transistors can in particular be associated with other structural or functional elements so as to design complex systems.

[0048] A particular aspect of the invention concerns the implementation of 2D materials to produce the nanowires or nanosheets of the device.

[0049] 2D materials typically correspond to compounds with a lamellar structure consisting of two-dimensional sheets, stacked along the crystallographic axis c. The atomic bonds within each sheet are strong, covalent in nature. The bonds between sheets are much weaker, of the Van der Waals type. These two-dimensional sheets are also called monolayers.

[0050] In the context of the present invention, the monolayers are preferably semiconductor monolayers of the MX2 type where M is molybdenum (Mo) or tungsten (W) and X from sulfur (S) or selenium (Se). Each "monolayer" here is composed of a plane of metal cations M inserted between two planes of anions X. A monolayer therefore typically comprises three atomic planes: the transition metal atoms (Mo or W) form a plane sandwiched between two planes of chalcogens (S, Se or Te, for example). Each transition metal atom is connected to six chalcogen atoms. These anions are in trigonal prismatic coordination with respect to the metal atoms. Monolayers of transition metal dichalcogenides MX2 have a hexagonal atomic lattice.

[0051] The monolayers of transition metal dichalcogenides MX2 are preferably based on molybdenum disulfide MoS2, MoSe2, MoTe2, WS2, WSe2.

[0052] An alternative possibility concerns the implementation of semiconductor oxides to produce the nanowires or nanosheets of the device, for example IWO, IGZO, ITO, InGaZnO, InGaO, InZnO, In2O3, IAZO. Another possibility concerns the implementation of graphene, hexagonal boron nitride "h-BN", phosphorene (also known as "Black Phosphorous" BP), in particular in the form of a monolayer.

[0053] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0054] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements. Thus, a spacer based on silicon nitride SiN may for example comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even a silicon oxynitride (SiON).

[0055] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 20. In the present invention, the dielectric layer may have ferroelectric properties.

[0056] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the stages follow one another immediately, with intermediate stages being able to separate them.

[0057] Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0058] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.

[0059] The term “selective etching with respect to” or “etching having selectivity with respect to” means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and having an etching rate of the material A greater than the etching rate of the material B. The selectivity is the ratio between the etching rate of the material A and the etching rate of the material B. It is noted SA:B. A selectivity SA:b of 10:1 means that the etching rate of the material A is 10 times greater than the etching rate of the material B.

[0060] The various patterns formed during the manufacturing steps typically have a structure intended to evolve during the process steps. Thus, the patterns may comprise the sacrificial layers of the initial stack, the layers based on 2D material or semiconductor oxide, the dielectric layers, continuous or discontinuous. The various patterns aim to form, at the end of the process, “transistor patterns” each comprising at least one conduction channel and a gate surrounding said channel, a dielectric barrier separating the gate and the channel, a source and a drain on either side of the channel. The assignment of the first and second layers in the initial stack may be reversed.

[0061] A preferably orthonormal reference frame, comprising the axes x, y, z is shown in the attached figures.

[0062] In the present patent application, we will preferably speak of thickness for a layer or a film, and of height for a device or a structure. The thickness is taken along a direction normal to the main extension plane of the layer or film. Thus, a surface layer of silicon (topSi) typically has a thickness along z. A gate pattern formed on such a surface layer has a height along z. The relative terms "on", "overcomes", "under", "underlying" refer to positions taken along the z direction. A "lateral" dimension corresponds to a dimension along a direction of the xy plane. A "lateral" or "laterally" extension means an extension along one or more directions of the xy plane.

[0063] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the cross-sectional figures.

[0064] The terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and..." and equivalents mean that the limits are included, unless otherwise stated.

[0065] The following description presents an example of implementation of the method according to the invention in a context of developing a complex 3D device. The scope of this description is obviously not limiting of the invention.

[0066] Figures 1A, 1B to 16A, 16B schematically illustrate steps in manufacturing a device comprising stacked GAA transistors. Figures nA (n=1... 16) correspond to first cross-sections each illustrating a different step of the manufacturing process. Figures nB (n=1... 16) correspond to second cross-sections each illustrating the same step as the corresponding figure nA.

[0067] As illustrated in Figures 1A, 1B, a first step consists of producing a stack E of semiconductor layers 10, 10 on a substrate S. The substrate S may be a substrate of the SOI (Silicon On Insulator), GeOI (Germanium On Insulator) or SGOI (Silicon-Germanium On Insulator) type. These known substrates comprise, according to the terminology common to those skilled in the art, a thick silicon SI layer called “Si bulk”, a silicon oxide S2 layer called “BOX” (Burried Oxide) and a thin surface layer, respectively based on silicon, germanium or silicon-germanium. This thin surface layer may advantageously correspond to the first layer 10 of the stack E.

[0068] Alternatively, the substrate S can be a bulk Si substrate.

[0069] According to one example, the stack E comprises an alternation of first layers 10 made of silicon-germanium (SiGe) and second layers 20 made of silicon (Si).

[0070] The concentration of Ge in the SiGe alloy can be 20%, 30% or 45% for example. This concentration of germanium is chosen so as to allow good selectivity of the etching of the SiGe compared to the Si, during the selective etching steps. The higher the concentration of Ge, the greater the selectivity to Si will be during the subsequent removal of the SiGe. This stack E is advantageously formed by epitaxy of the layers of SiGe 10 and Si 20. This step of forming the stack E is inexpensive and well known to those skilled in the art. The thicknesses of the Si and SiGe layers can typically be of the order of 10 nm, and more generally between 5 nm and 20 nm for example. In a known manner in order to avoid the formation of defects structural, the maximum thicknesses allowed for the SiGe layers depend in particular on the Ge concentration chosen.

[0071] In the example illustrated in figures 1A, 1B three layers 10 of SiGe are alternated with three layers 20 of epitaxially grown Si. A Si / SiGe super network is thus obtained. The number of layers of Si and SiGe can naturally be increased. This ultimately makes it possible to increase the number of stacked transistors in the final device.

[0072] Generally, the first material of the first layers 10 and the second material of the second layers 20 are chosen so that one can be etched selectively relative to the other. Thus, other pairs of first and second materials are possible. By respecting this condition of selectivity during etching, the first and second materials can be chosen from dielectric materials (oxides and nitrides for example), semiconductor materials, metallic materials.

[0073] As illustrated in Figures 2A, 2B, a conventional lithography / etching step is carried out in order to define first patterns 101M, and first openings 100. The etching is anisotropic and directed along z. It is configured to etch the stack E, here the Si / SiGe superlattice, over its entire height, stopping on the substrate S, here the BOX S2. It can be carried out by plasma using an HBr / 02 etching chemistry. The first patterns 10IM can have a length Li along x of between 10 nm and 500 nm. They preferably have a width h along y of between 10 nm and 120 nm, for example of the order of 40 nm. This first structuring of the E stack in the form of fins or "fins" according to current Anglo-Saxon terminology, makes it possible to define a plurality of superimposed nanowires or nanosheets.

[0074] For the sake of clarity, the following figures iB (i=3... 16) illustrate only one “end” pattern 101M.

[0075] As illustrated in Figures 3A, 3B, sacrificial gates 150 are then formed on the “end” patterns 101M. The formation of these sacrificial gates 150 is typically done by lithography / etching. The formation of the sacrificial gates 150 is configured so that the sacrificial gates 150 are straddled on the “end” patterns 101M, as illustrated in [Fig.3B]. The sacrificial gates 150 typically comprise an upper portion located on the “end” pattern 101M, and side portions located on the lateral flanks of the “end” pattern 101M. The sacrificial grids 150 typically rest on the substrate S. At this stage, the sacrificial grids 150 are typically surmounted by an etching mask 160, called a hard mask, implemented in the structuring of the sacrificial grids 150. The sacrificial grids 150 are for example based on polycrystalline silicon.A thin layer of SiO2 oxide, 7 nm thick for example, is preferably deposited beforehand. to the formation of the sacrificial gates 150. This thin layer of SiO2 oxide (not shown in the figures) is thus intercalated between the sacrificial gates 150 and the “end” patterns 101M. This thin layer of SiO2 oxide can form a stop layer for the subsequent etching of the sacrificial gates 150.

[0076] As illustrated in FIGS. 4A, 4B, first spacers 170 are then formed on the yz-oriented flanks of the sacrificial gates 150. In general, in z-projection, these spacers form a continuous ring around each sacrificial gate 150, with a closed contour. In cross-section, however, along the xz plane illustrated in [Fig.4A], the first spacer 170 has two facing portions on each of the flanks of the sacrificial gate 150. These two portions are generally designated as being the first spacers 170, even if they can be considered as belonging to a single spacer. The first spacers 170 typically extend to an upper face of the hard masks 160. The first spacers 170 are typically based on silicon nitride SiN or a dielectric material with a low dielectric constant, for example based on SiCO.

[0077] As illustrated in Figures 5A, 5B, after formation of the first spacers 170 by deposition / etching, the anisotropic etching along z is extended in order to define second patterns 102M, and second openings 200. The etching is configured to etch the stack E over its entire height, stopping on the substrate S. It can be carried out by plasma using HBr / O2 etching chemistry.

[0078] As illustrated in Figures 6A, 6B, after formation of the second openings 200, the first layers 10 are partially etched selectively to the second layers 20, to the substrate S and to the first spacers 170. The etching of the first material of the first layers 10 typically has a SiO:2o selectivity relative to the second material of the second layers 20, of at least 5:1, preferably at least 10:1. This partial etching aims to form first spaces 11 directly above the first spacers 170. This partial etching is typically stopped in time. It has an isotropic character and can be carried out by a wet or dry method, from the second openings 200. At the end of this partial etching, central parts of the first layers 10 are preserved under the sacrificial gates 150.

[0079] As illustrated in Figures 7A, 7B, the first spaces 11 are then filled with a dielectric material, for example with silicon nitride or with a low permittivity dielectric, to form internal spacers 171. These “internal” spacers 171 are integrated into the stack E, preferably directly above the first spacers 170. They are in contact with the central parts of the first layers 10. The formation of the internal spacers 171 is typically done from the second openings 200.

[0080] As illustrated in Figures 8A, 8B, the second layers 20 are then selectively etched at the central portions of the first layers 10 and at the internal spacers 171. The etching of the second material of the second layers 20 typically has a selectivity S2o:io with respect to the first material of the first layers 10, of at least 5:1, preferably at least 10:1. This total etching can be stopped at the time, possibly after an over-etching time intended to guarantee the total removal of the second material of the second layers 20. This total etching has an isotropic character and can be carried out by a wet or dry method, from the second openings 200. At the end of this etching, the second layers 20 are completely removed to form second spaces 21. The central portions of the first layers 10 are held by the sacrificial gates 150, as illustrated in [Fig.8B].

[0081] As illustrated in Figures 9A, 9B, a dielectric layer 30 is then deposited in the second spaces 21. This dielectric layer 30 is typically based on a high permittivity material, for example based on HfO2. The dielectric layer 30 is intended to form the gate dielectric layer between the channels of the GA A transistors and their surrounding gates. It can be formed by chemical vapor deposition CVD (acronym for “Chemical Vapor Deposition”), by chemical vapor deposition with organometallic precursors MOCVD (acronym for “Metal Organic Chemical Vapor Deposition”) or by atomic layer deposition ALD (acronym for “Atomic Layer Deposition”). It thus covers at least the central parts of the first layers 10 and the exposed lower face of the sacrificial gate 150, and preferably the internal spacers 171, and the first spacers 170.The dielectric layer 30 typically has a thickness of between 1 nm and 5 nm. According to an alternative example, this layer 30 may be based on a ferroelectric material such as HfZrO2, HZO, Si-doped HfO2 for example. Such a ferroelectric layer 30 may be advantageously used for producing memory transistors of the FeFET type (acronym for “ferroelectric field-effect transistor”).

[0082] As illustrated in Figures 10A, 10B, according to a first embodiment, a layer 40 based on a semiconductor material is then deposited on the gate dielectric layer 30 in the second spaces 21. The deposition of the semiconductor material is here configured so that the layer 40 completely fills the second spaces 21. The portions of the layer 40 located in the second spaces 21 thus have a perfectly controlled thickness, close to the thickness of the initial second layers. This layer 40 is intended to form the channels 41 of the GAA transistors directly above the sacrificial gates 150 and the central parts of the first layers 10. This layer 40 is also intended to form the sources 42 and the drains 43 of the GAA transistors directly above the first spacers 170 and the internal spacers 171.

[0083] The layer 40 is also typically deposited outside the second spaces 21, on the sides of the first spacers 170 and the internal spacers 171. This makes it possible to improve the contact recovery with the sources 42 and the drains 43 of the GAA transistors. The layer 40 thus has horizontal portions in the second spaces 21, in particular between the remaining parts of the first layers, and vertical portions on the sides of the first spacers 170 and the internal spacers 171. According to one possibility, the thickness of the vertical portions of the layer 40 is greater than the thickness of the horizontal portions of the layer 40. This makes it possible to reduce the contact resistance for the sources 42 and the drains 43 of the GAA transistors.The sources 42 and the drains 43 of the GAA transistors may comprise the horizontal portions directly above the first spacers 170 and the internal spacers 171, and at least in part the vertical portions on the sides of the first spacers 170 and the internal spacers 171.

[0084] The semiconductor material of the layer 40 is advantageously a two-dimensional material taken from the transition metal dichalcogenides MX2 with M molybdenum (Mo) or tungsten (W), and X sulfur (S), selenium (Se) or tellurium (Te). Such a 2D material can advantageously be deposited in the form of a thin layer comprising 1 to 10 atomic layers, preferably 1 to 5 atomic layers. The deposition of this 2D material can be done by CVD, MOCVD or ALD. Alternatively, the semiconductor material of layer 40 is a semiconductor oxide such as 1TTO (acronym for "Indium Tin Oxide"), IGZO (acronym for "Indium Gallium Zinc Oxide"), 1TW0 (meaning "Tungsten Doped Indium Oxide"), or indium oxide In2O3.Alternatively, the semiconductor material of layer 40 is graphene, hexagonal boron nitride "h-BN", phosphorene (also known as "Black Phosphorous" BP), in the form of a monolayer or a thin layer comprising 1 to 10 atomic layers, preferably 1 to 5 atomic layers.

[0085] As illustrated in Figures 1 1A, 1 1B, according to a second embodiment, the layer 40 based on the semiconductor material is deposited on the gate dielectric layer 30 in the second spaces 21 without completely filling the second spaces 21. In this case, the portions of the layer 40 located in the second spaces 21 may be significantly thinner than the initial second layers. These horizontal portions may have a thickness corresponding to only a few atomic layers, for example between 1 and 5 atomic layers of semiconductor material. The reduction in thickness of the layer 40 makes it possible to improve the electrostatic control of the transistors and therefore to reduce the dimensions of the channels 41. GAA transistors. The performance of the GAA transistors can be improved.

[0086] According to this second embodiment, as illustrated in FIGS. 12A, 12B, a dielectric plug 71 is then formed between the horizontal portions of the layer 40, in order to fill the second spaces 21. This makes it possible to electrically isolate the GAA transistors from each other. This also makes it possible to improve the mechanical strength of the device and / or to avoid deformations of the channels of the GAA transistors, for example by heating during operation. This dielectric plug 71 can be formed by CVD or ALD deposition followed by isotropic etching along z, in a conventional manner.

[0087] As illustrated in Figures 13A, 13B, the second openings can then be filled with one or more metal layers 60, for example based on Ti, TiN, W, or by other metals making it possible to ensure low contact resistance such as Bi, Ni, Au, Sb, etc., in order to form the source and drain contacts. Chemical mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the patterns 102M. The hard masks 160 are thus exposed.

[0088] As illustrated in Figures 14A, 14B, the hard masks 160 are first removed, then the sacrificial gates 150 are also removed. This removal can be carried out by wet etching with stopping on the thin stop layer based on SiO2 or another dielectric. The dielectric layer 30 is preserved. This wet etching typically has a high selectivity with respect to the stop layer and the first spacers 170. This wet etching can be based on a solution of ammonia salts TMAH (Tetramethylammonium Hydroxide) or TEAH (Tetraethylammonium Hydroxide). The SiO2-based barrier layer is then typically wet-etched to expose the dielectric layer 30. This removal of the sacrificial gates 150 makes it possible to form a main space 301 and third openings 300 opening onto the central portions of the first layers 10 ([Fig.l4B]).

[0089] As illustrated in figures 15A, 15B, the central parts of the first layers 10 are then completely removed by selective etching with respect to the dielectric layer 30, from the third openings 300. This etching aims to form third spaces 31 in place of the central parts of the first layers 10. This etching has an isotropic character and can be carried out by a wet or dry method, from the third openings 300.

[0090] As illustrated in Figures 16A, 16B, the main spaces 301 and the third spaces 31 are then filled with one or more metal layers 50, for example based on TiN, W, in order to form the surrounding gates of the GAA transistors. According to one possibility, before deposition of the metal layers 50, a dielectric layer based on a high permittivity material, for example based on HfO2, is previously deposited in the main spaces 301 and the third spaces 31. This allows to increase the thickness of the gate dielectric layer between the channels 41 of the GAA transistors and their surrounding gates 50. A chemical-mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the 102M patterns.

[0091] A microelectronic device comprising three transistors T1, T2, T3 stacked along z, with a covering gate 50, is thus advantageously obtained. The channels 41, the sources 42 and the drains 43 are preferably based on a two-dimensional material. Source and drain contacts 60S, 60, 60D electrically connect these GAA transistors T1, T2, T3 stacked along z.

[0092] In view of the above description, it appears clearly that the proposed method offers a particularly effective solution for forming stacked GAA transistors based on 2D material. This solution is furthermore advantageously compatible with standard microelectronics methods. The invention is however not limited to the embodiments previously described.

Claims

Claims

1. Method for manufacturing a microelectronic device comprising at least one transistor (T1, T2) comprising at least two channels (41a, 41b, 41c) based on a semiconductor material, a gate (50) surrounding said channels (41a, 41b, 41c), a source (42) and a drain (43), said channels (41a, 41b, 41c) being stacked in a main direction (z), said method comprising the following steps: Providing on a substrate (S) a stack (E) along the main direction (z) comprising a plurality of first layers (10) in a first material alternating with a plurality of second layers (20) in a second material, the first and second materials being different from the semiconductor material forming each channel (41a, 41b, 41c), Forming in this stack (E) first openings (100) defining first patterns (101M), Forming a sacrificial gate (150) straddling the first patterns (101M) and partly in the first openings (100), Form first spacers (170) on the first patterns (101M) and bordering the sacrificial grid (150), Forming in the first patterns (101M) second openings (200) defining second patterns (102M), Partially removing, from the second openings (200), the first material of the first layers (10) selectively to the second material of the second layers (20), so as to form first spaces (11) directly above the first spacers (170), Filling the first spaces (11) with a dielectric material to form internal spacers (171), Completely removing, from the second openings (200), the second material of the second layers (11) selectively to the first material of the first layers (10), so as to form second spaces (21) and to expose parts of the sacrificial grid (150), Forming a dielectric layer (30), called a gate dielectric layer, in the second spaces (21), on the exposed portions of the sacrificial gate (150) and the remaining portions of the first layers (10), directly above the sacrificial gate (150), • Depositing a layer (40) based on a semiconductor material in the second spaces (21), on the dielectric gate layer (30), directly above the sacrificial gate (150) and the first spacers (170), so as to form: • channels (41a, 41b, 41c) based on the semiconductor material directly above the sacrificial gate (150), and • a source (42) and a drain (43) based on the semiconductor material directly above the first spacers (170), • Removing the sacrificial gate (150) so as to form third openings (300), • Completely removing, from the third openings (300), the first material from the remaining parts of the first layers (10), so as to form third spaces (31) surrounding the channels (41) based on the semiconductor material, • Fill the third spaces (31) with a material, called gate material,so as to form a so-called wrapping gate (50) completely surrounding the channels (41a, 41b, 41c) of the at least one transistor (T1, T2).,

2. Method according to the preceding claim in which the deposition of the layer (40) based on the semiconductor material is also carried out on the first spacers (170) and on the internal spacers (171).

3. Method according to the preceding claim in which the deposition of the layer (40) based on the semiconductor material is configured to form lateral portions of layer (40) based on the semiconductor material on sides of the second pattern (102M) substantially parallel to the main direction (z), and horizontal portions of layer (40) based on the semiconductor material in the second spaces (21), such that the lateral portions are thicker than the horizontal portions.

4. Method according to any one of the preceding claims in which the formation of the encapsulating gate (50) is carried out after the deposition of the layer (40) based on the semiconductor material.

5. Method according to any one of the preceding claims in which the deposition of the layer (40) based on the semiconductor material is carried out by chemical vapor deposition or by atomic layer deposition.

6. A method according to any preceding claim wherein the semiconductor material is a two-dimensional (2D) material selected from transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

7. Method according to any one of claims 1 to 5 in which the semiconductor material is chosen from a semiconductor oxide, or graphene, hexagonal boron nitride or phosphorene.

8. A method according to any one of the preceding claims wherein the first material is chosen from SiGe and the second material is chosen from Si or vice versa.

9. A method according to any preceding claim wherein the formation of the sacrificial grid (150) is carried out such that the sacrificial grid (150) extends over an entire height of the first openings (100).

10. Method according to any one of the preceding claims in which the deposition of the layer (40) based on the semiconductor material is configured so that the layer (40) based on the semiconductor material completely fills the second spaces (21).

11. Method according to any one of claims 1 to 9 wherein the deposition of the layer (40) based on the semiconductor material is configured so that the layer (40) based on the semiconductor material partially fills the second spaces (21), said method further comprising, after deposition of the layer (40) based on the semiconductor material, a deposition of a dielectric layer (71) configured to fill the second spaces (21).

12. A method according to any preceding claim wherein the substrate (S) is a bulk silicon-based substrate.

13. A method according to any preceding claim wherein the first openings (100) are formed along a longitudinal direction (x) and the second openings (200) are formed along a transverse direction (y) perpendicular to the longitudinal direction (x), said first and second openings (100, 200) extending to the substrate (S).

14. Method according to any one of the preceding claims in which the stack (E) comprises as many first layers (10) of the first material as second layers (20) of the second material.

15. Method according to any one of the preceding claims in which the deposition of the layer (40) based on the semiconductor material is configured to form lateral portions of layer (40) based on the semiconductor material on flanks of the second pattern (102M) in the second openings (200), the method further comprising a formation of source and drain contacts (60S, 60, 60D) in said second openings (200) and on the lateral portions of layer (40) based on the semiconductor material, before the removal of the sacrificial gate (150).

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