Method of producing a device with superimposed transistors

Abstract

Title: Method for producing a device with stacked transistors The subject of the invention is a device comprising two transistors (T1, T2) stacked along z, the first transistor (T1) comprising channels (41a) stacked along z and first source and drain contacts (60Sa, 60Sd), the second transistor (T2) comprising channels (41b) stacked z and second source and drain contacts (60Sb, 60Db), the device being characterized in that the first source contact (respectively drain) and the second source contact (respectively drain) are distinct and isolated from each other by a first gate dielectric layer (31) and by a second gate dielectric layer (35). The invention also relates to a method for manufacturing this device. Figure for the abstract: Fig. 34A

Description

Title of the invention: Method for producing a device with superimposed transistors Technical field

[0001] The invention relates to the field of microelectronic technologies. It finds a particularly advantageous application in the manufacture of advanced CFET type devices (Complementary Field-Effect Transistors) comprising two co-integrated transistors, N-type and P-type, with a conformal gate. STATE OF THE ART

[0002] The evolution of transistor architecture has played a crucial role in the constant improvement of the performance of microelectronic devices and their continued miniaturization.

[0003] The classic MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) architecture based on silicon has been the foundation of the semiconductor industry.

[0004] To meet the increasing requirements for integration density, this classic architecture then gave way to other types of architectures better suited to the performances specified in technology nodes below 12 nm. The so-called "finFET" architecture, for example, makes it possible to meet the performances set by the 7 nm and 5 nm technology nodes.

[0005] More recently, an architecture of transistors with a surrounding gate called GAA transistors (acronym for Gate Ail Around) and with superimposed channels has emerged. This architecture responds to the problems of the next technological nodes, in particular from 3 nm and below.

[0006] In CFET devices adopting this GAA transistor architecture, two N and P type transistors with conformal gates and distinct stacked channel structures are conventionally juxtaposed.

[0007] In order to increase the integration density of microelectronic devices, other GAA architectures for CFETs have been developed. Document FR3090998 discloses an architecture based on the superposition of two N and P type GAA transistors. This makes it possible to reduce the size of the device in an integrated circuit. The method disclosed by this document nevertheless remains complex to implement. The number of process steps is high. The cost of the method, which depends in particular on the number of steps to be implemented, is significant.

[0008] Controlled industrial manufacturing, meeting the required quality requirements and limiting process costs, is an important issue for the development of GAA CFET transistor technologies.

[0009] There is therefore a need for a method of manufacturing GAA CFET transistors having a limited manufacturing cost.

[0010] One objective of the invention is to meet this need by proposing such a manufacturing method. Another objective of the invention is to propose a device having a GAA CFET architecture that can be reproduced more easily and with greater control. Another objective of the invention is to at least partially overcome the drawbacks of known methods and devices. SUMMARY

[0011] To achieve this objective, according to one embodiment, a microelectronic device is provided comprising at least two transistors superimposed along a main direction z, comprising: - A first transistor of a first type, comprising: • at least two first channels stacked along the main direction z, each channel being based on a first semiconductor material, • a first source and a first drain based on said first semiconductor material, • a first source contact and a first drain contact connected respectively to said first source and said first drain, • a first grid called a wrap-around grid, completely surrounding at least one of the first channels, • a first dielectric gate layer separating each first channel from the first encapsulating gate, - A second transistor of a second type, comprising: • at least two second channels stacked along the main direction z, each channel being based on a second semiconductor material, • a second source and a second drain based on said second semiconductor material, • a second source contact and a second drain contact connected respectively to said second source and said second drain, • a second grid called a wrap-around grid, completely surrounding at least one of the second channels, • a second gate dielectric layer separating each second channel from the second encapsulating gate.

[0012] Advantageously, the first source contact and one of the second source contact and the second drain contact are distinct and isolated from each other by the first gate dielectric layer and by the second gate dielectric layer.

[0013] Advantageously, the first drain contact and the other of the second source contact and the second drain contact are distinct and isolated from each other by said first gate dielectric layer and by said second gate dielectric layer.

[0014] In this architecture, the first and second gate dielectric layers advantageously have at least two functions: the insulation of the first and second channels with respect to the first and second gates, and the insulation of the first and second contacts between them.

[0015] This architecture is therefore designed by minimizing the number of distinct elements. As each distinct element typically requires at least one manufacturing step, this makes it possible to envisage a manufacturing method for this device architecture comprising a limited number of steps.

[0016] Another aspect of the invention relates to a method of manufacturing such a microelectronic device, comprising the following steps: - Providing on a substrate a first stack and a second stack superimposed in the z direction, said first stack comprising a plurality of first layers in a first material, alternating with a plurality of second layers in a second material, said second stack comprising a plurality of third layers in a third material, alternating with a plurality of fourth layers in a fourth material, said first and second stacks being separated by a dielectric layer, - Form, in the first stack and the second superimposed stack, first openings defining first patterns, - Form a sacrificial grid straddling the first patterns and partly in the first openings, - Form in the first patterns second openings defining second patterns, on either side of the sacrificial grid, - Form a first sacrificial layer in the second openings, on the sides of the second layers of the first stack, - Form a second sacrificial layer on the first sacrificial layer and on the sides of the fourth layers of the second stack, leaving an access space to the first sacrificial layer, - Remove the first sacrificial layer, from the access space, while keeping the second sacrificial layer, so as to form first cavities opening onto the sides of the second layers of the first stack, Removing from the first cavities the second material of the second layers selectively to the first material of the first layers, so as to form second spaces, Forming a first gate dielectric layer in the second spaces on exposed portions of the first material of the first layers, and in the first cavities on exposed portions of the second sacrificial layer, Depositing a layer based on a first semiconductor material in the second spaces, on the first gate dielectric layer, so as to form: • the first channels of the first transistor based on the first semiconductor material, directly above the sacrificial gate, • a first source and a first drain of the first transistor based on the first semiconductor material, on either side of the first channels of the first transistor, Filling the first cavities with a first electrically conductive material to form first source and drain contacts of the first transistor, Remove the second sacrificial layer, so as to form second cavities opening onto the sides of the fourth layers of the second stack, Removing from the second cavities the fourth material of the fourth layers selectively to the third material of the third layers, so as to form fourth spaces, Forming a second gate dielectric layer in the fourth spaces on exposed portions of the third material of the third layers, and in the second cavities on the first gate dielectric layer, Deposit a layer based on a second semiconductor material in the fourth spaces, on the second gate dielectric layer, so as to form: • second channels of the second transistor based on the second semiconductor material, directly above the sacrificial gate, • a second source and a second drain of the second transistor based on the second semiconductor material, on either side of the second channels of the second transistor, - Filling the second cavities with a second electrically conductive material to form second source and drain contacts of the second transistor, - Removing the sacrificial grid so as to form third openings, - Removing from the third openings, the first layers and the third layers, to form first spaces and third spaces respectively, - Fill the first and third spaces, to form respectively the first and second surrounding gates of the first and second transistors.

[0017] In this method, the first transistor is formed from the first stack and the second transistor is formed from the second stack. A principle of the method according to the invention consists in selectively replacing certain layers of the initial stacks, here the first and third layers, to typically form two superimposed gates, surrounding layers based on a semiconductor material forming the channels of the transistors, here the second and fourth layers. The advantages mentioned above for the device apply mutatis mutandis to the method according to the invention. In particular, the number of steps is reduced compared to known methods.

[0018] According to one possibility, the second and fourth layers are subsequently replaced by one or more semiconductor materials in order to form the channels of the transistors. In this case, the initial stacks do not include the semiconductor materials forming the channels of the transistors. The subsequent deposition of the semiconductor materials aims to better preserve the semiconductor materials. According to a preferred possibility, the semiconductor materials of the first and second channels are based on a two-dimensional (2D) material chosen from MX2 transition metal dichalcogenides with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S) or selenium (Se). The method makes it possible in particular to introduce layers of 2D material at the end of the process, after structuring the stack and in particular after the formation of the spacers. This advantageously makes it possible to limit the risk of degradation of the 2D material during the process.The 2D material is not exposed at all stages of the manufacturing process. The 2D material is thus preserved.

[0019] Such late introduction of the 2D material during the manufacturing process further allows the use of standard microelectronic technologies for the formation and structuring of the stack. There is no need to modify or adapt the standard technological structuring steps to the constraints of using the 2D material. The costs of the process are thus advantageously limited. The process can be more easily implemented in existing production lines.

[0020] Other objects, features and advantages of the present invention will become apparent from a consideration of the following description and accompanying drawings. It is understood that other advantages may be incorporated. BRIEF DESCRIPTION OF THE FIGURES

[0021] [Fig.lA][Fig.2A][Fig.3A][Fig.4][Fig.5][Fig.6][Fig.7][Fig.8][Fig.9][Fig.l0][Fig.ll][ Fig.l2][Fig.l3][Fig.l4][Fig.l5][Fig.l6][Fig.l7][Fig.l8][Fig.l9][Fig.20][Fig.21][Fig.2 2][Fig.23][Fig.24A] Figures 1A, 2A, 3A, 4, ..., 23 and 24A schematically illustrate, along xz cross sections, steps for manufacturing a GAA CFET transistor device, common to the first and second embodiments of the present invention.

[0022] [Fig.1B][Fig.2B][Fig.3B][Fig.24B] Figures 1B, 2B, 3B and 24B schematically illustrate, according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device as those represented in figures nA (n=1, 2, 3, 24) respectively.

[0023] [Fig.25A][Fig.26A][Fig.27A] Figures nA (n=25...27) schematically illustrate according to xz cross sections the steps of manufacturing a GAA CFET transistor device which follow the common steps shown in figures 1A, 2A, 3A, 4, ..., 23 and 24A, according to a first embodiment of the present invention.

[0024] [Fig.25B][Fig.26B][Fig.27B] Figures nB (n=25...27) schematically illustrate according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device as those represented in figures nA (n=25.. .27) respectively, according to a first embodiment of the present invention.

[0025] [Fig.28A][Fig.29A][Fig.30A][Fig.31A][Fig.32A][Fig.33A][Fig.34A] Figures nA (n=28...34) schematically illustrate according to xz cross sections the steps of manufacturing a GAA CFET transistor device which follow the common steps represented in figures 1A, 2A, 3A, 4, ..., 23 and 24A, according to a second embodiment of the present invention.

[0026] [Fig.28B][Fig.29B][Fig.30B][Fig.31B][Fig.32B][Fig.33B][Fig.34B] Figures nB (n=28...34) schematically illustrate according to transverse sections yz indicated in the corresponding figures nA, the same steps of manufacturing the device as those represented in figures nA (n=28...34) respectively, according to a second embodiment of the present invention.

[0027] In the cross-sectional figures, section planes are indicated (A-A', B-B', ..., M-M') with cross references to the section planes of the corresponding figures. The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses and / or dimensions of the different layers, patterns and reliefs are not representative of reality. For reasons of clarity, not all alphanumeric references are systematically repeated from one figure to another. It is understood that the elements already described and referenced, when reproduced in another figure, typically bear the same alphanumeric references, even if these are not explicitly mentioned. A person skilled in the art will easily identify the same element reproduced in different figures. DETAILED DESCRIPTION

[0028] Before commencing a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0029] According to a first embodiment, the first source contact and the second source contact are distinct and isolated from each other by the first gate dielectric layer and by the second gate dielectric layer, and the first drain contact and the second drain contact are distinct and isolated from each other by said first gate dielectric layer and by said second gate dielectric layer.

[0030] According to a second embodiment, the first source contact and the second drain contact are distinct and isolated from each other by the first gate dielectric layer and by the second gate dielectric layer, and the first drain contact and the second source contact are distinct and isolated from each other by said first gate dielectric layer and by said second gate dielectric layer.

[0031] According to one example, the first gate dielectric layer and the second gate dielectric layer are based on the same material, thereby forming a continuous dielectric layer between the first and second source contacts and between the first and second drain contacts.

[0032] According to one example, the first semiconductor material has a first type of conductivity, for example N-type, and the second semiconductor material has a second type of conductivity different from the first type of conductivity, for example P-type.

[0033] According to one example, the first semiconductor material and / or the second semiconductor material are based on a two-dimensional (2D) material chosen from dichal-cogenides of transition metals MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

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[0042] According to another example, the first semiconductor material and / or the second semiconductor material are based on a semiconductor oxide, for example based on IGZO (Indium Gallium Zinc Oxide), In2O3, IWO (tungsten doped indium oxide), ITO (Indium Tin Oxide), IAZO (Indium Aluminum Zinc Oxide), InGaZnO, InGaO, InZnO or an amorphous semiconductor oxide. According to another example, the first semiconductor material and / or the second semiconductor material are based on graphene, hexagonal boron nitride “h-BN”, phosphorene. According to one example, the first and second wrapping gates form a single gate common to the first and second transistors. According to an alternative example, the first and second wrapping grids are distinct. In one example, the first gate completely surrounds each first channel of the first transistor, and the second gate completely surrounds each second channel of the second transistor. According to one example, the method further comprises the following optional steps: - Forming first spacers between the first wrapping gate and the first source and drain contacts, Forming second spacers between the second wrap-around gate and the second source and drain contacts According to one example, the formation of the first and second spacers comprises the following steps: - Preferably form spacers bordering the sacrificial grid and resting on the first patterns, - Before forming the first sacrificial layer, partially removing, from the second openings, the first material of the first layers selectively to the second material of the second layers, so as to form first spacer cavities, preferably directly above the spacers, - Fill the first spacer cavities with a first dielectric material to form the first spacers, - Before forming the second sacrificial layer, partially removing, from the second openings, the third material of the third layers selectively to the fourth material of the fourth layers, so as to form second spacer cavities, preferably directly above the spacers, - Fill the second spacer cavities with a second dielectric material to form the second spacers. The first and second spacers are typically called internal spacers.

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[0052] In one example, the first and second dielectric materials are identical. In one example, the first material of the first layers is identical to the third material of the third layers. In one example, the first and second spacers are formed simultaneously. According to one example, the sacrificial grid comprises a first part and a second distinct part. According to one example, the removal of the sacrificial grid includes: - a first removal of the first sacrificial gate portion, configured to form a third opening opening only onto sides of the first layers, on a first side only of the first pattern, followed by a removal of the first layers from said third opening to form the first spaces, and a filling of said first spaces to form the first surrounding gate of the first transistor, and - a second removal of the second sacrificial gate portion, configured to form a third opening opening only onto sides of the third layers, on only a second side of the first pattern, followed by removal of the third layers from said third opening to form the third spaces, and filling of said third spaces to form the second surrounding gate of the second transistor. In one example, the second wrapping grid is formed before the first wrapping grid. According to one example, the first removal comprises forming a portion of insulation on flanks of the second stack at the first side of the first pattern, before filling the first spaces to form the first wrapping grid. In one example, the second removal includes forming a second portion of insulation on flanks of the first stack at the second side of the first pattern, before filling the third spaces to form the second enclosing grid. According to one example, the method comprises, prior to removing the sacrificial gate, separating the sacrificial gate into a distinct first portion and second portion, said first and second sacrificial gate portions extending respectively on the first and second sides of the first pattern, the first removal being performed on the first gate portion and the second removal being performed on the second gate portion. According to one example, before forming the sacrificial gate, a hard mask is formed on the first patterns, and the separation of the sacrificial gate is carried out by chemical-mechanical polishing with stopping on said hard mask.

[0053] The invention relates generally to a microelectronic device with GAA transistors and a manufacturing method. Such a microelectronic device may have a "GAA stacked nanosheet" type architecture, i.e. with stacked nanosheets and a fully encapsulating gate. An architecture with stacked nanowires and a fully encapsulating gate is also possible.

[0054] The nanowires or nanosheets typically each comprise a conduction channel of a transistor. These channels are stacked in a z direction. This means that they each occupy a level of given altitude in the z direction. A level can be defined between two planes perpendicular to the z direction.

[0055] Advantageously, the method according to the invention can be implemented for the production of GAA MOS transistors for the 5 nm and sub-5 nm technological nodes.

[0056] A microelectronic device comprising GAA transistors with stacked channels can be advantageously integrated into logic systems having 3D architectures. These transistors can in particular be associated with other structural or functional elements so as to design complex systems.

[0057] A particular aspect of the invention relates to the implementation of 2D materials to produce the nanowires or nanosheets of the device. These 2D materials have semiconductor properties, in particular through the presence of an electronic gap.

[0058] 2D materials typically correspond to compounds with a lamellar structure consisting of two-dimensional sheets, stacked along the crystallographic axis c. The atomic bonds within each sheet are strong, covalent in nature. The bonds between sheets are much weaker, of the Van der Waals type. These two-dimensional sheets are also called monolayers.

[0059] In the context of the present invention, the monolayers are preferably semiconductor monolayers of the MX2 type where M is molybdenum (Mo) or tungsten (W) and X is sulfur (S) or selenium (Se). Each "monolayer" is here composed of a plane of metal cations M inserted between two planes of anions X. A monolayer therefore typically comprises three atomic planes: the atoms of the transition metal (Mo or W) form a plane sandwiched between two planes of chalcogens (S, Se or Te, for example). Each transition metal atom is connected to six chalcogen atoms. These anions are in trigonal prismatic coordination with respect to the metal atoms. The monolayers of MX2 transition metal dichalcogenides have a hexagonal atomic lattice.

[0060] The monolayers of transition metal dichalcogenides MX2 are preferably based on molybdenum disulfide MoS2, MoSe2, MoTe2, WS2, WSe2.

[0061] An alternative possibility concerns the implementation of semiconductor oxides to produce the nanowires or nanosheets of the device, for example IWO, IGZO, ITO, InGaZnO, InGaO, InZnO, In2O3, IAZO. Another possibility concerns the implementation work of graphene, hexagonal boron nitride "h-BN", phosphorene (also known as "Black Phosphorous" BP), notably in monolayer form.

[0062] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition or application of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0063] A substrate, a film, a layer, “based” on a material A, is understood to mean a substrate, a film, a layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements. Thus, a spacer based on silicon nitride SiN may for example comprise non-stoichiometric silicon nitride (SiN), or stoichiometric silicon nitride (Si3N4), or even a silicon oxynitride (SiON).

[0064] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 20.

[0065] Several embodiments of the invention implementing successive steps of the manufacturing method are described below. Unless explicitly stated, the adjective “successive” does not necessarily imply, even if this is generally preferred, that the steps follow one another immediately, intermediate steps being able to separate them.

[0066] Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0067] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean actions that are unitary and inseparable in time and in the sequence of phases of the process.

[0068] The term “selective etching with respect to” or “etching exhibiting selectivity with respect to” means etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching speed of the material A greater than the etching speed of the material B. The selectivity is the ratio of the etching rate of material A to the etching rate of material B. It is denoted SA:B. An SA:b selectivity of 10:1 means that the etching rate of material A is 10 times higher than the etching rate of material B.

[0069] The various patterns formed during the manufacturing steps typically have a structure intended to evolve during the process steps. Thus, the patterns may comprise the sacrificial layers of the initial stacks, the layers based on 2D material or semiconductor oxide, the dielectric layers, continuous or discontinuous. The various patterns aim to form, at the end of the process, “transistor patterns” each comprising at least one conduction channel, a source and a drain on either side of the channel and a gate surrounding said channel, a dielectric barrier separating the gate from the channel and the drain contacts, respectively the source contacts, from each other. The assignment of the first, second, third and fourth layers in the initial stacks may be reversed or permuted.

[0070] A preferably orthonormal reference frame, comprising the axes x, y, z is shown in the attached figures.

[0071] In the present patent application, we will preferably speak of thickness for a layer or a film, and of height for a device or a structure. The thickness is taken along a direction normal to the main extension plane of the layer or film. Thus, a surface layer of silicon (topSi) typically has a thickness along z. A gate pattern formed on such a surface layer has a height along z. The relative terms "on", "overcomes", "under", "underlying" refer to positions taken along the z direction. A "lateral" dimension corresponds to a dimension along a direction of the xy plane. A "lateral" or "laterally" extension is understood to mean an extension along one or more directions of the xy plane. The sides here typically extend along a yz plane.

[0072] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the cross-sectional figures.

[0073] The terms "substantially", "approximately", "of the order of" mean to within 10%, and preferably to within 5%. Furthermore, the terms "between ... and..." and equivalents mean that the limits are included, unless otherwise stated.

[0074] The following description presents examples of implementation of the method according to the invention in a context of developing a complex 3D device. The scope of this description is obviously not limiting of the invention.

[0075] Figures 1A, 1B, 2A, 2B, 3A, 3B, 4 to 23, 24A, 24B, 25A, 25B, 26A, 26B, 27A, 27B schematically illustrate steps of manufacturing a CFET device with Stacked GAA transistors having source and drain contacts insulated by at least one gate dielectric layer, according to a first embodiment of the present invention. Figures nA (n=1, 2, 3, 24, 25, 26, 27) and Figures 4 to 23 correspond to first transverse sections along an xz plane each illustrating a different step of the manufacturing process. Figures nB (n=1, 2, 3, 24, 25, 26, 27) correspond to second transverse sections along a yz plane each illustrating the same step as the corresponding figure nA.

[0076] As illustrated in Figures 1A, 1B, a first step consists in producing on a substrate S a superposition in the z direction of a first stack El comprising an alternation of semiconductor layers 1, 2 and a second stack E2 comprising an alternation of semiconductor layers 3, 4, the stacks El, E2 being separated by an insulating layer 201. The substrate S can be a substrate of the SOI (Silicon On Insulator), GeOI (Germanium On Insulator) or SGOI (Silicon-Germanium On Insulator) type. These known substrates comprise, according to the terminology common to those skilled in the art, a thick silicon SI layer called “Si bulk”, a silicon oxide S2 layer called “BOX” (Burried Oxide) and a thin superficial layer, respectively based on silicon, germanium or silicon-germanium.This thin surface layer can advantageously correspond to the first layer 1 of the first EL stack. Alternatively, the substrate S can be a massive “Si bulk” substrate.

[0077] The first stack E1 comprises, according to one example, an alternation of first layers 1 made of silicon-germanium (SiGe) and second layers 2 made of silicon (Si). Advantageously, the second stack E2 also comprises an alternation of third layers 3 made of silicon-germanium (SiGe) and fourth layers 4 made of silicon (Si). Generally speaking, the pair of materials forming the third layers 3 and the fourth layers 4 of the second stack E2 may be different from the pair of materials forming the first layers 1 and the second layers 2 of the first stack EL. In the following, the same pair of materials forming the layers 1, 2 and the layers 3, 4 is adopted.

[0078] The concentration of Ge in the SiGe alloy can be 20%, 30% or 45% for example. This concentration of germanium is chosen so as to allow good selectivity of the etching of SiGe compared to Si, during the selective etching steps. The higher the concentration of Ge, the greater the selectivity to Si will be during the subsequent removal of the SiGe.

[0079] The first stack E1 is typically formed on a first substrate and the second stack E2 is typically formed separately on a second substrate. The alternation of layers 1, 2 and 3, 4 in the respective stacks E1, E2 is advantageously formed by epitaxy of the layers of SiGe 1, 3 and Si 2, 4. This step of formation of each stack E1, E2 is inexpensive and well known to those skilled in the art. The thicknesses of the Si and SiGe layers can typically be of the order of 10 nm, and more generally between 5 nm and 20 nm for example. In a known manner in order to avoid the formation of structural defects, the maximum thicknesses permitted for the SiGe layers 1, 3 depend in particular on the Ge concentration chosen.

[0080] An oxide deposit, for example based on SiO2, is preferably carried out on each stack E1, E2. The assembly and superposition of the two stacks E1, E2 can then be carried out in a known manner by transfer and oxide / oxide bonding. After bonding, the first stack E1 is thus separated from the second stack E2 by a continuous insulating layer 201, the thickness of which can typically be between 10 nm and 100 nm.

[0081] In the example illustrated in Figures 1A, 1B, four layers 1, 3 of SiGe are respectively alternated with three layers 2, 4 of epitaxially grown Si. A Si / SiGe superlattice is thus obtained. The number of Si and SiGe layers can naturally be increased. This ultimately makes it possible to increase the number of stacked channels per transistor in the final device.

[0082] Generally, the material(s) forming layers 1, 3 and the material(s) forming layers 2, 4 are chosen so that some can be etched selectively relative to others, in particular that of layers 1 with respect to that of layers 2 or vice versa, and that of layers 3 with respect to that of layers 4 or vice versa. Thus, other pairs of materials are possible. By respecting this condition of selectivity during etching, the materials forming layers 1, 2, 3, 4 can be chosen from dielectric materials (oxides and nitrides for example), semiconductor materials, metallic materials.

[0083] As illustrated in Figures 2A, 2B, a conventional lithography / etching step is carried out in order to define first patterns 101M, and first openings 100. The etching is anisotropic and directed along z. It is configured to etch all of the stacks E1, E2, here the two Si / SiGe superlattices separated by the insulating layer 201, over its entire height, stopping on the substrate S, here the BOX S2. It can be carried out by plasma using an HBr / O2 etching chemistry. The first patterns 101M can have a length Li along x of between 10 nm and 500 nm. They preferably have a width li along y of between 10 nm and 120 nm, for example of the order of 40 nm. This first structuring of the El, E2 stacks in the form of fins or “fins” according to current Anglo-Saxon terminology, makes it possible to define a plurality of superimposed nanowires or nanosheets.

[0084] For the sake of clarity, the following figures iB (i=3, 24, ..., 34) illustrate only one “end” pattern 10IM.

[0085] As illustrated in Figures 3A, 3B, sacrificial gates 150 are then formed on the “end” patterns 101M. The formation of these sacrificial gates 150 is typically done by deposition then lithography / etching. The formation of the sacrificial gates 150 is configured so that the sacrificial gates 150 are straddled on the “end” patterns 101M, as illustrated in [Fig. 3B]. The sacrificial gates 150 typically comprise an upper portion located on the “end” pattern 101M, and lateral portions located on the lateral flanks of the “end” pattern 101M. The sacrificial grids 150 typically rest on the substrate S. At this stage, the sacrificial grids 150 are typically surmounted by an etching mask 161, called a hard mask, implemented in the structuring of the sacrificial grids 150.The sacrificial gates 150 comprise, for example, in a known manner, a thin oxide layer SiO2 (thickness between 3 nm and 7 nm for example) and a thick layer of polycrystalline silicon or amorphous silicon. The thin oxide layer SiO2 (not shown in the figures) can form a stop layer during the etching of the polycrystalline silicon of the sacrificial gates 150. This thin oxide layer SiO2 is thus intercalated between the sacrificial gates 150 and the “end” patterns 101M. The hard mask 161 can be based on silicon oxide SiO2, silicon nitride SiN, or a SiO2 / SiN bilayer.

[0086] As illustrated in [Fig. 4], spacers 170 are then formed on the yz-oriented flanks of the sacrificial gates 150. In general, in z-projection, these spacers form a continuous ring around each sacrificial gate 150, with a closed contour. In cross-section, however, along the xz plane illustrated in [Fig. 4], the spacer 170 has two facing portions on each of the flanks of the sacrificial gate 150. These two portions are generally designated as the spacers 170, even if they can be considered as belonging to a single spacer. The spacers 170 typically extend to an upper face of the hard mask 161. The spacers 170 are typically based on silicon nitride SiN or a dielectric material with a low dielectric constant, for example based on SiCO.

[0087] As illustrated in [Fig.5], after formation of the spacers 170 by deposition / etching, the anisotropic etching along z is extended in order to define second patterns 102M, and second openings 200. The etching is configured to etch all of the stacks E1, E2 over their entire height, stopping on the substrate S. It can be carried out by plasma using HBr / O2 etching chemistry.

[0088] As illustrated in [Fig.6], after formation of the second openings 200, the first layers 1 and the third layers 3 are partially etched selectively to the second layers 2 and to the fourth layers 4 respectively, to the insulating layer 201, to the substrate S and to the spacers 170. The first layers 1 and the third layers 3 are advantageously etched by the same etching. The etching of the material of layers 1, 3 typically has a Si:2 (S3:4) selectivity relative to the material of layers 2, 4, of at least 5:1, preferably at least 10:1. This partial etching aims to form first and third spaces 10, 30 in line with the spacers 170 respectively in the first and third layers 1, 3. This partial etching is typically stopped in time. It has an isotropic character and can be carried out by a wet or dry method, from the second openings 200. At the end of this partial etching, central parts of layers 1, 3 are preserved under the sacrificial gates 150.

[0089] As illustrated in [Fig.7], the first and third spaces 10, 30 are then filled with a dielectric material, for example with silicon nitride or with a low permittivity dielectric, to form first and third internal spacers 101, 131. These “internal” spacers 101, 131 are integrated into the stacks E1, E2, preferably directly above the spacers 170. They are in contact with the central parts of the layers 1, 3. The formation of the internal spacers 101, 131 is typically done from the second openings 200.

[0090] As illustrated in [Fig.8], a dielectric layer 202, for example based on SiO2, is deposited on and between the second patterns 102M so as to fill the openings 200. This dielectric layer 202 is then planarized, typically by chemical-mechanical polishing CMP with stopping on the hard mask 161.

[0091] As illustrated in [Fig.9], the dielectric layer 202 is opened by etching so as to partially reform the second openings 200. The second openings 200 here define the location of the contacts of the two stacked transistors.

[0092] As illustrated in [Fig. 10], a conformal oxide layer 12 is preferably first deposited in the openings 200. The oxide layer 12 covers the sides and the bottom of the second openings 200. A first sacrificial layer 13 is then deposited in the second openings 200 on the oxide layer 12, so as to fill the second openings 200. This first sacrificial layer 13 is typically based on polycrystalline silicon or amorphous silicon. The oxide layer 12 and the sacrificial layer 13 are then typically planarized by chemical mechanical polishing CMP with stopping on the hard mask 161.

[0093] As illustrated in [Fig.l 1], the first sacrificial layer 13 is then partially removed by wet etching so as to form an access space 400 located opposite the layers 3, 4 of the second stack. The etching is configured so that the remaining part of the first sacrificial layer 13 extends along z up to the insulating layer 201. This wet etching can be based on a solution of ammonia salts TM AH (Tetramethylammonium Hydroxide) or TEAH (Tetraethylammonium Hydroxide).

[0094] As illustrated in [Fig. 12], a second sacrificial layer 14, for example based on SiO2, is formed in the access space 400, against the pattern 102M and on the remaining part of the first sacrificial layer 13. The formation of this second sacrificial layer 14 is typically done by deposition then etching. The second sacrificial layer 14 typically extends along z from the insulating layer 201 to the upper face of the hard mask 161.

[0095] As illustrated in [Fig. 13], the remaining portion of the first sacrificial layer 13 is then removed from the access space 400, by selective etching with respect to the second sacrificial layer 14, typically by wet etching. The exposed portion of the oxide layer 12 is also removed from the access space 400, to form first cavities 400a opening onto the sides of the second layers 2 of the first EL stack. The unexposed portion of the oxide layer 12, located between the second sacrificial layer 14 and the sides of the second stack, is retained.

[0096] As illustrated in [Fig.14], the second layers 2 of the first stack E1 are then selectively etched at the central parts of the first layers 1 and at the internal spacers 101 of the first stack E1. The etching of the material of the second layers 2 typically has a selectivity S2:i with respect to the material of the first layers 1, of at least 5:1, preferably at least 10:1. This total etching can be stopped at the time, possibly after an over-etching time aimed at guaranteeing the total removal of the second layers 2. This total etching has an isotropic character and can be carried out by a wet or dry method, from the first cavities 400a. At the end of this etching, the second layers 2 are completely removed to form second spaces 22. The central parts of the first layers 1 are held by the sacrificial gates 150.

[0097] As illustrated in [Fig. 15], a first gate dielectric layer 31 is then deposited in the second spaces 22 from the first cavities 400a. This first gate dielectric layer 31 is typically based on a high permittivity material, for example based on HfO2. The first gate dielectric layer 31 is intended to form at least in part the gate dielectric layer between the channels of the first transistor and the first encapsulating gate. It can be formed by CVD (acronym for “Chemical Vapor Deposition”), by MOCVD (acronym for “Metal Organic Chemical Vapor Deposition”) or by ALD (acronym for “Atomic Layer Deposition”).It thus covers at least the central parts of the first layers 1 and, in the first cavities 400a, the exposed faces of the second sacrificial layer 14 and of the oxide layer 12. The first gate dielectric layer 31 typically has a . thickness between 1 nm and 5 nm.

[0098] As illustrated in [Fig. 16], a layer 40 based on a first semiconductor material is then deposited on the first gate dielectric layer 31 in the second spaces 22. The deposition of the first semiconductor material is here configured so that the layer 40 completely fills the second spaces 22. The portions of the layer 40 located in the second spaces 22 thus have a perfectly controlled thickness, close to the thickness of the initial second layers. This layer 40 is intended to form the channels 41a of the first transistor T1, directly above the sacrificial gate 150 and the central parts of the first layers 1. This layer 40 is also intended to form the sources 42a and the drains 43a of the first transistor T1 directly above the first internal spacers 101.

[0099] The layer 40 is also typically deposited outside the second spaces 22, on the sides of the internal spacers 101. This makes it possible to improve the contact recovery with the sources 42a and the drains 43a of the first transistor TL. The layer 40 thus has horizontal portions in the second spaces 22, in particular between the remaining parts of the first layers 1, and vertical portions on the sides of the first internal spacers 101. According to one possibility, the thickness of the vertical portions of the layer 40 is greater than the thickness of the horizontal portions of the layer 40. This makes it possible to reduce the contact resistance for the sources 42a and the drains 43a of the first transistor TL. The sources 42a and the drains 43a of the first transistor T1 may comprise the horizontal portions directly above the internal spacers 101, and at least in part the vertical portions on the sides of the internal spacers 101.

[0100] The first semiconductor material of the layer 40 is advantageously a two-dimensional material taken from transition metal dichalcogenides, MoS2 for example for a first N-type transistor, and WSe2 or WS2 for a first P-type transistor. Such a 2D material can advantageously be deposited in the form of a thin layer comprising 1 to 10 atomic layers, preferably 1 to 5 atomic layers. The deposition of this 2D material can be done by CVD, MOCVD or ALD. According to another possibility, the semiconductor material of the layer 40 is a semiconductor oxide such as 1TTO (acronym for "Indium Tin Oxide"), IGZO (acronym for "Indium Gallium Zinc Oxide"), IWO (meaning "Tungsten-Doped Indium Oxide"), indium oxide In2O3.

[0101] According to a second variant not illustrated, the layer 40 based on the first semiconductor material is deposited on the first gate dielectric layer 31 in the second spaces 22 without completely filling the second spaces 22. In this case, the portions of the layer 40 located in the second spaces 22 can be significantly thinner than the initial second layers. These horizontal portions may have a thickness corresponding to only a few atomic layers, for example between 1 and 5 atomic layers of the first semiconductor material. Reducing the thickness of the layer 40 makes it possible to improve the electrostatic control of the first transistor and therefore to reduce the dimensions of the channels 41a of the first transistor T1. The performance of the first transistor T1 can be improved. According to this second variant, a dielectric plug is then formed between the horizontal portions of the layer 40, in order to fill the second spaces 22. This makes it possible to electrically isolate the channels 41a of the first transistor T1 from each other. This also makes it possible to improve the mechanical strength of the device and / or to avoid deformations of the channels 41a of the first transistor T1, for example by heating during its operation. This dielectric plug can be formed by CVD or ALD deposition followed by isotropic etching along z, in a conventional manner.

[0102] As illustrated in [Fig.17], the first cavities 400a can then be filled with one or more metallic materials to form the first source and drain contacts 60Sa, 60Da of the first transistors TL. These metallic materials are for example based on Ti, TiN, W, or other metals making it possible to ensure low contact resistance such as Bi, Ni, Au, Sb, etc. A chemical-mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the patterns 102M.

[0103] As illustrated in [Fig.18], an advantageous step is to form protective caps 162 aimed at protecting the first source and drain contacts 60Sa, 60Da during the subsequent steps of manufacturing the second transistor. The protective caps 162 may be based on silicon oxide SiO2, silicon nitride SiN, or a SiO2 / SiN bilayer.

[0104] As illustrated in [Fig.19], the oxide layer 12 and the second sacrificial layer 14 are then removed at least partially so as to define second cavities 400b opening onto the sides of the fourth layers 4 of the second stack E2. According to one possibility, a portion of the oxide layer 12 and a portion of the second sacrificial layer 14 are retained at the level of the dielectric layer 201, as illustrated in [Fig.19]. According to another possibility not illustrated, the oxide layer 12 and the second sacrificial layer 14 are completely removed.

[0105] As illustrated in [Fig.20], the fourth layers 4 of the second stack E2 are then selectively etched at the central parts of the third layers 3 and at the internal spacers 131. The etching of the material of the fourth layers 4 typically has a selectivity S4:3 with respect to the material of the third layers 3, of at least 5:1, preferably at least 10:1. This total etching can be stopped at the time, possibly after an over-etching time aimed at ensuring the total removal of the fourth layers 4. This total etching has an isotropic character and can be carried out by wet or dry method, from the second cavities 400b. At the end of this etching, the fourth layers 4 are completely removed to form fourth spaces 44. The central parts of the third layers 3 are held by the sacrificial grids 150.

[0106] As illustrated in [Fig.21], a second gate dielectric layer 35 is then deposited in the fourth spaces 44 from the second cavities 400b. This second gate dielectric layer 35 is typically based on a high permittivity material, for example based on HfO2. The second gate dielectric layer 35 is intended to form the gate dielectric layer between the channels of the second transistor T2 and the second surrounding gate. It can be formed by CVD, MOCVD or by ALD. It thus covers at least the central parts of the third layers 3 and the exposed part of the first gate dielectric layer 31, and preferably the spacers 170 and the internal spacers 131. The second gate dielectric layer 35 typically has a thickness of between 1 nm and 5 nm. It can be based on the same material forming the first gate dielectric layer 31.The first and second gate dielectric layers 31, 35 then form a continuous insulation layer on an upper portion of the first source and drain contacts 60Sa, 60Da, facing the second cavities 400b. According to another possibility, the first and second gate dielectric layers 31, 35 are based on two different dielectric materials. In all cases, the first and second gate dielectric layers 31, 35 are in contact with each other at least at the upper portion of the first source and drain contacts 60Sa, 60Da, facing the second cavities 400b.

[0107] As illustrated in [Fig.22], a layer 45 based on a second semiconductor material is then deposited on the second gate dielectric layer 35 in the fourth spaces 44 and in the second cavities 400b. As previously, the deposition of the second semiconductor material is here configured so that the layer 45 completely fills the fourth spaces 44. The portions of the layer 45 located in the fourth spaces 44 thus have a perfectly controlled thickness, close to the thickness of the initial fourth layers. This layer 45 is intended to form the channels 41b of the second transistor T2 directly above the sacrificial gate 150 and the central parts of the third layers 3. This layer 45 is also intended to form the sources 42b and the drains 43b of the second transistor T2 directly above the spacers 170 and the internal spacers 131.

[0108] The layer 45 is also typically deposited outside the fourth spaces 44, on the sides of the spacers 170 and the internal spacers 131. This makes it possible to improve the contact recovery with the sources 42b and the drains 43b of the second transistor T2. The layer 45 thus has horizontal portions in the fourth spaces 44, in particular between the remaining parts of the third layers 3, and vertical portions on the sides of the spacers 170 and the internal spacers 131. According to one possibility, the thickness of the vertical portions of the layer 45 is greater than the thickness of the horizontal portions of the layer 45. This makes it possible to reduce the contact resistance for the sources 42b and the drains 43b of the second transistor T2. The sources 42b and the drains 43b of the second transistor T2 may comprise the horizontal portions directly above the spacers 170 and the internal spacers 131, and at least in part the vertical portions on the sides of the spacers 170 and the internal spacers 131.

[0109] The second semiconductor material of the layer 45 is chosen so as to form a second transistor T2 having a conductivity of the opposite type to that of the first transistor TL. This second semiconductor material of the layer 45 is also preferably a two-dimensional material taken from transition metal dichalcogenides, MoS2 for example for a second N-type transistor, and WSe2 or WS2 for a second P-type transistor. According to another possibility, the second semiconductor material of the layer 45 is a semiconductor oxide such as 1TTO (acronym for “Indium-tin oxide”), 1TGZO (acronym for “Indium-zinc-gallium oxide”), IWO (meaning “Tungsten-doped indium oxide”), indium oxide In2O3.

[0110] The layer 45 based on the second semiconductor material can also be produced according to the second variant described previously.

[0111] As illustrated in [Fig.23], the second cavities 400b can then be filled with one or more metallic materials to form the second source and drain contacts 60Sb, 60Db of the second transistor T2. These metallic materials are for example based on Ti, TiN, W, or other metals making it possible to ensure low contact resistance such as Bi, Ni, Au, Sb, etc. Chemical mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the patterns 102M.

[0112] At this stage of the method, the CFET device comprises transistors T1, T2 superimposed or stacked along z. The channels 41a, 41b of each transistor T1, T2 have been formed and are also stacked along z. The source contacts 60Sa, 60Sb and drain contacts 60Da, 60Db of each transistor T1, T2 have also been made. The first source contact 60Sa is advantageously isolated from the second source contact 60Sb by the combination of the first and second gate dielectric layers 31, 35. The first drain contact 60Da is advantageously isolated from the second drain contact 60Db by the combination of the first and second gate dielectric layers 31, 35.

[0113] In order to obtain superimposed GAA transistors, the steps described below concern the production of functional grids surrounding the transistors, replacing the sacrificial grid and layers 1 and 3, according to two embodiments.

[0114] Figures 24A, 24B to 27A, 27B schematically illustrate, according to the first embodiment of the present invention, the production of a gate common to the transistors T1, T2 of the CFET device.

[0115] According to this first embodiment, as illustrated in FIGS. 24A, 24B, a mask 203 is formed so as to protect the first source and drain contacts 60Sa, 60Da and the second source and drain contacts 60Sb, 60Db. This mask 203 is opened so as to expose the hard mask 161 surmounting the sacrificial gate. This mask 203 may conventionally be based on a dielectric material, for example based on SiN or SiO2.

[0116] According to the first embodiment, as illustrated in Figures 25A, 25B, the hard mask 161 is first removed, then the sacrificial gate 150 is also removed. This latter removal can be carried out by wet etching with stopping on the thin stop layer based on SiO2 or another dielectric. This wet etching typically has a high selectivity with respect to the stop layer and / or the spacers 170. This wet etching can be based on a solution of ammonia salts TM AH (Tetramethylammonium Hydroxide) or TEAH (Tetraethylammonium Hydroxide). This removal of the sacrificial gate 150 makes it possible to form a main space 601 and third openings 600G, 600D opening onto the central parts of the first layers 1 and the third layers 3 ([Fig.25B]).

[0117] As illustrated in Figures 26A, 26B, the central portions of the first layers 1 and the third layers 3 are then fully etched selectively at the internal spacers 101, 131, at the insulating layer 201, at the first gate dielectric layer 31 and at the second gate dielectric layer 35 from the third openings 600G, 600D. One or more etchings may be implemented, depending on whether the materials of the first layers 1 and the third layers 3 are identical or different. For simplicity, only one etching is mentioned here. This etching aims to form first spaces 11 in place of the central portions of the first layers 1, and third spaces 33 in place of the central portions of the third layers 3.This total etching can be stopped at the time, possibly after an over-etching time aimed at guaranteeing the total removal of the first material from the first layers 1 and the total removal of the third material from the third layers 3. This total etching has an isotropic character and can be carried out by wet or dry means, from the third openings 600G, 600D.

[0118] As illustrated in Figures 27A, 27B, the third openings 600G, 600D, the main space 601, the first spaces 11 and the third spaces 33 are then filled with one or more metal layers, for example based on TiN, W, in order to form a gate 50 common to the first and second transistors T1, T2. This gate 50 is called encapsulating and completely surrounds the channels 41a, 41b of the first and second transistors T1, T2. According to one possibility, before deposition of the metal layers of the gate 50, a dielectric layer based on a high permittivity material, for example based on HfO2, is previously deposited via the third openings 600G, 600D, in the main space 601, the first spaces 11 and the third spaces 33. This makes it possible to increase the thickness of the gate dielectric layers between the channels of the transistors T1, T2 and the encapsulating gate 50. Chemical-mechanical polishing CMP is typically carried out in order to remove the excess metal deposited on the patterns 102M.This process in which the functional gate 50 is produced at the end of the process, after formation of the other elements of the transistors T1, T2, in particular after formation of the channels 41a, 41b, is called “last gate”.

[0119] According to another possibility not illustrated, the gate 50 common to the transistors T1, T2 can be produced before the formation of the channels 41a, 41b of the transistors T1, T2, in particular before the deposition of the first sacrificial layer 13, according to a process called “gate first”.

[0120] According to the first embodiment of the present invention, a CFET device comprising superimposed GAA transistors T1, T2, with common gate 50, and having source contacts 60Sa, 60Sb and drain contacts 60Da, 60Db insulated from each other by the gate dielectric layers 31, 35, is produced.

[0121] Figures 28A, 28B to 34A, 34B schematically illustrate a second embodiment of the CFET manufacturing method with GAA transistors having separate gates for each transistor T1, T2. Figures nA (n=28.. .34) correspond to first transverse sections along an xz plane each illustrating a different step of the manufacturing method. Figures nB (n=28.. .34) correspond to second transverse sections along a yz plane each illustrating the same step as the corresponding figure nA.

[0122] According to the second embodiment, as illustrated in Figures 28A, 28B, the sacrificial gate is here typically separated into two distinct parts 150a, 150b. This separation can be carried out by means of a hard mask 163. In particular, before forming the sacrificial gate 150 on the patterns 101M, the hard mask 163 is previously formed on the patterns 101M. After deposition of the sacrificial gate, a chemical-mechanical polishing step with stopping on the hard mask 163 makes it possible to form two distinct parts 150a, 150b of the sacrificial gate. The first sacrificial gate part 150a extends on a first side of the pattern 101M. The second sacrificial gate part 150b extends on a second side of the pattern 101M. In the following, these two distinct parts 150a, 150b are removed successively to be replaced by first and second functional grids.

[0123] The mask 203 is formed so as to protect the first source and drain contacts 60Sa, 60Da and the second source and drain contacts 60Sb, 60Db, as previously.

[0124] As illustrated in Figures 29A, 29B, the second sacrificial gate portion 150b is first removed so as to form a third opening 600G exposing flanks of the third layers 3 of the second stack E2, on a second side of the pattern 101M. A second insulation portion 204, for example based on SiO2, is then formed at the bottom of the third opening 600G, at the level of the stack E1. Only the flanks of the third layers 3 of the second stack E2 are here exposed through the opening 600G.

[0125] As illustrated in Figures 30A, 30B, the central parts of the third layers 3 are then completely etched selectively at the internal spacers 131, at the insulating layer 201, at the second gate dielectric layer 35 from the third opening 600G. This etching aims to form the third spaces 33 in place of the central parts of the third layers 3 with a view to producing the second gate of the second transistor T2. This total etching can be stopped in time, possibly after an over-etching time aimed at guaranteeing the total removal of the third material of the third layers 3. This total etching has an isotropic character and can be carried out by a wet or dry method, from the third opening 600G.

[0126] As illustrated in Figures 31 A, 31B, the third spaces 33 and the third opening 600G are then filled to form the second gate 50b around the channels 41b of the second transistor T2. According to one possibility, an additional dielectric layer is deposited in the third spaces 33 on the second gate dielectric layer 35, prior to filling the third spaces 33 and the third opening 600G with one or more metal layers. As previously, the metal layers may be based on TiN, W.

[0127] As illustrated in Figures 32A, 32B, the first sacrificial gate portion 150a is preferably first partially removed so as to form a third opening 600D on the first side of the pattern 10IM. During this intermediate step, the flanks of the second stack E2 on the first side of the pattern 101M are exposed. The flanks of the first stack E1 on the first side of the pattern 101M are masked by the remaining sacrificial gate portion 150a. A first insulation portion 205, for example based on SiO2, is then formed in the third opening 600D, on the remaining sacrificial gate portion 150a, to isolate the future first gate of the first transistor from the second gate 50b and the channels 41b of the second transistor T2.

[0128] As illustrated in Figures 33A, 33B, the remaining portion 150a of sacrificial gate is then completely removed through the third opening 600D. The central portions of the first layers 1 are then selectively etched at the internal spacers 101, at the insulating layer 201, at the first gate dielectric layer 31, from the third opening 600D. This etching aims to form first spaces 11 in place of the central portions of the first layers 1 with a view to producing the first gate of the first transistor T1. This total etching can be stopped at the time, possibly after an over-etching time aimed at ensuring the total removal of the first material of the first layers 1. This total etching has an isotropic character and can be carried out by a wet or dry method, from the third opening 600D.

[0129] As illustrated in Figures 34A, 34B, the first spaces 11 and the third opening 600D are then filled to form the first gate 50a around the channels 41a of the first transistor T1. According to one possibility, an additional dielectric layer is deposited in the first spaces 11 on the first gate dielectric layer 31, prior to filling the first spaces 11 and the third opening 600D with one or more metal layers. As previously, the metal layers can be based on TiN, W.

[0130] According to this second embodiment, a CFET device comprising superimposed GAA transistors T1, T2, with independent gates 50a, 50b, and having source contacts 60Sa, 60Sb and drain contacts 60Da, 60Db insulated from each other by the gate dielectric layers 31, 35, is produced. The independent gates 50a, 50b are here electrically independent and make it possible to independently control the superimposed P-type transistor and the N-type transistor.

[0131] The solutions detailed in this invention are particularly effective for manufacturing CFET devices with stacked GAA transistors. The invention is however not limited to the embodiments previously described.

[0132] In particular, the embodiment described with reference to Figures 34A and 34B provides an isolation of the first source contact from the second source contact by the first gate dielectric layer and by the second gate dielectric layer as well as an isolation of the first drain contact from the second drain contact by said first gate dielectric layer and by said second gate dielectric layer. The invention also extends to embodiments in which the first source contact and the second drain contact are distinct and isolated from each other by the first gate dielectric layer and by the second gate dielectric layer, and in which the first drain contact and the second source contact are distinct and isolated from each other by said first gate dielectric layer and by said second gate dielectric layer. of grid.

Claims

Claims

1. Microelectronic device comprising at least two superimposed transistors (T1, T2) in a main direction (z), comprising: A first transistor (Tl), comprising: • at least two first channels (41a) stacked along the main direction (z), each channel being based on a first semiconductor material, • a first source (42a) and a first drain (43a) based on said first semiconductor material, • a first source contact (60Sa) and a first drain contact (60Da) connected respectively to said first source (42a) and to said first drain (43a), • a first grid (50, 50a) called a covering grid, completely surrounding at least one of the first channels (41a), • a first dielectric gate layer (31) separating each first channel (41a) from the first surrounding gate (50, 50a), A second transistor (T2), comprising: • at least two second channels (41b) stacked in the main direction (z), each channel being based on a second semiconductor material, • a second source (42b) and a second drain (43b) based on said second semiconductor material, • a second source contact (60Sb) and a second drain contact (60Db) connected respectively to said second source (42b) and to said second drain (43b), • a second grid (50, 50b) called a covering grid, completely surrounding at least one of the second channels (41b), • a second gate dielectric layer (35) separating each second channel (41b) from the second surrounding gate (50, 50b), the device being characterized in that the first source contact (60Sa) and one of the second source contact (60Sb) and the second drain contact (60Db) are distinct and isolated from each other by the first gate dielectric layer (31) and by the second gate dielectric layer (35), and in that the first drain contact (60Da) and the other of the second source contact (60Sb) and the second drain contact (60Db) are distinct and isolated from each other by said first gate dielectric layer (31) and by said second gate dielectric layer (35).

2. Device according to the preceding claim in which the first gate dielectric layer (31) and the second gate dielectric layer (35) are based on the same material, thus forming a continuous dielectric layer between the first and second source contacts (60Sa, 60Sb) and between the first and second drain contacts (60Da, 60Db).

3. Device according to any one of the preceding claims in which the first semiconductor material and the second semiconductor material are based on a two-dimensional (2D) material chosen from transition metal dichalcogenides MX2 with M taken from molybdenum (Mo) or tungsten (W), and X taken from sulfur (S), selenium (Se) or tellurium (Te).

4. Device according to any one of the preceding claims in which the first and second encapsulating gates (50a, 50b) form the same gate (50) common to the first and second transistors (T1, T2).

5. Device according to any one of claims 1 to 3, in which the first and second surrounding gates (50a, 50b) are distinct, the first gate (50a) completely surrounding each first channel (41a) of the first transistor (T1), and the second gate (50b) completely surrounding each second channel (41b) of the second transistor (T2).

6. Device according to any one of the preceding claims in which the first semiconductor material has a first conductivity type, for example N-type, and the second semiconductor material has a second conductivity type different from the first conductivity type, for example P-type.

7. A method of manufacturing a microelectronic device according to any one of the preceding claims, the method comprising the following steps: Providing on a substrate (S) a first stack (El) and a second stack (E2) superimposed in the direction (z), said first stack (El) comprising a plurality of first layers (1) made of a first material, alternating with a plurality of second layers (2) made of a second material, said second stack (E2) comprising a plurality of third layers (3) made of a third material, alternating with a plurality of fourth layers (4) made of a fourth material, said first and second stacks (El, E2) being separated by a dielectric layer (201), Forming, in the superimposed first stack (El) and second stack (E2), first openings (100) defining first patterns (101M), Form a sacrificial grid (150) straddling the first patterns (101M) and partly in the first openings (100), Forming in the first patterns (101M) second openings (200) defining second patterns (102M), on either side of the sacrificial grid (150), Forming a first sacrificial layer (13) in the second openings (200), on the sides of the second layers (2) of the first stack (El), Forming a second sacrificial layer (14) on the first sacrificial layer (13) and on the sides of the fourth layers (4) of the second stack (E2), leaving a space (400) for access to the first sacrificial layer (13), Removing the first sacrificial layer (13), from the access space (400), while retaining the second sacrificial layer (14), so as to form first cavities (400a) opening onto the sides of the second layers (2) of the first stack (El), Removing from the first cavities (400a) the second material of the second layers (2) selectively to the first material of the first layers (1), so as to form second spaces (22), Forming a first gate dielectric layer (31) in the second spaces (22) on exposed portions of the first material of the first layers (1), and in the first cavities (400a) on exposed parts of the second sacrificial layer (14), • Deposit a layer (40) based on a first semiconductor material in the second spaces (22), on the first gate dielectric layer (31), so as to form: • the first channels (41a) of the first transistor (Tl) based on the first semiconductor material, directly above the sacrificial gate (150), • a first source (42a) and a first drain (43a) of the first transistor (Tl) based on the first semiconductor material, on either side of the first channels (41a) of the first transistor (Tl), Filling the first cavities (400a) with a first electrically conductive material to form first source and drain contacts (60Sa, 60Da) of the first transistor (Tl), Removing the second sacrificial layer (14), so as to form second cavities (400b) opening onto the sides of the fourth layers (4) of the second stack (E2), Removing from the second cavities (400b) the fourth material of the fourth layers (4) selectively to the third material of the third layers (3), so as to form fourth spaces (44), Forming a second gate dielectric layer (35) in the fourth spaces (44) on exposed portions of the third material of the third layers (3), and in the second cavities (400b) on the first gate dielectric layer (30), Depositing a layer (45) based on a second semiconductor material in the fourth spaces (44), on the second gate dielectric layer (35), so as to form: second channels (41b) of the second transistor (T2) based on the second semiconductor material, directly above the sacrificial gate (150), a second source (42b) and a second drain (43b) of the second transistor (T2) based on the second semiconductor material, on either side of the second channels (41b) of the second transistor (T2), • Filling the second cavities (400b) with a second electrically conductive material to form second source and drain contacts (60Sb, 60Db) of the second transistor (T2), • Remove the sacrificial grid to form third openings (600G, 600D), • Remove from the third openings (600G, 600D), the first layers (1) and the third layers (3), to form first spaces (11) and third spaces (33) respectively, • Fill the first and third spaces (11, 33), to form respectively the first and second grids (50a, 50b) surrounding the first and second transistors (T1, T2).

8. A manufacturing method according to the preceding claim, further comprising the following steps: • Form first spacers (101) between the first encapsulating grid (50a) and the first source and drain contacts (60Sa, 60Da), • Form second spacers (131) between the second wrapping gate (50b) and the second source and drain contacts (60Sb, 60Db).

9. A manufacturing method according to the preceding claim, wherein the formation of the first and second spacers (101, 131) comprises the following steps: • Preferably form spacers (170) bordering the sacrificial grid (150) and resting on the first patterns (101M), • Before forming the first sacrificial layer (13), partially remove, from the second openings (200), the first material of the first layers (1) selectively to the second material of the second layers (2), so as to forming first spacer cavities (10), preferably directly above the spacers (170), • Filling the first spacer cavities (10) with a first dielectric material to form the first spacers (101) • Before forming the second sacrificial layer (14), partially removing, from the second openings (200), the third material of the third layers (3) selectively to the fourth material of the fourth layers (4), so as to form second spacer cavities (30), preferably directly above the spacers (170), • Filling the second spacer cavities (30) with a second dielectric material to form the second spacers (131).

10. Manufacturing method according to the preceding claim, wherein the first material of the first layers (1) is identical to the third material of the third layers (3), and wherein the first and second spacers (101, 131) are formed simultaneously.

11. Manufacturing method according to any one of claims 7 to 10, wherein the sacrificial gate comprises a first part (150a) and a second part (150b) which are distinct, and wherein the removal of the sacrificial gate comprises: • a first removal of the first part (150a) of the sacrificial gate configured to form a third opening (600D) opening only onto sides of the first layers (1), on a first side only of the first pattern (101M), followed by a removal of the first layers (1) from said third opening (600D) to form the first spaces (11), and a filling of said first spaces (11) to form the first gate (50a) surrounding the first transistor (T1), and • a second removal of the second part (150b) of the sacrificial gate configured to form a third opening (600G) opening only onto sides of the third layers (3),from only a second side of the first pattern (101M), followed by removal of the third layers (3) from said third opening (600G) to form the, third spaces (33), and a filling of said third spaces (33) to form the second gate (50b) surrounding the second transistor (T2).

12. Manufacturing method according to the preceding claim in which the first removal comprises a formation of a first insulation portion (205) on sides of the first stack (E2) at the level of the first side of the first pattern (101M), before filling the first spaces (11) to form the first surrounding grid (50a).

13. A manufacturing method according to any one of claims 11 to 12 wherein the second removal comprises forming a second insulation portion (204) on sides of the first stack (El) at the second side of the first pattern (101M), before filling the third spaces (33) to form the second surrounding grid (50b).

14. A manufacturing method according to any one of claims 11 to 13, wherein the second encapsulating grid (50b) is formed before the first encapsulating grid (50a).

15. A manufacturing method according to any one of claims 11 to 14 comprising, before removing the sacrificial gate, separating the sacrificial gate into a first portion (150a) and a second portion (150b) distinct from each other, said first and second portions (150a, 150b) of sacrificial gate extending respectively on the first and second sides of the first pattern (101M), the first removal being carried out on the first portion (150a) of gate and the second removal being carried out on the second portion (150b) of gate.

16. Manufacturing method according to the preceding claim, in which, before formation of the sacrificial gate, a hard mask (163) is formed on the first patterns (101M), and in which the separation of the sacrificial gate is carried out by chemical-mechanical polishing with stopping on said hard mask (163).

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