Electronic circuit

Abstract

Electronic circuit The present description relates to an electronic circuit (400) comprising a first circuit (410) configured to generate, from a first periodic analog signal (Vxo), several second signals (Vref, Vlow, Vhigh) shifted in voltage level; a second circuit (420) configured to generate third digital periodic signals (Voutref, Voutlow, Vouthigh) as a function of the crossing, by said second signals (Vref, Vlow, Vhigh), of at least one threshold (Vhyst_l, Vhyst_h); and a third circuit (430) configured to determine an amplitude range in which the first signal (Vxo) is located, as a function of the number of third signals (Voutref, Voutlow, Vouthigh) present. Figure for the abstract: Fig. 4

Description

Title of the invention: Electronic circuit Technical field

[0001] The present description relates generally to electronic circuits and their operating methods. Prior art

[0002] Electronic circuits, particularly microcontrollers, use periodic signals. These periodic signals can, for example, come from oscillators, particularly crystal oscillators. Measuring and controlling the amplitude of the oscillations is important to ensure uniformity of operation from one circuit to another. Current circuits use a large chip area to achieve this. Summary of the invention

[0003] There is a need to obtain electronic circuits making it possible to measure and control the amplitude of periodic signal oscillations while reducing the chip area used.

[0004] One embodiment overcomes all or part of the drawbacks of known electronic circuits.

[0005] One embodiment provides an electronic circuit comprising: - a first circuit configured to generate, from a first periodic analog signal, several second signals shifted in voltage level; - a second circuit configured to generate third digital periodic signals as a function of the crossing, by said second signals, of at least one threshold; and - a third circuit configured to determine an amplitude range in which the first signal lies, based on the number of third signals present.

[0006] One embodiment provides a method of operating an electronic circuit comprising: - generate, by a first circuit of the electronic circuit, from a first periodic analog signal, several second signals shifted in voltage level; - generating, with a second circuit, third digital periodic signals as a function of the crossing, by said second signals, of at least one threshold; and - determine, with a third circuit, an amplitude range in which the first signal is located, depending on the number of third signals present.

[0007] In one embodiment, each third signal is generated when the corresponding second signal crosses two thresholds.

[0008] In one embodiment, the electronic circuit comprises a fourth circuit configured to allow adjustment of the amplitude of the first signal based on the determination of said amplitude range.

[0009] In one embodiment, the third circuit comprises three branches each comprising several flip-flops in series, each branch being configured to respectively receive one of the third signals on the clock input of said flip-flops of this branch.

[0010] In one embodiment, each branch comprises at least two D-type flip-flops in series.

[0011] In one embodiment, the third circuit comprises a first logic block configured to perform an AND function from an output of the series of flip-flops of a first branch among said branches and from an output of the series of flip-flops of a second branch among said branches.

[0012] In one embodiment, the third circuit comprises a second logic block configured to perform an AND function from the output of the series of flip-flops of the second branch and from an output of the series of flip-flops of a third branch among said branches.

[0013] In one embodiment, the third circuit is configured to generate a pulse on a first channel when the states of the outputs of the first and second branches are identical to a high logic state.

[0014] In one embodiment, the third circuit is configured to generate a pulse on a second channel when the states of the outputs of the second branch and the third branch are identical to a high logic state.

[0015] In one embodiment, the pulses are generated when the state of the signal at the output of the second branch is in a high state.

[0016] In one embodiment, the fourth circuit is configured to generate a command making it possible to modify the amplitude of the first signal as a function of the presence or absence of pulses on the first and second channels.

[0017] In one embodiment, each third signal is generated by a respective trigger threshold voltage comparator having said two thresholds as trigger thresholds.

[0018] In one embodiment, each voltage comparator is of the Schmitt trigger type.

[0019] In one embodiment, each voltage comparator has an input node connected to a first node, intended to receive the signal to be analyzed, via a respective capacitor; each input node of each comparator being intended to receive respectively one of the second signals.

[0020] In one embodiment, the first circuit comprises resistors in series between a supply node intended to receive a supply voltage and ground, each of the second signals being generated from the voltage present on a different node corresponding to a midpoint of two adjacent resistors of said series of resistors.

[0021] In one embodiment, the first circuit comprises a PMOS transistor and an NMOS transistor each having a conduction node connected to a reference node, the control nodes of said PMOS and NMOS transistors being connected to said reference node, another conduction node of the PMOS transistor being connected to the power node and another conduction node of the NMOS transistor being connected to ground.

[0022] In one embodiment, the reference node is connected to ground via one of said resistors in the resistance series.

[0023] In one embodiment, each comparator comprises a double inverter circuit connecting the power node and ground, said dual inverter circuit comprising two PMOS transistors and two NMOS transistors in series; a control node, common to said PMOS and NMOS transistors of said double inverter, being connected to said reference node.

[0024] In one embodiment, the first signal is from a crystal oscillator.

[0025] One embodiment provides an NFC microcontroller comprising a circuit as described above. Brief description of the drawings

[0026] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0027] [Fig.l] illustrates very schematically and in block form, an example of an electronic circuit of the type to which the described embodiments apply;

[0028] [Fig.2] represents a circuit of a block of [Fig.l] according to an example;

[0029] [Fig.3] represents an operating graph of the circuit of [Fig.2];

[0030] [Fig.4] very schematically represents a circuit of a block of [Fig.l] according to one embodiment;

[0031] [Fig.5] represents a circuit of [Fig.4] according to one embodiment;

[0032] [Fig.6] represents a circuit of [Fig.4] according to one embodiment;

[0033] [Fig.7] represents a circuit of [Fig.4] according to one embodiment;

[0034] [Fig.8] represents a timing diagram of the operation of the circuit of [Fig.4]; and

[0035] [Fig.9] represents a timing diagram of the operation of the circuit of [Fig.4]. Description of the embodiments

[0036] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0037] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0038] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0039] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0040] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0041] [Fig.l] illustrates very schematically and in block form, an example of an electronic device 100 of the type to which the described embodiments apply.

[0042] The device 100, which is for example a microcontroller, integrates for example a processing unit 104 (CTRL) comprising one or more processors for example under the control of instructions stored in an instruction memory (not illustrated).

[0043] The device 100 further comprises a module 106 (REF) having a periodic signal generation block comprising one or more oscillators. The generated signals are used, for example, for generating reference signals such as clock signals. The block 106 comprises, for example, one or more crystal oscillators (XO) or voltage-controlled oscillators (VCO). The block 106 comprises, for example, a circuit for measuring the envelope of the generated periodic signals to check the amplitude of the generated signals and, if necessary, to provide feedback on them to keep them within a desired amplitude range.

[0044] The device 100 may further integrate an antenna circuit 110 (ANTENNA) comprising for example an antenna and an impedance matching circuit. The device 100 is for example compatible with the NFC (Near Field Communication) near field communication protocol.

[0045] The device 100 may integrate other circuits implementing other functions. (for example, one or more volatile and / or non-volatile memories, other processing units, an I / O input / output interface), symbolized by a block 102 (FCT) in [Fig.l].

[0046] The blocks 102, 104, 106 and 110 are for example connected to each other and / or to the rest of the device 100 via a bus 108 carrying the required signals.

[0047] The present description relates more particularly to the module 106 whose generated periodic signals are for example used in the processes implemented by the other blocks 102, 104 and 110.

[0048] [Fig. 2] represents a circuit of block 106 of [Fig. 1] according to an example. More particularly, [Fig. 2] represents a circuit 206 configured to measure the envelope of a Vxo signal generated by one of the oscillators of block 106.

[0049] The circuit 206 shown comprises a diode D connected to ground via a capacitor C and a resistor R associated in parallel. A voltage Vxo_out corresponding to the oscillation amplitude of the signal Vxo is measured between the cathode of the diode D and ground.

[0050] [Fig.3] represents an operating graph of the circuit of [Fig.2]. More specifically, [Fig.3] illustrates the voltage Vxo_out. At each oscillation of the signal Vxo, the capacitor C charges on the rising part then slowly discharges on the falling part when the diode no longer conducts and this until the next rising part of the oscillation which gives a rectified voltage with a residual periodic variation (ripple in English). The voltage Vxo_out is then estimated more precisely using one or more differential comparators (not illustrated here) one of the inputs of which will be the DC comparison voltage level to give a stable result despite the residual periodic variation. In this example, it is appropriate to implement as many comparators as there are DC voltage levels to be compared.

[0051] With the miniaturization of circuits, the chip area required to implement the components of circuit 206, as well as for the differential comparators, must be reduced.

[0052] To do this, the described embodiments propose an electronic circuit comprising: - a first circuit configured to generate, from a first periodic analog signal, several second signals shifted in direct voltage level; - a second circuit configured to generate third digital periodic signals as a function of the crossing, by said second signals, of at least one threshold; and - a third circuit configured to determine an amplitude range in which the first signal lies, depending on the number of third signals present.

[0053] This allows for a simplification of design as well as a reduction in the required chip area by a factor of more than two.

[0054] [Fig.4] very schematically represents a circuit of a block of [Fig.l] according to one embodiment.

[0055] More particularly, [Fig.4] illustrates an embodiment of an electronic circuit 400 of block 106.

[0056] The circuit 400 comprises a first circuit 410 configured to generate, from a first periodic analog signal Vxo coming from an oscillator 404 (XO) of the block 106, several second signals Vhigh, Vlow, and Vref, shifted in voltage level, respectively on nodes N2, N3 and N4.

[0057] In the example shown, the circuit 410 comprises three capacitors 401, 403, 405 respectively connecting the nodes N2, N3 and N4 to a node NI on which the signal Vxo arrives.

[0058] The circuit 410 includes a resistor 407 connecting the node N2 and a node N2a via an optional first switch 415. The resistor 407 further optionally connects the node N2 and a node N2b via a second switch 413. Sel_vhigh control signals of the first and second switches are inverted between the two switches. The use of the optional switches 413 and 415 makes it possible to condition the start of the feedback on the oscillator implemented by the circuit 440 from a threshold different from the final target voltage.

[0059] The circuit 410 also comprises a resistor 409 connecting the node N3 and a node N3a as well as a resistor 411 connecting the node N4 and a node N4a.

[0060] In the example shown, the nodes N2a, N2b, N3a and N4a are connected to a circuit 412 configured to generate voltages offset relative to each other. The capacitors 401, 403, 405 make it possible to cut off the DC voltage level of the oscillation signal Vxo and the resistors 407, 409 and 411 make it possible to apply the respective offset of the voltages present on the nodes N2a, N2b, N3a and N4a to the signal Vxo devoid of DC voltage. The voltages Vhigh, Vlow, and Vref are therefore the images of the signal Vxo offset in voltage as are the voltages present on the nodes N2a or N2b, N3a and N4a.

[0061] In the illustrated example, the circuit 400 also comprises a second circuit 420 configured to generate third digital periodic signals Vouthigh, Voutlow and Voutref as a function of the crossing, by the second signals Vhigh, Vlow, and Vref, of at least one threshold, preferably two thresholds. The circuit 420 comprises an input, an input connected to the node N3, and another input connected to the node N4. The circuit 420 comprises a first voltage comparator 421 connecting the node N2 to a first input of a third circuit 430; a second voltage comparator 422 connecting node N3 to a second input of circuit 430; and a third voltage comparator 423 connecting node N4 to a third input of circuit 430. In one example, each of the voltage comparators has two trigger thresholds Vhyst_l, Vhyst_h and is for example of the Schmitt trigger type. In operation, each third signal is generated independently of the others from the moment the corresponding second signal crosses the two thresholds Vhyst_l, Vhyst_h. Each third signal Vouthigh, Voutlow and Voutref, consists of a periodic square wave signal, alternating between a high state and a low state, thus forming a digital signal with different duty cycles.

[0062] In the example shown, the circuit 400 comprises a third circuit 430 configured to determine an amplitude range in which the first signal Vxo is located, as a function of the number of third signals present.

[0063] In one example, the circuit 430 is configured to check, synchronously with a reference signal (cal clk) from Voutref, which of the third signals is present. Thus, a pulse is generated on a first channel (Status low) when the third signal Voutlow is periodically established at the same frequency as that of the signal cal clk. Similarly, a pulse is generated on a second channel (Status high) when the third signal Vouthigh is periodically established at the same frequency as that of the signal cal clk is in the high state.

[0064] If only the third signal Voutref is generated periodically but the third signals Voutlow and Vouthigh are not generated periodically, this means that the amplitude of the signal Vxo is located in a first amplitude range less than 2*(Vlow-Vref)+Vhyst_l. In another example, if only the third signals Voutref and Voutlow are generated periodically but the third signal Vouthigh is not generated periodically, this means that the amplitude of the signal Vxo is located in a second amplitude range between 2*(Vhigh-Vref)+Vhyst_l and 2*(Vlow-Vref)+Vhyst_l. In another example, if the third signals Vouthigh, Voutref and Voutlow are generated periodically, this means that the amplitude of the signal Vxo is located in a third amplitude range greater than 2*(Vhigh-Vref)+Vhyst_l.

[0065] In the example shown, the circuit 400 comprises a fourth circuit 440 configured to allow the adjustment of the amplitude of the Vxo signal as a function of the determination of the amplitude range of this Vxo signal.

[0066] The fourth circuit receives as input the first and second channels as well as the cal clk signal. As output it is connected, preferably connected, to the oscillator 404. In one example, the fourth circuit 440 generates a command making it possible to modify the amplitude of the Vxo signal as a function of the presence or absence of pulses on the first and second channels (respectively Status low, Status high) so as to synchronous with the cal clk signal. In an example, if a pulse is present at the same time on cal clk, on the first channel (Status low) and on the second channel (Status high), this means that the amplitude of the Vxo signal is located in the third amplitude range and that it is necessary, for example, to reduce the oscillator supply current control to reduce the oscillation amplitude. If a pulse is present at the same time on cal clk and on the first channel (Status low) but not on the second channel (Status high), this means that the amplitude of the Vxo signal is located in the second amplitude range and that it is not necessary to modify the oscillator supply current.If a pulse is present at the same time on cal clk, but not on the first channel (Status low) or on the second channel (Status high), this means that the amplitude of the Vxo signal is located in the first amplitude range and that it is necessary to feedback on the oscillator, for example by increasing the bias current of the oscillator 404.

[0067] In one example, in order to improve the robustness of the circuit 106, and for example to overcome the possibility of the presence of parasitic pulses on the third signals, it is possible to verify the presence of the third signals over a time of several consecutive periods of the signal Voutref for example.

[0068] The chip area required to implement the circuit 400 is at least two times smaller than that of an envelope detector as shown in [Fig.2].

[0069] [Fig.5] represents a circuit of [Fig.4] according to one embodiment. More particularly, the figure illustrates one embodiment of the circuit 430.

[0070] In the example shown, the circuit 430 comprises a first branch 512 having for example four flip-flops 536, in series, with their clock inputs connected to each other and to a node NVouthigh configured to receive the third signal Vouthigh. The term "flip-flops in series" means that the input of one of the flip-flops is connected to the output of the previous one. The last flip-flop of the series of flip-flops 536 is connected, preferably connected, to a node N5.

[0071] The circuit 430 comprises for example a second branch 514 with for example four flip-flops 534 in series, with their clock inputs connected to each other and to a node NVoutref configured to receive the third signal Voutref. The last flip-flop of the series of flip-flops 534 is connected, preferably connected, to a node N6.

[0072] In one example, the second branch 514 further comprises two other flip-flops 547, 548 in series with the series of flip-flops 534, their clock inputs being connected to each other and to the node NVoutref. The data input of the flip-flop 548 is for example connected to the node N6. The signal at the output of the flip-flop 548 is for example the signal cal clk.

[0073] The circuit 430 comprises for example a third branch 516 with for example four 532 flip-flops in series with their clock inputs connected to each other and to an NVoutlow node, configured to receive the Voutlow signal. The last flip-flop in the series of 532 flip-flops is connected, preferably connected, to an N7 node.

[0074] In the example presented, the number of flip-flops in series must be identical in each of the branches 512, 514 and 516 for the groups 532, 534 and 536.

[0075] In one example, the reset inputs of flip-flops in a series of the same branch are connected together.

[0076] In another example, an inverter 522 is for example connected in series with the data input of the first flip-flop of the series of flip-flops 534 of the second branch 514. In this case, the data inputs of the first flip-flops of the series 532 and 536 are connected together at a high logic level while the reset input of the flip-flops of the series 532 and 536 is also connected to the input of the inverter 522.

[0077] In the example shown, the circuit 430 further comprises a first logic function formed by a NAND logic gate 542 in series with an inverter 543 and a second logic function consisting of a logic gate formed by a NAND logic gate 544 in series with an inverter 545. The association of the circuits 542 and 543 forms an AND function from the signals present on the nodes N5 and N6. The association of the circuits 544 and 545 is configured to perform an AND function from the signals present on the nodes N6 and N7. The person skilled in the art may implement logic gates other than a NAND gate in series with an inverter to obtain an AND logic function. The signals generated will respectively define the simultaneous presence of synchronous signals on the nodes NVoutref and NVoutlow and on NVoutref and NVouthigh.

[0078] In the example shown, circuit 430 further comprises flip-flops 546, 551 and 552. Flip-flop 552 has its clock input connected to the output of the logic function formed by logic gates 542, 543 and its output connected to a node N12. Flip-flop 551 has its data input connected to the output of the logic function provided by the association of circuits 544 and 545 and its clock input connected to node N6. The Status low signal is found at the output of flip-flop 551. Flip-flop 546 has its clock input connected to node N6. The Status high signal is found at the output of flip-flop 546.

[0079] In the example shown, the circuit 430 further comprises a frequency divider circuit 530 connecting the node NVoutref to a node N9. The circuit 530 consists of flip-flops connected together so that the output of one flip-flop is connected to the clock input of the next flip-flop. This allows a division of the frequency of the signal present on the clock input of the first flip-flop as many times as there are flip-flops in the circuit 530. In the example shown, the circuit 530 comprises twelve flip-flops and the frequency present on the input of the first flip-flop (on the left) of the 530 circuit is divided by 2A12. The 530 circuit allows to define the period between each pulse of the cal clk signal.

[0080] In the example shown, the circuit 430 further comprises a circuit 526 configured to generate a time window. The circuit 526 comprises a flip-flop 550 whose clock input is connected to the node N9 and whose data input is connected to a high logic level. An output of the flip-flop 550 is connected to one or more (for example three) time shift cells associated in a series 540. The output of the last time shift cell is connected to a reset input of the flip-flop 550 via an inverter 549. The output of the flip-flop 550 is connected to the reset inputs of the flip-flops 546, 547, 548 and 551

[0081] In one example, the flip-flops of circuit 430 of [Fig.5] are of type D.

[0082] In operation, circuit 526 defines a window time length observation of the results of presence of simultaneous and synchronous signals on NVoutref and NVoutlow and on NVoutref and NVouthigh. In other words, the circuit 526 defines, at each calibration period, the generation of the Status high, Status low and cal clk pulses over a pulse duration t during which a pulse is also transmitted on the cal clk signal.

[0083] In operation, circuit 526 defines the reset to zero of the Status high, Status low and cal clk signals after the time window defined by circuit 526 via inverter 549.

[0084] The resetting of the flip-flops of the series 536 and 532 is given by the result of the branch 534. This allows a frequency control in a continuous manner, every four rising edges of the signal Voutref thanks to the inverter 522 but whose result will be verified at each calibration period for a time length t.

[0085] [Fig.6] represents a circuit of [Fig.4] according to one embodiment. More particularly, the figure illustrates one of the voltage comparators 421, 422 or 423 of [Fig.4],

[0086] In the illustrated example, one of the voltage comparators 421, 422, 423 is described. The other voltage comparators 421, 422, 423 are for example similar with dimensions and architecture as close as possible to each other.

[0087] In [Fig.6], the illustrated voltage comparator comprises a dual inverter circuit connecting a supply node N8 (VDD) and ground (GND). The dual inverter circuit comprises two PMOS transistors 610, 612 and two NMOS transistors 614, 616 in series. The PMOS and NMOS transistors of the dual inverter comprise a common control node connected to the input node N2, N3 or N4 of the respective comparator.

[0088] In the example shown, the voltage comparator further comprises a PMOS transistor 620 having a conduction node connected, preferably connected, to the power supply node N8, a control node connected, preferably connected, to the respective NVouthigh, NVoutlow, NVoutref node, and another conduction node connected, preferably connected, to a conduction node common to the transistors 610 and 612.

[0089] The illustrated voltage comparator also includes an NMOS transistor 618 having a conduction node connected, preferably connected, to ground, a control node connected, preferably connected, to the respective NVouthigh, NVoutlow, NVoutref node, and another conduction node connected, preferably connected, to a conduction node common to transistors 614 and 616.

[0090] In the example shown, the voltage comparator further comprises a PMOS transistor 622 and an NMOS transistor 624, a conduction node common to the two transistors 622, 624 of which is connected, preferably connected, to the respective node NVouthigh, NVoutlow, NVoutref. Another conduction node of the transistor 622 is connected, preferably connected, to the node N8 and another conduction node of the transistor 624 is connected, preferably connected, to ground. The control nodes of the transistors 622, 624 are connected to each other and to a conduction node common to the transistors 612 and 614.

[0091] In the illustrated example, the substrate nodes of transistors 610, 612 and 620 are connected to each other and connected to VDD. The substrate nodes of transistors 614, 616 and 618 are connected to ground.

[0092] In one example, the transistors of the voltage comparators 421, 422, 423 have dimensions and architecture that are as similar as possible to each other. In particular, the transistors 610, 620; 612, 614; and 616, 618 preferably have dimensions and architecture that are as similar as possible from one comparator to another.

[0093] [Fig.7] represents a circuit of [Fig.4] according to one embodiment. More particularly, [Fig.7] illustrates an example of the circuit 412.

[0094] In the example shown, the circuit 412 comprises about ten resistors connected in series between a power supply node, which may be the node N8, configured to be connected to a supply rail of a voltage VDD, and ground. The node N2a corresponds to the midpoint between the fourth and fifth resistors 719, 718 of the series. The node N2b corresponds to the midpoint between the fifth and sixth resistors 718, 717 of the series. The node N3a corresponds to the midpoint between the eighth and ninth resistors 721, 722 of the series. The node N4a corresponds to the midpoint between the ninth and tenth resistors 722, 723 of the series. The resistance scale obtained makes it possible to create different voltages at the nodes N2a, N2b, N3a, N4a.

[0095] In the example shown, the circuit 412 further comprises a circuit comprising a PMOS transistor 725 and an NMOS transistor 726. Transistor 725 has a conduction node connected to the power node N8, another conduction node connected to node N4a, a substrate node connected to node N8 and a control node connected to node N4a. Transistor 726 has a conduction node connected to node N4a, another conduction node connected to ground, a substrate node connected to ground and a control node connected to node N4a.

[0096] By short-circuiting the conduction nodes of transistors 726 and 725 corresponding to the drain of these transistors with their control node, this positions the voltage present on node N4a as being in the middle of the thresholds Vhyst_h and Vhyst_l. This makes it possible to obtain a duty cycle very close to 50% at the output of comparator 423 if transistors 725 and 726 are of similar dimensions and architectures to the respective transistors 612 and 614 of the comparator of [Fig.6]. This voltage at node N4a is imposed on the resistor scale and makes it possible to define the voltages present on nodes N3a, N2a and N2b according to their positioning on the resistor scale. Nodes N3a, N2b and N2a can be placed at other points on the resistive scale according to the voltage levels to be used as a comparison reference.

[0097] [Fig.8] represents a timing diagram of the operation of the circuit of [Fig.4]. More particularly, [Fig.8] illustrates the voltages Vhigh, Vlow and Vref in relation to the thresholds Vhyst_l and Vhyst_h as a function of time.

[0098] Before a time tl, the signal Vref is centered on 0.6V for example and Vhyst_l and Vhyst_h are located on either side of 0.6V.

[0099] At a time tl, only the signal Vref generates a signal at the output of one of the voltage comparators. This signal has a duty cycle of 50% for example if the circuit 412 as illustrated in [Fig.7] is used. None of the signals Vhigh and Vlow have crossed the two thresholds Vhyst_l and Vhyst_h.

[0100] Between time tl and a subsequent time t2, the signal Vxo, coming from the oscillator, increases in amplitude until the threshold Vhyst_l is crossed by the signal Vlow. The corresponding voltage comparator 422 then generates the square signal Voutlow. The amplitude of the signal Vxo is at this time greater than 2*(Vlow-Vref)+Vhyst_l. The amplitude of the signal Vxo is well established above Vlow when the signal Voutlow has the same frequency as the signal Voutref.

[0101] At time t3, Vhigh has crossed the thresholds Vhyst_h and Vhyst_l, which means that the amplitude Vxo becomes greater than 2*(Vhigh-Vref)+Vhyst_l. It then becomes necessary, if we wish to regulate the amplitude of Vxo between 2*(Vlow-Vref)+Vhyst_l and 2*(Vhigh-Vref)+Vhyst_l, to reduce, for example, the supply current of the oscillator.

[0102] [Fig.9] represents a timing diagram of the operation of the circuit of [Fig.4]. More particularly, [Fig.9] illustrates the pulses on the Status high signals, Status low and cal clk as a function of time.

[0103] The signal cal clk is the reference signal with pulses occurring periodically at times t4, t5, t6, t7 and t8 with a period Tcal which is defined by the circuit 530. In one example, for an oscillator frequency at 54.24 MHz, Tcal is 75 ps.

[0104] At time t4, which corresponds for example to time tl of [Fig.8], there are no pulses on the Status low and Status high signals.

[0105] At time t5, which corresponds for example to time t2 of [Fig.8], a pulse is present on the Status low signal. This means that the amplitude of Vxo is between 2*(Vlow-Vref)+Vhyst_l and 2*(Vhigh-Vref)+Vhyst_l and that it is for example not necessary to regulate the supply current of the oscillator.

[0106] At time t6, which corresponds for example to time t3 of [Fig.8], a pulse is present on the Status low and Status high signals. The amplitude of Vxo is therefore greater than 2*(Vhigh-Vref)+Vhyst_l. If we wish to regulate the amplitude of Vxo between 2*(Vlow-Vref)+Vhyst_l and 2*(Vhigh-Vref)+Vhyst_l, it is possible to reduce the supply current of the oscillator for example by a factor of 2.

[0107] At time t7, a pulse is still present on the Status low and Status high signals. The amplitude of Vxo is therefore still greater than 2*(Vhigh-Vref)+Vhyst_l. If we wish to regulate the amplitude of Vxo between 2*(Vlow-Vref)+Vhyst_l and 2*(Vhigh-Vref)+Vhyst_l, it is possible to reduce the supply current of the oscillator, for example this time by a factor of 4 compared to the current at time t5.

[0108] At time t8, a pulse is still present on the Status low and Status high signals. The amplitude of Vxo is therefore still greater than 2*(Vhigh-Vref)+Vhyst_l. If we wish to regulate the amplitude of Vxo between 2*(Vlow-Vref)+Vhyst_l and 2*(Vhigh-Vref)+Vhyst_l, it is possible to reduce the supply current of the oscillator, for example this time by a factor of 8 compared to the current at time t5. The same operation is repeated until the amplitude of Vxo returns between 2*(Vlow-Vref)+Vhyst_l and 2*(Vhigh-Vref)+Vhyst_l, i.e. there is no longer a pulse on Status high.

[0109] Dichotomously modulating the oscillator supply current allows the amplitude of Vxo to converge smoothly to the desired voltage range. Other types of feedback are possible.

[0110] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, the number of flip-flops in series in the first, second and third branches 512, 514, 516 of the circuit 430 is for example between zero and more than four. The more flip-flops there are in these branches, the more robustness there is. against parasitic impulses.

[0111] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, as regards the generation of the voltages Vhigh, Vlow and Vref, the person skilled in the art will be able to use his knowledge to deliver voltage-shifted signals from the signal Vxo. Even if the embodiment of [Fig. 7] makes it possible to generate a signal Voutref having a nearly perfect duty cycle of 50%, it is possible to generate Vref in other ways within the reach of the person skilled in the art so that it is not necessary for Vref to be generated to give at the output of the comparator 423 a signal Voutref which has a duty cycle of 50%.

[0112] Circuit 440 is not described in detail but the person skilled in the art will be able to use his knowledge to produce a circuit capable of checking whether pulses are present at the same time on cal clk, Status low and Status high and consequently modulating a parameter of the oscillator to modify its amplitude. The person skilled in the art will be able to use his knowledge for the feedback control acting on the oscillation amplitude of the oscillator 404. In one example, the person skilled in the art will be able to implement an oscillator 404 of Colpitts topology using a negative resistance called Rneg proportional to the current. A current control therefore varies the negative resistance. However, it is also possible to vary the negative resistance Rneg of the Colpitts type assembly by adjusting the values ​​of the capacitors.The person skilled in the art may implement other types of assemblies for the control feedback of the oscillator such as voltage-controlled assemblies.

Claims

Claims

1. Electronic circuit (400) comprising: - a first circuit (410) configured to generate, from a first periodic analog signal (Vxo), several second signals (Vref, Vlow, Vhigh) shifted in voltage level; - a second circuit (420) configured to generate third digital periodic signals (Voutref, Voutlow, Vouthigh) as a function of the crossing, by said second signals (Vref, Vlow, Vhigh), of at least one threshold (Vhyst_l, Vhyst_h); and - a third circuit (430) configured to determine an amplitude range in which the first signal (Vxo) is located, as a function of the number of third signals (Voutref, Voutlow, Vouthigh) present.

2. Method for operating an electronic circuit (400) comprising: - generating, by a first circuit (410) of the electronic circuit, from a first periodic analog signal (Vxo), several second signals (Vref, Vlow, Vhigh) shifted in voltage level; - generating, with a second circuit (420), third digital periodic signals (Voutref, Voutlow, Vouthigh) as a function of the crossing, by said second signals (Vref, Vlow, Vhigh), of at least one threshold (Vhyst_l, Vhyst_h); and - determining, with a third circuit (430), an amplitude range in which the first signal (Vxo) is located, as a function of the number of third signals (Voutref, Voutlow, Vouthigh) present.

3. A circuit according to claim 1, or a method according to claim 2, wherein each third signal (Voutref, Voutlow, Vouthigh) is generated when the corresponding second signal crosses two thresholds (Vhyst.l, Vhyst_h).

4. A circuit according to claim 1 or 3, or a method according to claim 2 or 3, wherein the electronic circuit comprises a fourth circuit (440) configured to allow adjustment of the amplitude of the first signal (Vxo) based on the determination of said amplitude range.

5. A circuit according to claim 1 or 3 or 4, or a method according to any one of claims 2 to 4, wherein the third circuit (430) comprises three branches (512,514,516) each comprising several flip-flops in series, each branch being configured to receive respectively one of the third signals (Voutref, Voutlow, Vouthigh) on the clock input of said flip-flops of this branch.

6. The circuit or method of claim 5, wherein each branch (512,514,516) comprises at least two D-type flip-flops in series.

7. Circuit or method according to claim 6, wherein the third circuit comprises a first logic block (542,543) configured to perform an AND function from an output (N5) of the series of flip-flops of a first branch (512) among said branches (152,154,156) and from an output (N6) of the series of flip-flops of a second branch (514) among said branches (512,514,516).

8. Circuit or method according to claim 7, wherein the third circuit (430) comprises a second logic block (544,545) configured to perform an AND function from the output (N6) of the series of flip-flops of the second branch (514) and from an output (N7) of the series of flip-flops of a third branch (516) among said branches (512,514,516).

9. Circuit or method according to claim 7 or 8, wherein the third circuit (430) is configured to generate a pulse on a first channel when the states of the outputs (N5,N6) of the first (512) and the second branch (516) are identical to a high logic state.

10. Circuit or method according to claim 9, in which the third circuit is configured to generate a pulse on a second channel when the states of the outputs (N6,N7) of the second branch (514) and the third branch (516) are identical to a high logic state.

11. The circuit or method of claim 10, wherein the pulses are generated when the state of the signal at the output of the second branch (514) is at a high state.

12. Circuit according to claim 11, in which the fourth circuit (440) is configured to generate a command making it possible to modify the amplitude of the first signal (Vxo) as a function of the presence or absence of pulses on the first and second channels.

13. A circuit or method according to any one of claims 3 to 12, wherein each third signal (Voutref, Voutlow, Vouthigh) is generated by a respective trigger threshold voltage comparator (421,422,423) having said two thresholds (Vhyst_l, Vhyst_h) as trigger thresholds.

14. A circuit or method according to claim 13, wherein each com- voltage regulator is of the Schmitt trigger type.

15. Circuit or method according to any one of claims 13 or 14, wherein each voltage comparator (421,422,423) has an input node (N2,N3,N4) connected to a first node (NI), intended to receive the signal to be analyzed, via a respective capacitor (401,403,405); each input node (N2,N3,N4) of each comparator (421,422,423) being intended to receive respectively one of the second signals (Vhigh,Vlow,Vref).

16. A circuit or method according to claim 15, wherein the first circuit (410) comprises resistors in series between a supply node (N8) for receiving a supply voltage (VDD) and ground, each of the second signals (Vref, Vlow, Vhigh) being generated from the voltage present on a different node (N2a, N3a, N4a) corresponding to a midpoint of two adjacent resistors of said series of resistors.

17. The circuit or method of claim 16, wherein the first circuit (410) comprises a PMOS transistor (616) and an NMOS transistor (614) each having a conduction node connected to a reference node (N4a), the control nodes of said PMOS and NMOS transistors (614,616) being connected to said reference node (N4a), another conduction node of the PMOS transistor being connected to the power node (N8) and another conduction node of the NMOS transistor being connected to ground.

18. A circuit or method according to claim 17, wherein the reference node (N4a) is connected to ground via one of said resistors (723) of the resistance series.

19. A circuit or method according to claim 18, wherein each comparator (421,422,423) comprises a double inverter circuit connecting the power node (N8) and ground, said double inverter circuit comprising two PMOS transistors (610,612) and two NMOS transistors (614,616) in series; a control node, common to said PMOS and NMOS transistors (610,612,614,616) of said double inverter, being connected to said reference node (N4a).

20. A circuit according to any one of claims 1 or 3 to 19 or a method according to any one of claims 2 to 19, wherein said first signal is from a crystal oscillator.

21. NFC microcontroller comprising a circuit (400) according to any one of claims 1 or 3 to 20.

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