Spin qubit electronic device

Abstract

Spin Qubit Electronic Device This description relates to an electronic device (100) comprising: - a semiconductor nanowire (104); - at least two disjoint first control gates (106), arranged side by side on the side of a first lateral face (108) of the nanowire, and configured to each control the electrostatic potential of a quantum dot (114) to be formed in the nanowire; - at least one second control gate (116) arranged on the side of a second lateral face (118), opposite the first lateral face, of the nanowire, and configured to control the electrostatic potential of a coupling region to be formed between two quantum dots; wherein all the first control gates are arranged only on the side of the first lateral face, and the second control gate(s) are arranged only on the side of the second lateral face. Figure for the abstract: Fig. 1

Description

Title of the invention: Spin qubit electronic device technical field

[0001] The present description relates in general to the field of spintronics, quantum devices and quantum computing. Previous technique

[0002] Quantum devices with qubits exist that are based on the formation of quantum dots, which ensure the confinement of elementary charges (electrons or holes). Quantum information is, for example, encoded on the spin of these particles. Quantum dots are formed by grids through which electrical confinement potentials are created. These grids allow for local adjustment of the electrostatic potential of the quantum dots, that is, the depth of the potential wells of the quantum dots. It is also necessary to be able to electrically control the tunneling coupling, that is, the height of the tunnel barriers, between neighboring quantum dots.

[0003] According to a first configuration, grids controlling the coupling between neighboring quantum dots and grids controlling the potentials of the quantum dots can be implemented in the same grid level, side by side. This first configuration is described, for example, in the document Ensar Vahapoglu et al., “Single-electron spin resonance in a nanoelectronic device using a global field” Sci. Adv., vol. 7 Issue 33, 13 August 2021, eabg9158.

[0004] One problem encountered with this first configuration is that the presence of all these control grids in the same level requires that the grids controlling the potentials in the quantum dots have a pitch, that is to say a space between the grids controlling the potentials of two neighboring quantum dots, which is relatively large in order to have the space necessary for the realization of the grids controlling the coupling between the neighboring quantum dots.

[0005] According to a second configuration, the grids controlling the coupling between neighboring quantum dots can be realized in a different grid level than that of the grids controlling the potentials of the quantum dots. This second configuration is described for example in the document by T. Bédécarrats et al., "A new FDSOI spin qubit platform with 40nm effective control pitch", 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 1-4.

[0006] One problem encountered with this second configuration is that the larger distance (for example, a few tens of nanometers) between the level of the grids controlling the coupling between neighboring quantum dots and the semi The conductor in which the quantum dots are made results in a less good electrostatic control of these grids. Summary of the invention

[0007] There is therefore a need to propose an electronic device that does not present one or more of the disadvantages described above.

[0008] One embodiment proposes a solution to all or part of the drawbacks of known solutions and relates to an electronic device comprising:

[0009] - a semiconductor nanowire;

[0010] - at least two first disjoint control grids, arranged one next to the the other on the side of a first lateral face of the semiconductor nanowire, and configured to each control the electrostatic potential of a quantum dot intended to be formed in the semiconductor nanowire;

[0011] - at least one second control grid arranged on the side of a second face lateral, opposite to the first lateral face, of the semiconductor nanowire, and configured to control the electrostatic potential of a coupling region intended to be formed between two quantum dots;

[0012] in which all the first control grids of the electronic device are arranged only on the side of the first lateral face, and the or all the second control grids of the electronic device are arranged only on the side of the second lateral face.

[0013] According to a particular embodiment, at least a part of an orthogonal projection of the second control grid in a plane parallel to the first lateral face of the semiconductor nanowire is arranged between orthogonal projections of the first two control grids in the plane parallel to the first lateral face of the semiconductor nanowire.

[0014] According to a particular embodiment, no part of the second grid is arranged between the first grids.

[0015] According to a particular embodiment, each of the first control grids covers a part of the first lateral face of the semiconductor nanowire and / or the second control grid covers a part of the second lateral face of the semiconductor nanowire.

[0016] According to a particular embodiment, each of the first control grids covers a part of an upper face of the semiconductor nanowire that is perpendicular to the first and second lateral faces, and / or the second control grid covers a part of the upper face of the semiconductor nanowire.

[0017] According to a particular embodiment, the parts of the upper face covered by the first control grids extend from a first edge su the upper surface of the semiconductor nanowire formed at the junction of the first side face and the top face, up to about half the distance separating the first and second side faces from each other.

[0018] According to a particular embodiment, the parts of the upper face covered by the first control grids extend from a first upper edge of the semiconductor nanowire formed at the junction of the first lateral face and the upper face to a second upper edge of the semiconductor nanowire formed at the junction of the second lateral face and the upper face.

[0019] According to a particular embodiment, the part of the upper face covered by the second control grid extends from a second upper edge of the semiconductor nanowire formed at the junction of the second lateral face and the upper face to about half the distance separating the first and second lateral faces from each other.

[0020] According to a particular embodiment, the electronic device further comprises a dielectric portion traversing the semiconductor nanowire from the upper face of the semiconductor nanowire to a lower face of the semiconductor nanowire opposite the upper face and arranged:

[0021] - between the parts of the upper face of the semiconductor nanowire covered by the first control gates and the portion of the top surface of the semiconductor nanowire covered by the second control gate, or

[0022] - between a portion of the upper face of the semiconductor nanowire disposed between the parts of the top face of the semiconductor nanowire covered by the first control gates and the part of the top face of the semiconductor nanowire covered by the second control gate.

[0023] According to a particular embodiment:

[0024] - an upper face of the second control grid, parallel to the upper face the upper surface of the semiconductor nanowire, is arranged in the same foreground plane as an upper face of each of the first control grids, or

[0025] - the upper face of each of the first control grids is arranged in a first plane located between a second plane in which is arranged the upper face of the second control grid and a third plane in which is arranged an upper face of the semiconductor nanowire which is perpendicular to the first and second lateral faces.

[0026] According to another embodiment, a method for implementing an electronic device is proposed, comprising:

[0027] - implementation of at least two first disjoint control grids, arranged one next to the other on the side of a first lateral face of a semi- nanowire conductor, and configured to each control the electrostatic potential of at least one quantum dot intended to be formed in the semiconductor nanowire;

[0028] - implementation of at least a second control grid arranged on the side of a second lateral face, opposite to the first lateral face, of the semiconductor nanowire, and configured to control the electrostatic potential of a coupling region intended to be formed between two quantum dots;

[0029] and in which all the first control grids of the electronic device are arranged only on the side of the first lateral face, and the or all the second control grids of the electronic device are arranged only on the side of the second lateral face.

[0030] According to a particular embodiment, the first and second control grids are implemented by:

[0031] - of at least one "lift-off" type deposit of at least one electrically driver, or

[0032] - of at least one deposit of at least one layer of electrically conductive material on a substrate including the semiconductor nanowire, then at least one etching of the layer of electrically conductive material made through openings made in a mask.

[0033] According to a particular embodiment, the method further comprises, after the "lift off" type deposition of the electrically conductive material or after the etching of the layer of electrically conductive material, the implementation of an additional etching of remaining portions of the electrically conductive material or of the layer of electrically conductive material, completing the realization of the first and second control grids.

[0034] According to a particular embodiment, the realization of the first and second control grids is implemented such that at least a part of an orthogonal projection of the second control grid in a plane parallel to the first lateral face of the semiconductor nanowire is disposed between orthogonal projections of the first two control grids in the plane parallel to the first lateral face of the semiconductor nanowire. Brief description of the drawings

[0035] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0036] - Figures [Fig. 1] and [Fig. 2] represent a first example of an electronic device according to a particular embodiment;

[0037] - [Fig. 3] represents a particular configuration of the first example device electronic according to a particular embodiment;

[0038] - Figures [Fig. 4] and [Fig. 5] represent a second example of an electrical device tronic according to a particular embodiment;

[0039] - Fig. 6 represents a particular configuration of the second example of electronic device according to a particular embodiment;

[0040] - Figure 7 represents a third example of an electronic device according to a particular embodiment;

[0041] - Fig. 8 represents a fourth example of an electronic device according to a particular embodiment;

[0042] - Fig. 9 represents a fifth example of an electronic device according to a particular embodiment;

[0043] - Figure 10 represents simulations of the tunnel coupling control between two quantum dots obtained in an electronic device according to a particular embodiment;

[0044] - [Fig. 11], [Fig. 12] and [Fig. 13] represent the steps of a first example of a method for manufacturing an electronic device according to a particular embodiment;

[0045] - [Fig. 14] represents one of the steps in a second example of a process for adaptation of an electronic device according to a particular embodiment;

[0046] - [Fig. 15] represents a sixth example of an electronic device according to a particular embodiment;

[0047] - [Fig. 16] represents a seventh example of an electronic device according to a a particular method of implementation. Description of the implementation methods

[0048] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0049] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0050] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0051] In the following description, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or Relative terms, such as "above," "below," "superior," "inferior," "lateral," etc., or orientation qualifiers, such as "horizontal," "vertical," etc., refer, unless otherwise specified, to the orientation of the figures. However, these terms do not imply the actual position and orientation of the device during its use.

[0052] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean within 10%, preferably within 5%.

[0053] A first example of an electronic device 100 according to a particular embodiment is described below in relation to Figures 1 and 2. [Fig.1] is a top view of the device 100 and [Fig.2] is a side section view of the device 100.

[0054] In this first example, as well as in the following embodiments, the device 100 comprises at least one support layer 102 on which a semiconductor nanowire 104 is disposed. According to a particular embodiment of the device 100, the nanowire 104 may correspond to a remaining portion of a surface semiconductor layer of a semiconductor-on-insulator substrate, for example, SOI (Silicon On Insulator). The support layer 102, in this case, may correspond to the stack comprising the buried dielectric layer disposed on the bulk semiconductor layer of the semiconductor-on-insulator substrate. The buried dielectric layer corresponds, for example, to a layer of SiO2, and the bulk layer comprises, for example, silicon.

[0055] For example, the nanowire 104 may contain silicon when the qubits intended for use in the device 100 are electron or hole qubits. Alternatively, the nanowire 104 may contain, for example, germanium when the qubits intended for use in the device 100 are hole qubits.

[0056] In this first example, as well as in the following embodiments, a width W of the 104 nanowire (dimension parallel to the Y-axis visible in Figures 1 and 2) is, for example, between 15 nm and 120 nm, or between 30 nm and 120 nm. A thickness H of the 104 nanowire (dimension parallel to the Z-axis visible in Figures 1 and 2) is, for example, between 5 nm and 20 nm. Finally, a length L of the 104 nanowire (dimension parallel to the X-axis visible in Figures 1 and 2) is a function of the number of quantum dots to be formed in the 104 nanowire, and is, for example, between 30 nm and 100 nm per qubit.

[0057] In this first example, as well as in some of the following embodiments, the device 100 comprises at least two first disjoint control grids 106, arranged side by side, each covering a portion of a first lateral face 108 of the nanowire 104 (face parallel to the (X,Z) plane in Figures 1 and 2), of a top face 112 of the nanowire 104 (face parallel to the (X,Y) plane in Figures 1 and 2), and of a first top edge 110 of the nanowire 104 formed at the The junction of the first lateral face 108 and the upper face 112. The first gates 106 are configured here to each control the electrostatic potential of one of the quantum dots 114 intended to be formed in the nanowire 104. Each of the first gates 106 has at least one electrically conductive portion. Part of each first gate 106 rests on the support layer 102 and another part of each first gate 106 rests on a portion of a dielectric layer 115 located on the nanowire 104.

[0058] In this first example and in the following embodiment examples, the device 100 comprises four first grids 106. Alternatively, the device 100 may, however, comprise a different number of first grids 106, this number being a function of the number of quantum dots 114 intended to be formed in the nanowire 104.

[0059] In a particular configuration applicable to the different embodiments of the device 100 described, each of the first grids 106 may include at least one electrically conductive material such as polysilicon, or a stack of several materials such as a stack of TiN, polysilicon and silicide.

[0060] In Figures 1 and 2, the quantum dots 114 intended to be formed in the nanowire 104 are symbolically represented. These quantum dots 114 are intended to be formed in parts of the nanowire 104 subjected to the electrostatic control of the first grids 106, this electrostatic control being obtained via the electrical potential applied to each of these first grids 106.

[0061] In a particular configuration applicable to the various embodiments of the device 100, each of the first grids 106 has a length LG (dimension parallel to the length L of the nanowire 104), for example, between 20 nm and 60 nm, and a height HG (dimension parallel to the height H of the nanowire 104), for example, between 20 nm and 60 nm. The height HG of the first grids 106 depends in particular on the material(s) used to form these first grids 106. In addition, two adjacent first grids 106 are spaced apart from each other by a distance SG (parallel to the length LG of each of the first grids 106), for example, between 20 nm and 100 nm. Finally, the part of each of the first grids 106 arranged on the upper face 112 of the nanowire 104 extends over a dimension RG, perpendicular to the length LG, for example between 0.2*W and W.

[0062] In a particular configuration that may correspond to that shown in Figures 1 and 2, the portions of the upper face 112 covered by the first grids 106 may extend from the first upper edge 110 to half the distance separating the first and second lateral faces 108, 118 from each other. In other words, in this particular configuration, RG = W / 2.

[0063] In the first example, as well as in the following embodiments of the device 100, the nanowire 104 is coated with a dielectric layer 115 intended to serve, in particular, as a gate oxide for the first gates 106. The dielectric layer 115 comprises, for example, SiO2 and / or Al2O3. The thickness of the dielectric layer 115 is, for example, between 2 nm and 20 nm. In [Fig. 1], the dielectric layer 115 is not shown so that the nanowire 104 is visible.

[0064] In this first example as well as in the following embodiment examples, the device 100 includes at least one second control grid 116 covering a part of a second lateral face 118, opposite to the first lateral face 108, of the nanowire 104, and configured to control the electrostatic potential of a coupling region intended to be formed between two quantum dots 114. In the example of [Fig.1], the control of the electrostatic potential of a coupling region intended to be formed between two quantum dots 114, by one of the second grids 116, is symbolically represented by an arrow.

[0065] In the following description, reference is made to several second control grids 116 of the device 100. However, the various characteristics described in connection with the second control grids 116 would also apply to the single second control grid 116 of the device 100 if the device 100 had only one second control grid 116.

[0066] In this first example as well as in the following embodiment examples, the device 100 includes three second grids 116. Alternatively, the device 100 may include a different number of second grids 116, this number being a function of the number of coupling regions between quantum dots 114 to be controlled.

[0067] In a particular configuration applicable to the various embodiments of the device 100, each of the second grids 116 has a length Lj (dimension parallel to the length L of the nanowire 104), for example, between 20 nm and 60 nm, and a height Hj (dimension parallel to the height H of the nanowire 104), for example, between 20 nm and 100 nm. In addition, two adjacent second grids 116 are spaced apart by a distance Sj (parallel to the length Lj of each of the second grids 116), for example, between 10 nm and 80 nm.

[0068] In the first embodiment, each of the second grids 116 has a height Hj equal to the height HG of the first grids 106. Thus, a top face 119 of each of the first grids 106, parallel to the top face 112 of the nanowire 104, is arranged in the same plane as a top face 121 of each of the second grids 116, also parallel to the top face 112 of the nanowire 104.

[0069] In the first embodiment, the second grids 116 do not cover parts of the upper face 112 of the nanowire 104. Furthermore, in the described example, the dielectric layer 115 also forms the grid oxide for the second grids 116.

[0070] In this first embodiment, for each of the second grids 116, at least a portion of an orthogonal projection, onto the first lateral face 108, of the portion of the second lateral face 118 covered by the second grid 116 is arranged between the portions of the first lateral face 108 covered by two adjacent first grids 106. In a particular configuration such as shown in Figures 1 and 2, the edges of the second grid 116 can be aligned with those of the first two grids 106, which means that there is no overlap between the orthogonal projection, onto the first lateral face 108, of the portion of the second lateral face 118 covered by each of the second grids 116 and the portions of the first lateral face 108 covered by the first two grids 106 arranged on either side of this second grid 116.Alternatively, it is possible to have such a partial overlap, for example such that at most, half of the surface of the orthogonal projection, on the first lateral face 108, of the part of the second lateral face 118 covered by each of the second grids 116 covers the parts of the first lateral face 108 covered by the first two grids 106 arranged on either side of this second grid 116.

[0071] A particular configuration of the electronic device 100 according to the first example is described below in relation to [Fig.3] which is a lateral cross-sectional view of the device 100.

[0072] The device 100 according to this particular configuration comprises all the elements of the device 100 according to the first example previously described.

[0073] However, in this particular configuration, the parts of the upper face 112 covered by the first grids 106 extend from the first upper edge 110 to a second upper edge 120 of the nanowire 104 formed at the junction of the second lateral face 118 and the upper face 112. Thus, in this particular configuration, RG = W.

[0074] A second example of an electronic device 100 according to a particular embodiment is described below in relation to Figures 4 and 5. [Fig.4] is a side section view of the device 100 and [Fig.5] is a top view of the device 100.

[0075] Device 100 according to this second example includes all the elements of device 100 according to the first example previously described.

[0076] However, in this second example, each of the second control grids 116 also covers a part of the second upper edge 120 of the nanowire 104, and a part of the upper face 112 of the nanowire 104.

[0077] In this second example, the portion of each of the second grids 116 arranged on the upper face 112 of the nanowire 104 can extend over a dimension Rj, perpendicular to the length Lj, for example between 0 and W / 2, or more generally such that RG + Rj < W.

[0078] In a particular configuration of this second example, the portions of the upper face 112 covered by the second grids 116 can extend from the second upper edge 120 to half the distance separating the first and second lateral faces 108, 118 from each other. In other words, in this particular configuration, Rj = W / 2. Such a particular configuration is shown in [Fig. 6].

[0079] A third example of an electronic device 100 according to a particular embodiment is described below in relation to [Fig.7] corresponding to a lateral sectional view of the device 100.

[0080] The device 100 according to this third example comprises all the elements of the device 100 according to the first and second examples described above. Furthermore, as in the first example described above, the second grids 116 do not cover parts of the upper face 112 of the nanowire 104.

[0081] On the other hand, unlike the previous examples in which each of the second grids 116 has a height Hj equal to the height HG of the first grids 106, the height Hj of each of the second grids 116 of the device 100 according to this third example is greater than the height HG of the first grids 106. By way of example, the value of the ratio Hj / Hg can be, for example, between 1 and 3. In this third example, the upper face 119 of each of the first grids 106 is arranged in a first plane located between a second plane in which the upper face 121 of each of the second grids 116 is arranged and a third plane in which the upper face 112 of the nanowire 104 is arranged.This configuration in which the height Hj of the second 116 grids is greater than the height HG of the first 106 grids further improves the electrostatic control of the coupling regions between the 114 quantum dots by the second 116 grids.

[0082] This characteristic, whereby each of the second grids 116 has a height Hj greater than the height HG of the first grids 106, can be applied to the examples of the device 100 described previously. In other words, it is possible to have second grids 116 with a height Hj greater than the height HG of the first grids 106 and which also cover a portion of the upper face 112 of the nanowire 104 (with Rj > 0).

[0083] A fourth example of an electronic device 100 according to a particular embodiment is described below in relation to [Fig.8] which is a top view of the device 100.

[0084] Device 100 according to this fourth example includes all the elements of device 100 according to the third example previously described.

[0085] The device 100 according to this fourth example further comprises a portion di electric 122 passing through the nanowire 104 from the upper face 112 to a lower face of the nanowire 104 opposite the upper face 112. The thickness of the dielectric portion 122 (dimension parallel to the Z axis) is therefore here at least equal to the thickness H of the nanowire 104.

[0086] The dielectric portion 122 is arranged between the parts of the upper face 112 of the nanowire 104 covered by the first grids 106 and the parts of the upper face 112 of the nanowire 104 covered by the second grids 116.

[0087] The length of portion 122 (a dimension parallel to the length L of the nanowire 104) is, for example, such that each of the first grids 106 is positioned opposite portion 122. The width of portion 122 (a dimension parallel to the width W of the nanowire 104) is, for example, equal to W - RG - Rj, as is the case in [Fig. 8]. Alternatively, it is possible that the width of portion 122 is less than W - RG - Rj.

[0088] In this fourth example, it is possible that each of the second grids 116 has a height Hj greater than or equal to the height HG of the first grids 106.

[0089] A fifth example of an electronic device 100 according to a particular embodiment is described below in relation to [Fig.9] which is a top view of the device 100.

[0090] The device 100 according to this fifth example comprises all the elements of the device 100 according to the fourth example described above. However, compared to the device 100 according to the fourth example described above, the device 100 according to this fifth example comprises several distinct and separate dielectric portions 122. Each of the dielectric portions 122 passes through the nanowire 104 from the upper face 112 to the lower face of the nanowire 104. The thickness of each of the dielectric portions 122 (dimension parallel to the Z-axis) is therefore equal to the thickness H of the nanowire 104.

[0091] In this fifth example, each of the dielectric portions 122 is disposed between a part of the upper face 112 of the nanowire 104 disposed between the parts of the upper face 112 of the nanowire 104 covered by the first grids 106 and the part of the upper face 112 of the nanowire 104 covered by one of the second grids 116.

[0092] The length of each of the portions 122 (dimension parallel to the length L of the nanowire 104) is, for example, greater than or equal to the length LG of each of the second grids 116 (equal in the example of [Fig. 9]). The width of each of the portions 122 (dimension parallel to the width W of the nanowire 104) is, for example, equal to W - Rg - Rj. Alternatively, it is possible that the width of each of the portions 122 is less than W - RG - Rj.

[0093] In this fifth example, it is possible that each of the second grids 116 has a height Hj greater than or equal to the height HG of the first grids 106.

[0094] In the various embodiments of the device 100, an electrical potential can be applied to the first grids 106 to create the quantum dots 114 in the nanowire 104. The second grids 116 are used to couple or decouple the qubits of the quantum dots 114 as needed, by applying suitable electrical potentials to them.

[0095] In all the embodiments of the device 100 described above, the overlap of the first grids 106 on the upper face 112 of the nanowire 104 strongly limits the impact of the second grids 116 on the electrostatic phenomena occurring in the regions of the nanowire 104 where the quantum dots 114 are formed.

[0096] In all embodiments of the device 100, the second grids 116 intended to ensure the control of the tunnel coupling between the quantum dots 114 are made at the same level, with a height Hj greater than or equal to the height HG of the first grids 106, as the first grids 106 intended to ensure the formation of the quantum dots 114 in the nanowire 104, and aligned opposite the spaces between the first grids 106.

[0097] In the various embodiments of the device 100 described above, for each of the second grids 116, at least a portion of an orthogonal projection, onto the first lateral face 108, of the portion of the second lateral face 118 covered by the second grid 116 is arranged between the portions of the first lateral face 108 covered by two adjacent first grids 106. This arrangement of the second grids 116 relative to the first grids 106 makes it possible to obtain strong electrostatic control of the tunneling coupling between the quantum dots 114, while avoiding the formation of unwanted quantum dots under the second grids 116.

[0098] The curves visible in [Fig. 10] represent the variation of the tunneling coupling t, expressed in peV, obtained in a device 100 by varying the voltage Vj, expressed in mV and corresponding to DC voltage pulses, applied to the second grids 116 of the device 100, and for different values ​​of voltage VG, expressed in mV, applied to the first grids 106 of the device 100 forming the quantum dots 114 in which electrons or holes are trapped and whose tunneling coupling is controlled. The curves referenced 10, 20, 30, 40 and 50 represent respectively the tunneling coupling t obtained for voltage values ​​VG of 50 mV, 75 mV, 100 mV, 125 mV and 150 mV respectively and for a variation of Vj between -0.4 mV and -0.05 mV.

[0099] These simulations show that in the device 100, the tunnel coupling between two quantum dots 114 can switch from an open state (t > 101 peV) to a closed state (t < 102 peV), or vice versa, with a variation of the voltage Vj applied to the second grids 116 of the order of 43 mV.

[0100] The control, called a, of the tunnel coupling t can be expressed by the equation: [Math 1] _ slogan

[0101] With device 100, the tunnel coupling control obtained is on the order of 900 VA. By way of comparison, the tunnel coupling control obtained with prior art devices is generally less than about 40 VA.

[0102] In the various examples described above, the edges of each of the second grids 116 are aligned with those of two neighboring first grids 106, which implies that LG = Sj and that Lj = SG. Alternatively, it is possible to have an overlap between the orthogonal projection, onto the first lateral face 108, of the part of the second lateral face 118 covered by the second grid 116 and the parts of the first lateral face 108 covered by the two neighboring first grids 106. In this case, the dimensions LG, SG, Lj, and Sj are such that Lj > SG and LG > Sj.

[0103] In all embodiment examples, it is possible to have LG > SG and Lj > Sj, which makes it possible to reduce the grid pitch achievable with device 100.

[0104] In all embodiment examples, it is also possible to have second grids 116 that are longer than the first grids 106, i.e., such that Lj > Lg, or shorter than the first grids 106, i.e., such that Lj < LG. Similarly, the dimension SG can be greater than, less than, or equal to the dimension Sj.

[0105] In all embodiment examples, it is possible to dimension and position the first and second grids 106, 116 such that LG + SG = Lj + Sj.

[0106] In all embodiment examples, the first and second grids 106, 116 can be dimensioned such that RG + Rj < W in order to avoid problems of unwanted electrical contact between the first and second grids 106, 116.

[0107] The device 100 may include a grid structure 106, 116 compatible with manufacturing processes in the microelectronics industry and which allows strong electrostatic control over the tunneling coupling between the quantum dots 114. The first grids 106 used for the formation of the quantum dots 114 and the second grids 116 used for controlling the tunneling coupling between the quantum dots 114 are arranged in the same grid level, which facilitates their realization.

[0108] The device 100 comprises at least two first grids 106, the number of first grids 106, and therefore also of second grids 116, being chosen according to the number of quantum dots 114 to be formed and controlled in the nanowire 104.

[0109] A first example of a method for realizing the electronic device 100 is described below in relation to figures 11 to 13.

[0110] The nanofil 104 is first produced, for example by etching the super layer fictitious of an SOI substrate. Other techniques can be implemented to form the nanowire 104 on the support layer 102.

[0111] The dielectric layer 115 is then made so as to cover the nanowire 104. For example, when the dielectric layer 115 comprises SiO2 and the nanowire 104 comprises silicon, the dielectric layer 115 can be made by thermal oxidation of the silicon of the nanowire 104.

[0112] The first grids 106 are then produced, for example by a "lift-off" type deposition of one or more electrically conductive materials. The structure obtained at this stage of the process is shown in [Fig. 11].

[0113] The second grids 116 are then produced, for example by a "lift-off" type deposition of one or more electrically conductive materials. The structure obtained at this stage of the process is shown in [Fig. 12].

[0114] An engraving step of the first and second grids 106, 116 is then carried out in order to obtain the desired dimensions for these grids 106, 116, in particular the desired dimensions RG and Rj. The device 100 thus obtained is shown in [Fig. 13].

[0115] As an alternative to the process described above, it is possible that the first and second grids 106, 116 are produced by implementing the same deposition step.

[0116] A second example of a method for making an electronic device 100 is described below.

[0117] The nanowire 104 and the dielectric layer 115 are first made, for example as previously described for the first example of a method for making the device 100.

[0118] One or more layers 124 of electrically conductive material are then deposited on the whole of the structure produced, i.e. on the nanowire 104 covered by the dielectric layer 115 and on the parts of the support layer 102 not covered by the nanowire 104 and the dielectric layer 115. [Fig. 14] represents a top view of the structure obtained at this stage of the process.

[0119] The layer(s) 124 are then etched using a hard mask, forming the first grids 106 and the second grids 116 either during the same etching step or during separate etching steps. The structure obtained at this stage of the process is similar to that shown in [Fig. 12].

[0120] An engraving step of the first and second grids 106, 116 is then carried out in order to obtain the desired dimensions for these grids 106, 116, in particular the desired dimensions RG and Rj. The device 100 thus obtained is similar to that shown in [Fig. 13].

[0121] As an alternative to the processes described above, it is possible to carry out the first and second grids 106, 116 directly to the desired dimensions, without having to implement the final engraving step described in connection with [Fig. 13].

[0122] Fig. 15 represents a fifth embodiment of device 100.

[0123] In this fifth example, unlike the previous embodiments, neither the first grids 106 nor the second grids 116 cover the upper face 112 of the nanowire 104, nor the upper edges 110, 120 of the nanowire 104. Furthermore, each of the first grids 106 covers a portion of the first lateral face 108 of the nanowire 104, and each of the second grids 116 covers a portion of the second lateral face 118 of the nanowire 104. In this fifth example, the following relationship is verified: RG = Rj = 0. The other features and variants previously described for the preceding embodiments, such as having first grids 106 with a different height than the second grids 116 (Hj HG), can be applied to this fifth embodiment.

[0124] Fig. 16 represents a sixth embodiment of device 100.

[0125] In this sixth example, unlike the previous embodiments, neither the first grids 106 nor the second grids 116 cover parts of the first and second lateral faces 108, 118 of the nanowire 104. Furthermore, each of the first grids 106 covers a part of the upper face 112 of the nanowire 104. The second grids 116 do not cover the upper face 112 of the nanowire 104. In this sixth example, the dimension RG is non-zero, and the dimension Rj is zero. Alternatively, it is possible that the second grids 116 cover a part of the upper face 112 of the nanowire 104, and therefore that Rj > 0, and / or that the heights HG and Hj of the first and second grids 106, 116 are different.

[0126] In this sixth example, the first and second grids 106, 116 do not rest directly on the support layer, but on at least one dielectric material 126 interposed between the support layer 102 and the first and second grids 106, 116. The dielectric material 126 can, for example, also be used to form the dielectric layer 115.

[0127] In this sixth example, the first and second grids 106, 116 form planar grids.

[0128] In all embodiments, the first control grids 106 are arranged on the side of the first lateral face 108 of the nanowire 104, and the second control grids 116 are arranged on the side of the second lateral face 118 of the nanowire 104.

[0129] In the various embodiment examples described, it is possible that no part of the second grid 116 is arranged, physically or in projection for example in a plane parallel to the first lateral face 108, between the first two grids 106.

[0130] In the various embodiments, at least part of a projection or thogonal of the or each of the second control grids 116 in a plane perpendicular to the upper face 112 of the nanowire 104, or in a plane parallel to the lateral faces 108, 118, can be arranged between orthogonal projections of two first control grids 106 in the plane perpendicular to the upper face 112 or in the plane parallel to the lateral faces 108, 118.

[0131] In the various embodiment examples, the first control grids 106 can be arranged in the same plane as the second control grid(s) 116.

[0132] In the various embodiments described above, except for the one described in relation to [Fig. 8], when Rj is non-zero, i.e., when the second grids 116 cover parts of the upper face 112 of the nanowire 104, the second grids 116 can be used to perform, in addition to controlling the coupling regions between the quantum dots 114, a spin read based on Pauli blockade (Elzerman-type read). In this case, the spin read is performed using quantum dots formed under the second grids 116.

[0133] In order to avoid triggering unwanted charge transfers with the qubits, and when the Rj dimension is non-zero, the device 100 can preferably be made such that it includes one or more dielectric portions 122 as previously described in connection with Figures 8 and 9, since this or these dielectric portions 122 then prevent such charge transfers. The second grids 116 can in this case be used as charge detectors by means of quantum dots formed under the second grids 116.

[0134] As an alternative to reading the qubits by the second grids 116, the reading of the qubits of the quantum dots 100 can be carried out using auxiliary quantum dots formed near lateral faces of the nanowire 104 which are for example perpendicular to the lateral faces 108, 118. For example, considering the device 100 shown in [Fig.1], these auxiliary quantum dots can correspond to those formed under each of the first two grids 106 closest to the ends of the nanowire 104.

[0135] As an alternative to the various embodiments described above, the nanofil 104 may not correspond to a remaining portion of a surface layer of a semiconductor-on-insulator type substrate, and may be formed, for example by deposition or any other suitable technique, on or from another type of support layer 102 corresponding for example to a bulk or massive substrate such as a semiconductor wafer.

[0136] As an alternative to the various embodiments described above, the gate oxides arranged between the nanowire 104 and the first gates 106 and / or the second gates 116 can be formed from portions of dielectric material different from the dielectric layer 115.

[0137] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0138] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the information given above. For example, the nature (wet, dry, etc.) of each of the engravings used can be chosen according to, in particular, the material(s) to be engraved.

Claims

Claims

1. Electronic device (100) comprising: - a semiconductor nanowire (104); - at least two first disjoint control gates (106), arranged next to each other on the side of a first lateral face (108) of the semiconductor nanowire (104), and configured to each control the electrostatic potential of a quantum dot (114) intended to be formed in the semiconductor nanowire (104); - at least one second control gate (116) arranged on the side of a second lateral face (118), opposite the first lateral face (108), of the semiconductor nanowire (104), and configured to control the electrostatic potential of a coupling region intended to be formed between two quantum dots (114);wherein all of the first control grids (106) of the electronic device (100) are arranged only on the side of the first lateral face (108), and the or all of the second control grids (116) of the electronic device (100) are arranged only on the side of the second lateral face (118).;

2. The electronic device (100) of claim 1, wherein at least a portion of an orthogonal projection of the second control gate (116) in a plane parallel to the first side face (108) of the semiconductor nanowire (104) is disposed between orthogonal projections of the two first control gates (106) in the plane parallel to the first side face (108) of the semiconductor nanowire (104).

3. An electronic device (100) according to one of the preceding claims, wherein no portion of the second grid (116) is disposed between the first grids (106).

4. Electronic device (100) according to one of the preceding claims, wherein each of the first control gates (106) covers a portion of the first lateral face (108) of the semiconductor nanowire (104) and / or wherein the second control gate (116) covers a portion of the second lateral face (118) of the nanowire of semiconductor (104).

5. An electronic device (100) according to one of the preceding claims, wherein each of the first control gates (106) covers a portion of an upper face (112) of the semiconductor nanowire (104) which is perpendicular to the first and second side faces (108, 118), and / or wherein the second control gate (116) covers a portion of the upper face (112) of the semiconductor nanowire (104).

6. The electronic device (100) of claim 5, wherein the portions of the top face (112) covered by the first control gates (106) extend from a first top edge (110) of the semiconductor nanowire (104) formed at the junction of the first side face (108) and the top face (112), to about half the distance separating the first and second side faces (108, 118) from each other.

7. An electronic device (100) according to claim 5, wherein the portions of the upper face (112) covered by the first control gates (106) extend from a first upper edge (110) of the semiconductor nanowire (104) formed at the junction of the first lateral face (108) and the upper face (112) to a second upper edge (120) of the semiconductor nanowire (104) formed at the junction of the second lateral face (118) and the upper face (112).

8. The electronic device (100) of claim 5 or 6, wherein the portion of the upper face (112) covered by the second control gate (116) extends from a second upper edge (120) of the semiconductor nanowire (104) formed at the junction of the second lateral face (118) and the upper face (112) to approximately half the distance separating the first and second lateral faces (108, 118) from each other.

9. An electronic device (100) according to claim 5, further comprising a dielectric portion (122) passing through the semiconductor nanowire (104) from the upper face (112) of the semiconductor nanowire (104) to a lower face of the semiconductor nanowire (104) opposite the upper face (112) and arranged: - between the parts of the upper face (112) of the semiconductor nanowire (104) covered by the first control gates (106) and the part of the upper face (112) of the semiconductor nanowire conductor (104) covered by the second control grid (116), or - between a portion of the upper face (112) of the semiconductor nanowire (104) arranged between the portions of the upper face (112) of the semiconductor nanowire (104) covered by the first control gates (106) and the portion of the upper face (112) of the semiconductor nanowire (104) covered by the second control gate (116).

10. Electronic device (100) according to one of the preceding claims, wherein: - an upper face (121) of the second control grid (116), parallel to the upper face (112) of the semiconductor nanowire (104), is arranged in the same first plane as an upper face (119) of each of the first control grids (106), or - the upper face (119) of each of the first control grids (106) is arranged in a first plane located between a second plane in which the upper face (121) of the second control grid (116) is arranged and a third plane in which an upper face (112) of the semiconductor nanowire (104) is arranged which is perpendicular to the first and second lateral faces (108, 118).

11. Method for producing an electronic device (100), comprising: - production of at least two first disjoint control grids (106), arranged one next to the other on the side of a first lateral face (108) of a semiconductor nanowire (104), and configured to each control the electrostatic potential of at least one quantum box (114) intended to be formed in the semiconductor nanowire (104); - production of at least one second control gate (116) arranged on the side of a second lateral face (118), opposite the first lateral face (108), of the semiconductor nanowire (104), and configured to control the electrostatic potential of a coupling region intended to be formed between two quantum dots (114); and wherein all of the first control grids (106) of the electronic device (100) are arranged only on the side of the first lateral face (108), and the or all of the second control grids (116) of the electronic device (100) are arranged only on the side of the second lateral face (118).

12. Method according to claim 11, in which the first and second control gates (106, 116) are produced by implementing: - at least one “lift off” type deposition of at least one electrically conductive material, or - at least one deposition of at least one layer of electrically conductive material (124) on a substrate including the semiconductor nanowire (104), then at least one etching of the layer of electrically conductive material (124) carried out through openings provided in a mask.

13. The method of claim 12, further comprising, after the lift-off deposition of the electrically conductive material or after the etching of the layer of electrically conductive material (124), carrying out an additional etching of remaining portions of the electrically conductive material or of the layer of electrically conductive material (124), completing the production of the first and second control gates (106, 116).

14. Method according to one of claims 11 to 13, the production of the first and second control gates (106, 116) is implemented such that at least a part of an orthogonal projection of the second control gate (116) in a plane parallel to the first lateral face (108) of the semiconductor nanowire (104) is arranged between orthogonal projections of the two first control gates (106) in the plane parallel to the first lateral face (108) of the semiconductor nanowire (104).

Images