Method for listening to a multipoint MDB bus

Abstract

The invention relates to a method for listening to data transmitted via a multipoint bus (MDB), the method comprising the steps of: connecting a terminal (MT) to a first link (L3) to be observed on the MDB bus (B2), transmitting a data signal emitted by a slave device (SL1, SL2) to a master device (MS1); interposing a matching circuit (ACT) on the first link to be observed; receiving a data signal transmitted by the slave device; transforming the received data signal by increasing the voltage difference between a high and a low state of the data signal, and by reducing the transition time between the high and low states; transmitting the transformed data signal to the master device and the terminal; and acquiring, by the terminal and the master device, data transmitted by the transformed data signal, at the connection point of the master device and the terminal. Figure 2

Description

Title of the invention: Method for listening to a multipoint MDB bus technical field

[0001] The present invention relates to the field of payment systems, and in particular to systems comprising a master device and several slave or peripheral devices interconnected by a multi-drop bus (MDB). This type of bus is commonly used in vending machines to connect a central control unit to peripheral devices. The slave devices may include, in particular, a coin acceptor, a bill reader, a bank card payment terminal, etc. State of the art

[0002] An MDB bus is configured to operate in master-slave mode. A unique address is assigned to each slave. The master queries each slave successively using the latter's address, and each slave responds when queried. If a slave does not respond within a predefined time, the master considers it to be no longer present on the bus.

[0003] In several situations, it is useful to be able to acquire data transmitted by the multipoint bus both from the master device to a slave device and from a slave device to the master device. However, the MDB bus architecture only allows one master device, and only the master device can receive data transmitted by a slave device.

[0004] Indeed, when two master devices are connected to the same MDB bus linked to one or more slave devices, the current supplied by an optocoupler of the slave device is halved. However, the signal inputs of both the master and slave devices are equipped with optocouplers. It turns out that this electrical level is insufficient to power the diodes of the optocouplers of the two master devices. Communication then becomes impossible.

[0005] A dedicated device exists, comprising a connector configured to receive only the data transmitted by the master device and the slave devices, for observing the transmissions passing through the bus. This device can be connected to a computer, for example, via a USB ("Universal Serial Bus") interface. Such a device is somewhat complex and therefore relatively expensive.

[0006] Furthermore, it is not always possible, particularly due to space and security concerns, to place a computer in a payment terminal installation. This solution is therefore generally unsuitable for monitoring the operation of such a system. installation for a long period of time.

[0007] It is desirable to be able to observe the data exchanges between a master device and slave devices interconnected by a multipoint MDB bus, by accessing the bus directly using a terminal. Summary

[0008] Embodiments relate to a method for listening to data transmitted by a multipoint bus (MDB), the method comprising steps of: connecting a terminal to a first link to be observed of the MDB bus, transmitting a data signal emitted by a slave device to a master device; interposing an adaptation circuit on the first link to be observed, between a connection point of the slave device and a connection point of the master device and the terminal; receiving a data signal transmitted by the slave device at the connection point of the slave device; transforming the data signal, by the adaptation circuit, by increasing a voltage difference between a high state and a low state of the data signal, and by reducing a transition time between the high state and the low state; transmitting, by the adaptation circuit, the transformed data signal to the connection point of the master device and the terminal;and acquire, via the terminal and the master device, data transmitted by the transformed data signal, at the connection point of the master device and the terminal.

[0009] In this way, it is possible to connect a terminal configured to observe the data transmitted by a slave device to a master device interconnected by an MDB bus. Indeed, thanks to the adaptation circuit, the parallel connection of the terminal with the master device does not significantly affect the shape of the signal transmitted by the slave device in a way that could prevent the master device from receiving the data transmitted by this signal.

[0010] According to one embodiment, the method comprises: a step of raising, by the adaptation circuit, the current intensity of the data signal transmitted to the master device and the terminal in order to reach a nominal value to power two optocouplers without the current intensity being excessive to power a single optocoupler, and / or a step of blocking, by the adaptation circuit, an optocoupler of the slave device emitting the data signal, following a transition from the low state to the high state, in a switching time equivalent to that achieved when a single master device is connected to the bus.

[0011] According to one embodiment, the connection of the terminal to the first link is made using a terminal master type connector.

[0012] Thus, it is not necessary to provide a terminal equipped with a connector specifically designed to connect to the data transmission link emitted by the slave devices on the MDB bus.

[0013] According to one embodiment, the method comprises steps consisting of: connecting the terminal to a second link to be observed of the MDB bus, the second link transmitting a data signal emitted by the master device to the slave device; and acquiring, by the terminal, data transmitted by the data signal transmitted by the master device, on the second link to be observed.

[0014] Thus, the terminal can be configured as a slave device and used to observe the data transmitted by the master device to one of the slave devices via the MDB bus.

[0015] According to one embodiment, the connection of the terminal to the second link is made using a terminal slave type connector.

[0016] Thus, it is not necessary to provide a terminal equipped with a connector specifically designed to connect to the data transmission link emitted by the master device on the MDB bus.

[0017] According to one embodiment, the method includes a step of transmitting, by the terminal, the acquired data to a processing unit, either directly or via a data transmission network such as the Internet.

[0018] Embodiments may also relate to a signal adaptation device comprising an adaptation circuit configured to: connect between a first connection point of a link to be observed of a multipoint bus (MDB) and a second connection point of the link to be observed, the link to be observed transmitting a data signal issued at the first connection point by a slave device to a master device connected at the second connection point and configured to receive the data signal; receive the data signal at the first connection point; transform the data signal by increasing a voltage difference between a high state and a low state of the data signal, and by reducing a transition time between the high state and the low state; and transmit the transformed data signal to the second connection point, the second connection point being connected to a terminal configured to observe the data signal.

[0019] Thanks to the adaptation device, it is possible to connect a terminal configured to observe the data transmitted by a slave device to a master device interconnected by an MDB bus. Indeed, the adaptation device prevents the parallel connection of a terminal to the master device from significantly altering the shape of the signal transmitted by the slave device in a way that could prevent the master device from receiving the data transmitted by that signal.

[0020] According to one embodiment, the device comprises: a first connector for connecting to a master device, a second connector for connecting to at least one slave device, in particular the slave connector of the terminal, and a third connector for connecting to a master connector of a terminal to observe the data signals transmitted from at least one slave device to the master device.

[0021] Thanks to the connectors, the adaptation device can be easily implemented when it is desired to use a terminal to collect the data exchanged between the master device and the slave devices.

[0022] According to one embodiment, the adaptation circuit comprises: a power supply circuit connected to transmission links of a supply voltage and a ground voltage of the MDB bus, the power supply circuit being configured to form a voltage source from the supply and ground voltages, a bipolar transistor comprising an emitter terminal connected to the second connection point, a first resistor connecting a collector terminal of the transistor to ground, a second resistor connecting a base terminal of the transistor to the first connection point, and a third resistor connecting the voltage source to the base terminal of the bipolar transistor or to the first connection point.

[0023] Thus, the adaptation device can be made simply with a few passive components and only one active component.

[0024] According to one embodiment: the first resistor has a fixed value such that the data signal transmitted by at least one slave device to the master device has a current intensity reaching a nominal value to power two optocouplers without the current intensity being excessive to power a single optocoupler, and / or the first and second resistors have values ​​chosen to block the bipolar transistor, following a transition from the low state to the high state of the data signal, in a switching time equivalent to that achieved when a single master device is connected to the bus.

[0025] According to one embodiment: the first resistance has a value between 40 and 60 Q, the second resistance has a value between 220 and 1.1 kQ, the third resistance has a value between 2.5 and 5.5 kQ when connected to the base terminal of the bipolar transistor, and between 200 Q and 1 kQ when connected to the first connection point.

[0026] By a simple choice of resistance values ​​of the adaptation device, the data signal from a slave device can be put into a correct shape when a second master device such as the terminal is connected to the MDB bus.

[0027] According to one embodiment, the power supply is between 3 and 6 V.

[0028] Embodiments may also relate to a payment system comprising: a master device, at least one slave device, a terminal for observing data exchanges between the master device and the slave device acting as both a master and a slave device, an adaptation device as previously defined, and a multipoint bus (MDB) connecting a master-type connector of the master device and a master-type connector of the terminal to the adapter device and a slave-type connector from each slave device to the adapter device.

[0029] According to one embodiment, the terminal includes a slave-type connector connected by the bus to the adapter device.

[0030] According to one embodiment, the terminal is a payment terminal having a function for observing the data transmitted by the bus between the master device and at least one slave device. Brief description of the figures

[0031] The present invention will be better understood with the aid of the following description of exemplary embodiments with reference to the accompanying figures, in which identical reference signs correspond to structurally and / or functionally identical or similar elements.

[0032] [Fig. 1] Figure 1 schematically represents a bus to which a master device and slave devices are interconnected,

[0033] [Fig.2] Figure 2 schematically represents an MDB-type bus to which a master device, slave devices, and a terminal configured to acquire the data transmitted between the master device and the slave devices are connected, according to one embodiment,

[0034] [Fig.3] Figure 3 is an electrical diagram of an adapter device for connecting the terminal to the bus, according to one embodiment,

[0035] [Fig.4] Figures 4A, 4B, 4C represent timing diagrams of signals present in the MDB bus, respectively in the absence of a second master device and the adaptation device, in the presence of a second master device and in the absence of the adaptation device, and in the presence of a second master device and the adaptation device,

[0036] [Fig. 5] Figure 5 is an electrical diagram of an adapter device for connecting the terminal to the bus, according to another embodiment,

[0037] [Fig. 6] Figure 6 shows a timing diagram of signals present in the MDB bus, in the presence of a second master device and the adaptation device. Detailed description

[0038] Figure 1 represents a system 1 comprising a multi-drop bus B1 ("Multi Drop Bus"), a master device MSI and slave devices SL1, SL2, SL3, the MSI devices, S1-SL3 being connected to the Bl bus. System 1 is for example an automatic dispenser in which the master device MSI is a central control unit and the slave devices SL1-SL3 are payment terminals including for example a coin acceptor, a bill reader, a bank card payment terminal.

[0039] It is desirable to connect a second master device MS2 in order to acquire the data transmitted by the slave devices SL1-SL3. However, if the bus link B1, dedicated to transmitting data from the slave devices, is simply connected to the second master device, the current emitted by the optocoupler of each slave device at its signal transmission port is divided between the two branches connected to the respective ports of the two master devices. The intensity of this current is thus halved. Since the signal inputs of the master device ports are equipped with optocouplers, the current received by the optocouplers at the reception terminal of the master devices MSI, MS2 is insufficient to power the LEDs of the optocouplers in the master devices. Consequently, the signals emitted by the slave devices cannot be received by either of the master devices.

[0040] By connecting the data transmission link of the slave devices to ground via a resistor, it is possible to send more current to the LEDs of the optocouplers of the master devices. However, this solution prevents the signal from returning to its high state and therefore prevents the receiving terminal from receiving the data transmitted by the master devices.

[0041] It can also be observed that the transition times between the high and low states of the signals emitted by the slave devices are too long, which prevents the master devices from detecting the data transmitted from the transmitted signals. Adding a power supply to reduce these times proves insufficient.

[0042] Figure 2 schematically represents a system 10 comprising an MDB-type B2 bus, to which are connected the master device MSI, slave devices SL1, SL2, and an MT terminal configured to acquire the data transmitted between the master device and the slave devices, according to one embodiment. The MT terminal may be a payment terminal additionally having a function for acquiring data transmitted via the B2 bus.

[0043] The master device MSI comprises a master MC connector connected to the B2 bus and including MVO, MG, MRX, MTX, and MCC terminals. The slave devices SL1 and SL2 each comprise a slave SC connector connected to the B2 bus and including SVI, SG, STX, SRV, and SCC terminals.

[0044] According to one embodiment, the MT terminal also includes a master type connector MC for connecting to the B2 bus as a master device, in order to be able to acquire data emitted by the slave devices SL1, SL2.

[0045] According to one embodiment, the MT terminal also includes an SC slave connector for connecting to the B2 bus as a slave device, in order to acquire data transmitted by the MSI master device. Through the SC connector, the MT terminal can also be configured to behave as a slave device in relation to the master device MSI, in the same way as the slave devices SL1, SL2.

[0046] The B2 bus includes a transmission link L1 for a supply voltage provided by the master device MSI. The L1 link is connected to the voltage output terminal MVO of the MC connector of the master device MSI, and to the voltage input terminal SVI of the SC connector of each of the slave devices SL1, SL2. In one embodiment, the supply voltage provided by the master device MSI is a DC voltage between 12 and 45 V.

[0047] The B2 bus also includes a ground voltage transmission link L2 supplied by the master device MSI. The L2 link is connected to the ground voltage output terminal MG of the MC connector of the master device MSI, and to the ground voltage input terminal SG of the SC connector of the slave devices SL1, SL2. In the example in Figure 2, the MT terminal SC connector is also connected to the L2 link.

[0048] The B2 bus also includes an L3 data transmission link from the slave devices SL1 and SL2 to the master device MSI. The L3 link is connected to the MRX data input terminal of the MC connector of the master device MSI, and to the STX data output terminal of the SC connector of the slave devices SL1 and SL2. In the example in Figure 2, the MT terminal SC connector is also connected to the L3 link.

[0049] The B2 bus also includes an L4 data transmission link from the master device MSI to the slave devices SL1 and SL2. The L4 link is connected to the MTX data output terminal of the MC connector of the master device MSI, and to the SRX data input terminal of the SC connector of the slave devices SL1 and SL2. In the example in Figure 2, the MT terminal SC connector is also connected to the L4 link.

[0050] The B2 bus also includes a common L5 data transmission link. The L5 link is connected to the common MCC transmission terminal of the MC connector of the master device MSI, and to the common SCC transmission terminal of the SC connector of the slave devices SL1 and SL2. In the example in Figure 2, the MT terminal SC connector is also connected to the L5 link.

[0051] According to one embodiment, the B2 bus comprises an AD adapter device with three connectors AC1, AC2, AC3. Connector AC1 is connected to the MC connector of the MSI master device by a TB1 bus segment. Connector AC2 is connected to the SC slave connectors of the SL1 and SL2 slave devices and the MT terminal by a TB2 bus segment. Connector AC3 is connected to the MC master connector of the MT terminal by a TB3 bus segment.

[0052] According to one embodiment, the AD adaptation device comprises a circuit An ACT adapter is interposed on the L3 data transmission link between the MRX terminal of the MC connector and the STX terminal of the SC connector. Thus, the adapter circuit includes an ARX data input terminal connected to an STX terminal and an ATX data output terminal connected to the MRX data input terminals of the MSI master device and the terminal.

[0053] Furthermore, the ACT circuit is powered via terminals AVI and AG, which are connected respectively to terminals MVO and MG of the master device MSI by bus segment TB1. The ACT circuit is configured to conform the data signal transmitted on the L3 link by the slave devices SL1, SL2, or the MT terminal as a slave, so that it can be processed by the master device MSI and the MT terminal as a master to extract the transmitted data. To this end, the ACT circuit is configured to increase the voltage difference between the high and low states of the data signal transmitted by the data output terminal STX of the SC connector of the slave devices SL1, SL2, and to decrease the duration of the transitions between the high and low states of this signal. The voltage difference between the high and low states of the data signal can be increased by decreasing only the low-state voltage.

[0054] Thanks to these arrangements, the master device MSI and the terminal MT can simultaneously receive the data transmitted by each of the slave devices SL1, SL2. Thanks to its slave-type SC connector, the terminal MT also receives all the data transmitted by the master device MSI. The terminal MT can, for example, be configured to store the data thus received in memory for processing, for example, analysis, and / or transmission to a local or remote processing unit connected to the terminal, either directly or via a data transmission network, such as the Internet.

[0055] Figure 3 shows the ACT circuit, according to an exemplary embodiment. In the exemplary embodiment of Figure 3, the ACT circuit comprises a PNP bipolar transistor T1 and three resistors RI, R2, and R3. The transistor T1 has an emitter terminal connected to the ATX terminal, a collector terminal connected to ground (defined by the voltage at the AG terminal) via resistor RI, and a base terminal connected to the ARX terminal via resistor R2 and to a voltage source ALM via resistor R3. The voltage source ALM is connected to the AVI and AG terminals and configured to generate a DC voltage SV from the voltage supplied by the master device MSI between the MVO and MG terminals.

[0056] The optocoupler transistor OP2 on the L3 link of the slave device is powered low by the data signal emitted by the slave device. This transistor is therefore conducting low. Transistor T1 is then also conducting, which allows the data signal at the ATX terminal to also reach a low state. The value The resistance RI is chosen to provide sufficient current at the ATX terminal to power the LEDs of the optocouplers OP1 of the master device MSI and the MT terminal, connected to the L3 link of the B2 bus. When the signal emitted by the slave device SL1 or SL2 reaches a high state, the LED of the optocoupler OP2 of the slave device SL1 or SL2 is no longer powered. However, the transistor of the optocoupler OP2 and the transistor T1 take too long to turn off. The rise time of the data signal is then excessive.

[0057] The resistance RI defines the current supplied to the ATX terminal that can be connected to the optocoupler OP1 of the MRX input of the master device and possibly to the optocoupler OP1 of the MRX input of the MT terminal.The value of the resistance RI can therefore be set to provide a nominal current to two optocouplers, without this current being excessive when only one optocoupler is connected to the ATX terminal.

[0058] Resistor R3, connecting the base of transistor Tl to the voltage source, allows transistor Tl to be switched off more quickly by bringing the data signal back up to the voltage supplied by the voltage source more rapidly. Thus, when the data signal transmitted by link L3 is high, transistor Tl is switched off. Transistor Tl is therefore biased by resistors R2 and R3. However, if the values ​​of resistors R2 and R3 are too high, the optocoupler transistor OP2 of the slave device takes too long to switch from the conducting state to the switching state. If the values ​​of resistors R2 and R3 are decreased, the switching of this transistor is faster and can reach the switching time obtained when a single slave device is connected to a single master device.If the values ​​of resistors R2 and R3 are too low, the switching times obtained are too different from those encountered when a single slave device is connected to a single master device.

[0059] By way of example, the supply voltage SV is between 3 and 6 V, for a DC voltage at terminal AVI between 12 and 45 V. The resistance RI is between 40 and 60 Ω, the resistance R2 is between 220 Ω and 1.1 kΩ, and the resistance R3 is between 2.5 and 5.5 kΩ. According to another example, the resistance R2 is fixed at 510 Ω and the resistance R3 is fixed at 3.9 kΩ.

[0060] Figures 4A, 4B, and 4C show timing diagrams of signals present in the MDB bus, respectively, in the absence of the MT terminal, with the terminal and in the absence of the AD adapter, and with both the terminal and the adapter. Figure 4A shows timing diagrams C1, C2, and C3. Timing diagram C1 represents a data signal emitted by a slave device SL1 or SL2 upstream of the optocoupler OP2. Timing diagram C2 represents the corresponding data signal at the input of the optocoupler OP1 of the master device MSI. Timing diagram C3 represents the corresponding data signal received by the master device MSI downstream of the optocoupler OP1. According to timing diagram C2, the voltage The low state voltage of the data signal is located approximately 2.2 V above the high state voltage.

[0061] Figure 4B shows timing diagrams C11, C12, and C13. Timing diagram C11 represents a data signal emitted by a slave device SL1, SL2, upstream of the optocoupler OP2. Timing diagram C12 represents the corresponding data signal input to the optocoupler OP1 of the master device MSI and the terminal MT. Timing diagram C13 represents the corresponding data signal received by the master device MSI or the terminal MT downstream of the optocoupler OP1. According to timing diagram C12, the low state voltage of the data signal is too high (approximately 3 V) to turn off the transistor of the optocoupler OP1. As a result, the signal output of the optocoupler OP1 remains high (timing diagram C13).

[0062] Figure 4C shows timing diagrams C21, C22, C23, C24. The timing diagram C21 represents a data signal emitted by a slave device SL1, SL2, upstream of the optocoupler OP2. Timing diagram C22 represents the corresponding data signal at the output of the optocoupler OP2 (at the input of the ACT circuit). Timing diagram C23 represents the corresponding data signal received by the master device MSI or the terminal MT upstream of the optocoupler OP1 (at the output of the ACT circuit). Timing diagram C24 represents the corresponding data signal received by the master device MSI or the terminal MT downstream of the optocoupler OP1. According to timing diagram C23, the low-state voltage of the data signal is approximately the same as the low-state voltage of timing diagram C2. The switching time of transistor T1 influences the time interval TCI between the rising edges of signals C21 and C24 and the time interval TC2 between the rising edges of signals C21 and C22.In Figure 4C, the TCI time interval is approximately 52 ps, when the resistances RI, R2 and R3 are respectively equal to 51 Q, 510 Q and 3.9 kQ. Under these conditions, the TC2 time interval is approximately 25 ps.

[0063] Figure 5 shows an ACT1 matching circuit, according to another embodiment. The ACT1 circuit differs from the ACT matching circuit in that the resistor R3 is omitted and replaced by a resistor R4 connected between the ATX terminal and the ALM voltage source.

[0064] According to one embodiment, the resistance R2 is between 220 and 1.1 kQ and the resistance R4 is between 200 Q and 1 kQ.

[0065] Figure 6 shows timing diagrams C31, C32, C33, and C34. Timing diagram C31 represents the data signal emitted by a slave device SL1 or SL2 upstream of the optocoupler OP2. Timing diagram C32 represents the corresponding data signal at the output of the optocoupler OP2 (input to the ACT1 circuit). Timing diagram C33 represents the corresponding data signal received by the master device MSI or the MT terminal upstream of the optocoupler OP1 (output to the ACT1 circuit). Timing diagram C34 represents the corresponding data signal received by the MSI master device or the MT terminal downstream of the 0P1 optocoupler.

[0066] The switching time of transistor T1 influences the time interval TCI between the rising edges of signals C31 and C34 and the time interval TC2 between the rising edges of signals C31 and C32. In Figure 6, the time interval TCI is reduced to approximately 24 ps when the resistances RI, R2, and R4 are equal to 51 Ω, 510 Ω, and 300 Ω, respectively. Under these conditions, the time interval TC2 is approximately 4 ps. By modifying the resistances (R3 replaced by R4) of the ACT matching circuit, the current supplied to the base of transistor Tl in the ACT1 circuit is about four times higher than in the ACT circuit, which allows the opening time of transistor Tl to be divided by at least four, with however a slight degradation of the closing time of transistor Tl resulting in small deviations of the falling edges of signals C31, C32, C33 with the falling edge of signal C34.

[0067] It will be clear to those skilled in the art that the present invention is susceptible of various embodiments. In particular, the invention is not limited to the circuit example shown in Figure 3. Indeed, other circuits can easily be devised by those skilled in the art to increase the voltage difference of the data signal between its high and low states, and to reduce the duration of the transitions between the high and low states of this signal.

Claims

Demands

1. 1. A method for listening to data transmitted by a multipoint bus (MDB), the method comprising the steps of: connecting a terminal (MT) to a first link (L3) to be observed of the MDB bus (B2), transmitting a data signal emitted by a slave device (SL1, SL2) to a master device (MSI); interposing a matching circuit (ACT) on the first link to be observed, between a connection point (STX) of the slave device and a connection point (MRX) of the master device and the terminal; receiving a data signal transmitted by the slave device at the connection point of the slave device; transforming the data signal, by the matching circuit, by increasing a voltage difference between a high state and a low state of the data signal, and by reducing a transition time between the high state and the low state;transmit, via the adaptation circuit, the transformed data signal at the connection point of the master device and the terminal; and acquire, via the terminal and the master device, data transmitted by the transformed data signal, at the connection point of the master device and the terminal.

2. 2. Method according to claim 1, comprising: a step of raising, by the adaptation circuit (ACT), a current intensity of the data signal transmitted to the master device (MSI) and the terminal (MT) in order to reach a nominal value to power two optocouplers (OP1) without the current intensity being excessive to power a single optocoupler, and / or a step of blocking, by the adaptation circuit (ACT), an optocoupler (OP2) of the slave device (SL1, SL2) transmitting the data signal, following a transition from the low state to the high state, in a switching time equivalent to that achieved when a single master device is connected to the bus (B2).

3. 3. Method according to claim 1 or 2, wherein the connection of the terminal (MT) to the first link (L3) is made using a master type connector (MC) of the terminal.

4. 4. A method according to any one of claims 1 to 3, comprising steps of: connecting the terminal (MT) to a second link to be observed (L4) of the bus MDB (B2), the second link transmitting a data signal emitted by the master device (MSI) to the slave device (SL1, SL2); and acquiring, by the terminal, data transmitted by the data signal transmitted by the master device, on the second link to be observed.

5. 5. Method according to claim 4, wherein the connection of the terminal (MT) to the second link (L4) is made using a slave-type connector (MC) of the terminal.

6. 6. A method according to any one of claims 1 to 5, comprising a step of transmitting, by the terminal (MT) the acquired data to a processing unit, directly or via a data transmission network such as the Internet.

7. 7. Signal adaptation device (AD) comprising an adaptation circuit (ACT) configured to: connect between a first connection point (STX) of a link to be observed (L3) of a multipoint bus (MDB) (B2) and a second connection point (MRX) of the link to be observed, the link to be observed transmitting a data signal issued at the first connection point by a slave device (SL1, SL2) to a master device (MSI) connected at the second connection point and configured to receive the data signal; receive the data signal at the first connection point; transform the data signal by increasing a voltage difference between a high state and a low state of the data signal, and reducing a transition time between the high state and the low state; and transmit the transformed data signal to the second connection point, the second connection point being connected to a terminal (MT) configured to observe the data signal.

8. 8. Device according to claim 7, comprising: a first connector (AC1) for connecting to a master device (MSI), a second connector (AC2) for connecting to at least one slave device (SL1, SL2, MT), and a third connector (AC3) for connecting to a master connector (MC) of a terminal (MT) for observing the data signals transmitted by at least one slave device to the master device.

9. 9. Device according to claim 7 or 8, wherein the adaptation circuit (ACT) comprises: a power supply circuit (ALM) connected to transmission links (L1, L2) of a supply voltage and a ground voltage of the MDB bus (B2), the power supply circuit being configured to form a voltage source (SV), from the supply and ground voltages, a bipolar transistor (T1) comprising an emitter terminal connected to the second connection point (MRX), a first resistor (RI) connecting a collector terminal of the transistor to ground, a second resistor (R2) connecting a base terminal of the transistor to the first connection point (STX), and a third resistor (R3, R4) connecting the voltage source (SV) to the base terminal of the bipolar transistor or to the first connection point.

10. 10. Device according to claim 9, wherein: the first resistor (RI) has a fixed value such that the data signal transmitted by at least one slave device (SL1, SL2) to the master device (MSI) has a current intensity reaching a nominal value to power two optocouplers (OP1) without the current intensity being excessive to power a single optocoupler, and / or the first and second resistors (R2, R3) have values ​​chosen to block the bipolar transistor (T1), following a transition from the low state to the high state of the data signal, in a switching time equivalent to that achieved when a single master device is connected to the bus (B2).

11. 11. Device according to claim 9 or 10, wherein: the first resistor (RI) has a value between 40 and 60 Q, the second resistor (R2) has a value between 220 and 1.1 kQ, the third resistor (R3, R4) has a value between 2.5 and 5.5 kQ when connected to the base terminal of the bipolar transistor (T1), and between 200 Q and 1 kQ when connected to the first connection point (STX).

12. 12. Device according to any one of claims 9 to 11, wherein the power supply (SV) is between 3 and 6 V.

13. 13. Payment system comprising: a master device (MSI), at least one slave device (SL1, SL2), a terminal (MT) for observing data exchanges between the master device and the slave device, which acts as both a master and a slave device, an adaptation device (AD) according to any one of claims 7 to 12, and a multipoint type bus (MDB) (B2) linking a master type connector (MC) of the master device and a master type connector (MC) of the terminal to the adaptation device and a slave type connector (SC) of at least one slave device (SL1, SL2, MT) to the adaptation device.

14. 14. System according to claim 13, wherein the terminal (MT) includes a slave type connector (SC) connected by the bus (B2) to the adaptation device (AD).

15. 15. System according to claim 14, wherein the terminal (MT) is a payment terminal having a function of observing the data transmitted by the bus (B2) between the master device (MSI) and at least one slave device (SL1, SL2).

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