Method of designing a calculator

Abstract

Method for designing a computer The present description relates to a method for designing a computer comprising: choosing a support (1200) from among supports each comprising a first location for the same first microchip; choosing a card adapted (1202) to the support chosen from among cards; assembling (1204; 1208) the first microchip on the chosen support and the chosen support on the chosen card. Each of the cards connects, via the support mounted on this card, an interface of the first microchip to a first interface of the card adapted to be connected to the first interface of another card. The first microchip directs data flows and implements calculations on the data flows. Figure for the abstract: Fig. 12

Description

Title of the invention: Method of designing a computer Technical field

[0001] The present description relates generally to electronic circuits. Prior art

[0002] In the automotive field, a single manufacturer generally has a wide range of vehicles.

[0003] Furthermore, the electronic / electrical architecture of vehicles is moving towards centralization, in each vehicle, of calculations and data processing on a single platform, system or computer, capable of addressing the multimedia application needs and assisted or autonomous driving of the vehicle.

[0004] However, in a range of vehicles, each vehicle has different computing and data processing needs depending, for example, on the one hand on the multimedia devices that it includes, i.e. the multimedia experience offered by this vehicle, and, on the other hand, on the level of its advanced driver assistance system (ADAS), i.e., for example, the level L2, L2+, L3 and L4 of the driver assistance system from which the vehicle benefits.

[0005] To meet the calculation and data processing needs of a whole range of vehicles, a first solution consists of embedding, in each vehicle, the same very high-performance processor and programming this processor by software according to the specific needs of the vehicle. An advantage of this solution is that the same computer will be used for the whole range of vehicles. Thus, the same computer package is used for the whole range of vehicles, this computer package comprising the computer, the computer encapsulation means, and, for example, cooling means. It is therefore not necessary to adapt, for each vehicle in the range, the chassis for receiving the computer package.However, this single ECU box and the single ECU it includes are designed to meet the data processing and computing needs of the highest-end vehicle, and are therefore oversized for lower-end vehicles. This leads, for example, to an increase in the cost of vehicles with lower processing and computing needs than those of the highest-end vehicles.

[0006] A second solution consists of developing, in the form of a system on chip, a specific, dedicated and different calculator for each set of vehicles having similar calculation and processing needs. Thus, each vehicle will receive a cal calculator sized for these data processing and calculation needs. However, for each different calculator, it is then necessary to design a calculator box dedicated to this calculator, which is complex, time-consuming and expensive. In addition, this also requires adapting, in the different vehicles, the chassis receiving the calculator box to the model of calculator box intended for the vehicle in question. Summary of the invention

[0007] There is a need to overcome all or part of the disadvantages of known computers, for example known computers intended to equip a range of products, for example vehicles, having different data processing and calculation needs.

[0008] One embodiment overcomes all or part of the drawbacks of known computers, for example known computers intended to equip a range of products, for example vehicles, having different data processing and calculation needs.

[0009] For example, one embodiment provides a method of designing a computer that makes it possible to obtain a large number of computers having different data processing and calculation capabilities and that can be arranged in a reduced number of computer housings.

[0010] For example, one embodiment provides a method for designing a large number of computers from a small number of elements.

[0011] For example, one embodiment provides a method of designing a computer that facilitates, i.e., makes less complex, the manufacture of a computer housing for the designed computer.

[0012] One embodiment provides a method of designing a computer comprising: choosing a support from a first support and a second support each comprising a first location configured to receive the same first microchip; selecting a card suitable for the support selected from a first card, a second card and a third card, the first and second cards each having a first location configured to receive the first support and the third card having a first location configured to receive the second support; assembling the first microchip on the first location of the chosen support; and assembling the chosen support on the first location of the chosen board, wherein: each of the cards is configured to connect, via the support that the first em placement of the card is configured to receive a first interface of the first microchip and a first interface of said card, the first interface of said card being adapted to be connected to the first interface of another card chosen from the first, second and third cards, the first holder comprises one or more second locations each configured to receive a corresponding second microchip; and The first microchip is configured to route data streams and perform computations on the data streams.

[0013] According to one embodiment, for each second location of the first support, the first support is configured to connect a second interface of the second microchip corresponding to this second location with a corresponding second interface of the first microchip.

[0014] According to one embodiment, when the chosen support is the first support, the method further comprises, for at least a second location of the first support, assembling the second microchip corresponding to this second location on this second location.

[0015] According to one embodiment: a first version of the first microchip has connection pads arranged in a first arrangement; a second version of the first microchip has connection pads arranged in a second arrangement, the second arrangement being determined by the first arrangement and having a higher pad density than the first arrangement; the first location of the first holder is configured to receive the first version of the first microchip and the first location of the second holder is configured to receive the second version of the first microchip.

[0016] According to one embodiment: the first card further comprises a second slot configured to receive a first auxiliary support having several slots each configured to receive a corresponding second microchip.

[0017] According to one embodiment, for one of the locations of the first auxiliary support, the first support, the first auxiliary support and the first card are configured to connect an interface of the second microchip corresponding to this location with a corresponding interface of the first microchip.

[0018] According to one embodiment, when the first support and the first card are chosen, the method further comprises: on said one of the locations of the first auxiliary support, assemble the corresponding second microchip; and assemble the first auxiliary support on the second location of the first card.

[0019] According to one embodiment, each second microchip corresponding to a location of the first auxiliary support implements accelerator functions for an advanced pilot assistance system, for example of level L3 or L4.

[0020] According to one embodiment: each of the second and third cards comprises a second location configured to receive a second auxiliary support having a single location configured to receive a second microchip corresponding to this location.

[0021] According to one embodiment: - the second auxiliary support, the second card and the first support are configured to connect an interface of the second microchip corresponding to the unique location of the second auxiliary support with a corresponding interface of the first microchip; and - the second auxiliary support, the third card and the second support are configured to connect an interface of the second microchip corresponding to the unique location of the second auxiliary support with a corresponding interface of the first microchip.

[0022] According to one embodiment, when the first support and the second card are chosen, the method further comprises: assembling the second microchip corresponding to the unique location of the second auxiliary support on this location; and assemble the second auxiliary support on the second location of the second card.

[0023] According to one embodiment, when the second support and the third card are chosen, the method further comprises: assembling the second microchip corresponding to the unique location of the second auxiliary support; and assemble the second auxiliary support on the second location of the third card.

[0024] According to one embodiment, the second microchip corresponding to the single location of the second auxiliary support implements accelerator functions for an advanced pilot assistance system, for example of level L3 or L4.

[0025] According to one embodiment, the second support is devoid, with the exception of its first location, of a location configured to receive a microchip.

[0026] According to one embodiment, the choice of card and support is determined by a calculation and processing capacity targeted for the calculator. Brief description of the drawings

[0027] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0028] [Fig.l] represents, schematically and in the form of blocks, an exemplary embodiment of a microchip;

[0029] [Fig.2] represents, schematically and in the form of blocks, an exemplary embodiment of another microchip, adapted to be connected to the microchip of [Fig.l];

[0030] [Fig. 3] schematically represents, in top view and in the form of blocks, an exemplary embodiment of a connection support configured to accommodate the microchip of [Fig. 1];

[0031] [Fig.4] represents, schematically and in sectional view, an example of implementation of the support of [Fig.3];

[0032] [Fig.5] schematically represents, in top view and in the form of blocks, an exemplary embodiment of another connection support configured to accommodate the microchip of [Fig.1];

[0033] [Fig.6] represents, schematically and in sectional view, an example of implementation of the support of [Fig.5];

[0034] [Fig.7] schematically represents, in top view and in the form of blocks, an exemplary embodiment of a card, configured to accommodate the support of [Fig.3];

[0035] [Fig.8] schematically represents, in top view and in the form of blocks, an exemplary embodiment of an auxiliary support, adapted to cooperate with the card of [Fig.7];

[0036] [Fig.9] schematically represents, in top view and in the form of blocks, an exemplary embodiment of another card, configured to accommodate the support of [Fig.3];

[0037] [Fig. 10] schematically represents, in top view and in the form of blocks, an exemplary embodiment of another auxiliary support, adapted to cooperate with the card of [Fig.9];

[0038] [Fig. 1 1] schematically represents, in top view and in the form of blocks, an exemplary embodiment of another card, configured to accommodate the support of [Fig. 5];

[0039] [Fig. 12] represents, in the form of a flowchart, an example of an embodiment of a method for designing a computer;

[0040] [Fig. 13] illustrates, schematically and in block form, examples of calculators obtained by implementing the method of [Fig. 12];

[0041] [Fig. 14] illustrates, schematically, an exemplary embodiment of a change in the arrangement of pads or connection balls of a microchip; and

[0042] [Fig. 15] illustrates, schematically, another example of an embodiment of a change in the arrangement of pads or connection balls of a microchip. Description of the embodiments

[0043] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0044] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0045] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0046] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0047] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0048] To address the different computing and data processing needs between vehicles in the same vehicle range, a solution is proposed here based on the hardware disaggregation of a range of computing and data processing systems. Hardware disaggregation consists of dividing the hardware architecture of a circuit into several distinct functional elements manufactured separately in the form of integrated circuits called microchips ("chiplets" in English), then rearranging and assembling these microchips in the same package to form a component. US patent 11756150 presents the principle of hardware disaggregation into microchips.

[0049] Herein proposed, for the design of computers, is a modular method of designing a computer based on disaggregation into microchips, making it possible to overcome the drawbacks described above.

[0050] [Fig.l] represents, schematically and in the form of blocks, an exemplary embodiment of a CL1 microchip.

[0051] The CL1 microchip is configured to direct, that is to say redistribute, data flows in a computer.

[0052] The microchip CL1 is further configured to implement protocol transpositions between a data stream that it receives and a corresponding data stream that it sends.

[0053] In addition to data flow switching and simple protocol transposition, the CL1 microchip is configured to implement processing on the data flows it receives, going beyond simple protocol transposition. Thus, a computer with relatively low data processing and computational needs can be implemented with a single microchip corresponding to the CL1 microchip, without it being necessary to connect, to the CL1 microchip, one or more generic computational microchips.

[0054] Preferably, the microchip CL1 is configured to perform fusions of separate received data streams, without preprocessing the received data streams, and then to provide the resulting merged data stream to another element, for example to a memory or to another microchip. In other words, the microchip CL1 is configured to implement early fusions of separate received data streams. Preferably, the microchip CL1 is further configured to perform processing, going beyond simple protocol transposition, on separate received data streams, and then to merge the results of these preprocessings in order to provide a corresponding merged data stream. In other words, the microchip CL1 is configured to implement late fusions of separate received data streams.

[0055] When the CL1 microchip is configured to implement late fusions and early fusions, this allows the implementation of multimodal fusions of separate data streams, the multimodal fusion strategies being, for example, particularly advantageous to implement for the field of artificial intelligence.

[0056] The microchip CL1 comprises at least one processing circuit, for example chosen from the group comprising central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs) and neural network processing units (NPUs). The provision of at least one processing circuit in the microchip CL1 allows the microchip CL1 to implement processing and calculations going beyond simple protocol transposition.

[0057] The CL1 microchip further comprises several interfaces allowing the connection of the CL1 microchip: - to one or more CL2 microchips; - to one or more CL3 microchips; - to sensors providing data streams to the CL1 microchip; - at least one other CL1 microchip; and - at least one memory circuit, for example of the dual data rate (DDR) or FLASH type.

[0058] For example, the microchip CL1 comprises at least one IT2 interface, preferably at least two IT2 interfaces, for example three IT2 interfaces. Each IT2 interface is configured to be connected to a microchip CL2.

[0059] For example, the microchip CL1 comprises at least one interface IT3. Each interface IT3 is configured to be connected to a microchip CL3.

[0060] By way of example, each IT2 interface is configured to allow the exchange of data over relatively short connection distances, for example less than 10 mm, whereas an IT3 interface is configured to allow the exchange of data over connection distances greater than those permitted by an IT2 interface.

[0061] Preferably, each CL2 microchip is a computational microchip, and each CL3 microchip is an accelerator microchip. By computational microchip, we preferably mean here a microchip configured to implement more generic computational and processing functionalities than that implemented by an accelerator microchip.

[0062] For example, a computing microchip includes one or more software-programmable processing units, which gives a generic character to the computing microchip. For example, the processing unit(s) of a computing microchip are selected from the group comprising CPUs, GPUs and NPUs. For example, since a computing microchip is intended to implement generic functionalities relative to the specific functionalities of accelerator microchips, a computing microchip does not include a DSP.

[0063] For example, an accelerator microchip comprises one or more software-programmable processing units, the processing unit(s) of an accelerator microchip being selected from the group comprising CPUs, GPUs, DSPs and NPUs. Preferably, since an accelerator microchip is intended to implement specific functionalities compared to the generic functionalities of computing microchips, an accelerator microchip comprises a DSP and / or a GPU, or even a processing circuit specifically developed to implement one or more specific functions.

[0064] According to one embodiment, each accelerator microchip is configured to implement accelerator functions for an advanced driver assistance system, AD AS. Preferably, these accelerator functions are dedicated to the implementation implementation of levels L3 and L4 of the AD AS system. Thus, preferably, a computer designed with the method proposed here and intended to be embedded in a motor vehicle, will include one or more accelerator microchips only when the AD AS level of the vehicle is a level greater than or equal to level L3, for example is level L3 or L4.

[0065] The microchip CL1 comprises at least one interface IT1 configured to be connected to an interface IT1 of another microchip CL1. The interface IT1 therefore makes it possible to network several microchips CL1.

[0066] The microchip CL1 comprises at least one ITm interface configured to be connected to a memory circuit.

[0067] Although not shown in [Fig.l], the microchip CL1 comprises at least one ITs interface configured to be connected to a sensor, so as to receive data from the sensor.

[0068] Although not shown in [Fig.l], the microchip CL1 may comprise other interfaces, for example one or more interfaces each configured to exchange data with a screen and / or for example one or more interfaces each configured to exchange data with a modem.

[0069] Preferably, the interfaces IT1, IT2 and IT3 of the microchip are physical ports, that is to say, for example, that these interfaces implement the aspects linked to the physical layers.

[0070] Preferably, the connection between an interface IT1 of the microchip CL1 and an interface IT1 of another microchip CL1 is implemented by a high-speed link (HLS). For example, a high-speed link is configured to transfer at least 4 gigabytes per second, preferably at least 8 gigabytes per second, regardless of whether this HSL link can be a serial link or a parallel link.

[0071] Preferably, each CL1 microchip is configured, during a data exchange between two CL1 microchips via their IT1 interfaces, to ensure cache coherence in the distributed memory associated with these two CLL chips. However, as the IT1 interfaces are capable of supporting cache coherence, these interfaces will also be capable of supporting input / output coherence, and input / output coherence may be implemented between two CL1 microchips connected to each other by their ITL interfaces. Note that, conversely, an interface configured to support input / output coherence will not necessarily be configured to support cache coherence.

[0072] Preferably, the connection between an interface IT2 of the microchip CL1 and a corresponding interface IT2c of a microchip CL2 is implemented by a high-speed link (HLS). Preferably, the microchip CL1 is configured, during a data exchange between the microchip CL1 and a microchip CL2, via their interfaces IT2 and IT2c, to ensure cache coherence in the distributed memory associated with these two microchips CL1 and CL2. However, when a microchip CL1 and a microchip CL2 are connected to each other via an interface IT2 of the microchip CL1, a high-speed link and an interface IT2c of the microchip CL2, and these two interfaces allow the implementation of cache coherence, it is also possible, for example, to implement input / output coherence between the memory associated with the microchip CL2 and the distributed memory associated with the microchip CL1.

[0073] Preferably, the connection between an interface IT3 of the microchip CL1 and a corresponding interface IT3c of a microchip CL3 is implemented by a high-speed link (HLS). Preferably, the microchip CL1 is configured, during a data exchange between the microchip CL1 and a microchip CL3, via their interfaces IT3 and IT3c and a high-speed link, to ensure input / output coherence between the memory associated with the microchip CL3 and the distributed memory associated with the microchip CL1. However, if these two interfaces also support protocols allowing the implementation of cache coherence, it is also possible, for example, to implement cache coherence in the distributed memory associated with these two microchips CL1 and CL3.

[0074] Although not illustrated in [Fig. 1], preferably the microchip CL1 comprises a direct memory access ("DMA") circuit.

[0075] Although this is not illustrated in [Fig. 1], preferably the microchip CL1 comprises at least one communication infrastructure, preferably a network on chip (NoC), configured to ensure data transfers internally to the microchip CL1, between its processing unit(s), its interfaces and / or its direct memory access circuit when the microchip CL1 has one.

[0076] [Fig.2] represents, schematically and in the form of blocks, an exemplary embodiment of a microchip CL2 adapted to be connected to the microchip of [Fig.l], and of a microchip CL3, adapted to be connected to the microchip of [Fig.l].

[0077] The CL2 microchip comprises an IT2c interface adapted to be connected to an IT2 interface of a CL1 microchip.

[0078] Preferably, the microchip CL2 further comprises an ITm interface for connecting a memory circuit to the microchip CL2, via the ITm interface.

[0079] The CL3 microchip comprises an IT3c interface adapted to be connected to an IT3 interface of a CL1 microchip.

[0080] Preferably, the CL3 microchip further comprises an ITm interface for connecting a memory circuit to the CL3 microchip, via the ITm interface.

[0081] Thus, an interface IT2c of a microchip CL2 is configured to be connected to an interface IT2, or even, for example, to an interface IT3, of a microchip CL1 when the length of the connection between these two interfaces is less than what the interfaces IT2 and IT2c allow, for example when the microchip CL2 is mounted on the same support as the microchip CL1.

[0082] Furthermore, an IT3c interface of a CL3 microchip is configured to be connected to an IT3 interface so as to allow transfers between these two interfaces over distances greater than those permitted between two IT2 and IT2c interfaces, which allows the CL3 microchip to be mounted on a support different from that of the CL1 chip.

[0083] However, since the IT3c and IT3 interfaces allow greater connection distances than those allowed by the IT2 and IT2c interfaces, an IT3c interface can, for example, be connected to an IT2 interface when the connection distance between these interfaces is less than the maximum connection distance over which the IT2 interface allows data transfer, and an IT3 interface can, for example, be connected to an IT2c interface when the connection distance between these interfaces is less than the maximum connection distance over which the IT2c interface allows data transfer.

[0084] [Fig. 3] schematically represents, in top view and in the form of blocks, an exemplary embodiment of an SI connection support configured to accommodate a CL1 microchip.

[0085] The support SI therefore comprises exactly one location EC1 (in dotted lines in [Fig.3]) configured to receive a microchip CL1.

[0086] The dimensions and electrical connection areas of location EC1 are determined by the dimensions and electrical connection areas of microchip CL1.

[0087] In this embodiment, the SI support further comprises at least one EC2 location configured to receive a corresponding CL2 or CL3 microchip, preferably a corresponding CL2 microchip.

[0088] Each EC2 location is configured to receive a CL2 (or CL3) microchip specific to this location. In other words, the dimensions and the electrical connection areas of each EC2 location are determined by the dimensions and the electrical connection areas of the CL2 (or CL3) microchip that this EC2 location is intended to receive. In other words, each EC2 location is intended to receive a corresponding CL2 (or CL3) microchip. For example, a first CL2 (or CL3) microchip corresponding to an EC2 location cannot be received by another EC2 slot configured to receive a second CL2 (or CL3) microchip, unless, for example, the first and second microchips are identical or the first and second microchips have the same dimensions with an identical physical and functional arrangement of their connection pads or balls.

[0089] In the example of [Fig.3], the SI support comprises exactly three EC2 locations.

[0090] In [Fig.3], by way of example, each location EC2 is configured to receive a corresponding microchip CL2 and dotted lines represent, for each location EC2, the interface IT2c of the microchip CL2 corresponding to the location EC2 as if this microchip were mounted, or received, by this location EC2. Similarly, dotted lines represent, for the location EC1, the interfaces IT1, IT2, IT3 and ITm of the microchip CL1 as if this microchip were mounted on the location EC1.

[0091] For each location EC2, the support SI is configured to connect the IT2c interface of the corresponding microchip CL2, i.e. of the microchip that this location is configured to receive, with a corresponding IT2 interface of the microchip CL1. In other words, for each location EC2, when the corresponding microchip CL2 is received by this location EC2 and the microchip CL1 is received by the location EC1, the support SI connects the IT2c interface of the microchip received by the location EC2 to a corresponding IT2 interface of the microchip CL1.

[0092] In [Fig.3], these connections are represented by arrows 300. In other words, each connection that the support SI comprises and which is configured to connect an interface IT1 of the microchip CL1 to an interface IT2c of a microchip of a location EC2, is represented by a double arrow 300.

[0093] In the example of [Fig. 3], each EC2 location is configured to receive a corresponding CL2 microchip, and the connections 300 therefore each connect an IT2c interface to a corresponding IT2 interface. In another example not shown, one or more of the EC2 locations are configured to receive a corresponding CL3 microchip. In this other example, for each EC2 location configured to receive a corresponding CL3 microchip, the connection 300 is then made between the IT3c interface of the CL3 microchip received by this EC2 location and the corresponding IT2 interface of the CL1 microchip.

[0094] [Fig.4] represents, schematically and in sectional view, an example of implementation of the SI support of [Fig.3], [Fig.4] being a sectional view taken along plane AA of [Fig.3].

[0095] In the example of [Fig.4], a microchip CL1 is mounted on the support SI, at the location EC1 of the support SI. Furthermore, in this example, none of the em- EC2 placements do not receive a CL2 (or CL3) microchip.

[0096] Preferably, as illustrated for the microchip CL1 in [Fig.4], each microchip CL1, CL2 and CL3 comprises a face provided with electrical connection pads (or balls) 400 so as to be electrically connected to the support on which this microchip is mounted, this face being turned towards the support when the microchip is assembled to the support.

[0097] In the example of [Fig.4], the support SI comprises an interposer 404, for example a silicon interposer or an organic interposer, mounted on a substrate 406, for example an organic substrate, for example a printed circuit board, electrical connection pads or balls 402 ensuring the electrical connection of the elements 404 and 406 to each other.

[0098] In another example not shown, the support SI only comprises the organic substrate 406, and the microchips CL1, and, when they are provided, the microchips CL2 (or CL3), are then directly mounted on substrate 406, by bringing the balls or pads 400 of each microchip into contact with the substrate 406.

[0099] However, the provision of an interposer 404 makes it possible to simplify the interconnection of the microchips CL1 and CL2 by the support SI.

[0100] Although this is not shown in [Fig.4], the SI support comprises, on the side of its face opposite the face of the SI support on which the CL1 microchip is mounted, pads or connection balls to allow the electrical connection of the SI support to a card ("board" in English) when the SI support is assembled on this card.

[0101] [Fig.5] schematically represents, in top view and in the form of blocks, an exemplary embodiment of another connection support configured to accommodate the CL1 microchip.

[0102] The S2 support includes many elements in common with the SI support, and only the differences between these two supports are highlighted here. Thus, unless otherwise indicated, everything that has been indicated for the SI support applies to the S2 support.

[0103] The support S2 differs from the support SI in that it does not include any location EC2. More generally, the support S2 does not include any location configured to receive a microchip, with the exception of the location EC1 configured to receive the microchip CL1.

[0104] Since the support SI and the support S2 are both configured to receive, in their locations EC1, the same microchip CL1, the location EC1 of the support SI has the same dimensions as the location EC1 of the support S2. Furthermore, since the support S2 has no other microchip location, the support S2 has smaller dimensions than those of the support SL.

[0105] [Fig.6] represents, schematically and in sectional view, an example of implementation of the support S2.

[0106] In the example of [Fig.6], the microchip CL1 is mounted on the support S2, at the location EC1 of the support S2.

[0107] In this example, the support S2 does not comprise an interposer, or, in other words, only comprises an organic support 500, for example a printed circuit card.

[0108] When the microchip CL1 is mounted on the support S2 as shown in [Fig.6], the connection balls or pads 400 of the chip CL1 ensure the electrical connection of the microchip CL1 to the support S2.

[0109] In another example, the support S2 may comprise an interposer in a manner similar to that described for the support SI of [Fig.4]. However, such an interposer is of little interest here and complicates the implementation of the support S2.

[0110] Although this is not shown in [Fig.4], the SI support comprises, on the side of its face opposite the face of the SI support on which the CL1 microchip is mounted, pads or connection balls to allow the electrical connection of the SI support to a card ("board" in English) when the SI support is assembled on this card.

[0111] [Fig.7] schematically represents, in top view and in the form of blocks, an exemplary embodiment of a card B1, configured to accommodate the support SL

[0112] The card B1, preferably a printed circuit board (PCB), comprises an ESI location configured to receive the SI support, the ESI location being delimited by dotted lines in [Fig.7].

[0113] The card B1 further comprises an interface ITB1. The card B1 is configured to connect, via the support SI, the interface of the microchip CL1 to the interface ITB1. This interface ITB1 is configured to be connected to an interface ITB1 of another card, for example of another card BL. In other words, when the support SI is mounted on the card Bl, at the location ESI of the card Bl, and the microchip CL1 is mounted on this support SI, at the location EC1 of the support SI, then the support SI and the card Bl connect the interface IT1 of the microchip CL1 to the interface ITB1 of the card BL.

[0114] Thus, by connecting the interface ITB 1 of the card B1 on which the microchip CL1 is mounted, to the interface ITB1 of another card, for example another card Bl, on which another microchip CL1 is mounted, the two microchips CL1 are connected to each other.

[0115] Thus, in an embodiment where each microchip CL1 comprises at least two interfaces IT1 and where each card Bl comprises at least two interfaces ITB1, several microchips CL1 can be connected in the form of a network by connecting together, by their interfaces ITB1, several cards, for example several cards BL

[0116] The card Bl comprises, in addition to the location ESI for the support SI, a location ES3 for an auxiliary support S3, the support S3 being configured to receive a CL3 chip, which will be connected to the IT3 interface of a CL1 microchip via its IT3c interface, and at least one other CL2 and / or CL3 microchip, preferably several CL3 microchips only. In other words, the S3 support comprises a location configured to receive a corresponding CL3 microchip, and at least one other location configured to receive a corresponding CL2 or CL3 microchip. In particular, the S3 support does not have a location to receive the CL1 chip, and is therefore qualified as auxiliary with respect to the SI and S2 supports.

[0117] [Fig.8] schematically represents, in top view and in the form of blocks, an exemplary embodiment of an auxiliary support S3, adapted to cooperate with the card B1 of [Fig.7].

[0118] The S3 support comprises at least two EC3 locations among which one EC3 location is configured to receive a CL3 microchip which will be connected to a CL1 microchip.

[0119] Each EC3 location is configured to receive a CL3 (or CL2) microchip specific to this location with the exception of one of the EC3 locations which is configured to receive only a CL3 microchip specific to this location and intended to be connected to a CL1 microchip. In other words, the dimensions and the electrical connection areas of each EC3 location are determined by the dimensions and the electrical connection areas of the CL3 (or CL2) microchip that this EC3 location is intended to receive. For example, a first CL3 (or CL2) microchip corresponding to an EC3 location cannot be received by another EC3 location configured to receive a second CL3 (or CL2) microchip, except, for example, if the first and second microchips are identical or if the first and second microchips have the same dimensions with an identical physical and functional arrangement of their connection pads or balls.

[0120] In the example of [Fig.8], the S3 support comprises exactly four EC3 locations.

[0121] In [Fig.8], each EC3 location is represented by dotted lines.

[0122] Referring again to [Fig.7], although not visible in [Fig.7], the support SI, auxiliary support S3 and card B1 are configured to connect an interface IT3 of microchip CL1 to an interface IT3c of microchip CL3 corresponding to the one of the EC3 slots of support S3 which is configured to receive the microchip EC3 intended to be connected to microchip CL1. In addition, for each other EC3 slot, support S3 is configured to connect the microchip EC2 or EC3 corresponding to this EC3 slot to the microchip EC3 of the slot EC3 configured to receive microchip CL3 which will be connected to microchip CL1. In other words, support S3 is configured to connect together the microchips which it receives on these EC3 slots and to connect one of these microchips, namely a microchip CL3, to a microchip CL1 via the card on which the support S3 is mounted and the support on which the microchip CL1 is mounted.

[0123] Furthermore, preferably the card B1 comprises at least one location EM for receiving a memory circuit. In particular, the card B1 comprises a memory location EM (below the location ESI in the example of [Fig.7]) and is configured to connect, via the support SI, a memory circuit received by this location to the microchip CL1, for example to an interface ITm of the microchip CL1, mounted on the support SI which is itself mounted on the card Bl.

[0124] According to one embodiment, the card B1 comprises, for each location EC3 of the support S3, a memory location EM (the four locations EM distributed around the location ES3 in the example of [Fig.7]) configured to receive a memory circuit, the card B1 is further configured to connect, via the support S3, a memory circuit received by this location EM to the microchip CL3 (or CL2), for example to an interface ITm of the microchip CL3 (or CL2), mounted on this location EC3 of the support S3 which is itself mounted on the card B1.

[0125] According to one embodiment, the card B1 comprises, for each location EC2 of the support SI, a memory location EM (not shown in [Fig.7]) configured to receive a memory circuit, and the card Bl is further configured to connect, via the support SI, a memory circuit received by this location EM to the microchip CL2 (or CL3), for example to an interface ITm of the microchip CL2 (or CL3), mounted on this location EC2 of the support SI which is itself mounted on the card Bl.

[0126] Preferably, the card B1 does not comprise any other location configured to receive a microchip support. In other words, preferably, the card B1 only comprises the locations ESI and ES3 configured to receive the respective microchip supports S1 and S3.

[0127] Preferably, the supports SI and S3 are each devoid of a location EM for receiving a memory circuit, the memory circuits associated with the different microchips mounted on the supports SI and S3 being mounted on the card B1 on which the supports SI and S3 are mounted. However, in alternative examples, for at least one microchip CL1, CL2 or CL3 to be connected to a memory, the location EM of this memory may be provided on the support on which this microchip is mounted, rather than on the card receiving this support.

[0128] [Fig.9] schematically represents, in top view and in the form of blocks, an exemplary embodiment of another B2 board, configured to accommodate the SI support. The B2 board includes many elements and functions in common with the Bl board, and only the differences between these two boards are highlighted here.

[0129] In particular, the card B2, for example a PCB, differs from the card B1 in that it does not comprise a location ES3 for receiving the support S3, but, instead, a location ES4 for receiving an auxiliary support S4 comprising a single location EC3 for receiving a microchip CL3 or CL2, preferably a microchip CL3.

[0130] Thus, the card B2 comprises the interface ITB1 configured to be connected to an interface ITB1 of another card, for example of another card B1 or B2. The card B2 is configured to connect, via the support SI, the interface of the microchip CL1 to the interface ITB1. In other words, when the support SI is mounted on the card B2, at the location ESI of the card B2, and the microchip CL1 is mounted on this support SI, at the location EC1 of the support SI, then the support SI and the card B2 connect the interface IT1 of the microchip CL1 to the interface ITB1 of the card B1.

[0131] Thus, in an embodiment where each microchip CL1 comprises at least two interfaces IT1 and where each card B1 or B2 comprises at least two interfaces ITB1, several microchips CL1 can be connected in the form of a network by connecting together, via their interfaces ITB1, several cards B1 or B2.

[0132] [Fig. 10] schematically represents, in top view and in the form of blocks, an exemplary embodiment of an auxiliary support S4, adapted to cooperate with the card B2 of [Fig.9].

[0133] The support S4 comprises a single location EC3 (in dotted lines in [Fig. 10]) configured to receive a corresponding CL3 or CL2 microchip, preferably a corresponding CL3 microchip.

[0134] Location EC3 of support S4 is configured to receive a CL3 microchip specific to this location and configured to be connected to a CL1 microchip.

[0135] Referring again to [Fig.9], although this is not visible in [Fig.9], the socket SI, the auxiliary socket S4 and the card B2 are configured to connect an interface IT3c of the microchip corresponding to the single location EC3 of the socket S4 with a corresponding interface IT3 of the microchip CL1. In other words, when the corresponding microchip CL3 is received by this single location EC3 of the socket S4, that the socket S4 is assembled on the card B2 at location ES4, that the microchip CL1 is received by the location EC1 of the socket SI and that the socket SI is assembled on the card B2 at location ESI, the interface IT3c of the microchip received by the location EC3 is then connected to a corresponding interface IT3 of the microchip CL1. This connection is made via the socket S4, the card B2 and the socket SL

[0136] Furthermore, preferably the card B2 comprises at least one location EM for receiving a memory circuit.

[0137] In particular, the card B2 comprises a memory location EM (below the location ESI in the example of [Fig.9]), and the card B2 is configured to connect, via the support SI, a memory circuit received by this location EM to the microchip CL1 mounted on the support SI, for example to an interface ITm of the microchip CLE

[0138] According to one embodiment, the card B2 comprises, for the location EC3 of the support S4, a memory location EM (below the location ES4 in the example of [Fig.9]) configured to receive a memory circuit. The card B2 is further configured to connect, via the support S4, a memory circuit received by this location EM to the microchip CL3 (or CL2), for example to an interface ITm of the microchip CL3 (or CL2), mounted on the location EC3 of the support S4 which is itself mounted on the card B2.

[0139] According to one embodiment, the card B2 comprises, for each location EC2 of the support SI, a memory location EM (not shown in [Fig.7]) configured to receive a memory circuit, and the card B1 is further configured to connect, via the support SI, a memory circuit received by this location EM to the microchip CL2 (or CL3), for example to an interface ITm of the microchip CL2 (or CL3), mounted on this location EC2 of the support SI which is itself mounted on the card B1.

[0140] Preferably, the card B2 does not comprise any other location configured to receive a microchip support. In other words, preferably, the card B2 comprises only the locations ES1 and ES4 configured to receive the respective microchip supports S1 and S4.

[0141] Preferably, the supports SI and S4 are each devoid of a location EM for receiving a memory circuit, the memory circuits associated with the different microchips mounted on the supports SI and S4 being mounted on the card B2 on which the supports SI and S4 are mounted. However, in alternative examples, for at least one microchip CL1, CL2 or CL3 to be connected to a memory, the location EM of this memory may be provided on the support on which this microchip is mounted, rather than on the card receiving this support.

[0142] [Fig. 11] schematically represents, in top view and in the form of blocks, an exemplary embodiment of a card B3, configured to accommodate the support S2 of [Fig.5].

[0143] The board B3, for example a PCB, differs from the boards B1 and B2 in that it does not include a location ESI for receiving the support SI, but instead a location ES2 for receiving the support S2 comprising a single microchip location for receiving the microchip CL1.

[0144] Thus, the card B3 comprises the interface ITB1 configured to be connected to an interface ITB1 of another card, for example of another card B1 or B2 or B3. board B3 is configured to connect, via socket S2, the interface of microchip CL1 to interface ITB1. In other words, when socket S2 is mounted on board B3, at location ES2 of board B3, and microchip CL1 is mounted on this socket S2, at location EC1 of socket S2, then socket S2 and board B3 connect interface IT1 of microchip CL1 to interface ITB1 of board B3.

[0145] Thus, in an embodiment where each microchip CL1 comprises at least two interfaces IT1 and where each card B1 or B2 or B3 comprises at least two interfaces ITB1, several microchips CL1 can be connected in the form of a network by connecting together, via their interfaces ITB1, several cards B1 or B2 or B3.

[0146] In addition, card B3 comprises, like card B2, a location ES4 configured to receive the auxiliary support S4.

[0147] Although this is not visible in [Fig.l 1], the support S2, the auxiliary support S4 and the card B 3 are configured to connect an interface IT3c of the microchip CL3 corresponding to the single location EC3 of the support S4 with a corresponding interface IT3 of the microchip CL1. In other words, when the corresponding microchip CL3 (or CL2) is received by this single location EC3 of the support S4, that the support S4 is assembled on the card B3 at the location ES4, that the microchip CL1 is received by the location EC1 of the support S2 and that the support S2 is assembled on the card B3 at the location ES2, the interface IT3c of the microchip CL3 received by the location EC3 is then connected to a corresponding interface IT3 of the microchip CL1. This connection is made via the support S4, the card B3 and the support S2.

[0148] Furthermore, the card B3 comprises at least one location EM for receiving a memory circuit.

[0149] In particular, the card B3 comprises a memory location EM (to the right of the location ES2 in the example of [Fig. 11]), and the card B3 is configured to connect, via the support S2, a memory circuit received by this location EM to the microchip CL1 mounted on the support S2, for example to an interface ITm of the microchip CL1.

[0150] According to one embodiment, the card B3 comprises, for the location EC3 of the support S4, a memory location EM (below the location ES4 in the example of [Fig. 11]) configured to receive a memory circuit. The card B3 is further configured to connect, via the support S4, a memory circuit received by this location EM to the microchip CL3 (or CL2), for example to an interface ITm of the microchip CL3 (or CL2), mounted on the location EC3 of the support S4 which is itself mounted on the card B3.

[0151] Preferably, the card B3 does not include another location configured for receive a microchip holder. In other words, preferably, the B3 board only includes the ES2 and ES4 slots configured to receive the respective S2 and S4 microchip holders.

[0152] Preferably, the supports S2 and S4 are each devoid of a location EM for receiving a memory circuit, the memory circuits associated with the different microchips mounted on the supports S2 and S4 being mounted on the card B3 on which the supports S2 and S4 are mounted. However, in alternative examples, for at least one microchip CL1, CL2 or CL3 to be connected to a memory, the location EM of this memory may be provided on the support on which this microchip is mounted, rather than on the card receiving this support.

[0153] [Fig. 12] represents, in the form of a flowchart, an example of an embodiment of a method for designing a computer.

[0154] In a step 1200 (block "SUPPORT"), a microchip support is chosen from at least the supports S1 and S2, preferably from only the supports S1 and S2.

[0155] At a step 1202 (block "BOARD"), for example implemented after step 1200, a card is chosen from at least the cards B1, B2 and B3, preferably only from the cards B1, B2 and B3.

[0156] The chosen card must be adapted to the chosen support. Thus if the chosen support is the support SI, the chosen card will be, for example, the card Bl or the card B2. On the other hand, if the chosen support is the support S2, the chosen card will be, for example, the card B3.

[0157] In practice, the choice of a support and a card in steps 1200 and 1202 is determined by a calculation and processing capacity targeted for the calculator.

[0158] For example, for a computer with significant data processing and calculation needs, for example a computer intended for a vehicle having an AD AS level L3 or L4 and comprising a significant number of multimedia devices, the card Bl associated with the supports SI and S3 is the one which will make it possible to obtain the computer with the greatest calculation and data processing capacity if each of the locations EC2 and EC3 of the respective supports SI and S3 receives a corresponding microchip CL2 or CL3.For example, conversely, for a computer with low data processing and calculation requirements, for example a computer intended for a lowest-end vehicle having an AD AS L2 level and comprising a low number, or even zero, of multimedia devices, the B3 card associated with the S2 support but without the S4 support being mounted on the B3 card, will make it possible to obtain the computer with the lowest calculation and data processing capacity, this calculation and processing capacity however remaining sufficient to address the needs of the vehicle.

[0159] At a step 1204 (block "CL1 ON SUPPORT"), for example implemented after steps 1200 and 1024, the chosen support receives the microchip CL1 in its location EC1. In other words, at this stage, the CL1 microchip is mounted on the location EC1 of the chosen support, so as to be assembled to this support. We recall here that the locations EC1 of the supports SI and S2 are configured to receive the same microchip CLE

[0160] In a step 1206 (block "CL2 ON SUPPORT"), for example implemented after steps 1200, 1202 and 1204, one or more microchips CL2 (or CL3) are mounted on the support SI, at locations EC2 corresponding to the support SI. Step 1206 is therefore not implemented when the support chosen in step 1200 is the support S2. Furthermore, even when the support chosen is the support SI, this step 1206 can be optional. However, in this case, the choice of the support S2 would have been more suitable.

[0161] When step 1206 is implemented, the number of EC2 locations of the SI support which actually receive a corresponding CL2 (or CL3) microchip depends, for example, on the computing and data processing power targeted for the designed computer. For example, for relatively high computing and data processing powers, each EC2 location of the SI support receives a corresponding CL2 (or CL3) microchip, whereas, for lower computing powers, only some of these EC2 locations receive corresponding CL2 (or CL3) microchips.

[0162] At a step 1208 (block "SUPPORT ON BOARD"), the selected support is assembled on the selected board. In other words, the selected board receives in its location ESI or ES2 the selected support SI or S2 respectively. Step 1028 is, for example, implemented after steps 1204 and 1206. However, in other examples, step 1208 is implemented directly after step 1202 and steps 1024 and 1206 are implemented after step 1208.

[0163] At a step 1210 (block "AUX SUPPORT"), an auxiliary support S3 or S4 is selected depending on the card Bl, B2 or B3 chosen. For example, if the card chosen is card Bl, the selected auxiliary support is support S3, whereas if card B2 or B3 is chosen, support S4 is then selected.

[0164] This step 1210 is, for example, implemented after step 1208, although it may, in other examples, be implemented simultaneously with steps 1200 and 1202.

[0165] Step 1210 is optional. For example, the choice of whether or not to select an auxiliary support to mount it on the chosen card is determined by the computing and data processing power targeted for the designed computer. Indeed, when the targeted computing power is achieved with only a support SI comprising the microchip CL1 and one or more microchips CL2 (or CL3) or a support S2 comprising the microchip CL1, it is then not necessary to provide an auxiliary support on the chosen card. Conversely, when the targeted computing power is not achieved with only the SI support comprising the CL1 microchip and one or more CL2 (or CL3) microchips or with only the S2 support comprising the CL1 microchip, an auxiliary support is selected to be mounted on the chosen card.

[0166] When step 1210 is actually implemented and an auxiliary support is selected in step 1210, in a following step 1212 (block "CL3 ON AUX SUPPORT"), if the auxiliary support is the support S4 (adapted to cards B2 and B3) a corresponding CL3 (or CL2) microchip is mounted on the single location EC3 of the support S4, and, if the auxiliary support is the support S3 (adapted to card B1), for at least the location EC3 of the support S3 configured to receive the CL3 microchip which will be connected to the CL1 microchip, the corresponding CL3 microchip is mounted on this location EC3 of the support S3, and each other EC3 location may or may not receive a corresponding CL3 (or CL2) microchip.

[0167] When step 1210 is actually implemented and an auxiliary support is selected in step 1210, in a following step 1214 (block "AUX SUPPORT ON BOARD"), for example implemented after or before step 1212, the auxiliary support S3 or S4 is mounted on the location ES3 or ES3 respectively of the card.

[0168] In a following step 1216 (block "ADD MEM"), for example implemented after step 1208, for example after the implementation of the optional steps 1210, 1212 and 1214, a memory circuit is mounted at a corresponding location EM of the card or of the support of the microchip CL1 to be connected to the microchip CL1. Optionally, for each microchip CL2 or CL3 assembled on the card, via the supports S1, S2, S3 or S4, a memory circuit can be mounted in a corresponding location EM of the card or of the support of this microchip CL2 or CL3 to be connected to this microchip CL2 or CL3.

[0169] Of course, the person skilled in the art will be able to implement the steps described above in another way other than that described as an example.

[0170] [Fig. 13] illustrates, schematically and in the form of blocks, examples of calculators obtained by implementing the method of [Fig. 12].

[0171] On the left in [Fig.13], the two supports SI and S2 are illustrated very schematically, in the form of blocks.

[0172] If the support SI is chosen, the card Bl can be chosen as represented by an arrow 1300 going from the support SI to the card Bl on which the support SI is mounted (assembly 1306 in [Fig. 13]), or the card B2 can be chosen as represented by an arrow 1302 going from the support SI to the card B2 on which the support S2 is mounted (assembly 1308 in [Fig. 13]).

[0173] If support S2 is chosen, card B3 is chosen as represented by an arrow 1304 going from support S2 to card B3 on which support S2 is mounted. (set 1310 in [Fig. 13]).

[0174] The auxiliary support S3 can then be selected to be mounted on the assembly 1306 of the card B1 and the support SI as represented by an arrow 1312 going from the assembly 1306 to an assembly 1314 comprising the card B1 on which the two supports SI and S3 are mounted.

[0175] Then the microchip CL1 is mounted on the support SI of the assembly 1314, at least one location EC2 of the support SI receives a corresponding microchip CL2 (or CL3) and at least one location EC3 of the support S3 receives a corresponding microchip CL3 (or CL2).

[0176] For example, when each location EC2 of the support SI of the set 1314 receives a corresponding microchip CL2 and each location EC3 of the support S3 of the set 1314 receives a corresponding microchip CL3, a computer 1316 is obtained as represented by an arrow 1318 going from the set 1314 to this computer 1316.

[0177] As another example, when only one location EC2 of the support SI of the assembly 1314 receives a corresponding microchip CL2 and only two locations EC3 of the support S3 of the assembly 1314 receive two corresponding microchips CL3, a computer 1320 is obtained as represented by an arrow 1322 going from the assembly 1314 to this computer 1320.

[0178] Of course, although this is not illustrated in [Fig.13], other examples of calculators can be obtained from the assembly 1314 depending on the locations EC2 of the support SI which receive or not corresponding microchips CL2 (or CL3) and the locations EC3 of the support S3 which receive or not corresponding microchips CL3 (or CL2).

[0179] Starting from the assembly 1306, when no auxiliary support is selected to be mounted on the card B1, the microchip CL1 is mounted on the support SI of the assembly 1306 and at least one location EC2 of the support SI receives a corresponding microchip CL2 (or CL3).

[0180] For example, when each location EC2 of the support SI of the assembly 1306 receives a corresponding microchip CL2, a computer 1324 is obtained as represented by an arrow 1326 going from the assembly 1306 to this computer 1324.

[0181] As another example, when a single location EC2 of the support SI of the assembly 1306 receives a corresponding microchip CL2, a computer 1328 is obtained as represented by an arrow 1330 going from the assembly 1306 to this computer 1328.

[0182] Of course, although this is not illustrated in [Fig. 13], other examples of calculators can be obtained from the assembly 1306 depending on the locations EC2 of the support SI which receive or not corresponding microchips CL2 (or CL3).

[0183] From the card B1 and the support SI, with or without the auxiliary support S3, [Fig. 13] shows that it is possible to design several computers which will have different processing and calculation capacities, and will therefore be adapted to different application needs. However, these different computers can all, advantageously, be placed in the same case, for example a case with dimensions determined by those of the card Bl.

[0184] In [Fig. 13], the step of adding one or more memory circuits in corresponding EM locations has not been illustrated.

[0185] Starting from assembly 1308, auxiliary support S4 can then be selected to be mounted on assembly 1308 as represented by an arrow 1332 going from assembly 1306 to an assembly 1334 comprising card B2 on which the two supports S1 and S4 are mounted.

[0186] Then the microchip CL1 is mounted on the support SI of the assembly 1334, at least one location EC2 of the support SI receives a corresponding microchip CL2 (or CL3) and the location EC3 of the support S4 receives a corresponding microchip CL3.

[0187] For example, when each location EC2 of the support SI of the assembly 1334 receives a corresponding microchip CL2 and the location EC3 of the support S4 of the assembly 1334 receives a corresponding microchip CL3, a computer 1336 is obtained as represented by an arrow 1338 going from the assembly 1334 to this computer 1336.

[0188] As another example, when a single location EC2 of the support SI of the assembly 1334 receives a corresponding microchip CL2 and the location EC3 of the support S4 of the assembly 1334 receives a corresponding microchip CL3, a computer 1340 is obtained as represented by an arrow 1342 going from the assembly 1334 to this computer 1340.

[0189] Of course, although this is not illustrated in [Fig. 13], other examples of calculators can be obtained from the assembly 1334 depending on the locations EC2 of the support SI which receive or not corresponding microchips CL2 (or CL3).

[0190] Starting from the assembly 1308, when no auxiliary support is selected to be mounted on the card B2, the microchip CL1 is mounted on the support SI of the assembly 1306 and at least one location EC2 of the support SI receives a corresponding microchip CL2 (or CL3).

[0191] For example, when a single location EC2 of the SI support of the assembly 1308 receives a corresponding CL2 microchip, a computer 1344 is obtained as represented by an arrow 1346 going from the assembly 1308 to this computer 1344.

[0192] As another example, when each location EC2 of the support SI of the assembly 1308 receives a corresponding microchip CL2, a calculator 1341 is obtained as represented by an arrow 1343 going from the assembly 1308 to this calculator 1341.

[0193] Of course, although this is not illustrated in [Fig.13], other examples of calculators can be obtained from the assembly 1308 depending on the locations EC2 of the support SI which receive or not corresponding microchips CL2 (or CL3).

[0194] From the card B2 and the support SI, with or without the auxiliary support S4, [Fig. 13] shows that it is possible to design several computers which will have different processing and calculation capacities, and will therefore be adapted to different application needs. However, these different computers can all, advantageously, be placed in the same housing, for example a housing with dimensions determined by those of the card B2.

[0195] In [Fig. 13], the step of adding one or more memory circuits in corresponding EM locations has not been illustrated.

[0196] Starting from the assembly 1310, the auxiliary support S4 can then be selected to be mounted on the assembly 1310 as represented by an arrow 1348 going from the assembly 1310 to an assembly 1350 comprising the card B3 on which the two supports S2 and S4 are mounted.

[0197] Then the microchip CL1 is mounted on the support S2 of the assembly 1350, and the location EC3 of the support S4 receives a corresponding microchip CL3 to obtain a computer 1352 as illustrated by an arrow 1354 going from the assembly 1350 to the computer 1352.

[0198] Starting again from the assembly 1310, when no auxiliary support is selected to be mounted on the card B3, the microchip CL1 is mounted on the support S2 of the assembly 1310 to obtain a computer 1356 as illustrated by an arrow 1358 going from the assembly 1310 to the computer 1356.

[0199] From the card B3 and the support S2, with or without the auxiliary support S4, [Fig. 13] shows that it is possible to design several computers which will have different processing and calculation capacities, and will therefore be adapted to different application needs. However, these different computers can all, advantageously, be placed in the same case, for example a case with dimensions determined by those of the card B3.

[0200] In [Fig. 13], the step of adding one or more memory circuits in corresponding EM locations has not been illustrated.

[0201] [Fig. 13] shows that from two supports SI and S2, three cards Bl, B2 and B3 and two auxiliary supports S3 and S4, it is possible to design several computers which will have different processing and calculation capacities, and will therefore be adapted to different application needs. However, advantageously, only three ECU housings are sufficient so that all these different ECUs can be mounted in a corresponding housing.

[0202] As previously indicated, each CL1 microchip comprises an IT1 interface and each card comprises an ITB1 interface. In addition, each assembly of a support SI or S2 on a corresponding card Bl, B2 or B3 makes it possible, when a CL1 microchip is mounted on this support, to connect the IT1 interface of the CL1 microchip to the ITB1 interface of the card. Thus, it is possible to connect two assemblies, i.e. two computers, preferably identical, each comprising a card Bl, B2 or B3, an SI or S2 support, and a CL1 microchip mounted on the support, via the ITB1 interfaces of the cards of these two assemblies, which amounts to connecting between two CL1 microchips via their CL1 interfaces. In this way, it is possible to introduce calculation redundancy between the two computers.For example, at least one of the CL1 chips is configured to compare the results of the calculations implemented by the computer to which it belongs with the results of the calculations implemented by the other computer to which the CLA microchip is coupled. This makes it possible, for example, to meet operational safety requirements or constraints, for example as defined by the ISO 26262 standard.

[0203] In the above description, the chip CL1 is the same whether it is mounted on the location EC1 of the support SI or the support S2. However, according to one embodiment, two versions of this single chip CL1 are provided, namely, a first version having its connection pads or balls 400 arranged according to a first arrangement, and a second version having its connection pads or balls 400 arranged according to a second arrangement in which the density of connection pads or balls 400 is higher than for the first arrangement, and in which the position of the connection pads or balls 400 is determined by the position of the connection pads or balls 400 of the first arrangement.

[0204] The first version of the microchip CL1 will be better suited to a support SI or S2, preferably a support S2, without an interposer. Conversely, the second version of the microchip CL1 will be better suited to a support SI or S2, preferably a support SI, comprising an interposer. Indeed, a support provided with an interposer generally has a density of connection regions intended to cooperate with the pads or balls 400 which is higher than that of a support without an interposer. The provision of an interposer in the support SI facilitates the design of the connections between the location EC1 and each location EC2 of the support SL. Since the support S2 does not comprise a location EC2, it is preferable for this support S2 to be without such an interposer.

[0205] Thus, according to one embodiment, the location EC1 of the support SI is configured to receive the first version of the microchip CL1, and the location EC1 of the S2 support is configured to receive the second version of the CL1 microchip.

[0206] The design of the second version of the microchip CL1 from the first version of the microchip CL1 is based on a replacement of each ball or pad 400 of the first version of the microchip CL1 by several a pattern of several pads or balls 400, and on the modification accordingly of the last metal level or levels of the interconnection structure of the first version of the microchip CL1. The design of the second version of the chip CL1 from the first version of the microchip CL1 then requires little effort. Furthermore, this is why, in the present description, it is considered that each location EC1 receives the same microchip CL1, although this location EC1 is, depending on the case, configured to receive the first or the second version of this microchip.

[0207] [Fig. 14] illustrates an example of transition from the first version of the CL1 microchip (on the left in [Fig. 13]) to the second version of this CL1 microchip (on the right in [Fig.13]).

[0208] In this example, each pad or ball 400 of the first version of the microchip CL1 is replaced, in the second version of the microchip CL1, by a pattern 1400 of four pads or balls 400, and, in addition, the pads or balls 400 of the second version are smaller than those of the first version.

[0209] [Fig. 15] illustrates another example of transition from the first version of the CL1 microchip (on the left in [Fig.13]) to the second version of this CL1 microchip (on the right in [Fig.13]).

[0210] In this example, each pad or ball 400 of the first version of the microchip CL1 is replaced, in the second version of the microchip CL1, by a pattern 1500 of four pads or balls 400, and, in addition, the pads or balls 400 of the second version are smaller than those of the first version.

[0211] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0212] In particular, although a microchip CL1 without a location configured to receive a microchip CL1 or CL3 has been described, in an alternative embodiment the microchip CL1 comprises, on the side of its face furthest from the support S1 or S2 on which the microchip CL1 is mounted, at least one location configured to receive a microchip CL2 or CL3.

[0213] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Method for designing a computer comprising: choosing a support (1200) from a first support (SI) and a second support (S2) each comprising a first location (EC1) configured to receive the same first microchip (CL1); choosing a card adapted (1202) to the support chosen from a first card (B1), a second card (B2) and a third card (B3), the first and second cards (B1, B2) each having a first location (ES1) configured to receive the first support (SI) and the third card (B3) having a first location (ES2) configured to receive the second support (S2); assembling the first microchip (CL1) on the first location (EC1) of the chosen support (1204); and assembling (1208) the selected support (SI; S2) on the first location (ESI; ES2) of the selected card (Bl, B2; B3), in which: each of the cards (Bl, B2; B3) is configured to connect, via the support (SI, S2) that the first location (ESI;ES2) of the card is configured to receive a first interface (IT1) of the first microchip (CL1) and a first interface (ITB1) of said card, the first interface of said card being adapted to be connected to the first interface of another card chosen from the first, second and third cards, the first support (SI) comprises one or more second locations (EC2) each configured to receive a corresponding second microchip (CL2, CL3); and the first microchip (CL1) is configured to direct data flows and implement calculations on the data flows.;

2. Method according to claim 1, wherein, for each second location (EC2) of the first support (SI), the first support is configured to connect a second interface (IT2c, IT3c) of the second microchip (CL2, CL3) corresponding to this second location with a corresponding second interface (IT2) of the first microchip (CL1).

3. Method according to claim 1 or 2, wherein, when the selected support is the first support (SI), the method further comprises, for at least a second location (EC2) of the first support, assembling (1206) the second microchip (CL2, CL3) corresponding to this second location on this second location.

4. A method according to any one of claims 1 to 3, wherein: a first version of the first microchip (CL1) has connection pads arranged in a first arrangement; a second version of the first microchip (CL1) has connection pads arranged in a second arrangement, the second arrangement being determined by the first arrangement and having a higher pad density than that of the first arrangement; the first location (EC1) of the first support (S1) is configured to receive the first version of the first microchip (CL1) and the first location (EC1) of the second support (S2) is configured to receive the second version of the first microchip (CL1).

5. Method according to any one of claims 1 to 4, wherein: the first card (Bl) further comprises a second location (ES3) configured to receive a first auxiliary support (S3) having several locations (EC3) each configured to receive a corresponding second microchip (CL3, CL2).

6. Method according to claim 5, wherein, for one of the locations (EC3) of the first auxiliary support (S3), the first support (SI), the first auxiliary support (S3) and the first card (Bl) are configured to connect an interface (IT3c) of the second microchip (CL3) corresponding to this location with a corresponding interface (IT3) of the first microchip (CL1).

7. Method according to claim 6, wherein, when the first support (SI) and the first card (Bl) are chosen, the method further comprises: on said one of the locations (EC3) of the first auxiliary support (S3), assembling (1212) the corresponding second microchip (CL3, CL2); and assembling (1214) the first auxiliary support (S3) on the second location (ES3) of the first card (Bl).

8. Method according to any one of claims 5 to 7, in which each second microchip (CL3) corresponding to a location of the first auxiliary support implements accelerator functions for an advanced pilot assistance system, for example of level L3 or L4.

9. A method according to any one of claims 1 to 8, wherein: each of the second and third cards (B2, B3) comprises a second location (ES4) configured to receive a second auxiliary support (S4) having a single location (EC3) configured to receive a second microchip (CL3, CL2) corresponding to this location.

10. Method according to claim 9, wherein: - the second auxiliary support (S4), the second card (B1) and the first support (S1) are configured to connect an interface (IT3c) of the second microchip (CL3, CL2) corresponding to the single location (EC3) of the second auxiliary support (S4) with a corresponding interface (IT3) of the first microchip (CL1); and - the second auxiliary support (S4), the third card (B3) and the second support (S2) are configured to connect an interface (IT3c) of the second microchip (CL3) corresponding to the single location (EC3) of the second auxiliary support (S4) with a corresponding interface (IT3) of the first microchip (CL1).

11. A method according to claim 9 or 10, wherein, when the first support (SI) and the second card (B2) are selected, the method further comprises: assembling (1212) the corresponding second microchip (CL2) to the single location (EC3) of the second auxiliary support (S4) on this location; and assembling (1214) the second auxiliary support (S4) on the second location (ES4) of the second card (B2).

12. A method according to claim 9 or 10, wherein, when the second support (S2) and the third board (B3) are selected, the method further comprises: assembling (1212) the corresponding second microchip (CL3) to the single location (EC3) of the second auxiliary support (S4); and assembling (1214) the second auxiliary support (S4) to the second location (ES4) of the third board (B3).

13. Method according to any one of claims 9 to 12, in which the second microchip (CL3) corresponding to the single location of the second auxiliary support implements accelerator functions for an advanced pilot assistance system, for example of level L3 or L4.

14. A method according to any one of claims 1 to 13, wherein the second support (S2) is devoid, with the exception of its first em- placement (EC1), location configured to receive a microchip.

15. Method according to any one of claims 1 to 14, in which the choice of the card (B1, B2, B3) and the support (SI, S2) is determined by a calculation and processing capacity targeted for the calculator.

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