Method of manufacturing a resistive memory cell of the OxRAM type and associated OxRAM type memory cell

Abstract

The invention relates to a method for manufacturing an OxRAM resistive memory cell, comprising the following steps: forming a TiN lower electrode, first implantation of Si atoms in the lower electrode with a first implantation dose and a first implantation acceleration voltage, said first implantation dose being strictly positive and strictly less than 0.7.1014 cm-2, second implantation of Si atoms in the lower electrode with a second implantation dose and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, said second implantation dose being strictly positive and strictly less than 0.6.1014 cm-2, the first and second accelerating voltages being chosen to have an implantation profile following the first and second implantation having a maximum concentration of Si at a depth between 1 and 3 nm from the upper surface of the lower electrode, deposition of an active layer on the implanted lower electrode, deposition of an upper electrode on the active layer. Figure to be published with the abstract: None.

Description

Title of the invention: Method for manufacturing a resistive memory cell of the OxRAM type and associated OxRAM type memory cell Technical field

[0001] The present invention relates generally to the field of microelectronics. It relates more particularly to the field of non-volatile resistive memories of the filamentary type.

[0002] In particular, the present invention relates to a method for manufacturing a resistive memory cell of the OxRAM type. It also relates to such a resistive memory cell of the OxRAM type obtained by the manufacturing method. STATE OF THE ART

[0003] Resistive memories, in particular oxide-based resistive memories (or OxRAM, for "Oxide-based Random Access Memories" according to the commonly used acronym), are non-volatile memories intended to replace Flash-type memories. In addition to a high integration density, they have a high operating speed and good compatibility with the manufacturing processes currently used in the microelectronics industry, in particular with the end-of-line (BEOL, for "Back-End Of Line" according to the commonly used acronym) process of CMOS technology (for "Complementary Metal Oxide Semi-conductor" according to the commonly used acronym).

[0004] OxRAM resistive memories comprise a multitude of memory cells, also called memory points. Each OxRAM memory cell consists of a MIM (Metal-Insulator-Metal) capacitor comprising an active material of variable electrical resistance, generally a transition metal oxide (e.g. HfO2, Ta2O 5, TiO2, etc.), arranged between two metal electrodes. The memory cell switches reversibly between two resistance states, which correspond to logic values ​​"0" and "1" used to encode a bit of information. In some cases, more than two resistance states can be generated, which makes it possible to store several bits of information in a single memory cell.

[0005] The information is written into the memory cell by switching it from a highly resistive state (or HRS, for “High Resistance State” according to the commonly used acronym of Anglo-Saxon origin), also called “OFF” state, to a weakly resistive state (or LRS, for “Low Resistance State”), or “ON” state. Conversely, to erase the information from the memory cell, it is switched from the weakly resistive state resistive (“OFF”) to highly resistive (“ON”) state.

[0006] The change in resistance of the memory cell is governed by the formation and rupture of a conductive filament of nanometric section between the two electrodes. This conductive filament is created thanks to the presence of oxygen vacancies present in the active layer of the memory cell. By modifying the potentials applied to the electrodes, it is possible to modify the distribution of the filament, and thus modify the electrical conduction between the two electrodes. In the active layer, the electrically conductive filament is either broken, or on the contrary reformed to vary the resistance level of the memory cell, during write cycles then resetting of this cell (SET operations, when the filament is reformed resulting in the LRS state, and RESET operations resulting in the HRS state, when the filament is broken again by respective application of a SET, VSEt or RESET, VRESEt voltage to the terminals of the electrodes).

[0007] Immediately after its manufacture, the resistive memory cell is in a virgin state characterized by a very high (so-called initial) resistance. This initial resistance is much higher than the resistance of the cell when it is in the highly resistive state. The oxide layer is in fact insulating in its initial state. In order for the memory cell to be used, it is necessary to carry out a so-called "forming" step. This step consists of a partially reversible breakdown of the oxide in order to generate the conductive filament for the first time (and therefore to place the memory cell in the low-resistive state). After this breakdown, the initially insulating oxide layer becomes active and the cell can switch between the low-resistive state and the high-resistive state by erasing and writing operations.The forming step is accomplished by applying between the two electrodes of the memory cell a voltage (called "forming" voltage) of a value much higher than the nominal operating voltage of the memory cell (used during the following write-erase cycles), for example a voltage of the order of 2.5 V for a nominal voltage of the order of 1.5 V.

[0008] The endurance of OxRAM memory cells is a crucial requirement, particularly for certain applications requiring very good endurance, beyond 1000 cycles, or even up to 10000 cycles (by cycle we mean a write / erase operation and by endurance, the fact that it is always possible to discriminate an HRS state from an LRS state beyond a given number of cycles). Summary of the invention

[0009] The present invention therefore aims to improve resistive memory cells of the OxRAM type, in particular by improving their endurance.

[0010] The invention then relates to a method of manufacturing a resistive memory cell. of the OxRAM type, comprising the following steps: • formation of a lower electrode made of titanium nitride, • first implantation of silicon atoms in the lower electrode with a first silicon implantation dose and a first implantation acceleration voltage, said first silicon implantation dose being strictly positive and strictly less than 0.7.1014 cm 2, • second implantation of silicon atoms in the lower electrode with a second silicon implantation dose and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, said second silicon implantation dose being strictly positive and strictly less than 0.6.1014 cm 2, the first and second acceleration voltages being chosen to have an implantation profile following the first and second implantation having a maximum concentration of silicon at a depth of between 1 and 3 nm from the upper surface of the lower electrode, • deposition of an active layer on the implanted lower electrode, • deposition of an upper electrode on the active layer.

[0011] Particularly surprisingly, doping the TiN lower electrode of the OxRAM cell with Si atoms makes it possible to considerably improve the endurance of the cell with certain conditions for implanting Si in the TiN. This unexpected technical effect firstly requires two implantations to be carried out, one with a lower Si ion acceleration voltage aimed at implanting the Si on the surface of the lower electrode of the OxRAM cell and the other with a higher Si ion acceleration voltage aimed at implanting the Si deeper into the lower electrode of the OxRAM cell. It also requires a particular implantation profile in the lower electrode with a maximum concentration of silicon at a depth of between 1 and 3 nm from the upper surface of the lower electrode.We will see later that with such conditions, the error rate (or BER for "Bit Error Rate" according to the commonly used acronym of Anglo-Saxon origin) on a set of memory cells obtained by the method according to the invention decreases with the number of cycles while it tends to increase for other types of cells and to present unsatisfactory values ​​for applications requiring significant endurance. The lower the error rate, the better the LRS and HRS states are distinguished on the scale of a matrix of memory cells.

[0012] By definition, this error rate corresponds to the percentage of memory cells in the set of memory cells considered which will not exhibit satisfactory properties.

[0013] note that the order of the first and second implantations can be reversed so that it is possible to carry out the first implantation before the second or conversely the second before the first. Preferably, however, the first implantation is carried out before the second implantation.

[0014] In addition to the characteristics which have just been mentioned in the preceding paragraphs, the manufacturing method according to the invention may have one or more additional characteristics among the following, considered individually or according to all technically possible combinations: • the first and second acceleration voltages are chosen to have an implantation profile following the first and second implantation having a maximum silicon concentration at a depth of between 1 and 1.6 nm from the upper surface of the lower electrode and a width of the implantation profile at half the value of the maximum silicon implantation concentration of between 1.6 nm and 2 nm. • the first and second acceleration voltages are chosen to have an implantation profile following the first and second implantation having a maximum silicon concentration at a depth of between 1.1 and 1.5 nm from the upper surface of the lower electrode and a width of the implantation profile at half the value of the maximum silicon implantation concentration of between 1.7 nm and 1.9 nm. • the deposition of the upper electrode on the active layer includes: • The deposition of a first conductive layer, in contact with the active layer and being chosen to create oxygen vacancies in the active layer, and • The deposition of a second conductive layer placed on the first conductive layer. • The material of the first conductive layer is titanium and the conductive material of the second conductive layer is titanium nitride. the first accelerating voltage is between 0.3 kV and 0.7 kV and the second accelerating voltage is between 1 kV and 2 kV. the first accelerating voltage is equal to 0.5 kV and the second accelerating voltage is equal to 1.5 kV. the first silicon implantation dose is equal to 0.5.1014cm2 and the second silicon implantation dose is equal to 0.3.1014cm2. The deposition of the active layer on the implanted lower electrode involves the following steps: • deposition of a layer of active material on the implanted lower electrode, • deposition of a layer of dielectric oxide on the material layer active, • implantation of silicon atoms through the dielectric oxide layer, the implantation dose and the implantation acceleration voltage being chosen so that the silicon atoms are implanted at least partly in the active material layer. • the active material is based on hafnium dioxide. • the dielectric oxide is based on aluminum oxide. • the step of implanting silicon through the dielectric oxide layer is carried out at an implantation acceleration voltage of between 1.5 and 3.5 kilovolts, and preferably equal to 2.5 kV, and a silicon implantation dose of between 1015cm2 and 5.1015cm2, and preferably equal to 2.1015 cm2. • the material of the first conductive layer is titanium and the conductive material of the second conductive layer is titanium nitride. • the thickness of the lower titanium nitride electrode is chosen between 10 and 200 nm.

[0015] The invention also relates to a resistive memory cell of the OxRAM type capable of being obtained by the method according to the invention.

[0016] At this stage, it is not possible to structurally characterize the OxRAM type resistive memory cell according to the invention other than by its production method. However, the manufacturing method according to the invention gives the OxRAM type memory cell according to the invention particularly advantageous endurance properties compared to those of the state-of-the-art OxRAM type resistive cells. BRIEF DESCRIPTION OF THE FIGURES

[0017] Other characteristics and advantages of the invention will emerge clearly from the description given below, for information purposes only and in no way limiting, with reference to the appended figures, among which:

[0018] [Fig.l] represents, in the form of a flowchart, the different stages of the method according to the invention,

[0019] [Fig.2], [Fig.3], [Fig.4], [Fig.5], [Fig.6], [Fig.7] and [Fig.8], represent the different stages of the process of [Fig.l],

[0020] [Fig.9] represents the different implantation profiles in the lower electrode of the OxRAM type memory cell according to the invention,

[0021] [Fig. 10] represents the BER error rate as a function of the number of cycles for different categories of OxRAM type memory cells including the memory cells according to the invention.

[0022] [Fig.l 1] and [Fig. 12] represent the evolution of the fraction of memory cells requiring one or more programming repetitions, in set and reset, depending on the number of cycles.

[0023] For clarity, identical or similar elements are identified by identical reference signs throughout the figures. DETAILED DESCRIPTION OF AN EMBODIMENT

[0024] [Fig.l] represents the flowchart illustrating the different steps of the method 100 for manufacturing an OxRAM memory cell according to the invention.

[0025] As shown in [Fig.2], the method 100 begins with a step 101 of forming a first electrode 1 formed by a titanium nitride layer corresponding to the lower electrode 1 of the OxRAM memory cell. This step therefore aims to form the lower electrode 1, for example on a substrate (substrate not shown in the figures). The lower electrode 1 has for example a thickness of between 10 and 200 nm, here 60 nm.

[0026] In practice, the lower electrode 1 is for example formed by reactive cathode sputtering in a vacuum deposition chamber.

[0027] Alternatively, the lower electrode 1 may be formed by chemical vapor deposition or according to a damascene structure.

[0028] The method 100 continues with a step 102 ([Fig.3]) corresponding to a first implantation of silicon Si atoms in the lower electrode 1.

[0029] According to this first implantation, the Si is implanted, in the TiN layer of the lower electrode 1, according to a determined profile 201 represented in [Fig.9]. The implantation dose DI and the implantation acceleration voltage VI are chosen to obtain an implantation on the surface of the lower electrode 1. The implantation dose DI of the silicon is strictly positive and strictly less than 0.7.1014 cm2; according to a preferred embodiment, the dose DI is equal to 0.5.1014cm 2. The acceleration voltage VI of the Si ions is between 0.3 kV and 0.7 kV; according to a preferred embodiment, the acceleration voltage is equal to 0.5 kV.

[0030] [Fig.9] shows in particular the different implantation profiles in the TiN layer corresponding to the lower electrode 1 whose upper surface is delimited by the dotted lines 200: the first implantation at dose DI and voltage VI is represented by profile 201 having a maximum concentration of Si at a depth of 1.2 nm from the upper surface of the lower electrode and a width of the implantation profile 201 at half the value of the maximum silicon implantation concentration equal to 1.5 nm. The implantation profiles represent a representative value of the implanted ions in a standardized manner (ratio of the volume concentration of implanted ions to the dose of implanted ions) as a function of the depth in the implanted layers.

[0031] The method 100 continues with a step 103 ([Fig.4]) corresponding to a second implantation of silicon Si atoms in the lower electrode 1.

[0032] According to this second implantation, the Si is implanted, in the TiN layer of the lower electrode 1, according to a determined profile 202 represented in [Fig.9] having a maximum concentration of Si at a depth of 2.2 nm from the upper surface of the lower electrode and a width of the implantation profile at half the value of the maximum silicon implantation concentration equal to 3.0 nm. The implantation dose D2 and the implantation acceleration voltage V2 of this second implantation are chosen to obtain a deeper implantation of the lower electrode 1. The silicon implantation dose D2 is strictly positive and strictly less than 0.6.1014 cm2; according to a preferred embodiment, the dose D2 is equal to 0.3.1014cm2. The acceleration voltage V2 of the Si ions is between 1 kV and 2 kV; according to a preferred embodiment, the acceleration voltage is equal to 1.5 kV.

[0033] At the end of steps 102 and 103, the overall profile resulting from the first and second implantations is illustrated by the reference 203 having a maximum silicon concentration Cmax at a depth of between 1 and 3 nm from the upper surface of the lower electrode (and preferably between 1 and 1.6 nm, and even more preferably between 1.1 and 1.5 nm, and here equal to 1.3 nm) and a width Wp of the implantation profile at half the value of the maximum silicon implantation concentration of between 1.6 nm and 2 nm (and preferably between 1.7 and 1.9 nm, and here equal to 1.86 nm). The area implanted by the first and two implantations of the lower electrode 1 is illustrated by the reference ZA in [Fig.4].

[0034] Then, the method continues with a step 104 ([Fig.5]) of depositing a layer of active material 2. This layer of active material 2 is formed on the lower electrode 1. The deposition of the layer of active material 2 is carried out in such a way that this layer has a substantially constant thickness at all points. In this description, the term "substantially constant" means a thickness not varying by more than 20%, preferably by more than 10%, and more preferably by more than 5%. Preferably here, the layer of active material 2 is based on amorphous hafnium dioxide HfO2. In the present description, the expression "based on" means that the layer concerned comprises more than 50% of the element mentioned after this expression (for example here, this means that the layer of active material 2 comprises more than 50% of hafnium dioxide). The layer of active material 2 here has a thickness of between 3 and 10 nm, for example here 5 nm.

[0035] In practice, the layer of active material 2 is deposited by an atomic layer deposition method (or ALD for “Atomic Layer Deposition” according to the commonly used acronym of Anglo-Saxon origin).

[0036] Alternatively, the layer of active material may be deposited by sputtering. Alternatively, the layer of active material may be deposited by a physical vapor deposition (PVD) method. Alternatively, the layer of active material may be deposited by an ion beam deposition (IBD) method.

[0037] As shown in [Fig.6], optionally, the method 100 continues with the step 105 of depositing a dielectric oxide layer 3. This dielectric oxide layer 3 is formed on the active material layer 2. The dielectric oxide layer 3 comprises, for example, a metal oxide or a semiconductor oxide. Preferably, it is an aluminum oxide A12O3. Alternatively, it may also be silicon dioxide SiO2.

[0038] The dielectric oxide layer 3 here has a thickness of between 0.3 and 1.5 nm, for example here 0.5 nm.

[0039] In practice, the dielectric oxide layer 3 is deposited by an atomic layer deposition (or ALD) method. Alternatively, the dielectric oxide layer 3 may be deposited by cathode sputtering. As a further variant, the dielectric oxide layer may be deposited by a physical vapor deposition (or PVD) method. As a further variant, the dielectric oxide layer may be deposited by an ion beam deposition (or IBD) method.

[0040] This dielectric oxide layer 3 deposited on the layer comprising the active material is positioned between the layer comprising the active material and the layer forming the upper electrode. This layer then acts as a diffusion barrier for oxygen vacancies (relative to the filament) and then improves the switching properties of the memory cell. In particular, this configuration makes it possible to improve the implementation of the write and erase cycles. As indicated previously, it is possible to dispense with this step 105 of depositing the dielectric oxide layer and to go directly from step 104 of depositing the layer of active material to step 106 of implanting silicon in the layer of active material.

[0041] As illustrated in [Fig.7], the method 100 continues with a step 106 of implanting silicon in the active layer formed by the dielectric oxide layer 3 in Al2O3 and the active material layer 2 in HfO2 formed in steps 104 and 105. The silicon is implanted according to a determined profile illustrated by the reference 204 in [Fig.9]. Thus, depending on whether the deposition 105 of the dielectric oxide layer takes place or not, the so-called active layer comprises either only the active material layer 2 or the stack of the active material layer and the dielectric oxide layer 3.

[0042] Advantageously, the implantation step 106 is implemented at an implantation acceleration voltage V3 of between 1.5 and 3.5 kV, here equal to 2.5 kV, for a D3 implantation dose of the order of 2.1015 cm 2.

[0043] As shown in [Fig.9], the implantation profile 204 extends into the already implanted zone ZA of the lower electrode 1.

[0044] The method finally continues with a step 107 of depositing a second electrode 4 forming the upper electrode ([Fig.8]). The upper electrode 4 is formed on the active layer formed as indicated previously from the active material layer 2 and the dielectric oxide layer 3. More particularly, the upper electrode 4 is deposited on the dielectric oxide layer 3.

[0045] The upper electrode 4 comprises a first conductive layer 41, for example made of titanium Ti and a second conductive layer 42, for example made of titanium nitride TiN. The step of depositing the upper electrode 4 therefore here comprises two sub-steps: a first sub-step of depositing the first conductive layer 41 and a second sub-step of depositing the second conductive layer 42.

[0046] The first conductive layer 41 is therefore first deposited on the dielectric oxide layer 3. The first conductive layer 41 is for example formed by cathode sputtering in a vacuum deposition chamber.

[0047] The first conductive layer 41 made of Ti has the particularity of being a layer suitable for creating oxygen vacancies in the active layer when this first conductive layer 41 is in contact with the active layer. According to the commonly used Anglo-Saxon term, the first conductive layer 41 is a layer of the “Oxygen scavenging layer” type. Since the mechanism for forming the conductive filament in the dielectric oxide layer 3 generally involves a reorganization of the oxygen vacancies within the dielectric oxide, the first conductive layer 41 makes it possible to facilitate the exchange of oxygen with the active layer. It will be noted that this first conductive layer 41 makes it possible to create oxygen vacancies in the active material layer 2 even when this first conductive layer is deposited on the dielectric oxide layer 3.In other words, the first conductive layer 41 creates oxygen vacancies in the active material layer 2 with or without deposition of the dielectric oxide layer 3.

[0048] Then, the second conductive layer 42 is deposited on the first conductive layer 41 formed. The second conductive layer 42 is for example formed by reactive cathode sputtering in a vacuum deposition chamber.

[0049] The first conductive layer 41 has a thickness of between 3 and 20 nanometers, here 5 nm. The second conductive layer 42 has a thickness of between 10 and 200 nanometers, here 150 nm.

[0050] At the end of this step 107, the OxRAM type memory cell 5 is obtained and is in the form of a stack of layers which extends along a z axis. The lower electrode 1, the active material layer 2, the dielectric oxide layer 3 and the upper electrode 4 form the different layers of this stack. The different layers extend parallel to each other (and parallel to a substrate, not shown, on which the memory cell 5 rests). The z axis is here perpendicular to the plane of the different layers of the stack forming the memory cell 5.

[0051] We will now show the advantages (in particular the better endurance performances) of the OxRAM type memory cell as represented in [Fig.8].

[0052] To do this, we will use an indicator, the error rate (or BER for "Bit Error Rate" according to the commonly used acronym of Anglo-Saxon origin) evaluated on a set of memory cells (here approximately 16,000 cells). By definition, this error rate corresponds to the percentage of memory cells in the set of memory cells considered which will not exhibit satisfactory properties.

[0053] In practice, this error rate is evaluated by representing the distributions of the memory cells of the set considered as a function of the resistance R (in Ohm Q) for the LRS and HRS states. The distributions of the memory cells are here considered in a cumulative manner (this is a cumulative distribution function or CDF for "Cumulative Distribution Function" according to the commonly used acronym of Anglo-Saxon origin). The error rate then corresponds to the point of intersection of the distributions representing the LRS and HRS states.

[0054] [Fig. 10] represents the BER error rate for 6 types of memory cells C1 to C6 as a function of the number of cycles performed on these cells, one cycle corresponding to a set and reset step. The C6 type cells are the OxRAM type memory cells according to the invention and as obtained at the end of the method 100 illustrated in [Fig.l] to 8. The other cells C1 to C5 have a stack of layers identical to the C6 type cells and differ from the latter only at the level of the doping of the lower electrode. Let us recall the implantation characteristics of the lower electrode of the C6 cells according to the invention: • First implantation at an accelerating voltage of 0.5 kV and an implantation dose of 0.5.1014cm2. • Second implantation at an accelerating voltage of 1.5 kV and an implantation dose of 0.3.1014cm2.

[0055] The Cl type cells have a lower electrode having undergone a single implantation with a low acceleration voltage (here 0.5 kV) and an implantation dose of 1.1014 cm2.

[0056] C2 type cells have a lower electrode that has undergone a double implantation: • First implantation at an accelerating voltage of 0.5 kV and an implantation dose of 1.1014cm 2. • Second implantation at an accelerating voltage of 1.5 kV and an implantation dose of 0.6.1014cm2.

[0057] C3 type cells have a lower electrode that has undergone double implantation: • First implantation at an accelerating voltage of 0.5 kV and an implantation dose of 1.1014cm2. • Second implantation at an accelerating voltage of 4 kV and an implantation dose of 7.1014cm2.

[0058] C4 type cells have a lower electrode that has undergone a double implantation: • First implantation at an accelerating voltage of 0.5 kV and an implantation dose of 2.1014cm2. • Second implantation at an accelerating voltage of 1.5 kV and an implantation dose of 1.2.1014cm2.

[0059] C5 type cells have a lower electrode that has not undergone any implantation.

[0060] As illustrated in [Fig. 10], apart from the C6 type cells according to the invention, the error rate of all the cell types C1 to C5 degrades with the number of cycles. Conversely, the memory cells according to the invention have an error rate which progressively decreases with the number of cycles until stabilizing from about a hundred cycles. The error rate of the memory cells according to the invention remains generally stable even after 10,000 cycles while it degrades, including for the C5 type cells having a non-implanted lower electrode.

[0061] Surprisingly, it is found that the simple implantation in Si of the lower electrode is not sufficient to improve the endurance performance of an OxRAM type memory cell since the cells of type C1 to C4 also have an implantation of the lower electrode and have degraded endurance performance. It is therefore appropriate that the particular conditions of implantation of the method according to the invention be carried out to obtain the endurance performance of the memory cell according to the invention, the intrinsic characteristics of which cannot be defined at this stage other than by its manufacturing method. It is also found that the error rate of the OxRAM type memory cells according to the invention begins to decrease with the number of cycles.It may therefore prove interesting to carry out a preliminary step (after its manufacture and before use) consisting of cycling the memory cell according to the invention over a number N of cycles (with N being an integer greater than or equal to 100) so as to obtain a lower error rate which then stabilizes.

[0062] Figures 11 and 12 illustrate another advantage of type memory cells OxRAM according to the invention. These figures are based on the so-called "intelligent programming" mechanism. This method consists of checking, after each operation, that the memory cell has the resistance level corresponding to the state in which it was programmed (set or reset). If this is not the case, the programming operation (set or reset) is repeated as many times as necessary and until a resistance level conforming to expectations is obtained: the necessary number of iterations is called repetition. More precisely, in [Fig.l 1] (set), the repetition consists of repeating the same set pulse. In [Fig. 12] (reset), the repetition consists of increasing the pulse voltage at each repetition.

[0063] Thus, [Fig. 1 1] shows the fraction of memory cells according to the invention C6 and memory cells without implantation of the lower electrode C5 that it was necessary to reprogram with a given number of repetitions (ranging from 2 to 5) for the set operations as a function of the number of cycles. As an example, we see that in the case where two repetitions are necessary, we have approximately one cell in 10,000 of type C5 or C6 that has been rewritten twice at the 100th cycle. [Fig. 12] shows the fraction of memory cells according to the invention C6 and memory cells without implantation of the lower electrode C5 that it was necessary to reprogram with a given number of repetitions (ranging from 2 to 5) for the reset operations as a function of the number of cycles.

[0064] In the case of reset operations ([Fig. 12]), it is observed that the more cycling operations are carried out with the C6 memory cells according to the invention, the less reprogramming pulses are needed. Conversely, the C5 type memory cells with an undoped lower electrode require more repetitions beyond a hundred cycles. This first result confirms the very good endurance of the memory cells according to the invention. Indeed, the fact of “stressing” the memory cells less due to the lower number of repetitions required, results in better endurance of the memory cells.

[0065] In the case of set operations ([Fig. 11]), a certain stability is observed, confirming once again the endurance performance of the memory cells according to the invention.

Claims

Claims

1. A method of manufacturing a resistive memory cell of the OxRAM type, comprising the following steps: - forming a lower electrode made of titanium nitride, - first implantation of silicon atoms in the lower electrode with a first silicon implantation dose and a first implantation acceleration voltage, said first silicon implantation dose being strictly positive and strictly less than 0.7.1014cm 2, - second implantation of silicon atoms in the lower electrode with a second silicon implantation dose and a second implantation acceleration voltage strictly greater than the first implantation acceleration voltage, said second silicon implantation dose being strictly positive and strictly less than 0.6.1014 cm2, the first and second acceleration voltages being chosen to have an implantation profile following the first and second implantation having a maximum concentration of silicon at a depth of between 1 and 3 nm from the upper surface of the lower electrode, - deposition of an active layer on the implanted lower electrode, - deposition of an upper electrode on the active layer.

2. The method of claim 1 wherein the first and second accelerating voltages are chosen to have an implantation profile following the first and second implantation having a maximum silicon concentration at a depth of between 1 and 1.6 nm from the upper surface of the lower electrode and a width of the implantation profile at half the value of the maximum silicon implantation concentration of between 1.6 nm and 2 nm.

3. The method of claim 2 wherein the first and second acceleration voltages are chosen to have an implantation profile following the first and second implantation having a maximum silicon concentration at a depth of between 1.1 and 1.5 nm from the upper surface of the lower electrode and an implantation profile width at half the value of the maximum silicon implantation concentration of between 1.7 nm and 1.9 nm.

4. Method according to one of the preceding claims, characterized in that the deposition of the upper electrode on the active layer comprises: - The deposition of a first conductive layer, in contact with the active layer and being chosen to create oxygen vacancies in the active layer, and - The deposition of a second conductive layer arranged on the first conductive layer.

5. A method according to one of the preceding claims, wherein the material of the first conductive layer is titanium and the conductive material of the second conductive layer is titanium nitride.

6. Method according to one of the preceding claims in which the first acceleration voltage is between 0.3 kV and 0.7 kV and the second acceleration voltage is between 1 kV and 2 kV.

7. Method according to one of the preceding claims in which the first acceleration voltage is equal to 0.5 kV and the second acceleration voltage is equal to 1.5 kV.

8. Method according to one of the preceding claims in which the first silicon implantation dose is equal to 0.5.1014cm2 and the second silicon implantation dose is equal to 0.3.1014 cm2.

9. Method according to one of the preceding claims in which the deposition of the active layer on the implanted lower electrode comprises the following steps: - deposition of a layer of active material on the implanted lower electrode, - deposition of a layer of dielectric oxide on the layer of active material, - implantation of silicon atoms through the layer of dielectric oxide, the implantation dose and the implantation acceleration voltage being chosen so that the silicon atoms are implanted at least partly in the layer of active material.

10. Method according to the preceding claim in which the active material is based on hafnium dioxide.

11. A method according to claim 9 or 10 wherein the dielectric oxide is based on aluminum oxide.

12. Method according to one of claims 6 to 8, in which the step of implanting silicon through the dielectric oxide layer is carried out at an implantation acceleration voltage of between 1.5 and 3.5 kilovolts, and preferably equal to 2.5 kV, and a silicon implantation dose of between 1015cm2 and 5.1015cm2, and preferably equal to 2.1015cm2.

13. Method according to one of the preceding claims, characterized in that the thickness of the lower titanium nitride electrode is chosen between 10 and 200 nm.

14. OxRAM type memory cell obtained by the method according to any one of claims 1 to 13.

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