Fabrication of a POI structure with a highly uniform piezoelectric layer

Abstract

The present invention relates to a method for manufacturing a piezoelectric structure on an insulator (POI), comprising providing a donor substrate including a piezoelectric substrate, wherein the piezoelectric substrate comprises or is composed of either lithium tantalate or lithium niobate, transferring a piezoelectric layer from the piezoelectric substrate to a target substrate, and polishing the transferred piezoelectric layer on the target substrate with a chemical-mechanical polishing suspension (CMP), wherein the CMP suspension consists of an aqueous suspension of amorphous silicon with a weight percentage of amorphous silicon in the range of 4 to 18. Figure 2 is shown in the abstract.

Description

Title of the invention: Fabrication of a POI structure with a highly uniform piezoelectric layer

[0001] The present invention relates to the method of manufacturing piezoelectric on insulator (POI) type structures, in particular POI structures usable for the manufacture of microelectronic, micromechanical and photonic devices.

[0002] In the fields of microelectronics, micromechanics, and photonics, POI structures are of increasing importance, for example, due to their superior sensitivity and information propagation properties. For instance, sensors such as surface acoustic wave (SAW) sensors or body acoustic wave (BAW) sensors, which use the piezoelectric effect to convert an electrical signal into a mechanical / acoustic wave, offer particularly advantageous options due to a wide variety of measurable ambient parameters, including, for example, temperature, pressure, stress, and torque.

[0003] A typical POI structure comprises a layer of piezoelectric material, in particular a single-crystal material such as, for example, lithium niobate (LiNbO3) or lithium tantalate (LiTaO3), on a support substrate made, for example, of silicon. Various methods for forming a thin layer of piezoelectric material on the support substrate are known in the art. The application of Smart Cut™ technology has proven particularly advantageous. According to this technology (see, for example, WO 2020 / 200986 Al), light species are implanted into a piezoelectric substrate formed on a support substrate to create a weakened region in the piezoelectric substrate, and then the piezoelectric substrate is bonded to a target substrate. By means of fracturing at the weakened region, the thin layer of piezoelectric material can be obtained on the support substrate.The transferred piezoelectric material layer is subjected to an annealing process and then to a polishing process, in particular by means of chemical-mechanical polishing, CMP, with the aim of improving the crystalline quality and obtaining the desired thickness uniformity of a single-domain layer of piezoelectric material with substantially all dipole moments aligned parallel to each other in a given direction.

[0004] However, despite recent technical progress, there is a risk that the uniformity of thickness obtained from the transferred piezoelectric material layer may not be high enough to meet the requirements of current applications.

[0005] Therefore, an object of the present invention is to provide a manufacturing technique for a POI structure (based on Smart Cut™ technology) with high thickness uniformity of the piezoelectric material layer.

[0006] The present invention achieves this goal by providing a method for manufacturing a piezoelectric structure on an insulator, POI, comprising the steps of

[0007] provide a donor substrate comprising a piezoelectric substrate, wherein the piezoelectric substrate comprises or is made up of one of lithium tantalate (LiTaO3) and lithium niobate (LiNbO3);

[0008] transfer a piezoelectric layer from the piezoelectric substrate to a target substrate (for example, a silicon substrate); and

[0009] polish the piezoelectric layer transferred to the target substrate with a chemical-mechanical polishing suspension, CMP, in which the CMP suspension consists of an aqueous suspension of amorphous silicon with a weight percentage of amorphous silicon in the range of 4 to 18.

[0010] The polishing step may be preceded by an annealing step to increase crystalline quality and consolidate the bond between the piezoelectric layer and the target substrate. The amorphous silicon used for the CMP suspension may comprise or consist of precipitated amorphous silicon particles with diameters in the range of 40 to 60 nm.

[0011] It is known in the prior art to polish the transferred piezoelectric layer in order to remove a multi-domain top layer comprising a plurality of regions exhibiting different polarities and to increase surface quality (reduce roughness) and thickness uniformity. However, in the prior art, a CMP suspension consisting of an aqueous suspension of amorphous silicon with a much higher weight percentage of amorphous silicon, namely in the range of 25 to 35, is used for the process of polishing the transferred piezoelectric layer. The inventors of the present invention have surprisingly discovered that polishing the transferred piezoelectric layer with a significantly lower concentration of amorphous silicon in the CMP suspension leads to better polishing results in terms of the thickness uniformity of the single-domain piezoelectric layer ultimately obtained.

[0012] Other parameters of the entire manufacturing process can be chosen in a manner that is customary and known to those skilled in the art (see, however, the description below). Depending on the actual choice of the piezoelectric material and the values ​​of the other parameters, a weight percentage of amorphous silicon in the range of 4 to 13, particularly 5 to 7, may be advantageous with regard to the resulting uniformity of thickness of the ultimately obtained transferred piezoelectric layer.

[0013] According to one embodiment, the step of providing the donor substrate (pseudodonor, PSD) comprises bonding a block of piezoelectric material to a support substrate (manipulator) via an adhesive layer, grinding and polishing the block of piezoelectric material to obtain the piezoelectric substrate, and implanting a species (e.g., hydrogen) into the piezoelectric substrate to obtain a weakened layer within the piezoelectric substrate. Thus, a suitable donor substrate for providing a high-quality piezoelectric layer over the weakened layer can be reliably fabricated. Bonding the block of piezoelectric material to the support substrate can be facilitated by a dielectric adhesive layer, for example, a photo(UV) polymer layer or a layer made of or comprising silicon dioxide and / or silicon nitride.

[0014] The step of transferring the piezoelectric layer to the target substrate may include bonding the donor substrate to the target substrate (on the side of the piezoelectric substrate) and fracturing the piezoelectric substrate at the weakened layer in an annealing process. Thus, the piezoelectric layer can be reliably transferred to the target substrate without excessively heavy defects. However, further post-treatment (annealing and polishing) is still necessary, as described above. It should be noted that naturally occurring silicon oxide may be present between the transferred piezoelectric layer and the target substrate. Furthermore, a dielectric bonding layer may be formed on or above a surface of the target substrate before transferring the piezoelectric layer to that surface.This dielectric assembly layer can be made of or comprise silicon oxide and / or silicon nitride, or a stack of layers composed of these materials. Furthermore, depending on the actual application, a charge-trapping layer can be formed on or above a surface of the target substrate prior to the transfer of the piezoelectric layer to that surface. The charge-trapping layer can be made of or comprise polycrystalline silicon.

[0015] For the polishing process, the target substrate with the transferred piezoelectric layer is positioned on a rotating head and brought into contact with a rotating polishing pad. According to particular embodiments, the head is rotated at 80 to 120 revolutions per minute (rpm), and the polishing pad is rotated in the same direction as the head at a different speed relative to the head, in the range of 90 to 130 rpm. These parameter ranges can prove advantageous in terms of the uniformity of thickness of the resulting polished piezoelectric layer.

[0016] According to another embodiment, the insert pressure applied to the target substrate to press it against a polishing pad is not greater than 20.68 kPa (3 psi) or is less than 18.96 kPa (2.75 psi), for example in the range of 17.24 kPa (2.5 psi) to 20.68 kPa (3 psi). For example, the ratio of the insert pressure to the The ring pressure used to hold the target substrate in place in a ring retainer during the polishing process is in the range of 1:2 to 5:3. These parameter ranges can prove advantageous in terms of the uniformity of thickness of the resulting polished piezoelectric layer, especially in combination with the parameter ranges mentioned above.

[0017] According to another embodiment, the flow rate of the CMP suspension is less than 250 ml / minute, 200 ml / minute, or 150 ml / minute, or is in the range of 150 ml / minute to 250 ml / minute. These parameter ranges can prove advantageous in terms of the uniformity of thickness of the resulting polished piezoelectric layer, particularly in combination with the parameter ranges mentioned above.

[0018] Furthermore, a POI structure is provided, comprising a piezoelectric layer formed on or above a target substrate and obtainable by the process according to some of the examples described above, wherein the piezoelectric layer has a thickness uniformity (thickness range across the layer diameter) of less than 50 nm, in particular less than 20 nm. In addition, a microelectronic, micromechanical, or photonic device, or a microelectromechanical system (MEMS), comprising such a POI structure is provided.

[0019] Additional features and advantages of the present invention will be described with reference to the drawings. In the description, reference is made to the accompanying drawings, which are intended to illustrate preferred embodiments of the invention. It should be understood that such embodiments do not represent the full scope of the invention.

[0020] [Fig.1] illustrates the steps of a manufacturing process for a POI structure according to an embodiment of the present invention.

[0021] [Fig.2] illustrates the technical effect of obtaining a piezoelectric layer highly uniform resulting from a manufacturing process of a POI structure according to an embodiment of the present invention.

[0022] A method for manufacturing a POI structure is provided herein, comprising a target substrate on which a piezoelectric layer with high thickness uniformity is formed. The high thickness uniformity results from a polishing step performed with a relatively highly dilute aqueous suspension of amorphous silicon. The method utilizes Smart Cut™ technology.

[0023] Figure 1 illustrates steps in a process for manufacturing a POI structure according to an embodiment of the present invention. The process is similar to a process described in WO 2020 / 200986 A1, but differs from the latter in the inventive method of polishing the transferred piezoelectric layer.

[0024] As shown in step i) of [Fig. 1], a donor substrate 1 is provided, which includes a piezoelectric substrate 1a formed on a support (manipulator) substrate 1b. The piezoelectric substrate 1a is made of lithium tantalate (LiTaO3) or lithium niobate (LiNbO3). The support substrate 1b can be made of a material (or a plurality of materials) having a coefficient of thermal expansion close to that of a target substrate 7, i.e., the coefficient of thermal expansion of the support substrate 1b differs from that of the target substrate 7 by less than the difference between the coefficient of thermal expansion of the piezoelectric substrate 1a and that of the target substrate 7. The support substrate 1b and the target substrate 7 can have identical coefficients of thermal expansion, and the two substrates can, for example, be made of or comprise silicon.Furthermore, the two substrates can have similar thicknesses.

[0025] To obtain the donor substrate 1, a solid block of piezoelectric material can first be attached to the support substrate 1b, for example using a molecular bonding technique. Bonding can be facilitated by a dielectric bonding (adhesion) layer (not shown in [Fig. 1]), for example, a photo(UV) polymer layer or a layer made of or comprising silicon oxide and / or silicon nitride. The bonding process may include the application of a low-temperature heat treatment (for example, at a temperature between 50 and 300°C, typically 100°C) to sufficiently increase the bonding energy to allow the subsequent thinning step. The piezoelectric substrate 1a is then formed by thinning, for example, by chemical-mechanical grinding and / or polishing.

[0026] The thinning step is carried out such that the piezoelectric substrate la has a sufficiently small thickness to reduce the stresses generated during the heat treatment applied in a subsequent processing step. On the other hand, the thickness must be sufficient to provide the piezoelectric layer 3 that is to be transferred to the target substrate 7, or to provide a plurality of such layers that are to be transferred one after the other in multiple transfer steps (after respective regeneration of the donor substrate 1) to respective target substrates. The thickness of the piezoelectric substrate la can, for example, be between 5 and 400 pm, for example, 20 pm or 100 pm.

[0027] Hydrogen (optionally supplemented with helium) is implanted ii) into the piezoelectric substrate through the exposed surface 4 to generate a weakened layer 2 which marks the separation of the piezoelectric layer 3 from the remaining portion 5 of the donor substrate 1. The nature and dose of the implanted species and the implantation energy can be chosen according to the thickness of the piezoelectric layer 3 which is to be transferred to the target substrate 7 and the physico- chemical properties of the piezoelectric substrate. For example, for a lithium tantalate substrate, a dose of hydrogen ions between 1016 and 51017 at / cm2 with an energy between 30 keV and 300 keV can be implanted to delimit the piezoelectric layer 3 with a thickness of 200 nm to 2000 nm, for example.

[0028] According to the process illustrated in [Fig. 2], the implantation step ii) is followed by the step of attaching iii) the donor substrate 1 to the support substrate 7 on the side of the piezoelectric substrate la by molecular adhesion and / or electrostatic bonding. A dielectric assembly layer 7b may be provided between the piezoelectric substrate la of the donor substrate 1 and the target substrate 7. The dielectric assembly layer 7b may comprise an oxide and may be made of or comprise silicon oxide and / or silicon nitride or a stack of layers composed of these materials. In addition, a charge-trapping layer, for example made of or comprising polycrystalline silicon, may be formed on or above the target substrate 7 in order to improve its electrical resistivity if this is desired by a real-world application.

[0029] The piezoelectric layer 3 is then detached from the remaining portion 5 of the donor substrate 1 to obtain iv) a POI structure 9 comprising the target substrate 7, the dielectric assembly layer 7b (if applicable), and the piezoelectric layer 3. Detachment at the weakened layer 2 is facilitated by heat treatment in a temperature range of approximately 100°C to 600°C to enable the transfer of the piezoelectric layer 3 to the target substrate 7. Alternatively, or in addition, detachment at the weakened layer 2 may be facilitated by the application of a blade or jet of gaseous or liquid fluid, or any other mechanical force applied to the weakened layer 2.

[0030] Post-treatment of the transferred piezoelectric layer 3 is necessary to obtain a transferred piezoelectric layer 3 with satisfactory crystalline and single-domain surface quality (reduced roughness) and thickness uniformity as required by real-world applications. The post-treatment includes a heat treatment v) of the piezoelectric layer 3, for example at approximately 500°C in a neutral atmosphere or an atmosphere containing oxygen. This heat treatment addresses crystalline defects present in the piezoelectric layer and strengthens the bond between the piezoelectric layer 3 and the target substrate 7.However, the heat treatment causes diffusion of the hydrogen contained in the piezoelectric layer 3, particularly in its upper part (with a thickness of approximately 50 nm or less, for example), and consequently the generation of a plurality of ferroelectric domains, giving the upper part a multi-domain character. In fact, the hydrogen implanted in the piezoelectric substrate during the piezoelectric layer definition step. The layer 3 above the weakened layer 2 is distributed within this substrate according to a profile exhibiting a concentration peak at the weakening plane 2. After fracturing at the weakened layer 2, the piezoelectric layer 3 transferred to the target substrate 7 therefore exhibits a high hydrogen concentration, and the heat treatment leads to the generation of multiple domains, i.e., a plurality of regions with different polarities. The performance of devices intended to be formed on / within the piezoelectric layer 3 would be significantly affected by such multiple domains.

[0031] In order to eliminate the multiple upper domains and increase the surface quality and thickness uniformity of the transferred piezoelectric layer 3, the post-treatment includes polishing the exposed surface of the piezoelectric layer 3 (see step vi) in [Fig. 1]. For example, 100 to 300 nm of the upper part of the piezoelectric layer 3 can be removed by the polishing process to achieve a predetermined target thickness, for example of about 600 nm.

[0032] According to the invention, the piezoelectric layer 3 is polished by CMP using a relatively highly dilute CMP suspension. Typically, an aqueous suspension of amorphous silicon with a weight percentage of 25 to 35% of amorphous silicon is used for the post-treatment CMP step following thermal annealing of the transferred piezoelectric layer. According to the invention, an aqueous suspension of amorphous silicon with a weight percentage of amorphous silicon in the range of only 4 to 18%, particularly in the range of 4 to 13%, and more particularly in the range of 5 to 7%, is used as the CMP suspension. Other parameters of the entire manufacturing process can be chosen in a manner known to those skilled in the art.A single-domain piezoelectric layer, in which substantially all dipole moments are aligned parallel to each other in a given direction, can therefore be formed on the target substrate 7, providing both the required thickness uniformity and surface and crystalline qualities.

[0033] For the polishing process, the target substrate 7 with the transferred piezoelectric layer 3 is positioned on a rotating head and brought into contact with a rotating polishing pad. It is preferable to use a single-zone head with a single retaining ring device rather than a multi-zone head with several retaining ring devices applying varying pressures. For example, during the polishing process, the head is rotated at 80 to 120 revolutions per minute (rpm) and the polishing pad is rotated in the same direction as the head at a different speed compared to the head, in the range of 90 to 130 rpm. For example, the head can be rotated at 75 rpm, and the polishing pad can be rotated at 100 rpm. The speed of a The reconditioning brush can be chosen to be similar to that of the polishing head or pad.

[0034] The pad pressure applied to the target substrate to press it against the polishing pad can be chosen to be no more than 20.68 kPa (3 psi) or less than 18.96 kPa (2.75 psi), for example, in the range of 17.24 kPa (2.5 psi) to 20.68 kPa (3 psi). For example, the ratio of the pad pressure to the ring pressure used to hold the target substrate in place in a ring retainer during the polishing process is in the range of 1:2 to 5:3. The flow rate of the CMP suspension can be chosen to be less than 250 ml / minute, 200 ml / minute, or 150 ml / minute, or can be chosen in the range of 150 ml / minute to 250 ml / minute.

[0035] The CMP suspension used according to the invention can be prepared by diluting a commercially available CMP suspension. For example, Klebosol® 30HB50 can be diluted with water to obtain a CMP suspension with a weight percentage of amorphous silicon in the range of 4 to 18, particularly in the range of 4 to 13, and more particularly in the range of 5 to 7. Klebosol® 30HB50 has 25 to 35% amorphous silicon by weight, and an average diameter of precipitated amorphous silicon particles of 50 nm. Assuming a 35% weight dilution of amorphous silicon by adding 1 part water to 1 part Klebosol® 30HB50 (1:1 dilution), the result is a CMP suspension containing 17.5% amorphous silicon by weight.A 1:4 dilution of Klebosol® 30HB50 containing 25% by weight of amorphous silicon gives a CMP suspension containing 5% by weight of amorphous silicon, and a 1:4 dilution of Klebosol® 30HB50 containing 35% by weight of amorphous silicon gives a CMP suspension containing 7% by weight of amorphous silicon.

[0036] Figure 2 illustrates examples of results for the thickness uniformity obtained (thickness range) of the piezoelectric layer of the POI structure after CMP polishing of the piezoelectric layer made of lithium tantalate with a CMP suspension obtained by diluting Klebosol® 30HB50 with dilutions from 1:1 to 1:6. The abscissa represents the diameter of the piezoelectric layer in mm and the ordinate represents the thickness of the piezoelectric layer (LTO) in nm. The thickness profiles are shown for dilutions of Klebosol® 30HB50 with water of 1:1, 1:2, 1:3, 1:3.5, 1:4, 1:5 and 1:6. Other polishing parameters were chosen within the ranges described above.

[0037] It can be seen that for dilutions of 1:5 and 1:6, edge elimination is considerably increased, resulting in a piezoelectric layer thickness range of 147.844 nm and 180.313 nm, respectively. However, for the other dilutions, at least quite satisfactory results could be obtained. The range The observed thickness across the layer diameter for the 1:1 dilution is 61.879 nm. Excellent results can be obtained for the other dilutions presented. The observed thickness range across the layer diameter for the 1:2 dilution is 36.82 nm, the observed thickness range across the layer diameter for the 1:3 dilution is 24.573 nm, the observed thickness range across the layer diameter for the 1:3.5 dilution is 23.186 nm, and the observed thickness range across the layer diameter for the 1:4 dilution is 21.849 nm.

Claims

Demands

1. A method for manufacturing a piezoelectric structure on an insulator, POI (9), comprising the steps of providing a donor substrate (1) comprising a piezoelectric substrate (la), wherein the piezoelectric substrate (1) comprises or is made up of one of lithium tantalate and lithium niobate; transferring a piezoelectric layer (3) from the piezoelectric substrate to a target substrate (7); and polishing the piezoelectric layer (3) transferred to the target substrate (7) with a chemical-mechanical polishing suspension, CMP, wherein the CMP suspension consists of an aqueous suspension of amorphous silicon with a weight percentage of amorphous silicon in the range of 4 to 18.

2. The method according to claim 1, wherein the CMP suspension consists of an aqueous suspension of amorphous silicon with a weight percentage of amorphous silicon in the range of 4 to 13, in particular 5 to 7.

3. The method according to claim 1 or 2, wherein the amorphous silicon comprises or is made up of precipitated amorphous silicon particles with diameters in the range of 40 to 60 nm.

4. The method according to any one of the preceding claims, wherein the donor substrate supply step (1) comprises bonding a block of piezoelectric material to a support substrate (1b) via a bonding layer, grinding and polishing the block of piezoelectric material to obtain the piezoelectric substrate (la) and implanting a species into the piezoelectric substrate (la) to obtain a weakened layer (2) in the piezoelectric substrate (la).

5. The method according to claim 4, wherein the step of transferring the piezoelectric layer (3) to the target substrate (7) comprises bonding the donor substrate (1) to the target substrate (7) and fracturing the piezoelectric substrate (1a) at the weakened layer (2).

6. The method according to any one of the preceding claims, further comprising performing an annealing treatment of the piezoelectric layer (3) transferred to the target substrate (7) before polishing the piezoelectric layer (3).

7. The method according to any one of the preceding claims, wherein the polishing comprises rotating the target substrate between 80 and 120 revolutions per minute and a polishing pad in the same direction as the head and in contact with the piezoelectric layer (3) at a different speed relative to the head of 90 to 130 revolutions per minute.

8. The method according to any one of the preceding claims, wherein the polishing comprises applying pad pressure to the target substrate (7) to press it against a polishing pad, which is not greater than 20.68 kPa or is less than 18.96 kPa, in particular in the range of 17.24 kPa to 20.68 kPa.

9. The method according to any one of the preceding claims, wherein the polishing comprises applying the CMP suspension to a polishing pad at a flow rate of less than 250 ml / minute or 200 ml / minute or 150 ml / minute, or in the range of 150 ml / minute to 250 ml / minute.

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