Vertical interconnect structure and method of manufacturing the same, packaged chip, and chip packaging method

By first forming conductive pillars on the substrate and then wrapping them with an insulating support layer, the problems of uneven vias and heat-affected zones caused by etching and laser ablation are solved. This method increases the length-to-diameter ratio and density of conductive pillars, thereby improving the reliability and process efficiency of chip packaging.

CN114334876BActive Publication Date: 2026-07-03HUAWEI TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
HUAWEI TECH CO LTD
Filing Date
2020-12-10
Publication Date
2026-07-03

AI Technical Summary

Technical Problem

When fabricating vertical interconnect structures, the unevenness of vias and heat-affected zones caused by etching and laser ablation processes affect the reliability of packaged chips. Existing processes are cumbersome and inefficient.

Method used

First, conductive pillars are formed on the substrate, and then an insulating support layer is wrapped around them to avoid the fabrication of through-holes. The conductive pillars are gradually lengthened using a photoresist layer as a mask. An insulating support layer is formed using materials such as amorphous silicon, and the thickness is controlled by deposition and polishing. A barrier layer and a dielectric layer are combined to isolate the conductive pillars and the insulating support layer.

Benefits of technology

The length-to-diameter ratio of the conductive pillars was increased, the minimum spacing between the conductive pillars was reduced, the distribution density of the conductive pillars was enhanced, the adverse effects of through-hole technology were avoided, and the reliability of the packaged chip and the process were improved and simplified.

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Abstract

This application discloses a vertical interconnect structure and its manufacturing method, a packaged chip, and a chip packaging method, belonging to the field of chip packaging technology. The method includes first forming conductive pillars on a first surface of a substrate, then forming a first insulating support layer on the first surface. The conductive pillars are located within the first insulating support layer, and the upper surface of the conductive pillars away from the substrate is not covered by the first insulating support layer. Finally, the substrate is removed. The first insulating support layer is formed of at least one material selected from amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, boron nitride, silicon dioxide, aluminum nitride, and diamond. By first forming conductive pillars on the substrate and then forming the first insulating support layer that encloses the conductive pillars, it is not necessary to create through-holes to accommodate the conductive pillars on the first insulating support layer through etching or laser ablation processes, thus avoiding the adverse effects of etching and laser ablation processes.
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