COMPUTER SYSTEM CONFIGURED TO SHARE DATA BETWEEN TWO PROCESSORS

Abstract

According to one aspect, a computer system is proposed comprising: - a first processor, called the sending processor (CPU1), and a second processor, called the receiving processor (CPU2), - a first memory, called the original memory (MEM1), associated with the sending processor (CPU1), and a second memory, called the destination memory (MEM2), associated with the receiving processor, said original memory being configured to store data that may be intended for the receiving processor, - a transmission module (TRM) controlled by the sending processor (CPU1) and by the receiving processor (CPU2), the transmission module (TRM) being configured to transfer a message (MSG) comprising data intended for the receiving processor from the original memory (MEM1) to the destination memory (MEM2). Figure for abstract: Figure 1

Description

Title of the invention: COMPUTER SYSTEM CONFIGURED TO SHARE DATA BETWEEN TWO PRO CESSORS

[0001] Embodiments and implementations relate to computer systems, and more particularly to the communication of data between several processors of a computer system.

[0002] Some computer systems have several processors (also referred to as “cores” or “Central Processing Units”).

[0003] These processors can be programmed to exchange data. The exchange of data between processors is also referred to as "inter-processor communication" (or by the acronym "IPC" from the English "Inter-Processor Communication" (IPC)).

[0004] The exchange of data between processors can be useful for various applications so that the processors can coordinate or collaborate. For example, a first processor can be used to control data acquisition by a sensor and a second processor can be used to process the acquired data. In this case, the data acquired using the first processor is made available to the second processor so that the latter can process it.

[0005] In particular, the processors can exchange data via a shared memory. The use of a shared memory allows the processors to access data stored in the same area of ​​the shared memory. This shared memory therefore makes it possible to exchange data between the processors.

[0006] This area of ​​shared memory is defined during a development phase of the computer programs implemented by the two processors. More particularly, it is appropriate to define the shared memory in linker files for the two processors. Thus, it is appropriate to agree on shared memory from the development of the computer programs implemented by two processors. Furthermore, it is also important to define from this development the size of the shared memory areas receiving the shared data.

[0007] The use of a shared memory also has the disadvantage of involving a copy of the shared data. In particular, the sending processor copies the data from an original memory into the shared memory. The receiving processor can then use and then erase the data copied into the shared memory or copy them into another memory in order to receive new data in the same shared memory area.

[0008] Furthermore, the transfer of the shared data is controlled directly by the sending processor and the receiving processor. Thus, the sending processor and the receiving processor cannot process other tasks while they control the transfer of the shared data.

[0009] It is also important to prevent the sending processor from writing new data into the shared memory before the receiving processor has read the previous data. To synchronize, the sending processor and the receiving processor then issue interrupts. In particular, the sending processor is configured to generate an interrupt to inform the receiving processor that new data is available in the shared memory. The receiving processor is configured to generate an interrupt once it has read the shared data. This management of interrupts by the processors also does not allow the processors to be put into a reduced consumption mode during the transfer of data.

[0010] There is therefore a need to propose a solution to simplify data communication between several processors.

[0011] According to one aspect, there is provided a computer system comprising: - a first processor, called the sending processor, and a second processor, called the receiving processor, - a first memory, called the original memory, associated with the sending processor, and a second memory, called the destination memory, associated with the receiving processor, said original memory being configured to store data that may be intended for the receiving processor, - a transmission module controlled by the sending processor and by the receiving processor, the transmission module being configured to transfer a message comprising data intended for the receiving processor from the source memory to the destination memory.

[0012] The computer system makes it possible to use a transmission module to transfer messages from an originating memory, associated and defined by a transmitting processor, to a destination memory, associated and defined by a receiving processor.

[0013] Such a computer system makes it possible to avoid using shared memory between two processors. It is therefore not necessary to define a static area of ​​memory to be shared for the two processors. Each processor can define its own memory area in which to store the message without agreeing with the other processor.

[0014] Furthermore, such a computer system has the advantage of allowing the processor sender and recipient processor to perform other tasks as soon as the message transfer begins. In fact, the transmission module takes care of the message transfer entirely. The sender processor and the recipient processor therefore do not carry out the message transfer themselves. The sender processor and the recipient processor can also switch to a low-power mode until the message transfer is complete.

[0015] Advantageously, the transmission module is a direct memory access controller.

[0016] In an advantageous embodiment, the transmission module comprises a first register controlled by the transmitting processor and configured to authorize a transfer of said message by said transmission module.

[0017] Preferably, the transmission module comprises a second register controlled by the transmitting processor and configured to store an original address pointing to an area of ​​the original memory comprising the data of the message to be transferred.

[0018] Thus, the transmitting processor can dynamically define its own memory area in which to store the data to be transferred.

[0019] In an advantageous embodiment, the transmission module comprises a third register controlled by the destination processor and configured to store a destination address pointing to an area of ​​the destination memory intended to receive the data of said message to be transferred.

[0020] Thus, the recipient processor can dynamically define its own memory area in which to store the data of the transmitted message.

[0021] Preferably, the transmission module comprises a fourth register controlled by the recipient processor and configured to store a length of the message to be transferred.

[0022] Advantageously, the sending processor is configured to read access the fourth register and to start the transfer of the message by the transmission module once the length of the message has been defined by the receiving processor in the fourth register. This makes it possible to carry out communication between the sending processor and the receiving processor using an already existing direct memory access controller, without modifying the computer system.

[0023] Preferably, the sending processor is configured to detect that the length of the message has been defined by the receiving processor when the value stored in the fourth register is different from zero.

[0024] In an advantageous embodiment, the transmission module comprises a synchronization register, the destination processor being configured to store information in the synchronization register making it possible to indicate that the destination memory is ready to receive the message, the transmission module being configured to generate an interrupt signal to the sending processor when the synchronization register indicates that the destination memory is ready to receive the message.

[0025] Such an interrupt signal makes it possible to simply inform the sending processor that the receiving processor is ready for the transfer of the message. In addition, the sending processor can enter a low-power mode or perform other tasks while waiting to receive the interrupt signal.

[0026] Preferably, the transmission module comprises an access control register configured to define access authorizations to the registers of the transmission module for the sending processor and for the receiving processor.

[0027] Advantageously, the transmission module is configured to generate a first interrupt signal intended for the recipient processor when a transfer of a message intended for the recipient processor is completed.

[0028] Preferably, the transmission module is configured to generate a second interrupt signal intended for the sending processor when a transfer of a message intended for the receiving processor is completed.

[0029] Advantageously, the transmission module comprises a fifth register configured to store contextual information indicating the end of transfer of the message, the recipient processor being configured to clear this fifth register in order to acknowledge the reception of a new message and to allow the transmission module to generate new interrupt signals during a next message transfer.

[0030] In an advantageous embodiment, the transmission module is configured to decrement during the transfer the value stored in the fourth register and initialized to the length of the message, the first interrupt signal and the second interrupt signal being generated when the value stored in the fourth register reaches zero.

[0031] Advantageously, the address stored in the second register of the transmission module points to a linked list in the original memory comprising a succession of addresses pointing to different memory areas comprising data intended for the destination processor, the transmission module being configured to successively transmit messages comprising the data of the different memory areas pointed to by said linked list.

[0032] According to another aspect, there is provided a method implemented by a computer system comprising: - a first processor, called the sending processor, and a second processor, called the receiving processor, - a first memory, called the original memory, associated with the transmitting processor, and a second memory, called destination memory, associated with the recipient processor, said original memory being configured to store data that may be intended for the recipient processor, - a transmission module, the method comprising: - a control of the transmission module by the sending processor and by the receiving processor in order to initialize a transfer of a message comprising data intended for the receiving processor from the source memory to the destination memory, then - a transfer of said message by the transmission module from the source memory to the destination memory.

[0033] Other advantages and characteristics of the invention will appear on examining the detailed description of the embodiment and implementation, which is in no way limiting, and the appended drawings in which:

[0034] [Fig.l] ;

[0035] [Fig.2] ;

[0036] [Fig.3]

[0037] [Fig.4] ;

[0038] [Fig.5] ; and

[0039] [Fig.6] schematically illustrate methods of implementation and realization of the invention.

[0040] [Fig.l] illustrates an embodiment of a SYS computer system. The SYS computer system may be a microcontroller. For example, the microcontroller may have an ARM® Cortex-M architecture.

[0041] The computer system SYS comprises a transmitter processor CPU1.

[0042] The computer system also comprises an original memory MEM1. The original memory MEM1 may be a volatile memory, in particular a random-access memory (also designated by the acronym “RAM”).

[0043] The original memory MEM1 comprises a set of buffer memories BUF1 (in English "buffer"). The original memory MEM1 is configured to store data for the sending processor CPU1. In particular, the original memory MEM1 is connected to the sending processor CPU1 so as to allow the sending processor CPU1 to access the original memory MEM1 in writing and reading.

[0044] The computer system SYS also comprises a destination processor CPU2.

[0045] The computer system also comprises a destination memory MEM2. The destination memory MEM2 can be a volatile memory, in particular a RAM.

[0046] The destination memory MEM2 comprises a set of memory areas, in particular buffer memories BUF2 (in English "buffer"). The destination memory MEM2 is configured to store data for the destination processor CPU2. In particular, the destination memory MEM2 is connected to the destination processor CPU2 so as to allow the destination processor CPU2 to access the destination memory MEM2 in writing and reading.

[0047] The computer system SYS also comprises a transmission module TRM. The transmission module TRM may be a direct memory access controller (also designated by the acronym “DMA”). Alternatively, the transmission module TRM may be a “mailbox” type circuit in an ARM® architecture when this circuit is configured to be able to perform a data transfer between the source memory MEM1 and the destination memory MEM2.

[0048] The transmission module TRM is shared between the sending processor CPU1 and the receiving processor CPU2. In particular, the transmission module TRM is configured to transmit data intended for the receiving processor and stored in the original memory MEM1 to the destination memory MEM2. This data is transmitted in at least one message MSG.

[0049] The transmission module TRM is connected to the original memory MEM1 so as to be able to read access to the original memory MEM1. This allows the transmission module TRM to receive the data stored in the original memory MEM1 to be transmitted to the destination memory MEM2.

[0050] The transmission module TRM is also connected to the destination memory MEM2 so as to be able to access this destination memory MEM2 in writing. This allows the transmission module TRM to write into the destination memory MEM2 the data received from the original memory MEM1.

[0051] The transmission module TRM is controlled by the transmitter processor CPU 1 or by the destination processor CPU2. In particular, the transmitter processor CPU1 is connected to the controller DMA1 to communicate to it control data CTRL1 making it possible to control certain registers of the transmission module TRM. The destination processor CPU2 is connected to the controller DMA1 to communicate to it control data CTRL2 making it possible to control other registers of the transmission module TRM.

[0052] It is also possible to define a security attribute to complete the isolation of the two processors CPU1 and CPU2. The security attribute is then used to define access rights of the processors CPU1 and CPU2 to the original memory MEM1 and to the destination memory MEM2. For example, the security attribute can allow access to the original memory MEM1 only for the sending processor CPU1, and to allow access to the destination memory CPU2 only for the receiving processor CPU2. This isolates the two processors CPU1 and CPU2 to better protect the data stored in the original memory MEM1 and in the destination memory MEM2.

[0053] The computer system SYS makes it possible to use a transmission module TRM to transfer messages MSG from the original memory MEM1, associated and defined by the sending processor CPU1, to the destination memory MEM2, associated and defined by the receiving processor CPU2.

[0054] Such a computer system SYS makes it possible to avoid using shared memory between two processors. It is therefore not necessary for the two processors to agree on an area of ​​memory to be shared. Each processor can define its own memory area in which to store the MSG message.

[0055] Furthermore, such a computer system SYS has the advantage of allowing the sending processor CPU1 and the receiving processor CPU2 to perform other tasks as soon as the transfer of the MSG message begins. Indeed, the transmission module TRM takes care of the transfer of the MSG message entirely. The sending processor CPU1 and the receiving processor CPU2 therefore do not carry out the transfer of the MSG message themselves. The sending processor CPU1 and the receiving processor CPU2 can also switch to a reduced consumption mode until the transfer of the MSG message is complete.

[0056] In addition, it is not necessary to copy the MSG messages in order to transfer them.

[0057] [Fig.2] illustrates a first embodiment of a TRM transmission module. Here, the TRM transmission module is a DMA1 direct memory access controller.

[0058] More particularly, the DMA1 controller comprises a first register RI controlled by the sending processor CPU1 to activate the transfer of the MSG message by the DMA1 controller when the receiving processor CPU2 is ready to receive the MSG message.

[0059] The DMA1 controller also comprises a second register R2 configured to store an original address @SRC of the original memory MEM1. The original address @SRC points to the memory area of ​​the original memory MEM1 comprising the data to be transferred. This second register R2 is also controlled by the transmitter processor CPU1. The transmitter processor CPU1 is configured to be able to define a different original address @SRC for each MSG message.

[0060] The DMA1 controller also includes a third register R3 configured to store a destination address @DST of the destination memory MEM2. The destination address @DST points to the memory area of ​​the destination memory MEM2 intended to receive data from the original memory MEM1. This third register R3 is controlled by the destination processor CPU2. The destination processor CPU2 is configured to set a destination address @DST for each MSG message to be received.

[0061] The DMA1 controller further comprises a fourth register R4 configured to define a length DAT_L of the MSG message to be transmitted. This length of the message makes it possible to indicate the length DAT_L of the MSG message that the destination memory MEM2 can receive. This length of the message corresponds in particular to the area of ​​the destination memory MEM2 allocated to store the data of the MSG message. This fourth register R4 is controlled by the destination processor CPU2. The transmitter processor CPU1 is configured to read the contents of this fourth register R4 in order to know the length of the MSG message to be used. Furthermore, the transmitter processor CPU1 is configured to determine that the destination processor CPU2 is ready to receive an MSG message when the value in this fourth register R4 is different from zero.The value of the fourth register R4 is configured to be decremented by the DMA1 controller during the transfer of an MSG message until it reaches zero at the end of the transfer.

[0062] The length DAT_L of the MSG message can be adjusted upon request from the processor CPU1. In particular, the destination processor is configured to define an initial message length. Then, the sending processor CPU1 is configured to send a message requesting the destination processor CPU2 to adjust the length DAT_L of the MSG message. The destination processor CPU2 is then configured to allocate an area of ​​memory corresponding to the length DAT_L of the MSG message requested by the sending processor CPU1. Subsequently, the destination processor CPU2 is configured to update the destination address @DST in the register R3 as well as the length DAT_L of the MSG message in the register R4. The sending processor CPU1 is then configured to check the value of the length DAT_L of the MSG message stored in the register R4 before authorizing the transfer of the MSG message.

[0063] Such a DMA1 controller thus has the advantage of allowing adjustment of the length of MSG messages.

[0064] The DMA1 controller further comprises a fifth register R5 configured to store contextual information (in English "flag") CLR_FG. The destination processor CPU2 is configured to clear this register R5 in order to acknowledge the reception of a new message and to allow the transmission module TRM to generate signals for interrupting a message transfer.

[0065] In particular, an interrupt signal is transmitted to the sending processor CPU1 via the NVIC1 connection when an MSG message is transmitted to the destination processor CPU2. In addition, an interrupt signal is transmitted to the destination processor CPU2 via the NVIC2 connection when an MSG message is received by the DMA1 controller from the sending processor CPU1.

[0066] [Fig.3] illustrates a second embodiment of a TRM transmission module, also corresponding to a DMA2 direct memory access controller.

[0067] The direct memory access controller DMA2 comprises the same registers RI, R2, R3, R4 and R5 as the direct memory access controller DMA1 described previously in relation to [Fig.2].

[0068] The direct memory access controller DMA2 also includes a synchronization register R6. This register R6 is used to indicate when the destination processor CPU2 is ready. The destination processor CPU2 is configured to set a control bit in this register R6 to indicate that it is ready to receive. In particular, this register is configured to generate an interrupt signal when the destination processor CPU2 indicates that it is ready to receive the MSG message.

[0069] In this case, the sending processor CPU1 no longer has to probe the value of the register R4 intended to contain the length of the MSG message. Thus, it is possible to modify a power supply mode of the sending processor CPU1 in order to reduce its consumption of the sending processor CPU1 while waiting for the receiving processor CPU2 to be ready to receive an MSG message.

[0070] The DMA2 controller also includes an access control register R7. The access control register makes it possible to isolate the registers so that the registers RI and R2 can be accessed only by the sending processor CPU1 and the registers R3, R4, R5 and R6 can be accessed only by the receiving processor CPU2.

[0071] This allows for high isolation between the sending processor CPU 1 and the receiving processor CPU2. In fact, each processor only has access to the registers that it can control. In addition, each processor only has access to the memory associated with it.

[0072] [Fig.4] illustrates a third embodiment of a transmission module TRM, corresponding here to a direct memory access controller DMA3. The registers RI, R2, R3, R4, R6 and R7 of the controller DM3 are similar to those described previously. However, in this embodiment, the registers R2 and R3 of the memory access controller DMA3 are configured to support linked lists.

[0073] In particular, the transmitting processor CPU 1 is configured to define in the register R2 a linked list of the memory areas of the original memory MEM1 containing different MSG messages to be transmitted. More particularly, the register R2 includes the address of the original memory MEM1 containing the linked list of these memory areas of the original memory MEM1.

[0074] The destination processor CPU2 is configured to define in the register R3 a linked list of the memory areas of the destination memory MEM2 intended to receive the different MSG messages. More particularly, the register R3 comprises the address of the destination memory MEM2 containing the linked list of these memory areas of the destination memory MEM2.

[0075] To synchronize the linked lists, the reloading of the linked lists is performed only when the sending processor CPU1 and the receiving processor CPU2 are ready, i.e. once the transfer of a previous MSG message is completed.

[0076] The DMA2 controller also includes a register R8 controlled by the sending processor CPU1 and a register R9 controlled by the receiving processor CPU2. These registers R8 and R9 respectively include control values ​​SRC_F and DEST_F, instead of a single register R5 storing the contextual information CLR_FG in the embodiment of [Fig.2]. These two registers R8 and R9 make it possible to restrict access to each register to a single processor. In this way, each processor controls a respective control value independently of the other processor.

[0077] The sending processor CPU1 is configured to receive an interrupt signal indicating that the receiving processor CPU2 is ready to receive the MSG message. Once the sending processor CPU1 has received this interrupt signal, the sending processor CPU1 is configured to read the length of the DAT_L message indicated by the receiving processor CPU1 in the register R4. In this way, the sending processor CPU1 no longer has to regularly poll the register R4 in order to know when the receiving processor CPU2 is ready to receive the MSG message.

[0078] [Fig. 5] illustrates an example of a method implemented by the sending processor CPU1 to transmit an MSG message intended for the receiving processor CPU2 via the DMA1 controller described in [Fig. 2]. In particular, the sending processor CPU1 is configured to execute a computer program comprising instructions, which when executed by the sending processor CPU1, cause the latter to implement such a method.

[0079] The method comprises a step 50 in which the transmitting processor CPU1 reads the value of the fourth register R4 intended to store the length of the message MSG.

[0080] The method comprises a test step 51 in which the sending processor CPU 1 determines whether the length of the message MSG has been defined by the processor CPU2. In particular, the sending processor CPU1 compares the value read from the fourth register R4 to zero. If the value read from the fourth register R4 is equal to zero, this means that the Recipient processor CPU2 has not yet set the length of the MSG message and recipient processor CPU2 is not yet ready to receive the MSG message. If the value read from the fourth register R4 is non-zero, this means that recipient processor CPU2 has set the length of the MSG message and recipient processor CPU2 is ready to receive the MSG message.

[0081] If the value read from the fourth register R4 is equal to zero, then the method resumes at step 50 so that the sending processor CPU1 continues to probe the value of the fourth register until the length of the message MSG is defined.

[0082] If the value of the fourth register R4 is different from zero, then the method continues with a step 52. In this step 52, the sending processor CPU1 activates the transfer of the message MSG by the controller DMA1. To do this, the processor CPU1 activates the connection NVIC1 and indicates the original address in the second register of the controller DMA1 then modifies the value of the first register of the controller DMA1 to activate the transfer of the message MSG. The controller DMA1 can then retrieve the message to be transmitted in the original memory MEM1 from the original address to copy it into the destination memory MEM2 at a destination address defined by the recipient processor CPU2.

[0083] Once the MSG message has been transmitted to the destination memory CPU2 by the DMA1 controller, the DMA1 controller generates an interrupt signal to signal the end of the transmission of the MSG message to the sending processor CPU1 and to the receiving processor CPU2.

[0084] The method also comprises a step 521 which, following receipt of the end of transmission interrupt signal for the MSG message, deactivates the NVIC1 connection used by the DMA1 controller.

[0085] The method then comprises a step 522 in which the sending processor CPU 1 generates a notification MSG_SN in order to signal to the application program executed by the processor CPU1 that the message is sent.

[0086] Then, the method comprises a test step 53 in which the sending processor CPU 1 determines whether the notification MSG_SN has been received by the application program.

[0087] If the sending processor CPU1 has not received the MSG_SN notification, then the test step is repeated.

[0088] If the sending processor CPU1 has received the interrupt signal, then this means that the MSG message has been successfully transferred to the receiving processor CPU2. Thus, the method can then resume at step 50 in order to transmit a new MSG message to the receiving processor CPU2.

[0089] [Fig.6] illustrates an example of a method implemented by the destination processor CPU2 to receive a message MSG in the destination memory MEM2 from the transmitter processor CPU1 via the controller DMA1 described in relation to [Fig.2]. In particular, the recipient processor CPU2 is configured to execute a computer program comprising instructions, which when executed by the recipient processor CPU2, cause the latter to implement such a method.

[0090] The method comprises a step 60 in which the destination processor CPU2 initializes the DMA1 controller by activating a clock of the DMA1 controller, by configuring it so that it can carry out a message transfer MSG from the source memory MEM1 to the destination memory MEM2 and so that it can generate an interrupt signal at the end of each message transfer via the NVIC2 connection.

[0091] The method then comprises a step 61 in which the recipient processor CPU2 defines the destination address @DST of the MSG message in the third register.

[0092] The method then comprises a step 62 in which the destination processor CPU2 clears the fifth register used for the interrupt signal. The destination processor CPU2 also defines the maximum length of the MSG message. The destination processor CPU2 activates the NVIC2 connection for the DMA1 controller so that the destination processor CPU2 can receive a transfer completion interrupt signal.

[0093] Next, the method comprises a test step 63 in which the destination processor CPU2 determines whether the message MSG has been received by the destination memory MEM2.

[0094] In particular, following step 62, the method comprises a step 621 in which the recipient processor CPU2, after having received the end of transmission interrupt signal of the MSG message, deactivates the NVIC2 connection of the DMA1 controller. Then, in step 622, the recipient processor CPU2 sends a notification MSG_RN to the application program that it is executing in order to inform it that the MSG message has been received by the recipient memory MEM2.

[0095] If, in step 63, the destination processor CPU2 has not received the interrupt signal, then this means that the MSG message has not been received. In this case, the test step 63 is repeated.

[0096] If, in step 63, the destination processor CPU2 has received the interrupt signal, then this means that the MSG message has been received. In this case, the method then comprises a step 64.

[0097] In this step 64 the destination processor CPU2 determines whether the next memory area of ​​the memory MEM2 is ready to receive a new MSG message.

[0098] If the next memory area is not ready to receive an MSG message, then step 64 is repeated.

[0099] If the next memory area is ready to receive an MSG message, then the method comprises a step 65 in which the recipient processor changes the memory area intended to receive a new MSG message. This new memory area intended to receive a new MSG message corresponds to the next memory area. Then, the method resumes at step 61 to receive a new MSG message.

[0100] Of course, the present invention is susceptible to various variants and modifications which will appear to those skilled in the art. For example, the computer system may comprise several destination processors and several destination memories. In this case, the transmission module comprises additional registers for each additional destination processor, in particular to indicate the memory areas of the destination memories. In particular, the transmission module comprises several communication channels (in particular “DMA” channels) for communicating with the different destination processors. Each channel is then a copy of the direct memory access controller which allows communication between two processors of the computer system, in the same manner as that described previously in relation to Figures 1 to 6.

Claims

Claims

1. Computer system comprising: - a first processor, called the sending processor (CPU1), and a second processor, called the receiving processor (CPU2), - a first memory, called the original memory (MEM1), associated with the sending processor (CPU1), and a second memory, called the destination memory (MEM2), associated with the receiving processor, said original memory being configured to store data that may be intended for the receiving processor, - a transmission module (TRM) controlled by the sending processor (CPU1) and by the receiving processor (CPU2), the transmission module (TRM) being configured to transfer a message (MSG) comprising data intended for the receiving processor from the original memory (MEM1) to the destination memory (MEM2).

2. The system of claim 1, wherein the transmission module (TRM) is a direct memory access controller.

3. System according to any one of claims 1 or 2, in which the transmission module (TRM) comprises a first register (RI) controlled by the transmitting processor and configured to authorize a transfer of said message by said transmission module.

4. System according to claim 3, in which the transmission module (TRM) comprises a second register (R2) controlled by the transmitting processor and configured to store an original address pointing to an area of ​​the original memory comprising the data of the message to be transferred.

5. System according to claim 4, in which the transmission module (TRM) comprises a third register (R3) controlled by the destination processor and configured to store a destination address pointing to an area of ​​the destination memory intended to receive the data of said message to be transferred.

6. System according to one of claims 5, in which the transmission module (TRM) comprises a fourth register (R4) controlled by the recipient processor and configured to store a length (DAT_L) of the message to be transferred.

7. The system of claim 6, wherein the transmitting processor is configured to read access to the fourth register and to start the transfer of the message by the transmission module (TRM) once that the length of the message has been defined by the receiving processor in the fourth register.

8. The system of claim 6, wherein the sending processor is configured to detect that the length of the message has been set by the receiving processor when the value stored in the fourth register is non-zero.

9. System according to one of claims 1 to 8, in which the transmission module (TRM) comprises a synchronization register (R6), the recipient processor being configured to store information in the synchronization register (R6) making it possible to indicate that the destination memory (MEM2) is ready to receive the message, the transmission module (TRM) being configured to generate an interrupt signal intended for the transmitter processor (CPU1) when the synchronization register indicates that the destination memory (MEM2) is ready to receive the message.

10. System according to one of claims 1 to 9, in which the transmission module (TRM) comprises an access control register (R7) configured to define access authorizations to the registers of the transmission module (TRM) for the transmitting processor (CPU1) and for the receiving processor (CPU2).

11. System according to one of claims 1 to 10, in which the transmission module is configured to generate a first interrupt signal intended for the recipient processor when a transfer of a message intended for the recipient processor is completed.

12. System according to one of claims 11, in which the transmission module is configured to generate a second interrupt signal intended for the sending processor when a transfer of a message intended for the receiving processor is completed.

13. System according to one of claims 1 to 12, in which the transmission module (TRM) comprises a fifth register (R5) configured to store contextual information (CLR_FG) indicating an end of transfer of the message, the recipient processor (CPU2) being configured to clear this fifth register (R5) in order to acknowledge the reception of a new message and to allow the transmission module (TRM) to generate interrupt signals during a next message transfer.

14. The system of claims 6 and 13, wherein the transmission module (TRM) is configured to decrement during the transfers the value stored in the fourth register (R4) and initialized to the message length (DAT_L), the first interrupt signal and the second interrupt signal being generated when the value stored in the fourth register (R4) reaches zero.

15. System according to one of claims 4 to 14, in which the address stored in the second register (R2) of the transmission module (TRM) points to a linked list in the original memory (MEM1) comprising a succession of addresses pointing to different memory areas of the original memory (MEM1) comprising data intended for the destination processor (CPU2), the transmission module (TRM) being configured to successively transmit messages comprising the data of the different memory areas pointed to by said linked list.

16. Method implemented by a computer system (SYS) comprising: - a first processor, called the sending processor (CPU1), and a second processor, called the receiving processor (CPU2), - a first memory, called the original memory (MEM1), associated with the sending processor (CPU1), and a second memory, called the destination memory (MEM2), associated with the receiving processor, said original memory being configured to store data that may be intended for the receiving processor, - a transmission module (TRM), the method comprising: - a control of the transmission module (TRM) by the sending processor (CPU1) and by the receiving processor (CPU2) in order to initialize a transfer of a message comprising data intended for the receiving processor (CPU2) from the original memory (MEM1) to the destination memory (MEM2), then - a transfer of said message (MSG) by the transmission module (TRM) from the original memory (MEM1) to the destination memory (MEM2).

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