Variable capacitance polarization device

Abstract

Variable Capacitor Biasing Device. This description concerns a device (500). A first circuit (BG) provides a first current (Ibg) flowing through a first resistive element receiving a temperature-stable voltage, and a second current (Iptat) proportional to the temperature. A second resistive element (R) comprises MOSFETs (T) in series and diode configuration, and has a first terminal connected to a reference potential (GND) and a second terminal connected to a supply potential (VDD). A second circuit (C1) provides, in the second resistive element (R), a copy (Ibgc1) of the first current (Ibg). A third circuit (C2) applies a voltage to a back gate (600) of the transistors (T), determining the second current (Iptat). Figure for the abstract: Fig. 5

Description

Title of the invention: Variable capacitance polarization device technical field

[0001] This description relates generally to electronic circuits, and more particularly to electronic circuits comprising a variable capacitor. Prior art

[0002] Many electronic circuits include a variable capacitor, that is, a capacitive component having an adjustable capacitance value. For example, voltage-controlled oscillators are electronic circuits that include a variable capacitor.

[0003] Electronic circuits incorporating a variable capacitance present several drawbacks. For example, their operation may depend on temperature in addition to the value of their variable capacitance, which is problematic. This is the case, for instance, in voltage-controlled oscillators incorporating a variable capacitance, such as voltage-controlled oscillators configured to provide a radio frequency signal having, for example, a frequency greater than 1 GHz, or even greater than 10 GHz, for example, approximately 20 GHz. Summary of the invention

[0004] There is a need to overcome all or part of the disadvantages of electronic circuits comprising a variable capacitance.

[0005] For example, there is a need for a device providing a voltage to a variable capacitance of an electronic circuit which makes it possible to compensate at least in part for the effect of temperature on an operating parameter of the electronic circuit.

[0006] For example, there is a need for a device to supply a voltage to a variable capacitance of a voltage-controlled oscillator which makes it possible to compensate at least in part for the effect of temperature on the frequency of the oscillator, for example when the frequency of the oscillator is controlled by a phase-locked loop (PLL).

[0007] An embodiment overcomes all or part of the disadvantages of known electronic circuits comprising a variable capacitance.

[0008] For example, an embodiment overcomes all or part of the disadvantages of known devices supplying a voltage to a variable capacitance of an electronic circuit.

[0009] For example, an embodiment overcomes all or part of the drawbacks of the dis known positives providing a voltage to a variable capacitance of a voltage-controlled oscillator, for example a voltage-controlled oscillator controlled by a phase-locked loop.

[0010] One embodiment provides a device comprising: a first bandgap circuit configured to apply a temperature-stable voltage across the terminals of a first resistive element so that a first current flows through it, and to provide a second current proportional to the absolute temperature; a second resistive element comprising one or more MOS transistors in series and each mounted as a diode, the second resistive element having a first terminal connected to a node for the application of a reference potential and a second terminal coupled to a node for the application of a supply potential; a second circuit connected to the first circuit and configured to provide a first copy of the first current, and that said first copy flows through the second resistive element; and a third circuit connected to the first circuit and configured for: - provide a copy of the second current, provide a first control voltage from said copy of the second current, and apply the first control voltage to a back gate of the transistors in the resistive element, or - provide a second copy of the first current and a copy of the second current, provide a first control voltage from a difference between the second copy of the second current and the copy of the first current, and apply the first control voltage to a back gate of the transistors of the second resistive element.

[0011] According to one embodiment, the second terminal of the second resistive element is configured to provide a bias voltage to a variable capacitance.

[0012] According to one embodiment, the device includes the variable capacitance, the variable capacitance is configured to receive a setting voltage and the bias voltage, and a difference between the setting voltage and the bias voltage determines a value of the capacitance.

[0013] According to one embodiment, the second resistive element is in series with a resistor, the second terminal of the second resistive element is configured to provide a first bias voltage to a variable capacitance and is connected to a first terminal of said resistor, and a second terminal of said resistor is configured to provide a second bias voltage to the variable capacitance.

[0014] According to one embodiment, the device includes the variable capacitance, the variable capacitance is configured to receive a setting voltage and the first and second bias voltages, and a difference between the setting voltage and the first bias voltage and a difference between the setting voltage and the second bias voltage determine a value of the capacitance.

[0015] According to one embodiment, the device includes a voltage-controlled oscillator comprising the variable capacitor.

[0016] According to one embodiment, the device includes a circuit for supplying the regulating voltage, said circuit comprising, for example, a phase-locked loop.

[0017] According to one embodiment, the third circuit comprises a resistor having a first terminal connected to the node of application of the reference potential or to the node of application of the supply potential, a second terminal of said resistor being configured to provide the first control voltage and being connected to the rear gate of the transistors of the second resistive element.

[0018] According to one embodiment, the third circuit includes a smoothing capacitor connected between the back gate of the transistors of the second resistive element and the node of application of the reference potential.

[0019] According to one embodiment, the transistors of the second resistive element are all N-channel transistors or are all P-channel MOS transistors.

[0020] According to one embodiment, the transistors of the second resistive element are all implemented on silicon on insulator.

[0021] According to one embodiment, the third circuit includes a circuit for adjusting the slope of the first control voltage with the temperature.

[0022] According to one embodiment, the adjustment circuit comprises one or more assemblies, each comprising: - a first resistor and a first switch in series between the node where the supply potential is applied and the second terminal of the resistor providing the first control voltage, and - a second resistor and a second switch in series between the second terminal of the resistor providing the first control voltage and the node applying the reference potential, a value of the second resistor in the assembly being identical to a value of the first resistor in the assembly.

[0023] According to one embodiment, the adjustment circuit comprises several of said assemblies, and a value of the first resistance is different in each of said assemblies.

[0024] According to one embodiment, the first control voltage is determined by the difference between the second copy of the first current and the copy of the second current, and the slope adjustment circuit includes a fourth circuit configured to provide the second copy of the first current, and a fifth circuit configured to provide the second copy of the second current, a gain of the fourth circuit and a gain of the fifth circuit being adjustable so as to allow the slope of the first control voltage to be adjusted with temperature. Brief description of the drawings

[0025] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0026] Fig. 1 represents, schematically and in block form, an example of a circuit comprising a variable capacitance;

[0027] [Fig.2] schematically represents an example of variable capacity;

[0028] Figure 3 schematically represents another example of variable capacity

[0029] [Fig.4] illustrates by means of curves an example of the operation of an example of a circuit comprising a variable capacitance;

[0030] [Fig.5] represents, schematically and partly in block form, one embodiment of a device;

[0031] [Fig.6] represents an example of another embodiment of a circuit of the device of [Fig.5];

[0032] [Fig. 7] represents yet another embodiment of the circuit the [Fig.6];

[0033] [Fig.8] represents another embodiment of a resistive component of the device of [Fig.5];

[0034] [Fig.9] represents a variant embodiment of the circuit of [Fig.5]; and

[0035] [Fig. 10] represents an example of an embodiment of another circuit of the device of the [Fig.5]. Description of the implementation methods

[0036] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0037] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0038] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0039] In the following description, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to Orientation qualifiers, such as the terms "horizontal", "vertical", etc., refer, unless otherwise specified, to the orientation of the figures.

[0040] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0041] Fig. 1 represents schematically and in block form an example of a VCO circuit comprising a variable capacitance Cvar.

[0042] The VCO circuit is a voltage-controlled oscillator. The VCO circuit is configured to provide an OUT signal at a frequency Fvco whose value is determined by the value of a tuning voltage Vtune. More specifically, the tuning voltage Vtune is a voltage that adjusts the capacitance value of the variable capacitor Cvar, and the value of the OUT signal's frequency Fvco is determined at least in part by the capacitance value of the Cvar component. The Vtune voltage is, for example, received by a terminal 104 of the capacitor Cvar.

[0043] In this example, the capacitor Cvar also receives a bias voltage Vbiasl. The voltage Vbiasl is, for example, received by a terminal 106 of the capacitor Cvar. The capacitance value of the capacitor Cvar, for example between two terminals 100 and 102 of the Cvar component, is then determined by the difference between the voltages Vtune and Vbiasl.

[0044] Although not illustrated in [Fig. 1], in other examples, the capacitance Cvar is configured to receive, in addition to the voltages Vtune and Vbias1, another bias voltage Vbias2. In these other examples, the capacitance value of the Cvar component is then determined by the difference between the voltages Vtune and Vbias1 and by the difference between the voltages Vtune and Vbias2, the difference between the voltages Vbias1 and Vbias2 being kept constant.

[0045] By way of example, the frequency Fvco of the OUT signal is controlled by a phase-locked loop (not shown in [Fig. 1]). The phase-locked loop is, for example, configured to supply, or control, the voltage Vtune so that the frequency Fvco is equal to a setpoint frequency Flock.

[0046] By way of example, the VCO circuit and the phase-locked loop controlling the Fvco frequency of the OUT signal are part of a radio frequency circuit and are configured so that the Fvco frequency of the OUT signal is greater than 1 GHz, preferably greater than 10 GHz, for example approximately 20 GHz. By way of example, the radio frequency circuit is a clock signal generation circuit. By way of alternative or complementary example, the radio frequency circuit is part of a wireless radio frequency signal transmission and / or reception circuit.

[0047] Figure 2 schematically represents an example of variable capacity Cvar.

[0048] In this example, the capacitor Cvar comprises two variable-capacitance components, Cvarl and Cvar2, for example, two varactors (or variable-capacitance diodes). The capacitance value of each component, Cvarl and Cvar2, is determined by the voltage across that component. Each component, Cvarl and Cvar2, has one electrode coupled, preferably connected, to terminal 104 receiving the voltage Vtune, and another terminal coupled to terminal 106 receiving the voltage Vbiasl. For example, the dipole Cvarl is connected between terminal 104 and a node 200 coupled to terminals 106 and 100, the dipole Cvar2 being connected between terminal 104 and a node 202 coupled to terminals 106 and 102. For example, node 200, respectively 202, is coupled to terminal 106 by a resistance RI, respectively R2, the resistance RI, respectively R2, being for example connected between nodes 200 and 106, respectively between nodes 202 and 106.For example, node 200, respectively 202, is coupled to terminal 100, respectively 102, by a decoupling capacitor Cdl, respectively Cd2, the capacitor Cdl, respectively Cd2, being for example connected between nodes 200 and 100, respectively between nodes 202 and 102.

[0049] The Vbiasl voltage is a bias voltage of the Cvar component and generally has a constant value. By varying the value of the Vtune voltage, the voltage across each of the Cvarl and Cvar2 components is then modified, resulting in a change in the capacitance value of each of the Cvarl and Cvar2 components, and therefore in the capacitance value of the Cvar component.

[0050] Fig. 3 represents, schematically, another example of variable capacitance Cvar.

[0051] The Cvar capacity of [Fig. 3] includes all the elements of the Cvar capacity of [Fig. 2]. Thus, unless otherwise indicated, everything described for the Cvar capacity of [Fig. 2] applies to the Cvar capacity of [Fig. 3].

[0052] Furthermore, the capacitance Cvar of [Fig. 3] comprises two variable-capacitance components Cvar3 and Cvar4, for example, two varactors. The capacitance value of each of the components Cvar3 and Cvar4 is determined by the voltage across that component. Each of the components Cvar3 and Cvar4 has one electrode coupled, preferably connected, to terminal 104 receiving the voltage Vtune, and another electrode coupled to a terminal 108 of the Cvar component, terminal 108 receiving the voltage Vbias2. For example, the dipole Cvar3 is connected between terminal 104 and a node 204 coupled to terminals 108 and 100, the dipole Cvar4 being connected between terminal 104 and a node 206 coupled to terminals 108 and 102. For example, node 204, respectively 206, is coupled to terminal 108 by a resistor R3, respectively R4, the resistor R3, respectively R4, being for example connected between nodes 204 and 108, respectively between nodes 206 and 108.For example, node 204, respectively 206, is coupled to terminal 100, respectively 102, by a decoupling capacitor Cd3, respectively. Cd4, the capacity Cd3, respectively Cd4, being for example connected between nodes 204 and 100, respectively between nodes 206 and 102.

[0053] The Vbias2 voltage is a bias voltage for the Cvar component and generally has a constant value. Furthermore, the difference between the Vbias1 and Vbias2 voltages is preferably constant. By varying the value of the Vtune voltage, the voltage across each of the components Cvar1, Cvar2, Cvar3, and Cvar4 is modified, resulting in a change in the capacitance value of each of the components Cvar1, Cvar2, Cvar3, and Cvar4, and therefore in the capacitance value of the Cvar component.

[0054] Due to the presence of two bias voltages Vbias 1 and Vbias 2, rather than just the bias voltage Vbias 1 as in [Fig. 2], the capacitance Cvar of [Fig. 3] exhibits a more linear variation in its capacitance value with the voltage Vtune than that of the capacitance Cvar of [Fig. 2]. Thus, when the capacitance Cvar is used to adjust the frequency of a voltage-controlled oscillator, the variation of the oscillator's frequency with the voltage Vtune is more linear when the capacitance Cvar of [Fig. 3] is used than when the capacitance Cvar of [Fig. 2] is used.

[0055] As previously mentioned, circuits with a variable capacitance can have an operation that depends on temperature in addition to the value of their variable capacitance, which poses a problem. This is the case, for example, in voltage-controlled oscillators, such as the VCO oscillator in [Fig. 1], whose frequency is controlled by a phase-locked loop.

[0056] Fig. 4 illustrates by means of curves an example of operation of the VCO oscillator of Fig. 1 when the oscillator has its frequency Fvco controlled by a phase-locked loop to the setpoint value Flock.

[0057] A curve Tt illustrates the evolution, at a nominal operating temperature, for example ambient temperature, of the frequency Fvco of the OUT signal of the VCO oscillator as a function of the voltage Vtune.

[0058] In this example, the frequency Fvco increases, for example in a substantially linear fashion, with the value of the voltage Vtune.

[0059] The phase-locked loop controls the voltage Vtune to a value such that the frequency Fvco is equal to the frequency Flock (point 400 in [Fig.4]). The phase-locked loop is then said to be locked.

[0060] A curve Te illustrates the evolution of the frequency Fvco of the VCO oscillator's output signal as a function of the voltage Vtune, at a low temperature lower than the nominal temperature. A curve Th illustrates the evolution of the frequency Fvco of the VCO oscillator's output signal as a function of the voltage Vtune, at a high temperature, higher than the ambient temperature.

[0061] In this example, for a given voltage value Vtune, the frequency Fvco decreases as the temperature increases. The Te curve then corresponds to a translation of the Tt curve towards higher Fvco frequencies, and the Th curve then corresponds to a translation of the Tt curve towards lower Fvco frequencies.

[0062] Since the VCO oscillator's Fvco frequency is controlled by the phase-locked loop, in this example where the Fvco frequency increases with increasing Vtune voltage and decreases with increasing temperature, the loop decreases the value of Vtune voltage as the temperature decreases to maintain the Fvco frequency equal to the Flock frequency. In particular, at the low temperature corresponding to curve Te, the Vtune voltage is decreased to a value corresponding to point 402 in [Fig. 4], for which curve Te takes the Flock value. Symmetrically, the loop increases the value of Vtune voltage as the temperature increases to maintain the Fvco frequency equal to the Flock frequency. In particular, at the high temperature corresponding to curve Te, the Vtune voltage is increased to a value corresponding to point 404 of curve Th. However, as illustrated in [Fig.[4], at point 404 corresponding to the maximum value that the Vtune voltage can take, the Fvco frequency is lower than the Flock frequency, and the phase-locked loop is no longer locked.

[0063] The fact that the phase-locked loop can no longer be locked when the temperature varies from the nominal operating temperature can arise when the temperature increases or decreases from the nominal temperature, in circuits where the frequency Fvco increases when the voltage Vtune increases as illustrated in [Fig.4], but also in circuits where the frequency Fvco decreases when the voltage Vtune increases, and / or in circuits where the frequency Fvco increases when the temperature decreases as illustrated in [Fig.4], but also in circuits where the frequency Fvco decreases when the temperature decreases.

[0064] By way of example, the variation of the frequency Fvco with temperature is related at least in part to the variation of the capacitance value of the component Cvar with temperature, and, more generally, to the variation with temperature of the values ​​of the components of the cell ("tank" in English) of the oscillator.

[0065] To reduce the dependence of the frequency Fvco on temperature, that is to say to bring the curves Te and Th closer to the curve Tt, one could consider replacing the Cvar component of the VCO circuit with two Cvar components in parallel, one being controlled by the voltage Vtune as previously described, and the other being controlled by a voltage determined by the temperature so as to compensate for the variation of the frequency Fvco with the temperature.

[0066] However, in addition to increasing the surface area of ​​the Cvar capacitance, and therefore of the VCO circuit, This increases the number of parasitic capacitances, which is problematic, for example, particularly in the radio frequency domain.

[0067] Whereas usually the bias voltage(s) Vbiasl and Vbias2 of a variable capacitor are constant and do not depend on temperature, it is proposed here to make them dependent on temperature.

[0068] For example, it is proposed here to make the bias voltage Vbias1 of a variable capacitor receiving only one bias voltage, or the two bias voltages Vbias1 and Vbias2 of a variable capacitor receiving two bias voltages, temperature-dependent. The way in which this or these bias voltages depend on temperature (increases or decreases with temperature) is determined so as to compensate for the effect of temperature variation on the operation of an electronic circuit comprising a variable capacitor whose capacitance value is determined by the difference between a control voltage Vtune and each bias voltage it receives. In an embodiment where the variable capacitor receives two bias voltages, the difference between the two bias voltages is provided to remain constant when the temperature varies.

[0069] Thus, a device configured to provide one or more bias voltages for a variable capacitor, each dependent on temperature, is proposed here, for example, to compensate for the effect of temperature variation on the operation of a circuit including such a variable capacitor. The choice of how each of the variable capacitor's bias voltages varies with temperature—for example, increasing when the temperature increases or decreasing when the temperature increases—depends on the application. For example, the choice of how each of the bias voltages varies with temperature is made to compensate for temperature variations in a parameter whose value is at least partially determined by that of the capacitor.

[0070] By way of example, the circuit is an oscillator, for example configured to provide a radio frequency signal, and the variable capacitor is part of the oscillator's cell (or "tank"). The variation of the variable capacitor's bias voltages with temperature is then configured to compensate for a variation in the oscillator's operating frequency (Fvco) with temperature. Indeed, the Fvco frequency depends on the value of the capacitance in the oscillator's cell (or "tank") and, more generally, on the value of each of the components in this cell (or "tank"), and the values ​​of these components vary with temperature.

[0071] Figure 5 represents, schematically and partly in block form, a method of implementation of such a device 500.

[0072] The device 500 includes a band-gap circuit, referred to as BG in [Fig.5].

[0073] The BG circuit includes a resistive element R55 and is configured to apply a temperature-stable voltage across the resistive element R55, such that a current Ibg flows through it. In other words, the BG circuit is configured to generate the temperature-stable voltage Vbg and to apply this voltage across the resistive element R55. A detailed example of a BG circuit will be described later with reference to [Fig. 10]. In addition to the current Ibg, the BG circuit is further configured to provide a temperature-dependent current Iptat, preferably linearly dependent with temperature. The current Iptat is a current proportional to the absolute temperature (PTAT, from the English "Proportional To Absolute Temperature") that increases as the temperature increases.

[0074] The device 500 also includes a circuit CL. The circuit CL includes a resistive element R. The resistive element R has one terminal connected to a node 502 configured to receive a reference potential GND, for example, ground. The element R is configured to provide the voltage Vbiasl, this voltage Vbiasl then being available across the terminals of the element R. The voltage Vbiasl is a bias voltage of a variable capacitor, for example, a variable capacitor Cvar.

[0075] The element R comprises, preferably consists of, one or more MOS (Metal Oxide Semiconductor) transistors in series between the conduction terminals of the resistive element R. Each of these transistors T is configured as a diode, that is, its drain is connected to its gate. When the component R comprises several transistors T, they are all of the same type; for example, they are all NMOS transistors, as is the case in the example in [Fig. 5], where the component R comprises exactly two N-channel (or NMOS) transistors T. Preferably, the transistors T are all identical. By way of example, an advantage of implementing the resistive element R with Q transistors T in series, each configured as a diode, is that the small-signal resistance is Q / gm and is therefore low, where Q is an integer greater than or equal to 1, and gm is the transconductance of a transistor T.This results in low noise on the voltages available across the terminals of the resistive element R.

[0076] The Cl circuit is connected to the BG circuit and is configured to provide a copy Ibgcl of the current Ibg to the resistive element R. In other words, the Cl circuit is configured to provide a current Ibgcl which is a copy of the current Ibg, and for this current Ibgcl to flow between the conduction terminals of the component R.

[0077] In the remainder of this description, unless otherwise indicated, when it is stated that a first current is a copy of a second current, this means that the first current is equal to the second current up to a multiplicative factor.

[0078] The device 500 further includes a circuit C2. The circuit C2 is connected to the circuit BG. The circuit C2 is configured to provide a temperature-dependent bias voltage VI to the rear gates of the transistors T of the element R. Thus, when the temperature varies, the voltage V1 varies, which changes the resistance value of each of the transistors T, therefore the value of the voltage Vbiasl available across the terminals of the element R, that is to say the voltage Vbiasl available on the terminal of the element R which is not connected to node 502.

[0079] Since T transistors have back gates, they are therefore implemented on semiconductor on insulator (SOI), for example on fully depleted silicon on insulator (FDSOI).

[0080] In the embodiment of [Fig. 5], the circuit C2 is more particularly configured to provide a copy Iptatcl of the current Iptat, and so that the voltage V1 is determined by the current Iptatcl, for example, varies linearly with this current Iptatcl. Thus, when the temperature varies, the current Iptat varies, from which it follows that the current Iptatcl varies, which leads to a corresponding variation in the voltage VI. The variation in the voltage V1 results in a variation in the resistance value of the component R, and therefore in a corresponding variation in the voltage Vbiasl. It follows that, without changing the value of the voltage Vtune, the capacitance value of a variable capacitor such as that of [Fig. 2] is changed when the temperature varies.

[0081] In the embodiment illustrated in [Fig. 5], the device 500 is configured to also supply the bias voltage Vbias2 in addition to the voltage Vbiasl. The voltages Vbiasl and Vbias2 are bias voltages of a variable capacitance, for example, the variable capacitance Cvar of [Fig. 3]. For this purpose, in the circuit Cl, the resistive element R is connected in series with a resistor R51. Thus, one terminal of element R is connected to node 502, another terminal of element R is connected to one terminal of resistor R51 and supplies the voltage Vbiasl, and the other terminal of resistor R51 supplies the voltage Vbias2. Preferably, resistor R51 is matched to resistor R55, from which it follows that the difference between voltages Vbias 1 and Vbias2 is constant and, in particular, does not depend on temperature because current Ibgcl is a copy of current Ibg equal to Vbg / R55.

[0082] According to one embodiment, when the device 500 is configured to supply the two voltages Vbias1 and Vbias2, the device 500 includes a variable capacitor (not shown in [Fig. 5]) configured to receive the bias voltages Vbias1 and Vbias2 and the tuning voltage Vtune, and having its capacitance value determined by the difference between the voltages Vbias1 and Vtune and by the difference between the voltages Vbias2 and Vtune. By way of example, this variable capacitor is the capacitance Cvar described in relation to [Fig. 3]. According to one embodiment, the device further includes a voltage-controlled oscillator, for example the VCO oscillator of [Fig. 1], comprising this variable capacitor. According to one embodiment, the device includes a circuit for supplying the voltage Vtune, for example a loop with a variable voltage. Phase rusting.

[0083] In another embodiment not shown, the device 500 is configured to supply only the bias voltage Vbiasl. In this other embodiment, the resistor R51 can be omitted.

[0084] In one embodiment, when the device 500 is configured to supply only the bias voltage Vbiasl, the device 500 includes a variable capacitor configured to receive the voltage Vbiasl and a tuning voltage Vtune, and having its capacitance value determined by the difference between the voltages Vbiasl and Vtune. By way of example, this variable capacitor is the capacitance Cvar described in relation to [Fig. 2]. In one embodiment, the device further includes a voltage-controlled oscillator, for example the VCO oscillator of [Fig. 1], comprising this variable capacitor. In another embodiment, the device includes a circuit for supplying the voltage Vtune, for example a phase-locked loop.

[0085] According to one embodiment, as illustrated in [Fig. 5], the circuit C2 includes a resistor R52 configured to supply the voltage VI. The resistor R52 has one terminal connected to node 502 and another terminal connected to the back gate of transistor T (or node 600), the voltage V1 being available at this other terminal. In the embodiment shown in [Fig. 5], the circuit C2 is configured to supply the current Iptatcl to node 600. The current Iptatcl then flows between the terminals of the resistor R52, which converts the current Iptatcl into the voltage VL

[0086] By way of example, the resistor R52 has a value such that, at the nominal operating temperature, the voltage V1 is equal to half of a supply potential VDD of the device 500, the potential VDD being preferably positive and referenced to the potential GND.

[0087] Preferably, the circuit C2 includes a smoothing capacitor Cf connected between node 600 and node 502.

[0088] By way of example, circuit BG includes a P-channel MOSFET T1 configured to carry current Iptat, and circuit C2 includes a P-channel MOSFET T2 mounted in mirror image of transistor T1 so that transistor T2 supplies current Iptatcl to node 600. In the example of [Fig. 5], transistor T2 is connected to node 600 and in series with resistor R52, which is configured to supply voltage VL

[0089] By way of a more detailed example, transistor T1 has its source coupled to a node 504 configured to receive the supply potential VDD, for example by a resistor R53, resistor R53 preferably having one terminal connected to transistor T1 and one terminal connected to node 504. The gate of transistor T1 is connected to a node A. Transistor T2 then has its gate connected to node A and its source coupled to node 504, for example by a resistor R54, resistor R54 preferably having one terminal connected to transistor T2 and one terminal connected to node 504.

[0090] By way of example, the BG circuit further includes a P-channel MOSFET T3 configured to carry the current Ibg, and the Cl circuit includes a P-channel MOSFET T4 mounted in mirror image of transistor T3 so that transistor T4 supplies the current Ibgcl. Transistor T4 is connected in series with the resistive element R. Transistor T3 is, for example, connected in series with the resistive element R55 across which the BG circuit applies the temperature-stable voltage Vbg. The resistive element R55, for example a resistor, has one terminal connected to node 502. As a result, the current Ibg flows between the terminals of element R55, that is, through element R55, and through transistor T3, which is connected in series with element R55 between nodes 504 and 502. Transistor T3 has its source coupled to node 504, for example, via a resistor R56, with one terminal connected to transistor T3 and the other to node 504.The gate of transistor T3 is connected to a node B. Transistor T4 then has its gate connected to node B and its source coupled to node 504, for example by a resistor R57, the resistor R57 preferably having one terminal connected to transistor T4 and one terminal connected to node 504. Transistor T4 is in series with resistor R57 between nodes 504 and 502.

[0091] In the example embodiment described in relation to [Fig.5], the circuit C2 is configured to provide the current Iptatcl copy of the current Iptat, provide the voltage V1 determined by the current Iptatcl, and apply the voltage VI to the rear gate of the transistors T of the resistive element R.

[0092] In other embodiments, as will be described in relation to Figures 6 and 7, the circuit C2 is configured to provide a copy of the current Ibg at node 600 and a copy of the current Iptat at node 600, provide the voltage V1 which is then determined by a difference between these two copies of current, and apply the voltage VI to the back gate of the transistors T of the resistive element R.

[0093] Fig. 6 represents an example of such an embodiment of the C2 circuit.

[0094] Circuit C2 of [Fig. 6] comprises, like the example circuit C2 described in relation to [Fig. 5], transistor T2 configured to supply the current Iptatcl. Transistor T2 has its source coupled to node 504, for example via resistor R54, and its drain coupled, for example connected, to node 600 corresponding to the node where transistor T2 connects to resistor R52.

[0095] The circuit C2 further includes a circuit C3 configured to provide an Ibgc3 copy of the current Ibg.

[0096] The current Ibgc3 is supplied to node 600 such that a current Idiff flowing through resistor R52 is equal to the difference between the currents Iptatcl and Ibgc3. More precisely, in the example of [Fig. 6], circuit C3 is configured so that the current Idiff is equal to the current Iptatcl minus the current Ibgc3. Thus, when the temperature As the temperature increases, the differential current (Idiff) increases, which results in the voltage (V1) increasing.

[0097] By way of example, circuit C3 includes a P-channel MOS transistor T5 configured to provide a copy Ibgc2 of the current Ibg, transistor T5 being mirrored to transistor T3. For example, transistor T5 has its source coupled to node 504, for example by a resistor R58, resistor R58 preferably having one terminal connected to transistor T5 and one terminal connected to node 504. The gate of transistor T5 is connected to node B. The drain of transistor T5 is coupled to node 600.

[0098] In the example in [Fig. 6], transistor T5 is coupled to node 600 by an N-channel MOS current mirror 602, the current mirror 602 being configured here to supply current Ibgc3 from current Ibgc2. For example, the current mirror 602 comprises an N-channel MOS transistor T6 having its drain connected to a node 604 and its source coupled to node 502, for example by a resistor R59, resistor R59 having, for example, one terminal connected to node 502 and one terminal connected to the source of transistor T6. The gate of transistor T6 is connected to the drain of transistor T6. The current mirror 602 further includes an N-channel MOS transistor T7 having its drain connected to node 600 and its source coupled to node 502, for example by a resistor R60, the resistor R60 having, for example, one terminal connected to node 502 and one terminal connected to the source of transistor T7. The gate of transistor T7 is connected to the gate of transistor T6.In the example in [Fig.6], transistor T5 is connected to node 604 via its drain.

[0099] Fig. 7 represents an example of another embodiment of the C2 circuit.

[0100] Compared to [Fig. 6], in the example of [Fig. 7] the circuit C2 is configured so that the current Idiff in the resistor R52 is equal to the difference between a copy Ibgc2 of the current Ibg and a copy Iptatc2 of the current Iptat, and, more precisely, so that the current Idiff is equal to the current Ibgc2 minus the current Iptatc2. Thus, as the temperature increases, the current Idiff decreases, hence the voltage V1 decreases.

[0101] Circuit C2 of [Fig.7] therefore differs from circuit C2 of [Fig.6] in that: -transistor T2, configured to supply current Iptatc1 to node 600 in circuit C2 of [Fig. 6], was replaced by transistor T5, configured to supply current Ibgc2 in circuit C2 of [Fig. 7], so that current Ibgc2 is supplied to node 600; and - the C3 circuit of the C2 circuit of [Fig.7] is not configured to supply the Ibgc3 current to node 600, as was the case in [Fig.6], but to supply the Iptatc2 current to node 600.

[0102] For example, transistor T5 remains mounted in mirror image of transistor T3, with its gate connected to node B, its source coupled to node 504, for example by resistor R58, but its drain is connected to node 600 rather than to node 604 as was the case in [Fig.6]. Symmetrically, transistor T2 remains mounted in mirror image of transistor T1, with its gate connected to node A, its source coupled to node 504, for example by resistor R54, but its drain is connected to node 604 coupled to node 600 by current mirror 602. Current mirror 602 then provides current Iptatc2 from current Iptatcl.

[0103] In the device 500 described above with reference to Figures 5 to 7, the resistive element consists of MOS transistors in series, each configured as a diode. This reduces noise on the Vbias voltage compared to a device in which a temperature-dependent current would have been directly supplied to a resistor to obtain the Vbias voltage across that resistor.

[0104] Furthermore, the prediction of the component R as described allows the gain to be adapted between a temperature variation and a corresponding variation of the voltage Vbiasl by modifying the number of transistors T of the component R.

[0105] In the examples of embodiments and variants described above, the component R comprises, preferably consists of, one or more N-channel MOS transistors T.

[0106] Figure 8 represents another embodiment of the resistive component R of the device of the [Fig.5].

[0107] In component R of the embodiment of [Fig.8], each transistor T of component R is P-channel rather than N-channel as previously described.

[0108] Although this is not illustrated in [Fig.8], the drain of transistors T is then on the side of node 502. For example, transistor T of resistive element R which has a terminal connected to node 502 has its drain connected to node 502.

[0109] Compared to the case where the transistors T are N-channel, the direction of variation of the voltage V1 with temperature is reversed for a corresponding case where the transistors T are P-channel, so that the direction of variation of the voltage Vbiasl with temperature remains the same.

[0110] Figure 9 shows an alternative embodiment of circuit C2. In Figure 9, the variant The implementation is applied to circuit C2 of [Fig.6], although this variant can also be applied to circuit C2 of [Fig.7], the latter implementation being within the reach of a person skilled in the art from the description given below in relation to [Fig.9].

[0111] In this variant, the circuit C2 includes a circuit for adjusting the slope of the voltage VI with temperature, and therefore the slope of the voltage Vbiasl with temperature. This allows adjusting how the variation of the frequency Fvco with temperature is compensated by the variation of the voltage Vbiasl with temperature, for example so that, for a given voltage Vtune, the variation of the frequency Fvco with temperature is as small as possible.

[0112] More particularly, in the example of [Fig. 9], this control circuit comprises several Ki sets, with i a strictly positive integer index. In the example of [Fig. 9], i is equal to 3.

[0113] Each set Ki (Kl, K2, K3 in [Fig.9]) comprises: - a resistor R8i (R81, R82, R83 in [Fig.9]) and a switch SW8i (SW81, SW82, SW83 in [Fig.9]) connected in series between node 600 and node 502; and - a resistor R9i (R91, R92, R93 in [Fig.9]) and a switch SW9i (SW91, SW92, SW93 in [Fig.9]) connected in series between node 600 and node 504.

[0114] For example, in each Ki set, switch SW8i is connected to node 502 and switch SW9i is connected to node 504.

[0115] In each set Ki, the resistance R8i of the set is identical to the resistance R9i of that set Ki. For example, each resistance R8i is matched to the corresponding resistance R9i. Furthermore, for each set Ki, the values ​​of the resistances R8i and R9i of set Ki are preferably different from those of the resistances R8i and R9i of the other sets Ki.

[0116] By way of example, in a so-called "binary" configuration, for i greater than or equal to 2, the value of the resistor R9i, respectively R8i, with index i, is equal to twice the value of the resistor R9i-1, respectively R8i-1, with index i-1. For example, in each set Ki, the value of the resistors R8i and R9i in the set is a multiple of the value of the resistor R52. For example, in each set Ki, the value of the resistors R8i and R9i is equal to 2(i) 6 times the value of the resistor R52.

[0117] As another example, in a so-called "thermometric" configuration, the value of each resistance R8i, respectively R9i, is determined, for example during a setting or calibration phase, independently of the value of the other resistances R8i, respectively R9i.

[0118] The switches SW8i and SW9i of the Ki assemblies are controlled by a digital trim signal supplied by a circuit not shown. For example, the trim signal comprises i bits, each bit of the trim signal controlling a corresponding Ki assembly. The trim signal is configured so that the switches SW9i and SW8i of the same Ki assembly are in the same on or off state.

[0119] In another, unillustrated example of implementing the Vbias 1 voltage slope adjustment circuit with temperature, the adjustment circuit comprises: a circuit configured to provide a copy of the current Iptat at node 600, namely transistor T2 providing the copy Iptatcl in the embodiment of [Fig. 6] and circuit C3 providing the copy Iptatc2 in the embodiment of [Fig. 7]; and a circuit configured to provide a copy of the current Ibg at node 600, namely circuit C3 providing the copy Ibgc3 in the embodiment of [Fig. 6], and transistor T5 providing the copy Ibgc2 in the embodiment of [Fig. 7], and, in Furthermore, the gain of the circuit providing the copy of the current Ibg at node 600 is adjustable, as is the gain of the circuit providing the copy of the current Iptat at node 600.

[0120] In this way, adjusting the gains of these two circuits allows the slope of the voltage VI, and therefore of the voltage Vbiasl, to be adjusted with the temperature.

[0121] In the described embodiments, when the copy Iptatcl of the current Iptat supplied to node 600 corresponds to a positive current (as in [Fig. 6]), the voltage VI increases with temperature. Conversely, when the copy Iptatc2 of the current Iptat supplied to node 600 corresponds to a negative current, that is, a positive current Iptatc2 drawn from node 600 (as in [Fig. 7]), the voltage VI decreases with temperature.

[0122] Consider, by way of example, the case where the circuit configured to provide the copy of the current Iptat at node 600 comprises the transistor T2 in series with the resistor R52 ([Fig. 6]) and where the circuit configured to provide the copy of the current Ibg at node 600 corresponds to circuit C3 of [Fig. 6]. In this example, the transistor T2 is implemented by several P-channel MOS transistors selectively connected in parallel with each other by switches controlled by a first control signal, such that the current Iptatc1 supplied by the transistor T2 at node 600 is equal to a*Iptatunit, with a a factor, preferably an integer, whose value depends on the state of the first control signal, and Iptatunit a current determined by the current Iptat, for example proportional to or equal to the current Iptat.In this example, transistor T7 (or alternatively transistor T5, although this may result in the drain-source saturation voltage of transistor T7 not being constant, leading to saturation problems for transistor T7 at high currents) is implemented by several N-channel MOS transistors (P-channel when it concerns transistor T5) selectively connected in parallel with each other by switches controlled by a second control signal, so that the current Ibgc3 supplied by transistor T7 at node 600 is equal to [3*Ibgunit], where [3] is a factor, preferably an integer, whose value depends on the state of the second control signal, and Ibgunit is a current determined by the current Ibg, for example, proportional to or equal to the current Ibg. Modifying the values ​​of the gains a and [3] then allows the slope of the voltage VI, and therefore the voltage Vbiasl, to be adjusted with temperature.

[0123] Preferably, in the example above, the values ​​of the gains a and [3 and of the currents Ibgunit and Iptatunit are configured so that, at the nominal operating temperature, the voltage V1 is equal to VDD / 2. In other words, the gains a and [3 are chosen so that, at the nominal operating temperature, a*Iptatunit - [3*Ibgunit = VDD / (2*R52), which fixes the relationship between a and [3, for example, because the currents Iptatunit and Ibgunit at the nominal temperature are known. For example, when at the nominal operating temperature Iptatunit is equal to Ibgunit and to current Idiff with VI equal to VDD / 2, the gains a and [3 satisfy a - [3 = 1.

[0124] As another example, consider the case where the circuit configured to provide a copy of the current Iptat at node 600 corresponds to circuit C3 ([Fig.7]) and where the circuit configured to provide a copy of the current Ibg at node 600 includes transistor T5 in series with resistor R52 ([Fig.7]). In this example, transistor T5 is implemented by several P-channel MOS transistors selectively connected in parallel with each other by switches controlled by a first control signal, so that the current Ibgc2 supplied by transistor T5 at node 600 is equal to [3*Ibgunit], with [3] a factor, preferably an integer, whose value depends on the state of the first control signal, and Ibgunit a current determined by the current Ibg, for example proportional to or equal to the current Ibg.In this example, transistor T7 (or alternatively transistor T2, although this may result in the drain-source saturation voltage of transistor T7 not being constant, leading to saturation problems for transistor T7 at high currents) is implemented by several N-channel MOS transistors (P-channel when it concerns transistor T2) selectively connected in parallel with each other by switches controlled by a second control signal, so that the current Ipatc2 supplied by transistor T7 at node 600 is equal to a * Iptatunit, where a is a factor, preferably an integer, whose value depends on the state of the second control signal, and Iptatunit is a current determined by the current Iptat, for example, proportional to or equal to the current Iptat. Modifying the values ​​of the gains a and [3] then allows the slope of the voltage VI, and therefore the voltage Vbiasl, to be adjusted with temperature.

[0125] Preferably, in the example above, the values ​​of the gains a and [3 and of the currents Ibgunit and Iptatunit are configured so that, at the nominal operating temperature, the voltage V1 is equal to VDD / 2. In other words, the gains a and [3 are chosen so that, at the nominal operating temperature, [3*Ibgunit - a*Iptatunit = VDD / (2*R52), which fixes the relationship between a and [3, for example, because the currents Iptatunit and Ibgunit at the nominal temperature are known. For example, when at the nominal operating temperature Iptatunit is equal to Ibgunit and the current Idiff with VI equal to VDD / 2, the gains a and [3 satisfy [3 - a = 1.

[0126] In the embodiments and variants described above, the resistor R52 is connected between node 600 and node 502. In other embodiments and variants, compared to what has been described previously, the resistor R52 is connected between node 600 and node 504. The implementation of these other embodiments and variants is within the grasp of a person skilled in the art, based on the functional indications given above.

[0127] Figure 10 illustrates an example of a BG circuit that can be used to put into operates the 500 device, it being understood that the person in the trade may plan to use other circuits B G.

[0128] In this example, the BG circuit includes transistor T1 having its source coupled to node 504, for example by resistor R53, its gate connected to node A, and its drain connected to its gate, and transistor T3 having its source coupled to node 504, for example by resistor R56, its gate connected to node B and its drain connected to one terminal 1000 of resistor R55, the other terminal 1002 of resistor R55 being connected to node 502. As an example, a compensation capacitor is connected between gate B of transistor T3 and node 504, to improve stability.

[0129] The BG circuit further includes an NPN bipolar transistor T8 coupling the drain A of transistor T1 to node 502. The transistor T8 has, for example, its collector connected to node A, and its emitter coupled to node 502 by a resistor R61. The base of transistor T8 is connected to terminal 1000 of resistor R55.

[0130] The BG circuit also includes a P-channel MOS transistor T9 mounted in mirror image of transistor TL. Transistor T9 has, for example, its gate connected to node A, its source coupled to node 502, for example via a resistor R62 preferably connected between node 504 and transistor T9. An NPN bipolar transistor T10 of the BG circuit couples the drain of transistor T9 to resistor R61. Transistor T10 has its base connected to the base of transistor T8, and, for example, its collector connected to the drain of transistor T9 and its emitter coupled to resistor R61, for example via a resistor R63 preferably having one terminal connected to transistor T10 and another terminal connected to resistor R61.

[0131] Transistors T1, T8, T9, and T10, and resistors R53, R61, R62, and R63 are sized so that the voltage Vbg across terminal 1000 of resistor R55 is temperature stable, i.e., constant with temperature. Furthermore, bipolar transistors T8 and T10 are, for example, sized so that the current in transistor T8 is of the PTAT type. For example, transistor T10 is implemented by connecting several transistors identical to transistor T8 in parallel, so that the voltage across resistor R63 is of the PTAT type.

[0132] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0133] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Device (500) comprising: a first bandgap circuit (BG) configured to apply a temperature-stable voltage (Vbg) across a first resistive element such that a first current (Ibg) flows through it, and to provide a second current (Iptat) proportional to the absolute temperature; a second resistive element (R) comprising one or more MOS transistors (T) in series and each mounted as a diode, the second resistive element (R) having a first terminal connected to a node (502) for applying a reference potential (GND) and a second terminal coupled to a node (504) for applying a supply potential (VDD); a second circuit (Cl) connected to the first circuit (BG) and configured to provide a first copy (Ibgcl) of the first current (Ibg) and such that said first copy flows through the second resistive element (R);and a third circuit (C2) connected to the first circuit (BG) and configured to: - provide a copy (Iptatcl) of the second current (Iptat), provide a first control voltage (VI) from said copy of the second current, and apply the first control voltage to a back gate (600) of the transistors (T) of the resistive element, or - provide a second copy (Ibgc3; Ibgc2) of the first current (Ibg) and a copy (Iptatcl; Iptatc2) of the second current (Iptat), provide a first control voltage (VI) from a difference (Idiff) between the second copy of the second current and the copy of the first current, and apply the first control voltage to a back gate (600) of the transistors (T) of the second resistive element.;

2. Device according to claim 1, wherein the second terminal of the second resistive element (R) is configured to provide a bias voltage (Vbiasl) to a variable capacitance (Cvar).

3. Device according to claim 2, wherein: the device (500) comprises the variable capacitance (Cvar); the variable capacitance (Cvar) is configured to receive a tuning voltage (Vtune) and the bias voltage (Vbiasl); and a difference between the tuning voltage and the bias voltage determines a value of the capacitance.

4. Device according to claim 1, wherein: the second resistive element (R) is in series with a resistor (R51); the second terminal of the second resistive element (R) is configured to provide a first bias voltage (Vbias1) to a variable capacitance (Cvar) and is connected to a first terminal of said resistor (R51); and a second terminal of said resistor (R51) is configured to provide a second bias voltage (Vbias2) to the variable capacitance.

5. Device according to claim 4, wherein: the device (500) comprises the variable capacitance (Cvar); the variable capacitance (Cvar) is configured to receive a tuning voltage (Vtune) and the first and second bias voltages (Vbias1, Vbias2); and a difference between the tuning voltage and the first bias voltage and a difference between the tuning voltage and the second bias voltage determine a value of the capacitance.

6. Device according to claim 3 or 5, wherein the device (500) comprises a voltage-controlled oscillator (VCO) comprising the variable capacitance (Cvar).

7. Device according to claim 6, wherein the device (500) comprises a tuning voltage supply circuit (Vtune), said circuit comprising, for example, a phase-locked loop.

8. Device according to any one of claims 1 to 7, wherein the third circuit (C2) comprises a resistor (R52) having a first terminal connected to the reference potential application node (502) or the supply potential application node (504) of said resistor (R52) being configured to provide the first control voltage (VI) and being connected to the rear gate (600) of the transistors (T) of the second resistive element (R).

9. Device according to claim 8, wherein the third circuit (C2) includes a smoothing capacitor (Cf) connected between the back gate (600) of the transistors (T) of the second resistive element (R) and the node (502) for applying the reference potential (GND).

10. Device according to any one of claims 1 to 9, wherein the transistors (T) of the second resistive element (R) are all N-channel transistors or are all P-channel MOS transistors.

11. A device according to any one of claims 1 to 10, in which the transistors (T) of the second resistive element (R) are all implemented on silicon on insulator.

12. Device according to any one of claims 1 to 11, wherein the third circuit (C2) includes a circuit for adjusting a slope of the first control voltage (VI) with the temperature.

13. Device according to claim 12 taken in its dependence on claim 8, wherein the adjustment circuit comprises one or more assemblies (K1, K2, K3) each comprising: - a first resistor (R91, R92, R93) and a first switch (SW91, SW92, SW93) in series between the node (504) for applying the supply potential (VDD) and the second terminal of the resistor (R52) providing the first control voltage (VI), and - a second resistor (R81, R82, R83) and a second switch (SW81, SW82, SW83) in series between the second terminal of the resistor providing the first control voltage (VI) and the node (502) for applying the reference potential (GND), a value of the second resistor of the assembly being identical to a value of the first resistor of the assembly.

14. Device according to claim 13, wherein: the adjustment circuit comprises several of said assemblies (K1, K2, K3); and a value of the first resistance (R91, R92, R93) is different in each of said assemblies.

15. Device according to claim 12, wherein: the first control voltage (VI) is determined by the difference between the second copy (Ibgc3; Ibgc2) of the first current (Ibg) and the copy (Iptatcl; Iptatc2) of the second current (Iptat); the slope adjustment circuit comprises a fourth circuit (C3, T7; T5) configured to provide the second copy of the first current (Ibg), and a fifth circuit (T2; C3, T7) configured to provide the second copy of the second current (Iptat), a gain of the fourth circuit and a gain of the fifth circuit being adjustable so as to permit the adjustment of the slope of the first control voltage (VI) with temperature.

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