Low noise crystal oscillator using self timed intermittent dc biasing

Abstract

This application relates to a low-noise crystal oscillator using self-timed intermittent DC-coupled biasing. The crystal oscillator includes: a P-type metal-oxide-semiconductor transistor, an N-type metal-oxide-semiconductor transistor, a feedback capacitor disposed between one of a first and second gate node and a source node; a shunt capacitor disposed between one of a power supply node and a ground node and the source node; an AC coupling capacitor disposed between the first node and the second gate node; a crystal disposed between one of the first and second gate nodes and one of the ground node and the power supply node; a first DC-coupled network that couples a first bias node to the first gate node according to a first gate voltage state of the first gate node; and a second DC-coupled network that couples a second bias node to the second gate node according to a second gate voltage state of the second gate node.

Description

Technical Field

[0001] This disclosure relates to a crystal oscillator, and more particularly to a crystal oscillator that uses self-timed intermittent DC coupling for biasing to eliminate noise. Background Technology

[0002] In this disclosure, a signal is defined as a voltage value that carries specific information and whose voltage is variable, and which may change over time. The voltage value of the signal at any given moment represents the state at that moment. Logic signals have two states: low and high; a logic signal is considered high when its voltage value exceeds a predetermined threshold, and low otherwise. Referring to a logic signal Q, the phrases "Q is high" or "Q is low" respectively represent "Q is in a high state" or "Q is in a low state". Note that the threshold of the first logic signal may differ from the threshold of the second logic signal.

[0003] A clock signal (referred to here as "clock") is defined as a logic signal that transitions periodically between low and high states. A clean clock signal is characterized by maintaining a consistent periodicity in its transitions between low and high states, while noise in the clock signal disrupts this periodicity.

[0004] Crystal oscillators capable of generating low-noise and clean clock signals are in high demand. Figure 1A circuit diagram of a prior art crystal oscillator 100, disclosed by Lin in U.S. Patent 10,666,197, is shown. The oscillator includes a crystal 120, a PMOS (P-channel metal-oxide-semiconductor) transistor 111, an NMOS (N-channel metal-oxide-semiconductor) transistor 112, three capacitors 141, 142, and 143, and two resistors 131 and 132. Crystal 120 determines the oscillation frequency of the oscillation signal VOSC, which is a clean and periodic signal that can be used as a clock signal. Capacitor 142 provides strong alternating current (AC) coupling between the gates of NMOS transistor 112 and PMOS transistor 111, and together with capacitors 141 and 143, establishes a negative impedance to the oscillation signal VOSC to maintain oscillation. Resistors 131 and 132 provide DC coupling from the first bias node VB131 and the second bias node VB132 to the PMOS transistor 111 and NMOS transistor 112, respectively, to establish appropriate bias conditions. The crystal oscillator 100 is able to generate a low-noise clock signal primarily because the NMOS transistor 112 and the PMOS transistor 111 operate in tandem, forming a regenerative circuit, thus exhibiting superior performance compared to existing technologies using only a single PMOS or NMOS transistor. However, the crystal oscillator 100 still has a drawback: resistors 131 and 132 can become significant noise sources, potentially introducing noise into the oscillation signal VOSC.

[0005] The current expectation for crystal oscillators is not only to use NMOS and PMOS transistors to provide regeneration functions, but also to reduce the noise impact from the bias circuit. Summary of the Invention

[0006] In some implementations, one of the objectives of this disclosure is, but not limited to, using PMOS transistors and NMOS transistors to operate in tandem to form a regenerative network to establish oscillations, and employing a bias scheme that utilizes intermittent DC coupling synchronized with the oscillations to reduce noise effects.

[0007] In some embodiments, the crystal oscillator includes: a P-channel metal-oxide-semiconductor transistor whose gate, source, and drain are respectively connected to a first gate node, a source node, and a ground node; an N-channel metal-oxide-semiconductor transistor whose gate, source, and drain are respectively connected to a second gate node, the source node, and a power supply node; a feedback capacitor disposed between the first gate node or the second gate node and the source node; a shunt capacitor disposed between the power supply node and the ground node and the source node; an AC coupling capacitor disposed between the first gate node and the second gate node; a crystal disposed between the first gate node and the second gate node and the ground node and the power supply node; a first DC coupling network for coupling a first bias node to the first gate node according to a first gate voltage state of the first gate node; and a second DC coupling network for coupling a second bias node to the second gate node according to a second gate voltage state of the second gate node. Attached Figure Description

[0008] Figure 1 A schematic diagram of a crystal oscillator in the prior art is shown; and

[0009] Figure 2 A schematic diagram of a crystal oscillator is shown for one embodiment of the present disclosure.

[0010] Symbol Explanation

[0011] 100: Crystal Oscillator

[0012] 111, 112: Transistor

[0013] 120: Crystal

[0014] 131, 132: Resistors

[0015] 141, 142, 143: Capacitors

[0016] 200: Crystal Oscillator

[0017] 211, 212: Transistors

[0018] 220: Crystal

[0019] 241: Feedback capacitor

[0020] 242: AC coupling capacitor

[0021] 243: Shunt capacitor

[0022] 250: Diode-based DC-coupled network

[0023] 251: Transistor

[0024] 252: First resistor

[0025] 260: Diode-based DC-coupled network

[0026] 261: Transistor

[0027] 262: Second resistor

[0028] NG1: First gate node

[0029] NG2: Second gate node

[0030] NS: Source node

[0031] VB1, VB131: First bias node

[0032] VB2, VB132: Second bias node

[0033] VDD: Power Node

[0034] VG1: First gate voltage

[0035] VG2: Second gate voltage

[0036] VOSC: Oscillation signal Detailed Implementation

[0037] This disclosure relates to crystal oscillators. While several embodiments are described in this specification and are considered preferred embodiments of this disclosure, it should be understood that this disclosure can be implemented in various ways and is not limited to the specific embodiments described below, nor to the specific implementations of the features in those embodiments. Furthermore, to avoid obscuring the essential points of this disclosure, certain well-known details have not been shown or described.

[0038] Those skilled in the art will be familiar with the microelectronics-related terms and basic concepts in this disclosure, such as "voltage," "signal," "logic signal," "clock," "source follower," "oscillator," "bias," "alternating current (AC)," "direct current (DC)," "power supply," "ground," "resistance," "capacitor," "impedance," "CMOS (Complementary Metal-Oxide-Semiconductor)," "NMOS (N-channel Metal-Oxide-Semiconductor) transistor," and "PMOS (P-channel Metal-Oxide-Semiconductor) transistor." These terms are used in the field of microelectronics, and their related concepts are understandable to those skilled in the art; therefore, detailed explanation is unnecessary herein.

[0039] Those skilled in the art can recognize the symbol for a MOS (Metal-Oxide-Semiconductor) transistor and can identify the "source," "gate," and "drain" terminals associated with PMOS (P-channel Metal-Oxide-Semiconductor) and NMOS (N-channel Metal-Oxide-Semiconductor) transistors. For the sake of brevity, the "source terminal," "gate terminal," and "drain terminal" may be simply referred to as "source," "gate," and "drain," respectively, and their meanings should be understandable from the context without causing confusion. Those skilled in the art can understand circuit diagrams containing PMOS and / or NMOS transistors without needing a detailed description of the interconnections between the components in the diagram.

[0040] A MOS transistor, whether PMOS or NMOS, is said to be configured as a diode topology when its gate is electrically connected to its drain terminal.

[0041] A MOS transistor has a critical voltage; when the voltage between the gate and the source is less than this critical voltage, the MOS transistor is in a non-conducting state.

[0042] This disclosure is described from an engineering perspective. For example, regarding two variables X and Y, when describing "X equals Y," it means "X is approximately equal to Y," that is, "the difference between X and Y is within the specified engineering tolerance." Similarly, when describing "X is zero," it means "X is approximately zero," that is, "X is within the specified engineering tolerance." Furthermore, when describing "X is significantly less than Y," it means "X is negligible compared to Y," that is, "the ratio between X and Y is within the specified engineering tolerance, making X negligible compared to Y."

[0043] In this disclosure, a "power node" is defined as a circuit node having a voltage approximately equal to the power supply voltage, which is greater than zero but may have slight high-frequency fluctuations. Conversely, a "ground node" refers to a circuit node with a voltage approximately zero, although slight high-frequency fluctuations may still be present. In this disclosure, "VDD" is used to denote a power node, and the ground symbol is used to denote a ground node, and these symbols are readily recognizable to those skilled in the art.

[0044] like Figure 2As shown, in one embodiment of this disclosure, the crystal oscillator 200 includes: a crystal 220 disposed between a first gate node NG1 and a ground node; a PMOS transistor 211 whose gate, source, and drain are respectively connected to the first gate node NG1, the source node NS, and the ground node; an NMOS transistor 212 whose gate, source, and drain are respectively connected to the second gate node NG2, the source node NS, and the power supply node VDD; a feedback capacitor 241 disposed between the first gate node NG1 and the source node NS; a shunt capacitor 243 disposed between the source node NS and the ground node; an AC coupling capacitor 242 disposed between the first gate node NG1 and the second gate node NG2; a first diode-based DC coupling network 250 for coupling a first bias node VB1 to the first gate node NG1; and a second diode-based DC coupling network 260 for coupling a second bias node VB2 to the second gate node NG2.

[0045] Both the first bias node VB1 and the second bias node VB2 have low impedance characteristics, thereby providing a well-defined, stable, and smooth DC bias voltage. In one embodiment, by way of example but not limitation, the first bias node VB1 is a ground node, and the second bias node VB2 is a power supply node VDD.

[0046] The first gate voltage VG1 at the first gate node NG1 is an oscillation signal with a frequency approximately equal to the resonant frequency of crystal 220. PMOS transistor 211 is configured as a source follower and, together with feedback capacitor 241 and shunt capacitor 243, forms a regenerative network. This regenerative network presents a negative impedance at the first gate node NG1, thereby maintaining the oscillation of the first gate voltage VG1. NMOS transistor 212 is also configured as a source follower. AC coupling capacitor 242 ensures that the second gate voltage VG2 at the second gate node NG2 is approximately equal to the first gate voltage VG1 in AC characteristics. This configuration allows NMOS transistor 212 and PMOS transistor 211 to operate in tandem, thereby enhancing the performance of their source follower functions.

[0047] Crystal oscillator 200 and Figure 1The prior art crystal oscillator 100 shown is generally similar, except that the crystal oscillator 200 uses two diode-based DC coupling networks 250 and 260 to provide DC bias coupling for the PMOS transistor 211 and the NMOS transistor 212, instead of using only two resistors. The first diode-based DC coupling network 250 includes a first resistor 252 and an NMOS transistor 251 connected in diode form. The source terminal of the NMOS transistor 251 is connected to a first bias node VB1, the drain terminal of the NMOS transistor 251 is coupled to a first gate node NG1 via the first resistor 252, and the gate terminal of the NMOS transistor 251 is connected to its drain terminal. Similarly, the second diode-based DC-coupled network 260 includes a second resistor 262 and a PMOS transistor 261 connected in the form of a diode. The source terminal of the PMOS transistor 261 is connected to the second bias node VB2, the drain terminal of the PMOS transistor 261 is coupled to the second gate node NG2 via the second resistor 262, and the gate terminal of the PMOS transistor 261 is connected to its drain terminal.

[0048] Using a diode-based DC coupling network to establish the bias condition offers the advantage of low noise. When the first gate voltage VG1 of the first gate node NG1 is below a specific voltage (related to the critical voltage of the NMOS transistor 251), the NMOS transistor 251 is essentially non-conductive. For example, if the first bias node VB1 is grounded and the first gate voltage VG1 oscillates between -1V and 1V, while the critical voltage of the NMOS transistor 251 is 0.6V, then when the first gate voltage VG1 is between -1V and 0.6V, the diode-based DC coupling network 250 is essentially non-conductive; when the first gate voltage VG1 is between 0.6V and 1V, the resistance of this network is approximately equal to the resistance of the first resistor 252. Therefore, compared to existing techniques that use only resistors for DC coupling, this method significantly reduces noise impact. The same principle applies to the second diode-based DC-coupled network 260, which is essentially non-conductive when the second gate voltage VG2 of the second gate node NG2 is higher than a specific voltage associated with the critical voltage of the PMOS transistor 261.

[0049] In different embodiments, it is possible to Figure 2The two diode-based DC coupling networks 250 and 260 shown can be modified, adjusted, or replaced in various ways. For example, the NMOS transistor 251 connected as a diode can be replaced with a PMOS transistor connected as a diode; the first resistor 252 and the NMOS transistor 251 connected as a diode can be interchanged, such that the source of the NMOS transistor 251 is connected to the first bias node VB1 through the first resistor 252, while the drain is directly connected to NG1; the first resistor 252 can also be repositioned between the drain and gate of the NMOS transistor 251, while the gate of the NMOS transistor 251 is directly connected to the first gate node NG1, and so on. Regardless of the specific configuration, the following two objectives must be met: under static conditions, DC coupling should be provided so that the bias voltages of the first bias node VB1 and the second bias node VB2 can be coupled to the gates of the PMOS transistor 211 and the NMOS transistor 212, respectively, to establish bias conditions. Under dynamic conditions, when the crystal oscillator 200 oscillates, the DC-coupled network should be effectively non-conducting for most of the oscillation period and synchronized with the timing of the oscillation, thereby minimizing the noise impact from DC coupling. In summary, the DC coupling in some embodiments of this disclosure is performed in a self-timing, intermittent manner and synchronized with the oscillation, thereby significantly reducing the noise impact.

[0050] Although, Figure 2 The crystal 220 shown is positioned between the first gate node NG1 and the ground node, but it should be understood that positioning the crystal 220 between the first gate node NG1 and the power node VDD is equally feasible. This is because the power node VDD is considered "AC ground" and therefore has equivalent functionality to the ground node in terms of AC characteristics. Similarly, positioning the shunt capacitor 243 between the source node NS and the power node VDD is functionally equivalent to positioning the shunt capacitor 243 between the source node NS and the ground node.

[0051] Placing the feedback capacitor 241 between the second gate node NG2 and the source node NS is functionally equivalent to placing it between the first gate node NG1 and the source node NS. This equivalence stems from the effect of the AC coupling capacitor 242, which effectively couples the first gate node NG1 and the second gate node NG2, making them substantially identical in AC characteristics. Furthermore, placing the crystal 220 between the second gate node NG2 and the ground node is functionally equivalent to placing it between the first gate node NG1 and the ground node. In practice, the crystal 220 can be placed between either the first gate node NG1 or the second gate node NG2 and either the ground node or the power node VDD; these four possible configurations are functionally equivalent.

[0052] Although the embodiments of this disclosure are described above, they are not intended to limit the disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on its explicit or implicit content. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the claims of this specification.

Claims

1. A crystal oscillator, comprising: A P-channel metal-oxide-semiconductor transistor, wherein its gate, source and drain are respectively connected to a first gate node, a source node and a ground node; An N-channel metal-oxide-semiconductor transistor, wherein its gate, source and drain are respectively connected to a second gate node, the source node and a power supply node; A feedback capacitor is disposed between the source node and one of the first gate node or the second gate node; A shunt capacitor is disposed between the source node and one of the power node and the ground node; An AC coupling capacitor is disposed between the first gate node and the second gate node; A crystal is disposed between one of the first gate node and the second gate node and one of the ground node and the power node; A first DC coupling network for coupling a first bias node to the first gate node according to the state of a first gate voltage of the first gate node; and A second DC coupling network is used to couple a second bias node to the second gate node according to the state of a second gate voltage of the second gate node.

2. The crystal oscillator of claim 1, wherein both the first bias node and the second bias node have low impedance.

3. The crystal oscillator of claim 2, wherein the first DC-coupled network is substantially non-conductive when the first gate voltage is below a specific voltage.

4. The crystal oscillator of claim 3, wherein the first DC-coupled network comprises a metal-oxide-semiconductor transistor connected in the form of a diode and a resistor, and the particular voltage is determined by a threshold voltage of the metal-oxide-semiconductor transistor connected in the form of a diode.

5. The crystal oscillator of claim 2, wherein the second DC-coupled network is substantially non-conductive when the second gate voltage is higher than a specific voltage.

6. The crystal oscillator of claim 5, wherein the second DC-coupled network comprises a metal-oxide-semiconductor transistor connected in the form of a diode and a resistor, and the particular voltage is determined by a threshold voltage of the metal-oxide-semiconductor transistor connected in the form of a diode.

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