Transmitting module and method for sending differential signals in a serial bus system

Abstract

Title: Transmitting module and method for sending differential signals in a serial bus system The transmitting module 121 has a first transmitting stage 121A, a second transmitting stage 121B, a third transmitting stage 121C and a fourth transmitting stage 121D, the first to fourth transmitting stages being connected in a full bridge in which the first and fourth transmitting stages are connected in series and the third and second transmitting stages are connected in series, each transmitting stage has at least two transistors TM_CH1, TM_CHn, the first and third transmitting stages each have a polarity inversion diode D1, D2. Figure for abstract: Fig. 10

Description

Title of the invention: Transmission module and method for sending differential signals in a serial bus system

[0001] The present invention relates to a transmission module and a method for sending differential signals in a serial bus system, in which in particular a voltage source of Vcc = 3.3 V is used for transmission / reception devices. State of the art Differential signals are used, for example, in CAN bus systems or in Ethernet bus systems according to the 10-BASE-T1S standard for data transmission on a bus. Devices in vehicles and / or other technical devices are connected to the bus. The signals signal in series the data that must be transmitted for communication between the devices via the bus. The devices form participant stations on the bus, which are also called nodes. Each participant station has at least one transmitting / receiving device, also called a transceiver.

[0003] For data transmission via CAN, Classical CAN and CAN FD are standardized, for example, in the international standard ISO11898-1:2015. CAN FD is often used today at a bit rate of 2 Mbit / s and an arbitration bit rate of 500 kbit / s. Transceiver devices called CAN SIC allow the use of CAN FD with up to 8 Mbit / s. For higher data rates of up to 20 Mbit / s, CAN XL is currently available. In all bus systems based on the mentioned CANs, a bus signal CAN_H and, ideally, a bus signal CAN_L are activated separately on a bus for a transmit TxD signal. For this purpose, at least in the first communication phase, a bus status is actively activated in the bus signals CAN_H and CAN_L. The other state of the bus is not energized and is established due to a terminating resistance of the bus lines or bus strands.Due to the differently excited states, the shapes of the CAN_H, CAN_L bus signals may deviate from the ideal signal shape in a real bus system having branch lines, faulty adaptations etc. This may lead to errors when evaluating the bus signals received by the bus.

[0004] Nowadays in CAN bus systems a voltage source of Vcc = 5 V is used for the transmitting / receiving devices (transceiver) in order to produce the different voltage levels for the differential signals on the bus.

[0005] In order to reduce costs, it is considered to use a voltage source of Vcc = 3.3 V for the transmitting / receiving devices. Such a lowering of the supply voltage would be advantageous, since the voltage of 3.3 V is used in many micro-control units today. In addition, many other modules could also be powered by this voltage.

[0006] Lowering the supply voltage from 5 V to 3.3 V only offers the desired advantage if already existing devices for a CAN bus with a supply voltage of 5 V can continue to be used. For this purpose, any number of 5 V participant stations (5 V nodes) and 3 V participant stations (3.3 V nodes) must be able to communicate simultaneously on a bus.

[0007] It must be taken into account in this respect that the current CAN bus has, due to the differential CAN_H, CAN_L signals, on average a voltage of Vcc / 2, i.e. 2.5 V. This is achieved by the fact that each bus participant station strives via a standardized resistance network, by means of a current source, to maintain the bus more or less exactly at 2.5 V. The bus voltage substantially follows the lowest node voltage (voltage at the participant station), thus typically being slightly lower than 2.5 V.

[0008] When transmitting, a CAN participant station (node) can connect its transmitting / receiving device exactly between a dominant state and a recessive state. For the dominant state, it excites the CAN_H level to about 3.5 V and the CAN_L level to about 1.5 V. The difference between the CAN_H level and the CAN_L level is then in a range of 2 V. A minimum of 1.5 V is required by the international standard ISO11898-1:2015. The transition from the recessive state to the dominant state or vice versa is carried out as symmetrically as possible around the virtual line 0, which is at Vcc / 2. The sum of the CAN_H and CAN_L levels remains as much as possible at 5 V.

[0009] A serious problem is that even small deviations in the mV range result in already significant electromagnetic emissions, which cause EMV disturbances (EMV = electromagnetic compatibility) of other electrical devices. There are therefore maximum permissible electromagnetic emission requirements, which must be met by each transmitting / receiving device (transceiver). However, these requirements on electromagnetic emissions represent a very big challenge.

[0010] In relation to CAN FD, in transceivers for CAN-SIC or transceivers for CAN-XL in the arbitration phase, which is also referred to as SIC Mode or SIC operating type, a third state, the sic state, must be produced in addition to the recessive (rec) and predominant (dom) states. To meet the emission requirements of the IEC62228-3 standard, a common mode voltage of the bus lines must be maintained within narrow limits. for CAN_H, CAN_L signals in three transmission states, namely recessive, predominant, sic. The common-mode voltage is generated on a phase-locking coil, which is used in particular during a certification measurement to check compliance with the IEC62228-3 standard. The phase-locking coil is also called Common-Mode-Choke (CMC). The task of the phase-locking coil is to allow differential signals (DM = differential mode) to pass through as much as possible without influence and to suppress common-mode signals (CM = common mode) as completely as possible. However, in real operation, the phase-locking coil produces a differential signal with an unwanted common-mode signal superimposed on it at the output from a differential signal without a common-mode component at the input.This is unfavorable because it is injected from the bus side thus directly into the CAN bus and is visible to other CAN modules.

[0011] The requirements are even higher in mixed operation if there is at least one participant station on the bus having a transmitting / receiving device (transceiver) which excites other voltage levels for CAN_H and CAN_L in the dominant state than the transmitting / receiving devices (transceiver) of other participant stations. The reasons for this are as follows.

[0012] If parameters of the physical layer are changed, reestablishing interoperability between the participant stations is usually very expensive. It is therefore very desirable that a 3.3 V CAN bus works exactly like the 5 V CAN bus, except that the voltages on the bus are different. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model).

[0013] Thus a 3.3 V node (participant station) must carry for the dominant state on the bus, the CAN_H signal at approximately 3 V and the CAN_L signal clearly below 1 V, in order to exceed the specified minimum level difference of 1.5 V.

[0014] A peculiarity in the mixed operation is that a 5 V node puts the bus on 2.5 V in the recessive phase, while a 3 V node aims on the bus about 1.65 V. By raising the CAN_L voltage in the CAN to 3.3 V in the direction of 1 V, the voltage in the recessive state can be raised to about 1.9 V. But there remains a difference of about 500 to 600 mV between the 5 V node and the 3.3 V node. In a configuration of this kind, the bus takes any voltage between 1.9 V and 2.5 V and it constantly passes a current in the directions of the 3.3 V node, but which is in the range below the microampere.

[0015] If then however a participant station (node) starts to transmit and goes into the dominant state, the participant station (node) takes the operation not of "its" zero line, but of the mixed operation. Consequently the sum of the levels of CAN_H and CAN_L changes when switching and again when reconnecting.

[0016] This predictably leads to large EMV emissions. Mixed operation is therefore not possible so simply. Statement of the invention

[0017] The present invention therefore aims at a transmission module and a method for sending differential signals in a serial bus system, which solve the problems mentioned above. In particular, it is sought that the transmission module and the method for sending differential signals in a serial bus system, which allow the compensation of disturbing quantities, which affect the transmission behavior of the transmission module.

[0018] This is achieved by a transmitter module for a differential signal transmitter module in a serial bus system comprising a first transmitter stage for producing at least one transmitter current for a first signal to be sent over a bus of the bus system, a second transmitter stage for producing at least one transmitter current for a second signal to be sent over the bus as a differential signal with respect to the first signal, a third transmitter stage for producing at least one transmitter current for the first signal and a fourth transmitter stage for producing at least one transmitter current for the second signal, in which the first to fourth transmitter stages are connected in a full bridge in which the first and fourth transmitter stages are connected in series and the third and second transmitter stages are connected in series,wherein each of the transmitter stages has at least two transistors for producing at least one transmitter current and wherein the first and third transmitter stages are respectively connected by a polarity reversal diode to a bus voltage supply terminal for protection against a positive return feed into a terminal for the bus voltage supply and a negative return feed from a terminal for ground.

[0019] The described transmitter module makes operation in a bus system according to the international standard for CAN possible even with a voltage supply of 3.3 V. Furthermore, operation in a bus system in which there are 3.3 V and 5 V participant stations and thus mixed operation takes place is also possible. In this respect, it is ensured at low cost, even during mixed operation, in a CAN bus system that the limit values ​​required for the transmission of a transmitting / receiving device can be observed even for CAN XL. The transmitter module meets in particular the standard IEC62228-3, which sets limit values ​​to be respected for the dom, sic and rec bus states.

[0020] Thus, for example, the transmission module described above can, in the sic state, adapt the impedance between the bus lines for the CAN_H and CAN_L signals very well to the characteristic impedance or to the impedance of the bus line used. For the impedance Zw of the bus line used, Zw = 100 Ohm or Zw = 120 Ohm are used. The transmission module thus reduces reflections and therefore allows operation in the bus system at higher bit rates.

[0021] The described transmitter module enables a time-staged and controlled switching operation by dividing its four transmitter stages into n parts and can represent in particular the required 3V-CAN levels. A switch-on according to a Gaussian error function can thus be achieved. This makes it possible to set a smooth behavior during the switch-on operation. The possible variation of time stages during switch-on prevents the occurrence of a narrowband frequency line in the radiation frequency spectrum.

[0022] Alternatively, it is possible to carry out with the described transmission module a staged connection operation controlled by fixed time steps and varied voltage steps. It is also possible in this way to influence the transmission behavior of the transmission module so as to comply with the limit values ​​given in advance.

[0023] Furthermore, the described transmission module can reduce effects due to the asymmetrical behavior of the transmission stages, which can appear in the transmission states dom, sic, rec and make the transmission worse. The transmission module prevents unequal behavior of components in the transmission stages A, B (Effect 1) of a full bridge, so as to minimize or prevent in the dom state a variation of the Common-Mode voltage compared to the rec state. Furthermore, the transmission module can prevent unequal behavior of components in transmission stages A / D and C / B of the full bridge (Effect 2), so as to minimize or prevent in the sic state a variation of the Common-Mode voltage compared to the rec state.This is particularly advantageous, since only if, from the Common-Mode level of the rec state, the Common level in the dom state and in the sic state adapt to those of the rec state, can a sufficient emission result be obtained, however the causes which lead to the behavior of Effect 1 may be other than those which lead to Effect 2.

[0024] The invention is characterized, in addition to the point mentioned above, by the following points:

[0025] Point 2 transmission module following point 1, in which the output terminals of the full bridge are provided for connection to a bus terminating resistor.

[0026] Item 3 transmitting module according to one of the above items, wherein the polarity reversal diode is a connected polarity reversal diode, which can be shunted or short-circuited.

[0027] Point 4 transmitting module according to one of the points above, in which the first and third transmitting stages are connected by the same polarity inversion diode to the bus voltage supply terminal.

[0028] Item 5 transmitting module according to one of the above items, wherein the polarity reversal diode is mounted in a polarity reversal circuit, which has besides a first transistor a second transistor and a resistor and wherein the second transistor has an on-state resistance value which is much smaller than the resistance value of the resistor.

[0029] Item 6 emission module according to item 5, wherein the drain terminal of the first transistor is connected to the anode of the polarity reversal diode, wherein the source terminals of the first and second transistors are connected to the cathode of the polarity reversal diode, wherein the gate terminal of the first transistor is connected to the drain terminal of the second transistor and is via the resistor connected to the terminal for ground and, wherein the gate terminal of the second transistor is connected to the terminal for the bus voltage supply.

[0030] Point 7 emission module according to point 5 or 6, in which a gate terminal to source terminal section of the first transistor has a protection filter against pulse type disturbances.

[0031] Item 8 transmitting module according to one of the above items, wherein the second and fourth transmitting stages each have a polarity reversal diode for protection against a positive return supply in the terminal for the bus voltage supply and a negative return supply from a terminal for ground and wherein the polarity reversal diode of the second transmitting stage and the fourth transmitting stage is a pn type polarity reversal diode, which is a parasitic of a transistor and which is wired in a fixed manner so that the polarity reversal diode cannot be shunted or short-circuited.

[0032] Item 9 transmitting module according to one of the above items, in which the polarity reversal diodes are shaped to establish a median voltage of about 1.9 V when the transmitting module operates with a voltage supply of about 3.3 V.

[0033] Item 10 transmitting module according to one of the above items, further comprising a control circuit for controlling connectable components of the first to fourth transmitting stages depending on a digital transmitting signal and an established type of operation for the transmitting module.

[0034] Item 11 transmission module according to item 10, in which the control circuit is designed for the staged and controlled connection of at least two current stages of the transmission stages.

[0035] Point 12 emission module according to one of the points above, in which each of the emission stages has a current mirror composed of two transistors producing at least one emission current.

[0036] Item 13 emission module according to one of items 1 to 11, in which each of the emission stages has at least two current stages, which are connected in parallel, in which each of the at least two current stages has a transistor for producing the at least one emission current, in which the at least two transistors have different dimensions and in which a number n of the at least two current stages is the same for each of the first to fourth emission stages, n being a natural number greater than 1.

[0037] Point 14 emission module according to one of the points above, in which the at least two transistors producing the at least one emission current are CMOS transistors.

[0038] Item 15 emission module according to one of the above items, wherein the CMOS transistors of the first emission stage are PMOS transistors, wherein the CMOS transistors of the second emission stage are NMOS transistors, wherein the CMOS transistors of the third emission stage are PMOS transistors and wherein the CMOS transistors of the fourth emission stage are NMOS transistors.

[0039] The invention also relates to a transmission / reception device for a participant station for a serial bus system comprising a transmission module according to the invention and a reception module for receiving signals from the bus.

[0040] The invention also relates to a participant station for a serial bus system comprising a transmitting / receiving device according to the invention and a communication control device for controlling the communication in the bus system and for generating a digital transmission signal for controlling the first to fourth transmission stages.

[0041] According to one embodiment, the participant station according to the invention is designed for communication in a bus system, in which at least occasionally collision-free exclusive access of a participant station to the bus of the bus system is ensured.

[0042] The invention further relates to a method for sending differential signals in a serial bus system in which the method is carried out by a transmission module and in which the method has the stages, production by a first transmission stage, of at least one transmission current for a first signal to be sent on a bus of the bus system, production, by a second transmission stage, of at least one transmission current for a second signal which is to be sent on the bus as a differential signal with respect to the first signal, production, by a third transmission stage, of at least one transmission current for the first signal and production, by a fourth transmission stage, of at least one transmission current for the second signal, in which the first to fourth transmission stages are connected in a full bridge in which the first to fourth transmission stages are connected in series and the third and second transmission stages are connected in series,wherein each of the transmitter stages has at least two transistors for producing the at least one transmitter current and wherein the first and third transmitter stages are respectively connected by a polarity reversal diode to a terminal for the bus voltage supply for protection against a positive return supply in a terminal for the bus voltage supply and negative return supply from a terminal for ground.

[0043] The method offers the same advantages as those mentioned with regard to the transmission module.

[0044] Other possible embodiments of the invention also include combinations not explicitly mentioned of features or embodiments described before or in the following. With reference to the exemplary embodiments, the skilled person will also add individual aspects as an improvement or supplement to the respective basic form of the invention. Description of the drawings

[0045] The invention will be explained in a more precise manner with reference to the attached drawing and with the aid of exemplary embodiments. In the drawing:

[0046] [Fig. 1] is a block diagram of a bus system according to a first exemplary embodiment;

[0047] [Fig.2] is a diagram illustrating the structure of a message, which is sent from a first participant station of the bus system according to the first exemplary embodiment;

[0048] [Fig. 3] is a time-dependent curve of a digital transmission signal in operation of the bus system in the first and / or second participant station, which is connected to at least one first participant station on the same bus of the bus system;

[0049] [Fig.4] is a curve as a function of time of CAN_H and CAN_L bus signals at the second participant station according to the first embodiment example;

[0050] [Fig.5] is a curve as a function of time of a differential VDIFF voltage of the CAN_H and CAN_L bus signals at the first and second participant stations according to the first exemplary embodiment;

[0051] [Fig.6] is a time-dependent curve of a digital reception signal that the first or second participant station produces from a signal received from the bus, which is based on the transmission signal of [Fig.3];

[0052] [Fig.7] is a time-dependent curve of CAN_H and CAN_L bus signals, which can be produced on the bus by the first participant station according to the first embodiment example from the transmission signal of [Fig.3];

[0053] [Fig.8] is an example of a time-dependent curve of a digital transmission signal, which is to be transformed in an arbitration phase (SIC operating type of a transmission module) into bus signals CAN_H, CAN_L for a bus of the bus system of [Fig.l];

[0054] [Fig.9] is the time-dependent curve of the bus signals CAN_H, CAN_L when changing between a recessive bus state and a dominant bus state and back to the recessive bus state, which are sent to the bus in the arbitration phase (SIC operation type) based on the transmit signal of [Fig.8];

[0055] [Fig. 10] is a diagram of a transmission module for a participant station of the bus system according to the first embodiment example;

[0056] [Fig. 11] is a time diagram representing the switching on of various current stages of a transmitter stage for a first special example of the transmitter module of [Fig. 10];

[0057] [Fig. 12] shows a detail of a transmitter stage for a second special example of the transmitter module of [Fig. 10];

[0058] [Fig. 13] is a diagram of a transmission module for a participant station of the bus system according to a second exemplary embodiment;

[0059] [Fig. 14] is a diagram of a transmission module for a participant station of the bus system according to a third exemplary embodiment; and

[0060] [Fig. 15] is a diagram of a transmission module for a participant station of the bus system according to a fourth exemplary embodiment.

[0061] In the figures, similar elements or elements having the same function are, unless otherwise indicated, provided with the same references.

[0062] Description of the examples of embodiment

[0063] [Fig.l] represents a bus system 1, which can be for example at least in some places, a CAN bus system, a CAN-FD bus system, etc. The bus system 1 can find application in a vehicle, in particular in a motor vehicle, an airplane, etc., or in a hospital, etc.

[0064] In [Fig.l] the bus system 1 has a plurality of participant stations 10, 20, 30, which are respectively connected to a bus 40 or to a bus line by a first bus strand 41 and by a second bus strand 42. The bus strands 41, 42 can be referred to in a CAN bus system also as CANH and CANL for conducting CAN_H, CAN_L signals on the bus 40.

[0065] Via the bus 40, messages 45, 46, 47 can be transmitted in the form of signals between the various participant stations 10, 20, 30. The participant stations 10, 20, 30 are, for example, control devices or display devices of a motor vehicle.

[0066] As shown in [Fig.l], the participant stations 10, 30 each have a communication control device 11 and a transmitting / receiving device 12. The transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122. The participant station 10 uses a supply voltage of 3.3 V, at least 3.0 V. At least one of the participant stations 20, 30 uses a supply voltage of 5 V. By way of illustration, the following examples show an example of a network or bus system 1, in which the participant station 20 has a supply voltage of 5 V and the participant stations 10 and 30 have a supply voltage of 3.3 V, at least 3.0 V. Other possibilities can also be considered.

[0067] The participant station 20 has a communication control device 21 and a transmission / reception device 22. The transmission / reception device 22 has a transmission module 221 and a reception module 222.

[0068] The transmitting / receiving devices 12 of the participant stations 10, 30 and the transmitting / receiving device 22 of the participant station 20 are respectively connected directly to the bus 40, even if this is not shown in [Fig.l].

[0069] The communication control devices 11, 21 respectively serve to control a communication of the respective participant station 10, 20, 30 via the bus 40 with at least one other participant station among the participant stations 10, 20, 30, which are connected to the bus 40.

[0070] The communication control devices 11 establish and read first messages 45, 47, which are for example modified CAN messages 45, 47. In this respect, the modified CAN messages 45, 47 are established for example on the basis of the CAN XL format. The transmitting / receiving device 12 serves to transmit and receive messages 45, 47 via the bus. The transmitting module 121 receives a digital transmit TxD signal established by the communication control device 11 for one of the messages 45, 47 and transforms this into signals on the bus 40 as described in more detail with reference to [Fig. 3], [Fig. 4] and [Fig. 7]. The digital transmit TxD signal may be at least occasionally or in some places a signal modulated in pulse width. The receiving module 121 receives signals sent on the bus 40 in accordance with messages 45 to 47 and produces a digital receive RxD signal, an example of which is shown in [Fig. 6]. The receiving module 122 sends the receive RxD signal to the communication control device 11.

[0071] Furthermore, the communication control device 11 may optionally be configured for the production and reading of second messages 46, which are, for example, CAN FD messages 46. The transmission / reception device 12 may be configured accordingly.

[0072] The communication control device 21 can, like a conventional CAN control unit, be implemented according to ISO 11898-1:2015, i.e. as a conventional CAN FD-tolerant CAN control unit or a CAN FD control unit or a CAN SIC control unit. The communication control device 21 generates and reads second messages 46, for example CAN FD messages or CAN SIC messages. The transmitting / receiving device 22 serves to send and receive the messages 46 via the bus 40. The transmitting module 221 receives a digital transmit signal TxD generated by the communication control device 21 and transforms this into signals for a message 46 on the bus 40 as described in more detail with reference to [Fig. 3] and [Fig. 4].The receiving module 222 receives signals sent on the bus 40 in accordance with messages 45 to 47 and thus produces a digital receive signal RxD, an example of which is shown in [Fig. 6]. The transmitting / receiving device 22 is implemented as a conventional CAN FD transmitter / receiver or a conventional CAN SIC transmitter / receiver, if necessary.

[0073] For sending messages 45, 46, 47 by CAN SIC or CAN XL, proven properties are taken into account, which provide the robustness and ease of use of CAN and CAN FD, in particular a frame structure with identifier and arbitration according to the known CSMA / CR method, as will be described in more detail below.

[0074] Via the two participant stations 10, 30, it is possible to carry out training and then transmission of messages 45, 46, 47 having different CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format as well as the reception of messages 45, 46, 47 of this type. This will be described in more detail in the following for a message 45.

[0075] [Fig. 2] represents for the message 45 a frame 450, which is in particular a CAN XL frame as given by the communication control device 11 for the transmission / reception device 12 for sending on the bus 40. In this respect the communication control device 11 produces the frame 450 in the present embodiment as compatible with CAN FD. Alternatively the frame 450 is compatible with any standard to be followed for CAN FD.

[0076] According to [Fig. 2] the frame 450 for CAN communication on the bus 40 is subdivided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase). The frame 450 has, after a start SOF bit, an arbitration field 453, a control field 454, a first switching field 455, a data field 456, a checksum field 457, a second switching field 458 and an end of frame field 459, in which there is an EOF marking (EOF = End of Frame). The checksum field 457, the second switching field 458 and the end-of-frame field 459 form an end-of-frame phase 457, 458, 459 of the frame 450. In the end-of-frame field 459 there may be a confirmation field (ACK = Acknowledge), which contains at least one ACK bit and which is not shown in the figures.

[0077] Unlike frame 450 of [Fig.2] there is no switching field 455, 458 in a CAN FD frame, which the participant station 20 uses for the second message 46.

[0078] For all the CAN versions mentioned above, it is ensured that in the arbitration phase 451, by means of an identifier (ID) in the bit-by-bit arbitration field 453 between the participant stations 10, 20, 30, the participant station 10, 20, 30 wishing to send the message 45, 46, 47 having the highest priority and therefore for the immediately following time obtains exclusive access to the bus 40 of the bus system 1 for sending connected data in phase 452. In the arbitration phase 451, a physical layer is used as in CAN and CAN-FD. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model).

[0079] During phase 451, the known CSMA / CR method is used, which allows simultaneous access of the participant stations 10, 20, 30 to the bus 40, without the message 45, 46, 47 having the highest priority being disturbed. In this way, further bus participant stations 10, 20, 30 can be added to the bus system 1 in a relatively simple manner, which is very advantageous.

[0080] The CSMA / CR method results in so-called recessive states being given to the bus 40, which can be overwritten by other participant stations 10, 20, 30 having dominant levels or dominant states on the bus 40. In the recessive state, high-ohmic relationships prevail at the various participant stations 10, 20, 30, which, in combination with the bus circuitry interference, results in fairly long time constants. This results in a limitation of the current maximum bit rate of the CAN-FD physical layer to currently about 2 megabits per second in actual vehicle use.

[0081] At the end of the arbitration phase 451, we move to the CAN XL data phase 452; switching is carried out using the first switching field 455 of [Fig.2],

[0082] In the data phase 452, the useful data of the CAN-XL frame 450 and respectively the message 45 composed of the data field 456 as well as the checksum field 457 and a part of the second switching field 458 are sent in CAN XL alongside a part of the first switching field 455. In CAN FD, the useful data of the CAN-FD frame and respectively the message 46 composed of the data field 456 as well as the checksum field 457 are sent.

[0083] At the end of data phase 452, we return to arbitration phase 451. In CAN XL, switching is carried out using the second switching field 458 of [Fig.2],

[0084] A transmitter of the message 45 only begins a transmission of bits of the data phase 452 on the bus 40, if and only if the participant station 10 as transmitter has won the arbitration and the participant station 10 as transmitter thus has for the transmission an exclusive access to the bus 40 of the bus system 1.

[0085] In the end-of-frame EOF field, a bit sequence is provided, which marks the end of frame 450. The bit sequence of the end-of-frame (EOF) field thus serves to characterize the end of frame 450. The end-of-frame (EOF) field serves to send a number of 7 recessive bits at the end of frame 450. Together with an ACK delimiter possibly present in the confirmation field not shown, a number of 8 recessive bits is sent at the end of frame 450. The mentioned bit sequence of recessive bits is a bit sequence which cannot occur within frame 450. The end of frame 450 can thus be identified reliably by the participant stations 10, 30.

[0086] The participant station 10 carries out, from an instant or time tl, starting more precisely with time tl, for a duration T_M1 of time, a detection of the bus potential or the bus voltage, which applies to the bus 40. The detection is carried out after the occurrence of an event EL. The event El is that a predetermined number of recessive bits directly following one another has appeared at the end of the frame 450, more precisely in the end field (EOF).

[0087] Optionally, the participant station can, from a time t2, starting more precisely at time t2, for a duration T_M2, perform a detection of the bus potential or the bus voltage, which applies to the bus 40. The detection is performed after an event E2 has occurred. The event E2 is that at the end of the first communication phase (arbitration phase 451) the participant station is determined, which has in the second communication phase following (data phase 452) exclusive access to bus 40 and thus can send its message.

[0088] This detection or these detections or this measurement or these measurements are described in the following with the aid of the figures.

[0089] After the end field (EOF), which has 7 bits, comes in frame 450 an Inter Frame Space (IFS), which is not shown in [Fig.2]. This Inter Frame Space (IFS) is conformed in CAN FD according to ISO 11898-1:2015. The Inter Frame Space (IFS) has at least 3 bits.

[0090] Furthermore the fields and bits mentioned are known from ISO 11898-1:2015 and will therefore not be described here in a more precise manner.

[0091] The participant stations 10, 30 thus use in the arbitration phase 451 as the first communication phase in part, in particular up to the FDF bit (inclusive), a known format of CAN / CAN-FD according to ISO 11898-1:2015. It is possible, however, compared to CAN or CAN FD in the data phase 452 as the second communication phase, to have an increase in the net data transmission rate, in particular up to beyond 10 megabits per second. Furthermore, an increase in the size of the useful data per frame, in particular up to approximately 2 kbytes or any other value, is possible.

[0092] [Fig. 3], [Fig. 5] and [Fig. 6] illustrate by way of example the signals, which are produced at the participant stations 10, 20, 30, when the bus system 1 is in operation. [Fig. 4] illustrates by way of example the signals, which are sent from the participant stations 20 to the bus 40, when the bus system 1 is in operation. As already mentioned, the participant station 20 uses a supply voltage of 5 V. [Fig. 7] shows the bus signals, which each of the participant stations 10, 30 produces instead of the bus signals, which are shown in [Fig. 4]. As already mentioned, the participant stations 10, 30 use a supply voltage of approximately 3.3 V at least 3.0 V.

[0093] When the bus system 1 is energized, each of the modules 121, 221 of [Fig.l] can transform a transmission TxD signal of the communication control device 11, which belongs to it, in series into corresponding CAN_H, CAN_L signals for CAN or CAN FD for the bus strands 41, 42 and send these signals to the terminals for CAN_H and CAN_L on the bus 40. The respective communication control device 11, 21 sends the transmission TxD signal of [Fig.3] as a function of time t (serial) to the transmission modules 121, 221 belonging to it, as shown in [Fig.l].

[0094] As shown by way of example in [Fig.3], the transmit signal TxD has the voltage states H (High = High) and L (Low = Low) having a corresponding voltage U. The various bits of the TxD signal have a bit time t_bt 1, as shown in [Fig.3] for the arbitration phase 451. In CAN FD and CAN XL the bits of the TxD signal can be sent in the data phase 452 with a shorter bit time t_bt2, as shown in [Fig.4].

[0095] The sequence of states H, L of the transmit signal TxD of [Fig. 3] and states 401, 402, which follow for the signals CAN_H, CAN_L in [Fig. 4], as well as the resulting curve of the voltage VDIFF of [Fig. 5] only serves to illustrate the operation of the participant station 10. The sequence of data states for the bus states 401, 402 can be chosen as required.

[0096] Following the example of [Fig. 4] the signals CAN_H and CAN_L have at least in the arbitration phase 451 the dominant and recessive bus level or bus states 401, 402, as is known from CAN. Since the participant station 20 uses a supply voltage of 5 V, it excites for the dominant state 401 the CAN_H level to about 3.5 V and the CAN_L level to about 1.5 V, as shown in [Fig. 4]. The recessive state 402 is established at 2.5 V, which is equal to the average bus voltage Vcm = 2.5 V.

[0097] As shown in [Fig.5] for the difference voltage VDIFF = CAN_H -CAN_L on the bus 40, the difference between the CAN_H level and the CAN_L level for the dominant state 401 is then in a range of 2 V.

[0098] The receiving modules 122, 222 form, from the signals CAN_H and CAN_L, received from the bus 40 and shown in [Fig. 4] and respectively from the difference voltage VDIFF of [Fig. 5], a receiving RxD signal according to [Fig. 6]. For the production of the digital receiving RxD signal of [Fig. 6], the respective receiving module 122, 222 uses reception thresholds as is known. The receiving RxD signal is shown in [Fig. 6] without travel time delay. The receiving module 122 routes this receiving RxD signal to the communication control device 11, 21 belonging to it, as shown in [Fig. 1].

[0099] According to the ISO 11898-1:2015 standard, the communication control device 11,21 compares its bits sent themselves according to a 450 frame and a transmission TxD signal ([Fig.3]), at the sampling point AP (Sample-Point) ([Fig.4] and [Fig.5]), to the bits observed on the bus 40 following the reception RxD signal ([Fig.6]). A difference is evaluated as a fault, apart from the arbitration and the ACK bit.

[0100] In contrast to [Fig. 4], [Fig. 7] shows the signals CAN_H and CAN_L, which the participant stations 10, 30 produce in the arbitration phase 451 and the data phase 452 on the bus 40. At least in the arbitration phase 451, the dominant and recessive bus levels or bus states 401, 402 are used as already shown in [Fig. 4]. As in the example mentioned, the participant stations 10, 30 use a supply voltage of 3.3 V, they excite for the state 401 dominating the CAN_H level at about 2.9 V and the CAN_L level at about 0.9 V as shown in [Fig.7]. The recessive 402 state is established at 1.9 V, which is equal to the average bus voltage Vcm = 1.9 V. In the 452 data phase, a physical 452_P layer other than the physical 451_P layer in the 451 arbitration phase can be used for CAN XL. It follows that the CAN_H levels are excited to values ​​for the states Ll, ​​LO, as shown in [Fig.7]. In the 451 arbitration phase, a physical layer is used as in CAN and CAN-FD. The physical layer corresponds to the bit transmission layer or layer 1 of the known OSI model (Open Systems Interconnection Model).

[0101] The transmission module 121 produces, for the transmission signal TxD of [Fig.3], the signals CAN_H, CAN_L of [Fig.7] for the bus strands 41, 42, so that the state LO forms a state LW (Low = Low). In addition, the state Ll is formed for a state HI (High = High).

[0102] To increase the bit rate for CAN XL, the transmitting / receiving devices 12 can be configured for CAN SIC.

[0103] As shown more precisely in [Fig.8] and [Fig.9], the transmit module 121 produces in CAN SIC for the transmit signal TxD of [Fig.8] the signals CAN_H, CAN_L according to [Fig.9] for the bus strands 41, 42 with an average bus voltage Vcm_sic = 1.9 V and in such a way that, in addition, there is a state 403 (sic). The state 403 (SIC) can have a different length as shown with the state 403_0 (sic) when changing from state 402 (rec) to state 401 (dom) and with the state 403_l (sic) when changing from state 401 (dom) to state 402 (rec). State 403_0 (sic) is shorter in time than state 403_l (sic). To produce signals according to [Fig.9], the transmission module 121 is put into a SIC operating type (SIC-Mode).

[0104] The transition from the short sic 403_0 state in the CiA610-3 is not required and the state depends on the type of implementation. The time duration of the "long" 403_l (sic) state is specified for CAN-SIC as well as also for the SIC operation type in CAN-XL as t_sic < 530ns, starting with the rising edge of the transmit TxD signal of [Fig.8].

[0105] The participant station 10, in particular the transmitting / receiving device 12, carries out, from the instant or a time t3, more precisely starting with the instant t3, after the occurrence of an event E3, for a duration T_M3, a detection of the bus potential or the bus voltage, which applies to the bus 40. The event E3 is, that one leaves the state 401 (dom) and respectively one passes from the state 401 (dom) to the state 403 (sic). Depending on the result of the detection, the participant station 10 ensures that the average bus voltage Vcm is approximately 2.5 V ([Fig. 4]) or 1.9 V ([Fig. 7]) as the pre-bus voltage on the bus 40. The setting to the pre-bus voltage on bus 40 or the 2.5 V potential can be carried out in particular during bit 7 of the end of frame EOF field or during one of the following 4 recessive bits.

[0106] The transmission module 121 must adapt as well as possible in the "long" state 403_l (sic) the impedance between the bus strands 41 (CANH) and 42 (CANL) to the inductance Zw characteristic of the bus line used. In this respect, we have Zw = 1000Ohm or 1200hm. This adaptation prevents reflections and thus allows operation at fairly high bit rates. For the sake of simplification, we will always refer to the state 403 (sic) or the sic state 403 in the following.

[0107] The transmission module 121 can be used for the production of signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC and CAN-XL. CAN-Typ Communication phase / bit rate Bus states Transmit module states CAN-FD Arbitration dom, rec dom, sic, rec CAN-SIC Arbitration dom, sic, rec dom, sic, rec CAN-XL Arbitration or arbitration and data field for 1st case where no transition to fast operation type takes place dom, sic, rec dom, sic, rec CAN-XL Data phase L0, Ll L0, Ll Table 1: CAN_Types for the 121 transmitter module.

[0108] The state of the transmitting module can thus be produced not only in CAN-SIC or CAN-XL (xl_sic). The sic state of the transmitting module can also be produced in CAN-FD. In CAN-FD the time for the sic state of the transmitting module is twice as short as in CAN-SIC or CAN-XL.

[0109] [Fig. 10] shows the basic structure of the transmission module 121 for one of the participant stations 10, 30. The transmission module 12 can produce CAN_H, CAN_L according to [Fig.9] having the states 401, 402, 403 and CAN_H, CAN_L signals according to [Fig.7] having the states L0, Ll, as described previously.

[0110] The transmission module 121 has four transmission stages, namely a first transmission stage 121A, a second transmission stage 12IB, a third transmission stage 12IC, a fourth transmission stage 121D. As shown in [Fig.10], the transmission stages 121A to 121D are mounted in a full bridge.

[0111] The transmission module 121 is connected to the bus 40, more precisely to its first bus strand 41 for CAN_H or CAN-XL_H and to its second bus strand 42 for CAN_L or CAN-XL_L. Each of the transmit stages 121A to 121D is connected to bus 40.

[0112] The voltage supply for supplying the first and second bus strands 41, 42 with electrical energy is provided via at least one terminal 43, in particular via the CAN supply with a voltage of 3.3 V. The connection to ground and to CAN_GND is provided via a terminal 44. The first and second bus strands 41, 42 are terminated by a terminating resistor 49. The terminating resistor 49 is mounted in the full bridge as an external load resistor. The resistor 49 is mounted in the bridge branch between the terminals for the bus strands 41, 42.

[0113] The first emission stage 121A of [Fig. 10] has a polarity inversion circuit D_A, and a parallel circuit 121A1, in which a first to nth current stage is connected in parallel, n being a natural number > 1. There is further a control circuit T_A. The first current stage has a transistor TM_CH1 with a diode connected in parallel. The diode connected in parallel comes parasitically from the transistor TM_CH1. The nth current stage has a transistor TM_CHn with a diode connected in parallel. The diode connected in parallel returns parasitically from the transistor TM_CHn. A second to nth current stage which are possibly present in the circuit 121A in parallel is not or are not shown in [Fig. 10] while being shaped in the same way as what is described for the transistor TM_CH1 or the transistor TM_CHn. Transistors TM_CH1 to TM_CHn are respectively a CMOS transistor for example a PMOS transistor.In particular, each of the transistors TM_CH1 to TM_CHn is a high-voltage resistant PMOS switching transistor for about 60V to 81V. The abbreviation "CMOS" designates a semiconductor element in which MOSFETs both p-channel and n-channel are used on a common substrate. The abbreviation CMOS represents the English designation "complementary-metal-oxide-semiconductor". The abbreviation "MOSFET" stands for metal-oxide field-effect transistor. The control circuit T_A controls the transistors TM_CH1, TM_CHn, of the first to nth current stages of the current stage 121A according to the transmission signal TxD and the SIC, FAST_TX type of established operation of the transmission module 121.

[0114] The first polarity inversion circuit D_A has a diode Dl, a first transistor TRI, a second transistor TR2, a resistor RI and possibly a capacitor CL. The diode Dl comes parasitically from the transistor TRI. The transistor TR2 has its own parasitic diode which is not shown in [Fig.10]. The transistors TRI, TR2 are PMOS transistors. The note of the diode Dl is connected to the terminal of drain of the first transistor TRI and to the supply voltage VCC at terminal 43. The cathode of the diode DI is connected to the source terminal of the first transistor TRI and to the source terminal of the second transistor TR2. The gate terminal of the first transistor TRI is connected to the drain terminal of the second transistor TR2 to one terminal of the resistor RI and to one terminal of the possible capacitor Cl. The other terminal of the resistor RI is connected to ground, in particular to terminal 44 (GND). In addition, the other terminal of the possible capacitor Cl is connected to ground, in particular to terminal 44 (GND). The gate terminal of the second transistor TR2 is connected to the supply voltage VCC at terminal 43. The drain terminal of the first transistor TRI and the gate terminal of the second transistor TR2 are thus connected to terminal 43 and thus to the supply voltage VCC.Diode DI is conductive in operation and short-circuited by means of transistors TRI, TR2 and resistor RI, in other words it is shunted. Transistor TRI forms with diode DI a shuntable diode which consists of the parasitic bulk-drain diode of transistor TRI. The function of the polarity inversion circuit D_A will be described in more detail in the following.

[0115] The second emission stage 121B of [Fig. 10] has a polarity reversal diode D_B and a parallel circuit 121B1, in which a first to nth current stage are connected in parallel, n being the natural number greater than 1. There is further a control circuit T_B. The first current stage has a transistor TM_CL1 with a diode connected in parallel. The diode connected in parallel comes parasitically from the transistor TM_CL1. The nth current stage has a transistor TM_CLn with a diode connected in parallel. The diode connected in parallel comes parasitically from the transistor TM_CLn. A second to n-unth current stage which are possibly present in the parallel circuit 121B1 but which is not or are not shown in [Fig. 10], are shaped in the same way as described for the transistor TM_CL1 or the transistor TM_CLn. Transistors TM_CL1 to TM_CLn are respectively a CMOS transistor, for example an NMOS transistor.In particular, each of the transistors TM_CH1 to TM_CHn is a high voltage resistant NMOS switching transistor for about 60V to 80V. The control circuit T_B controls the transistors TM_CL1 to TM_CL of the first to nth current stages of the transmit stage 121B according to the transmit signal TxD and the established operating TIC, FAST_TX of the transmit module 121.

[0116] The third emission stage 121C of [Fig. 10] has a polarity inversion circuit D_C and a parallel circuit 12ICI, in which a first to nth current stage is connected in parallel, n being the natural number greater than 1. There is further a control circuit T_C. The first current stage has a transistor TC_CL1 with a diode connected in parallel. The diode connected in parallel comes parasitically from transistor TC_CL1. The nth current stage has a transistor TC_CLn with a diode connected in parallel. The diode connected in parallel comes parasitically from transistor TC_CLn. A second to nth current stage which are possibly present in circuit 121C1 in parallel but which is not or are not shown in [Fig. 10] and / or are constituted in the same way as described for transistor TC_CL1 or transistor TC_CLn. Transistors TC_CL1 to TM_CLn are respectively a CMOS transistor for example a PMOS transistor. In particular each of transistors TC_CL1 to TC_CLn is a PMOS switching transistor resistant to high voltage for about 60V to 80V. The control circuit T_C controls the transistors TC_CL1 to TC_CLn of the first to nth current stages of the transmission stage 121C according to the transmission signal TxD and the established operating type SIC, FAST_TX of the transmission module 121.

[0117] The second polarity inversion circuit D_C has a diode D2, a first transistor TR3, a second transistor TR4, a resistor R2 and possibly a capacitor C2. Diode D2 comes parasitically from transistor TR3. Transistor TR4 has its own parasitic diode which is not shown in [Fig.10]. Transistors TR3, TR4 are PMOS transistors. The anode of diode D2 is connected to the drain terminal of the first transistor TR3 and to the supply voltage VCC at terminal 43. The cathode of diode D2 is connected to the source terminal of the first transistor TR3 and to the source terminal of the second transistor TR4. The gate terminal of the first transistor TR3 is connected to the drain terminal of the second transistor TR4, to one terminal of resistor R2 and to one terminal of the possible capacitor C2. The other terminal of resistor R2 is connected to ground, in particular to terminal 44 (GND).The other terminal of capacitor C2 is furthermore connected to ground, in particular to terminal 44 (GND). The gate terminal of the second transistor TR4 is connected to the supply voltage VCC at terminal 43. The drain terminal of the first transistor TR3 and the gate terminal of the second transistor TR4 are thus connected to terminal 43 and thus to the supply voltage VCC. Diode D2 is in conductive operation and is short-circuited with the help of transistors TR3, TR4 and resistor R2, in other words it is shunted. Transistor TR3 forms with diode D2 a shuntable diode which consists of the parasitic bulk-drain diode of transistor TR3. The function of the polarity reversal circuit D_C will be described in more detail in the following.

[0118] The fourth emission stage 121D of [Fig. 10] has a polarity reversal diode D_D and a parallel circuit 121D1, in which a first to nth current stage is connected in parallel, n being the natural number greater than 1. There is further a control circuit T_D. The first current stage has a transistor TC_CH1 with a diode connected in parallel. The diode connected in parallel comes parasitically from transistor TC_CH1. The nth current stage has a transistor TC_CHn with a diode connected in parallel. The diode connected in parallel comes parasitically from transistor TC_CHn. A second to n -1 -unth current stage which are possibly present in the parallel circuit 121D1, but which are not or which is not shown in [Fig. 10] are / are shaped in the same way as described for transistor TC_CH1 or transistor TC_CHn. Transistors TC_CH1 to TC_CHn are respectively a CMOS transistor for example an NMOS transistor. In particular, each of the transistors TC_CH1, TC_CHn is a high voltage resistant NMOS switching transistor for about 60 V to 80 V. The control circuit T_D controls the transistors TC_CH1 to TC_CHn of the first to nth current stages of the transmitting stage 121D according to the transmitting signal TxD and the established operating type SIC, FAST_TX of the transmitting module 121.

[0119] The current stages 1 to n of each of the emission stages 121A to 121D are designated in [Fig. 11] also as current stages SI to Sn. The number n can be chosen in any way, the number n can in particular and thus the number of stages or the number of current stages be chosen between 1 and 60. Alternatively, however, a number larger or smaller than 60 can be chosen for n.

[0120] Each of the polarity reversal diodes D_B, D_D protects the emission stage 121B, 121D which belongs to it against a positive return supply on terminal 43 (CAN_GND). Each of the polarity reversal diodes D_B, D_D can also be referred to as a blocking diode. Each of the polarity reversal diodes D_B, D_D can be a pn type diode which is a parasitic pn junction of a transistor (silicon) which is wired in a fixed manner so that the transistor can never be driven and the diode can never be short-circuited / shunted. The forward voltage of each of the polarity reversal diodes D_B, D_D is in particular about 0.7 V.

[0121] Each of the polarity inversion circuits D_A, D_C protects the transmitting stage 121A, 121C which belongs to it against a positive return supply on terminal 43 (CAN-Supply) and a negative return supply on terminal 44 (CAN_GND). Each of the circuits D_A, D_C can also be designated as a blocking circuit.

[0122] As mentioned, the gate terminal of the first TRI transistor is grounded, in particular to terminal 44 (GND) via the resistor RL. If the voltage of the source terminal of the TRI transistors, TR2 rises, in particular by the supply by VCC_min = 3.0 V, the channel parallel to the diode D1, therefore via the TRI transistor, becomes conductive. The forward voltage of the diode D1 thus decreases. For a supply by VCC_min = 3.0 V, the levels according to [Fig.7] or [Fig.9] can be produced under all conditions to be respected.

[0123] Just as with the polarity reversal diodes D_B, D_D, there is also with the polarity reversal circuit D_A the protection against the reverse supply. As described, the transistor TR2 is a PMOS transistor. The transistor TR2 conducts, if it applies to its gate terminal which is connected terminal 43 at least a threshold voltage below the potential at the source terminal of the transistor TR2. If the voltage at the cathode of the diode DI rises, which is equal to the potential of the source terminal of the second transistor TR2 with approximately a transistor threshold voltage via the voltage VCC at terminal 43, the transistor TR2 becomes conductive, the voltage at the gate of the transistor TRI rises and the transistor TRI turns off. Due to this, the parasitic diode DI becomes effective. This achieves the protection against the reverse supply.

[0124] For this purpose, the transistors TRI, TR2 are shaped so that the value of the on-state resistance of the second transistor TR2 is much smaller than the resistance value of the resistor RI. We therefore have: Ron_TR2«Rl.

[0125] Optionally, the gate-source section of transistors TRI, TR2 is filtered in particular by an RC filter, which is formed of the resistor RI and the capacitor Cl. The polarity inversion circuit D_A is thus robust with respect to pulse-type disturbances, in particular DPI, ISO pulses, etc.

[0126] As mentioned, the gate terminal of the first transistor TR3 is connected to ground via resistor R2, in particular to terminal 44 (GND). If the voltage rises at the source terminal of transistors TR3, TR4 in particular by the supply by VCC_min = 3.0V, the channel becomes conductive in parallel to diode D2, therefore by transistor TR3. The forward voltage of diode D2 thus decreases. For a supply by VCC_min = 3.0V, the levels according to [Fig.7] or [Fig.9] can be produced under all conditions to be observed.

[0127] Just as with the polarity reversal diodes D_B, D_D, the reverse feed protection is also achieved with the polarity reversal circuit D_C. As described, the transistor TR4 is a PMOS transistor. The transistor TR4 conducts if it applies to its gate terminal, which is connected to terminal 43, at least one threshold voltage below the potential at the source terminal of the transistor TR4. If the voltage at the cathode of the diode D2 rises, which is equal to the potential of the source terminal of the second transistor TR4, with approximately one transistor threshold voltage by the voltage VCC at terminal 43, the transistor TR4 becomes conductive, the voltage at the gate of the transistor TR3 rises and the transistor TR3 turns off. Due to this, the parasitic diode D2 becomes effective. This achieves the reverse feed protection.

[0128] For this purpose, transistors TR3, TR4 are shaped so that the value of the on-state resistance of the second transistor TR4 is much smaller than the resistance value of resistor R3. We therefore have: Ron_TR4«R2.

[0129] Optionally the gate-source sections of the transistors TR3, TR4 are filtered in particular by an RC filter, which is formed of the resistor R2 and the capacitance of C2. The polarity inversion circuit D_C is thus robust with respect to pulse-type disturbances in particular DPI, pulse-ISO, etc.

[0130] Each of the circuits 121A1, 121B1, 121C1, 121D1, more precisely parallel to the control circuit T_A, T_B, T_C, T_D, which belongs to it, establishes a current value for the stage 121A, 121B, 121C, 121D which belongs to it as a function of the type (SLOW or SIC, FAST_TX of operation) of the transmission module 121 and of the transmission signal TxD. The current value of the various transmission stages 121A, 121B, 121C, 121D is therefore adjustable according to the type (SLOW or SIC, FAST_TX of operation) of the transmission module 121 and according to the transmission signal TxD. This is described in a more precise manner in the following with the aid of [Fig. 11] and [Fig. 12], as well as Table 2 and Table 3.

[0131] In the transmission module 121, the transmission stage 121A is connected between terminal 43 for the voltage supply, terminal 41 (CANH) for the signal CAN_H and, with respect to the polarity inversion circuit D_A, between terminal 43 for the supply voltage VCC and terminal 44 (CAN_GND) for ground. The transmission stage 121C is connected between terminal 43 for the voltage supply and terminal 42 (CANL) and, with respect to the polarity inversion circuit D_C, between terminal 43 for the supply voltage VCC and terminal 44 (CAN_GND) for ground. The transmission stage 121D is connected between terminal 41 (CANH) for the signal CAN_H and terminal 43 (CAN_GND) for ground. The transmitter stage 121B is connected between terminal 42 (CANL) for the CAN_L signal and terminal 43 (CAN_GND) for ground. The transmitter stage 121A is connected to the CAN-H path for the transmitter module 121. The transmitter stage 121D is connected to the CAN-H path.In the CAN-L path is mounted on one hand the 121C transmission stage. On the other hand, the 121B transmission stage is mounted in the CAN-L path.

[0132] The transmission module 121 is thus constituted in the CAN-H path and in the CAN-L path of a parallel circuit 121A1, 121B1, 121C1, 121D1 and of a determined number of current stages. An individual current stage is realized by a parallel circuit consisting of CMOS switches and their parasitic diode as described previously. The parallel circuit of all the current stages is connected in the CAN-H path and in the CAN-L path in series with a polarity inversion circuit D_A, D_C or a polarity inversion diode D_B, D_D, as described previously.

[0133] The operating mode of the circuit of [Fig. 10] as a function of the operating type of the transmission module 121 and the state 401 of the bus (dom), 403 (sic), 402 (rec) in the SIC operating type (arbitration phase 451) and L0, L1 in the data phase 452 is explained using the following table 2. Table 2 gives, depending on the state of the transmission module 121 and the state of the bus 40 which follows, on the bus and the differential voltage VDIFF in volts (V) on the bus 40, the standardized or required impedance of the transmission module 121. VDIFF bus status in Volt (V) TM_CH1 to T M_CHn (standard impedance) TM_CH1 to T M_CHn (standard impedance) TM_CH1 to T M_CHn (standard impedance) TM_CH1 to T M_CHn (standard impedance) dom 2 1 1 Infinite Infinite sic 0 1 / 2 1 / 2 1 / 2 1 / 2 rec 0 Infinite Infinite Infinite Infinite L0 1 1 / 2 1 / 2 Infinite Infinite L1 -1 Infinite Infinite 1 / 2 1 / 2 Table 2: Standardized impedance of the transistors of the 121 emission stage depending on the emission state or the bus state.

[0134] If the impedance is "infinite" the transmission module 121 or the respective transmission stage 121A, 121B, 121C, 121D is switched off or is not conductive.

[0135] The distribution of each circuit 121A1, 121B1, 121C1, 121D1 parallel to the [Fig. 10] in n parts where the n current stages allow a time-staged and controlled switching operation between the bus states 401, 402, 403 in the phase (SIC operation type) 451 or the bus states L0, L1 of the data phase 452. For this purpose the resistance values ​​of the resistors of the n current stages are set as illustrated by [Fig.l 1] in a specific example.

[0136] [Fig. 11] shows an example of the current level per switching stage or current stage SI, S12. In the example shown, twelve current stages SI, S2 to S6 up to S12 are used for each of the parallel circuits 121A1, 121B1, 121C1, 121D1. We therefore have n = 12.

[0137] The value of the current I (Vertical axis in [Fig.l 1]) and respectively II, 12,16,112 etc. is set by choosing the value of the series resistance of the respective current stage SI to S12. The various current stages SI to S12 (Horizontal axis in [Fig. 11]) thus have different resistance values.

[0138] For the production of the states 401, 402, 403 of the bus in the arbitration phase (SIC operating type) 451 or the states L0, L1 of the bus of the data phase 452, we shifts in time or the various current stages SI to S12 are switched off using the CMOS transistors of the current stages SI to S12. A corresponding electric current I thus passes into the CANH path or the CANL path, in which the hierarchically higher emission stage 121A, 121B, 121C, 121D is mounted.

[0139] In general, it is advantageous to design the staggering (stagger stages) and the resistors per switching stage or respectively per current stage SI to S12, so that the shape of the difference signal VDIFF follows Gaussian error functions. This analytically produces the smallest emission.

[0140] For the transition from a state 402 (recessive) to a state 401 (dominant), which corresponds to a rising edge of the difference voltage VDIFF of [Fig. 5], the current in the CANH path and in the CANL path is increased step by step by switching the resistors of the parallel circuits 121A1, 121B1, 121C1, 121D1 in a time-shifted manner for the production of a dominant level at the bus 40. The transition from a state 401 (dominant) to a state 402 (recessive), which corresponds to a falling edge of the difference voltage VDIFF of [Fig. 5], is carried out in a corresponding manner by switching the resistors of the parallel circuits 121A1, 121B1, 121C1, 121D1 in a time-shifted manner, whereby the current is lowered step by step. current in the CANH and CANL channel. The total current, which is given by the sum of currents II to 112 or respectively II up to all current stages SI to Sn, passes during state 401 (dominant).In this case all current stages SI to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1 are switched on and the total current for the production of the dominant level of nominal VDIFF = 2 V passes through the bus resistor or the terminating resistor 49.

[0141] By adjusting in time and by choosing the current levels of the various current stages SI to S12 by adjusting the transistors of the transmitter module 121, as described above, it is possible to equalize the bus signals CAN_H, CAN_L with each other when switching between the states 401, 402 so as to achieve the symmetrical curve of CAN_H and CAN_L according to [Fig.7] and respectively for the transmitter module 221 of [Fig.4]. The structure of the transmitter module 121 allows a time-shifted switching of the various current stages of the parallel circuits 121A1, 121B1, 121C1, 121D1. By this time-dependent control, it is possible to equalize the signal shape of CAN_H and CAN_L as required, according to [Fig.7] or [Fig.9] or [Fig.4]. Targeted shaping of the signal curves for CAN_H and CAN_L is possible.Overall, the bus states 401, 402, 403 can be formed in the arbitration phase (SIC operating type) 451 or the bus states L0, L1 of the data phase 452 according to the requirements.

[0142] The resistances of the various current stages SI to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1 and thus their respective proportions to the total current can be chosen differently to obtain the smallest possible emission, in particular a small emission of the emission module 121. It is advantageous for a small emission to switch on or off little current I (large resistance value) at the beginning and at the end of a transition operation between states 401, 402 of the bus and to switch on or off in the middle of the transition operation a lot of current (small resistance value). The adjustment shown in [Fig. 11] of the currents of the current stages SI to S12 is therefore very advantageous.

[0143] Unlike an embodiment having the same resistances in the current stages SI to Sn of the parallel circuits 121A1, 121B1, 121C1, 121D1, the configuration according to [Fig. 10] avoids having an increase in the current during switching off, the transition from state 401 (dominant) to state (402) (recessive).

[0144] The granularity of the time staging for switching on or off the individual current stages SI to S12 is in a range of approximately 2 ns. Such small stages or steps for the time staging cause small common-mode interference and have a small negative influence on the transmission. The voltage stages, which are set by the resistors or resistance states of the current stages SI, S2 to S6 to S12, are kept fixed and vary the time staging in such a way that, during the switching operation, a behavior as gentle as possible (according to a Gaussian error function) is set. The variation of the time steps or time stages also prevents the occurrence of a narrowband front frequency line in the transmission frequency spectrum.

[0145] Alternatively, the staggering steps can be achieved using fixed time steps and modified voltage steps.

[0146] By the structure shown of the transmission module 121, a symmetrical passage of the bus signals CAN_H and CAN_L ([Fig.7] or 9 or 4) is made possible for abrupt transition edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating type) 451 or the bus states L0, L1 of the data phase 452.

[0147] On the one hand, due to the structure shown in the transmission module 121, due to the use of fast CMOS switches or CMOS transistors, much steeper transition edges are achieved between the bus states 401, 402, 403 in the arbitration phase 451 (SIC operating type) or the bus states L0, L1 of the data phase 452. On the other hand, during the transition operations, the symmetry necessary for compliance with the emission limit values ​​of the time-dependent curve of the CAN_H and CAN_L signals of the bus is achieved. An equalization (matching) of the characteristic curves is achieved by the choice or use of resistors, more precisely transistors, parallel circuits 121A1, 121B1, 121C1, 121D1.

[0148] The CMOS transistors of the emission stages 121A1, 121B1, 121C1, 121D1 operate as a switch, i.e. with a maximum voltage between the gate terminal and the source terminal.

[0149] The dominant state 401 (dom) is determined by an equalization (matching) of the transistors TM_CH1 to TM_CHn (transmitting stage 121A) with the transistors TM_CL1 to TM_CLn (transmitting stage 121B). In this case and also in the following the concept "equalization" means a possibility of an active adjustment stage. According to another possibility, "equalization" means that the resistance values ​​adapt as best as possible, which normally takes place without an equalization stage or an adjustment stage.

[0150] The sic state (sic) is determined by an equalization (Matching) of the transistors TM_CH1, TM_CHn (transmission stage 121A) with the transistors TC_CL1 to TC_CLn (transmission stage 121C) and an equalization (Matching) of the transistors TC_CH1 to TC_CHn (transmission stage 121D) with the transistors TM_CL1 to TM_CLn (transmission stage 121B).

[0151] In the XL-Fast operating type, the L0 state is determined by matching the transistors TM_CH1 to TM_CHn (transmitting stage 121 A) with the transistors TM_CL1 to TM_CLn (transmitting stage 121B). The L1 state is determined by matching the transistors TC_CL1 to TC_CLn (transmitting stage 121C) with the transistors TC_CH1 to TC_CHn (transmitting stage 121D).

[0152] [Fig. 12] shows a particular example of the structure of the emission stage 121B of [Fig.10]. Consequently, the emission stage 121B has in the parallel circuit 121B1 three stages S_I, S_II, S_IIL. The first current stage S_I has a transistor TM_CL1. The second current stage S_II has a transistor TM_CL2. The third current stage S_III has a transistor TM_CL3.

[0153] For the following description of the circuit of [Fig. 10] having the configuration according to [Fig. 11] or [Fig. 12], it will be assumed that also each of the emission stages 121A, 121C, 121D has in its parallel circuit 121A1, 121C1, 121D1, which belongs to it, three stages S_I, S_II, S_III according to the example of [Fig. 12].

[0154] The following table 3 shows the control of the three transistors TM_CL1, TM_CL2 and TM_CL3 of the emission stage 121B of [Fig. 12] as well as the corresponding transistors of the emission stages 121 A, 121C, 121D of [Fig. 10] depending respectively on the emission stages 121A / 121B and the emission stages 121C, 121D. Operating type of the 121 transmitting module CAN-FD, CAN-SIC, CAN-XL (xl_sic) (Type of transmitting operation in the 451 arbitration phase) CAN-XL (xl-fasttx) (Type of transmitting operation in the 452 data phase) State of the dom sic bus rec L0 L1 121A / 121B: Typical values ​​in Ohm (Q) about 3 0 about 120 infinite about 60 infinite Transistor 1 passing passing blocked passing blocked Transistor 2 passing blocked blocked passing blocked Transistor 3 passing blocked blocked blocked blocked 121C / 121D: Typical values ​​in Ohm (Q) infinite about 120 infinite infinite about 60 Transistor 1 blocked passing blocked blocked passing Transistor 2 blocked blocked blocked passing Transistor 3 blocked blocked blocked blocked Table 3: Impedance required depending on the emission state

[0155] The transmission module 121 can thus produce the fairly abrupt edges required on the CAN_H and CAN_L bus signals and comply with the transmission limit values.

[0156] Alternatively, more than three current stages may be used in the respective transmit stages 121A, 121B, 121C, 121D, as previously described.

[0157] [Fig. 13] shows a transmission module 1210 according to a second exemplary embodiment. The transmission module 1210 is made up of several parts in the same way as the transmission module 121 according to the first exemplary embodiment. Therefore, only the differences compared to the first exemplary embodiment will be described in the following.

[0158] Unlike the first embodiment, the transmission module 1210 according to the present embodiment has a polarity inversion circuit D_AC and transmission stages 121A0, 121B, 121C0, 121D. The transmission stages 121A0, 121B, 121C0, 121D are mounted in a full bridge. The terminating resistor 49 is mounted in the branch of the bridge between the terminals for the strands 41, 42 of the bus.

[0159] The polarity inversion circuit D_AC serves as a polarity inversion circuit, common for the transmit stages 121A0, 12ICO. The polarity inversion circuit D_AC is constituted like the polarity inversion circuit D_A of [Fig. 10]. therefore refer for the polarity inversion circuit D_AC to the description of the polarity inversion circuit D_A in [Fig. 10].

[0160] The emission module 1210 of the present embodiment example offers, depending on the dimensioning, compared to the emission module 121 of the previous embodiment example, a saving in semiconductor surface area of ​​approximately 0.04mm2. If, for example, silicon is used as the semiconductor, a silicon surface area of ​​approximately 0.04mm2 can be saved.

[0161] The transmission module 1210 of the present exemplary embodiment can therefore be manufactured and can operate in a resource-saving and cost-effective manner than the transmission module 121 of [Fig. 10]. The transmission module 1210 of the present exemplary embodiment also requires less space than the transmission module 121 of [Fig. 10],

[0162] [Fig. 14] shows a transmission module 1211 according to a third embodiment. The transmission module 1211 is in many parts constituted in the same way as the transmission module 121 according to the first embodiment. Therefore, only the differences compared to the first embodiment will be described in the following.

[0163] Unlike the first embodiment, the transmission module 1211 of [Fig. 14] has four transmission stages 121A5, 121B5, 121C5, 121D5 and four current mirror circuits 121A7, 121B7, 121C7, 121D7 instead of the stages 121A1, 121B1, 121C1, 121D1 and the circuits 121A1, 121B1, 121C1, 121D1 in parallel of [Fig. 10].

[0164] The first transmitting stage 121A5 has the polarity inversion circuit D_A, which is connected in series with the current mirror circuit 121A7. The polarity inversion circuit D_A is constructed and connected as described above with reference to [Fig.10],

[0165] The current mirror circuit 121A7 has at least one current mirror composed of a transistor TM_CH and a transistor TM_CHs and at least one current well I_A1. Up to n current mirrors can be connected in parallel with each other. The transistors TM_CH, TM_CHs are CMOS transistors, in particular PMOS transistors.

[0166] The current well I_A1 is connected to the drain terminal of the transistor TM_CHs and to the gate terminals of the transistors TM_CH, TM_CHs or respectively to these. The current well I_A1 is further connected by its other terminal to ground, in particular to terminal 44. The transistors TM_CH, TM_CHs are respectively connected to each other at their gate terminal and their source terminal. Furthermore, with respect to the polarity inversion circuit D_A, the source terminals of the transistors TRI, TR2 and the cathode of the diode DI are connected to the gate terminals and the source terminals of the transistors TM_CH, TM_CHs.

[0167] The second emission stage 121B5 has the polarity inversion diode D_B, which is connected in series with the current mirror circuit 121B7. The current mirror circuit 121B7 has at least one current mirror composed of a transistor TM_CL and a transistor TM_CLs and at least one current source I_B1. Up to n current mirrors can be connected in parallel with each other. The transistors TM_CL, TM_CLs are CMOS transistors, in particular NMOS transistors.

[0168] The current source I_B 1 is connected to the drain terminal of the transistor TM_CLs and to the gate terminals of the transistors TM_CL, TM_CLs or respectively to these. Furthermore, the current source I_B1 is connected at its other terminal to the bus voltage supply, in particular to terminal 43. The transistors TM_CL, TM_CLs are connected to each other at their gate terminal and their source terminal respectively. Furthermore, the cathode of the polarity reversal diode D_B is connected to the drain terminal of the transistor TM_CL.

[0169] The third transmitter stage 121C5 has the polarity inversion circuit D_C, which is connected in series with the current mirror circuit 121C7. The polarity inversion circuit D_C is constructed and connected as described above with reference to [Fig.10],

[0170] The current mirror circuit 121C7 has at least one current mirror composed of a transistor TC_CL and a transistor TC_CLs and at least one current well I_C1. Up to n current mirrors can be connected in parallel with each other. The transistors TC_CL, TM_CLs are CMOS transistors, in particular PMOS transistors.

[0171] The current well I_C1 is connected to the drain terminal of the transistor TC_CLs and to the gate terminals of the transistors TC_CL, TC_CLs or respectively to these. Furthermore, the current well I_C1 is connected to its other terminal to ground, in particular to terminal 44. The transistors TC_CL, TC_CLs are respectively connected to each other at their gate terminal and their source terminal. Furthermore, with respect to the polarity inversion circuit D_C, the source terminals of the transistors TR3, TR4 and the cathode of the diode D2 are connected to the gate terminals and the source terminals of the transistors TC_CL, TC_CLs.

[0172] The fourth emission stage 121D5 has the polarity inversion diode D_D, which is connected in series with the current mirror circuit 121D7. The current mirror circuit 121D7 has at least one current mirror composed of a transistor TC_CH and a transistor TC_CHs and at least one current source I_D1. Up to n current mirrors can be connected between them. The transistors TC_CH, TC_CHs are CMOS transistors, in particular NMOS transistors.

[0173] The current source I_D1 is connected to the drain terminal of the transistor TC_CHs and to the gate terminals of the transistors TC_CH, TC_CHs or respectively to these. In addition, the current source I_D1 is connected, at its other terminal, to the power supply in bus voltage, in particular at terminal 43. Transistors TC_CH, TC_CHs are connected to each other at their gate terminal and their source terminal respectively. In addition, the cathode of the polarity reversal diode D_D is connected to the drain terminal of transistor TC_CH.

[0174] The emission stages 121A5, 121B5, 121C5, 121D5 are mounted in a full bridge. The terminating resistor 49 is mounted in the branch of the bridge between the terminals for the strands 41, 42 of the bus.

[0175] The transmit stages 121A5, 121B5, 121C5, 121D5 can be excited as previously described with reference to the transmit stages 121A1, 121B1, 121C1, 121D1 of [Fig. 10]. In this respect, the current sources I_B1, 1_D1 and the current sinks I_A1, 1_C1 are controlled according to an EMV-compatible analytical form, in order to produce the transmit states and the bus states according to the preceding table 1 or respectively the impedances according to the preceding table 2. The EMV-compatible analytical form produces for example, as a function of the time t, a current curve in / or at the output of the transmit stages 121A5, 121B5, 121C5, 121D5, as indicated and previously described in [Fig. 11] for current stages SI to S12.

[0176] In this way, the emission module 1211 can also produce, for a supply by VCC_min = 3.0V in all the conditions to be observed, the levels following [Fig.7] or [Fig.9].

[0177] [Fig. 15] shows a transmission module 1212 according to a fourth embodiment. The transmission module 1212 of [Fig. 15] is constituted in many parts in the same way as the transmission module 1211 of [Fig. 14]. Therefore, only the differences from the first embodiment will be described in the following.

[0178] Unlike the transmission module 1211 of [Fig. 14], the transmission module 1212 according to the present embodiment has a polarity inversion circuit D_AC and transmission stages 121A6, 121B5, 121C6, 121D5. The transmission stage 121A6 does not have a polarity inversion circuit and is therefore equivalent to the current mirror circuit 121A7. The transmission stage 121C6 does not have a polarity inversion circuit and is therefore equivalent to the current mirror circuit 121C7.

[0179] The emission stages 121A6, 121B5, 121C6, 121D5 are mounted in a full bridge. The terminating resistor 49 is mounted in the branch of the bridge between the terminals for the strands 41, 42 of the bus.

[0180] The polarity inversion circuit D_AC serves as a common polarity inversion circuit for the transmit stages 121A6, 121C6. The polarity inversion circuit D_AC is constituted like the polarity inversion circuit D_A of [Fig. 10]. Therefore, for the polarity inversion circuit D_AC, reference will be made to the description of the polarity inversion circuit D_A of [Fig. 10].

[0181] The emission module 1212 of the present embodiment offers, depending on the dimensioning, compared to the emission module 1211 of [Fig. 14] a saving of a semiconductor surface of approximately 0.04mm2. If, for example, silicon is used as the semiconductor, a saving of a silicon surface of approximately 0.04mm2 can be made.

[0182] The transmitting module 1212 of the present exemplary embodiment can therefore be manufactured and excited in a resource-saving and less expensive manner than the transmitting module 1211 of [Fig. 14]. The transmitting module 1212 of the present exemplary embodiment also requires less space than the transmitting module 1211 of [Fig. 14].

[0183] All the previously described embodiments of the transmission modules 121, 1210, 1211, 1212 of the transmission / reception devices 12, 22 of the stations 10, 20, 30 of the participants of the bus system 1 and of the method executed therein according to the first and second embodiment examples and their modifications can be applied individually or in all possible combinations. In addition, the following modifications can be considered in particular.

[0184] The bus system 1 described above according to the first and second embodiment examples is described using a bus system based on the CAN protocol. The bus system 1 according to the first and / or second embodiment examples can, however, alternatively be another type of communication network, in which the signals are transmitted in the form of differential signals. It is advantageous, but not a mandatory prerequisite, that in the bus system 1, at least for determined periods of time, collision-free exclusive access of a participant station 10, 20, 30 to the bus 40 is ensured.

[0185] The bus system 1 according to the first and / or second embodiment examples and their modifications is in particular a CAN bus system or a CAN-HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system. However, the bus system 1 may be another communication network, in which the signals are transmitted in the form of differential and serial signals via the bus.

[0186] The functionality of the previously described embodiments can thus be used, for example, in transmitting / receiving devices 12, 22, which can be excited in a CAN bus system or in a CAN-HS bus system or in a CAN FD bus system or in a CAN SIC bus system or in a CAN XL bus system.

[0187] It is possible, for both bus states 401, 402 at least from time to time, not to use dominant and recessive bus states, but, instead, a first bus state and a second bus state, both of which are energized. An example of such a bus system is a CAN XL bus system.

[0188] The number and arrangement of the participant stations 10, 20, 30 in the bus system 1 according to the first example and the second embodiment examples and their modifications is arbitrary. In particular, there may be only participant stations 10 or only participant stations 30 in the bus systems 1 of the first or second embodiment examples.

Claims

Claims

1. Module (121; 1210; 1211; 1212) for transmitting differential signals in a serial bus system (1) comprising a first transmission stage (121A; 121A0; 121A5; 121A6) for producing at least one transmission current (Il to In; IA1) for a first signal (CAN_H) to be sent on a bus (40) of the bus system (1), a second transmission stage (121B; 121B5) for producing at least one transmission current (Il to In; IB 1) for a second signal (CAN_L) to be sent on the bus (40) as a differential signal relative to the first signal (CAN_H), a third transmission stage (121C; 121C0; 121C5; 121C6) for producing at least one transmission current (Il to In; ICI) for the first signal (CAN_H) and a fourth transmission stage (121D; 121D5) for producing at least one transmission current (Il to In; ID1) for the second signal (CAN_L), in which the first to fourth transmission stages are mounted in a full bridge, in which the first and fourth stages (121A, 121D;121A0, 121D; 121A5, 121D5; 121A6, 121D5) are connected in series and the third and second emission stages (121C, 121B; 121C0, 121B; 121C5, 121B5; 121C6, 121B5) are connected in series, wherein each of the emission stages has at least two transistors (TM_CH1, TM_CHn; TM_CH, TM_CHs; TM_CL1, TM_CLn; TM_CL, TM_CLs; TC_CL1, TC_CLn; TC_CL, TC_CLs; TC_CH1, TC_CHn; TC_CH, TC_CHs) for producing at least one emission current (Il to In; IA 1; IB 1, ICI; ID1) and wherein the first and third emission stages are connected respectively by a polarity reversal diode (DI; D2) at a bus voltage supply terminal (43) for protection against a positive return feed into a terminal (43) for the bus voltage supply and a negative return feed from a terminal (44) for ground.;

2. Transmission module (121; 1210; 1211; 1212) according to claim 1, in which the output terminals (41, 42) of the bridge complete are provided for connection to a terminal resistor (49) of the bus (40).

3. Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, in which the polarity reversal diode (DI; D2) is a connected polarity reversal diode (DI; D2), which can be shunted or short-circuited.

4. Transmission module (1210; 1212) according to one of the preceding claims, in which the first and third transmission stages (121A0, 121C0; 121A6, 121C6) are connected by the same polarity inversion diode (D1) to the bus voltage supply terminal (43).

5. Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, in which the polarity reversal diode (D1; D2) is connected in a polarity reversal circuit (D_A; D_C; D_AC), which has, in addition to a first transistor (TR1; TR3), a second transistor (TR2; TR4) and a resistor (RI; R2) and in which the second transistor (TR2; TR4) has an on-state resistance value which is much smaller than the resistance value of the resistor (RI; R2).

6. Emission module (121; 1210; 1211; 1212) according to claim 5, wherein the drain terminal of the first transistor (TR1; TR3) is connected to the anode of the polarity reversal diode (D1; D2) wherein the source terminals of the first and second transistors (TR1, TR2; TR3, TR4) are connected to the cathode of the polarity reversal diode (D1; D2) wherein the gate terminal of the first transistor (TR1; TR3) is connected to the drain terminal of the second transistor (TR2; TR4) and is via the resistor (TR1; R2) connected to the terminal (44) for ground and wherein the gate terminal of the second transistor (TR2; TR4) is connected to the terminal (43) for the bus voltage supply.

7. A transmitting module (121; 1210; 1211; 1212) according to claim 5 or 6, wherein a gate terminal to source terminal section of the first transistor (TR1; TR3) has a filter (TR1, C1; R2, C2) for protection against pulse-type disturbances.

8. Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, wherein the second and fourth transmission stages (121B, 121D; 121B5, 121D5) each have a polarity reversal diode (D_B; D_D) for protection against a positive return supply in the terminal (43) for the bus voltage supply and a negative return supply from a terminal (44) for ground and wherein the polarity reversal diode (D_B; D_D) of the second transmission stage (121B; 121B0) and the fourth transmission stage (121D; 121D0) is a polarity reversal diode (D_B; D_D) of the pn type, which is a parasitic of a transistor and which is wired in a fixed manner so that the polarity reversal diode (D_B; D_D) cannot be shunted or short-circuited.

9. Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, in which the polarity reversal diodes (DI; D_B; D2; D_D) are designed to generate a median voltage (Vcm) of approximately 1.9 V when the transmission module (121; 1210) is operated with a voltage supply of approximately 3.3 V.

10. Transmission module (121; 1210; 1211; 1212) according to one of the preceding claims, further comprising a control circuit (T_A; T_B; T_C; T_D) for controlling connectable components of the first to fourth transmission stages depending on a digital transmission signal (TxD) and an operating type (SIC; FAST_TX) set for the transmission module (121; 1210; 1211; 1212).

11. Transmission module (121; 1210) according to claim 10, in which the control circuit (T_A; T_B; T_C; T_D) is designed for the time-staged and controlled connection of at least two current stages (SI to Sn) of the transmission stages (121A; 121A0; 121B; 121C; 121C0; 121D).

12. Transmission module (1211; 1212) according to one of the preceding claims, wherein each of the transmission stages (121A5; 121A6; 121B5; 121C5; 121C6; 121D5) has a current mirror composed of two transistors (TM_CH1, TM_CHn; TM_CH, TM_CHs; TM_CL, TM_CLs; TC_CL, TC_CLs; TC_CH, TC_CHs) for producing at least one transmission current (IA1; IB 1, ICI; ID1).

13. Transmission module (121; 1210) according to one of claims 1 to 11, wherein each of the transmission stages (121A; 121A0; 121B; 121C; 121C0; 121D) has at least two current stages (S1 to Sn), which are connected in parallel, wherein each of the at least two current stages (S1 to Sn) has a transistor (TM_CH1, TM_CHn; TM_CL1, TM_CLn; TC_CL1, TC_CLn; TC_CH1, TC_CHn) for producing the at least one transmission current (Il to In; IA1; IB1, ICI; ID1), wherein the at least two transistors have different dimensions and wherein a number n of the at least two current stages (S1 to Sn) is the same for each of the first to fourth emission stages, n being a natural number greater than 1.

14. Emission module (121; 1210; 1211; 1212) according to one of the preceding claims, in which the at least two transistors (TM_CH1, TM_CHn; TM_CH, TM_CHs; TM_CL1, TM_CLn; TM_CL, TM_CLs; TC_CL1, TC_CLn; TC_CL, TC_CLs; TC_CH1, TC_CHn; TC_CH, TC_CHs) for producing the at least one emission current (Il to In; IA 1; IB 1, ICI; ID1) are CMOS transistors.

15. Emission module (121; 1210; 1211; 1212) according to one of the preceding claims, in which the CMOS transistors of the first emission stage (121A; 121A0; 121A5; 121A6) are PMOS transistors, in which the CMOS transistors of the second emission stage (121B; 121B5) are NMOS transistors, in which the CMOS transistors of the third emission stage (121C; 121C0; 121C5; 121C6) are PMOS transistors, and in which the CMOS transistors of the fourth emission stage (121D; 121D5) are NMOS transistors.

16. Transmitting / receiving device (12; 22) for a participant station (20) for a serial bus system (1) comprising a transmitting module (121; 1210; 1211; 1212) according to one of the preceding claims and a receiving module (122) for receiving signals from the bus (40).

17. A participant station (10; 20; 30) for a serial bus system (1) comprising a transmitting / receiving device (12; 22) according to claim 16, a communication control device (11; 21) for controlling the communication in the bus system (1) and for generating a digital transmission signal (TxD) for controlling the first to fourth transmission stages.

18. Participant station (10; 20; 30) according to claim 17, wherein the participant station (10; 20; 30) is designed for communication in a bus system (1), in which at least occasionally collision-free exclusive access of a participant station (10, 20, 30) to the bus (40) of the bus system (1) is ensured.

19. Method for sending differential signals in a serial bus system (1), in which the method is carried out by a transmission module (121; 1210; 1211; 1212) and in which the method has the stages of producing, by a first transmission stage (121A; 121A0; 121A5; 121A6), at least one transmission current (I1 to In, IA1) for a first signal (CAN_H) to be sent on a bus (40) of the bus system (1), producing, by a second transmission stage (121B; 121B5), at least one transmission current (I1 to In; IB 1) for a second signal (CAN_L), which is to be sent on the bus (40) as a differential signal with respect to the first signal (CAN_H), producing, by a third stage (121C; 121C0; 121C5; 121C6) of emission, of at least one current (Il to In; ICI) of emission for the first signal (CAN_H) and production, by a fourth stage (121D; 121D5) of emission, of at least one current (Il to In;ID1) for transmitting the second signal (CAN_L), wherein the first to fourth transmitting stages are connected in a full bridge, wherein the first and fourth transmitting stages (121 A, 121D; 121A0, 121D; 121A5, 121D5; 121A6, 121D5) are connected in series and the third and second transmitting stages (121C, 121B; 121C0, 121 B; 121C5, 121B5; 121C6, 121B5) are connected in series, wherein each of the transmitting stages has at least two transistors (TM_CH1, TM_CHn; TM_CH, TM_CHs; TM_CL1, TM_CLn; TM_CL, TM_CLs; TC_CL1, TC_CLn; TC_CL, TC_CLs; TC_CH1, TC_CHn; TC_CH, TC_CHs) for producing at least one emission current (Il to In; IA 1; IB 1, ICI; ID1) and wherein the first and third emission stages are respectively connected by a polarity reversal diode (DI; D2) to a terminal (43) for the bus voltage supply for protection against a positive return supply in a terminal (43) for the bus voltage supply and a negative return supply from a terminal (44) for ground.

Images