Manufacturing process for a photonic or optoelectronic device
By employing a protective layer to isolate metal studs from resin contact during trench formation, the method addresses contamination and damage issues, ensuring the integrity of photonic or optoelectronic devices.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- STMICROELECTRONICS INT NV
- Filing Date
- 2024-05-17
- Publication Date
- 2026-06-05
AI Technical Summary
The existing manufacturing process for photonic or optoelectronic devices results in contamination or damage to metal studs, particularly aluminum studs, due to prolonged contact with resin during trench formation and subsequent resin removal.
A method involving the formation of a protective layer, such as an alumina or nitride layer, to cover the metal stud, followed by a passivation element with specific openings, allowing for the trench to be formed without direct contact with resin, and subsequent removal of the protective layer to access the stud.
Preserves the metal studs from contamination and damage while enabling the formation of deep trenches, ensuring the integrity and functionality of the device.
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Abstract
Description
Title of the invention: Method for manufacturing a photonic or optoelectronic device. Technical field
[0001] This description relates generally to photonic or optoelectronic devices, such as image acquisition devices or image sensors, and their manufacturing process. Previous technique
[0002] The manufacturing process for photonic or optoelectronic devices comprises several phases.
[0003] In a first phase (FEOL or 'front end of line'), components such as, among others, transistors, diodes, resistors and / or capacitors, are formed in and / or on a semiconductor substrate.
[0004] In a second phase (BEOL or 'back end of line') of the process, the components are interconnected by an electrical interconnection structure. An interconnection structure typically comprises conductive metallic tracks (or lines), generally several metallic tracks stacked on multiple levels and electrically insulated from each other by insulating layers. Vias pass through one or more insulating layers of the interconnection structure so as to electrically connect the metallic tracks together.
[0005] The interconnection structure end is the level furthest from the substrate. It may include at least one additional metal trace and / or at least one metal pad for connecting components of the integrated circuit to other locations of said integrated circuit or for connecting the integrated circuit to another electronic circuit, for example a printed circuit board.
[0006] The vias, the metal tracks, as well as the additional metal track, can be made of copper.
[0007] In the case of optical and / or photonic devices, the metallic pad is often made of aluminum in order to allow for wire bonding.
[0008] Such devices are also generally equipped with a trench extending from the top face of the device to the substrate. The depth of the trench can reach several tens of micrometers, particularly in the case of photonic devices.
[0009] Given the depth of the trench, it must be formed at the end of the process.
[0010] The trench is, for example, formed according to the following steps: - formation of a resin mask, the openings of the mask being arranged opposite the position of the trench, the resin mask covering the block, - engraving of the trench, - removal of the resin.
[0011] However, these steps can lead to contamination or damage to the aluminum stud because, on the one hand, prolonged contact between the polymer material of the resin and the aluminum stud results in contamination of the surface of the aluminum stud, and on the other hand, the removal of the resin can damage the surface of the stud. Summary of the invention
[0012] There is a need to obtain a manufacturing process for a photonic or optoelectronic device that allows deep trenches to be formed while preserving the metal studs of the device.
[0013] This goal is achieved by a method for manufacturing a photonic or optical device comprising the following steps: a) provide a semiconductor substrate having a first zone and a second zone, the semiconductor substrate being covered by a stack, an upper part of the stack covering the first zone being a dielectric layer in which an interconnecting element is formed, a metallic pad being formed on the interconnecting element, b) form a protective layer at least on the first area to cover at least the metal stud, c) form a passivation element on the first and second zones, the passivation element comprising a lower layer of a material different from the material of the protective layer, d) form a first opening in the passivation element above the metal stud, the first opening extending from an upper face of the passivation element to the protective layer, e) form a second opening at the level of the second zone, the second opening extending from an upper face of the passivation element to the semiconductor substrate, f) remove the protective layer positioned in the first opening to make the metal stud accessible.
[0014] According to one embodiment, the metal stud is made of aluminum.
[0015] According to one embodiment, the protective layer is an alumina layer.
[0016] According to one embodiment, the protective layer is removed by wet etching.
[0017] According to one embodiment, the protective layer is a nitride layer.
[0018] According to one embodiment, an additional oxide layer is formed at least on the metal pad between step a) and step b).
[0019] According to one embodiment, the protective layer is removed by dry etching.
[0020] According to one embodiment, the lower layer of the passivation element is in oxide. According to one embodiment, the passivation element comprises (at least) another oxide layer and / or a nitride layer.
[0021] According to one embodiment, the passivation element successively comprises a lower layer of undoped silicate glass, an intermediate layer of phosphorus-doped silicon oxide and an upper layer of nitride.
[0022] According to one embodiment, step d) is carried out by etching through a first layer of resin having a through hole opposite the first opening to be formed. According to another embodiment, step e) is carried out by etching through a second layer of resin having another through hole opposite the second opening to be formed, the second layer of resin filling the first opening, and wherein the process comprises, before step f), a step in which the resin filling the first opening is removed.
[0023] This objective is also achieved by a photonic or optical device comprising a support substrate having a first zone and a second zone, the semiconductor substrate being covered by a stack, an upper part of the stack covering the first zone being a dielectric layer in which an interconnecting element is formed, a metallic pad being formed on the interconnecting element, a passivation element covering the stack at the level of the first zone and the second zone, the passivation element comprising a lower layer, a protective layer being disposed between the stack and the passivation element, the lower layer being made of a material different from the material of the protective layer, a first opening extending from an upper face of the passivation element to an upper face of the metallic pad, a second opening,extending from the upper face of the passivation element to the semiconductor substrate, at the level of the second zone.
[0024] According to a particular embodiment, the second opening penetrates the semiconductor substrate to a depth of at least 10 pm.
[0025] According to a particular embodiment, the protective layer is made of alumina.
[0026] According to a particular embodiment, the protective layer is made of nitride and in in which an additional oxide layer is placed under the protective layer.
[0027] According to a particular embodiment, part of the stack covering the second zone is a waveguide. Brief description of the drawings
[0028] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:
[0029] Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9 and Fig. 10 represent, schematically, different stages of a manufacturing process of a photonic or optoelectronic device, according to a particular embodiment of the invention;
[0030] [Fig. 1 1] schematically represents, in side and cross-sectional view, a photonic or optoelectronic device, according to another particular embodiment of the invention; and
[0031] [Fig. 12] schematically represents, in side view and in section, a photonic device according to another particular embodiment of the invention.
[0032] In the various figures, the different elements are not represented at a uniform scale in order to make the figures more legible. Description of the implementation methods
[0033] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.
[0034] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, Figures 1 to 11 represent the semiconductor substrate and the upper level (or end) of the interconnection structure, i.e., the level furthest from the substrate. Furthermore, these figures represent only an insulating layer in this upper level, in which an interconnection element is formed and covered by a conductive pad. However, this upper level may include several interconnection elements (vias and / or pads), several conductive tracks, and / or other insulating layers. The interconnection structure also generally includes at least one other level below the upper level, in which, in particular, other interconnection elements are arranged. Between the upper level and the substrate, the device includes an intermediate level.For illustrative purposes, this intermediate level (denoted 'Zi') is shown in [Fig. 12]. In Figures 1 to 11, the upper part of the interconnection structure and the substrate are shown, but not the intermediate level, to make the figures more legible.
[0035] The vias and studs of the interconnection structure can be generally referred to as "interconnection elements", the interconnection elements may also include conductive tracks.
[0036] Also for the sake of clarity, the electronic components formed in or on the substrate are not shown.
[0037] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.
[0038] For the sake of clarity, the expressions "different materials," "chemically different materials," etc., when referring to two materials, mean that the two materials differ in terms of the elements present, their proportions, and / or the way in which the atoms are arranged in their structures. For example, they may have a different chemical nature (e.g., an oxide and a nitride) or they may belong to the same class of materials (e.g., they are both oxide materials), but they contain at least one structural element (i.e., an element with a stoichiometric percentage of at least 20%) that differs from each other. For example, aluminum oxide (Al₂O₃) and silicon dioxide (SiO₂) are considered to be two different materials.
[0039] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.
[0040] When referring to a layer, level or upper face or surface, reference is made to the layer, level or face or surface furthest from the substrate, compared to another layer, level, face or surface closer to the substrate.
[0041] Unless otherwise specified, the expressions "approximately", "roughly", and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.
[0042] Unless otherwise specified, between X and Y means that the terminals X and Y are included in the range.
[0043] In the following description, a layer or film is said to be transparent to radiation when the transmittance of the radiation through the layer or film is greater than 50%, and preferably greater than 70%.
[0044] The device may be a photonic device. It may also be an optoelectronic device.
[0045] We will now describe in more detail the manufacturing process of a photonic or optoelectronic device with reference to Figures 1 to 11.
[0046] The process comprises the following steps: a) provide a basic structure comprising a semiconductor substrate 100, having a first zone ZI and a second zone Z2, the substrate being covered by a stack, an upper part of the stack covering the first zone ZI being a dielectric layer 210 in which an interconnecting element 220 is formed, a metal pad 230 being formed on the interconnecting element 220 ([Fig.1]), b) form a protective layer 300 at least on the metal pad 230 ([Fig.2]), c) form a passivation element 400 covering the first zone ZI and on the second zone Z2 ([Fig.3]), d) form a first opening 601 in the passivation element 400 above the metal stud 230, the first opening 601 extending from an upper surface of the passivation element 400 to the protective layer 300 (figures 4 to 6), e) form a second opening 602 in the passivation element 400 at the level of the second zone Z2, the second opening 602 extending from a top surface of the passivation element 400 until it penetrates the substrate 100 (figures 7 to 9), f) remove the protective layer 300 positioned in the first opening 601 to make the metal stud 230 accessible ([Fig. 10]).
[0047] The basic structure provided in step a) (only part of which is shown in Figures 1 to 11) comprises a semiconductor substrate 100 covered by a stack.
[0048] The substrate 100 is made of a semiconductor material. Preferably, it is silicon. The substrate has, for example, a thickness of between 775 pm and 850 pm.
[0049] The substrate 100 is covered by a stack comprising different layers and different elements.
[0050] The stack can have a thickness of between 10 and 20 µm.
[0051] A first part of the stack is positioned above the first zone ZI and a second part of the stack is positioned above the second zone Z2.
[0052] The first part of the stack and the second part of the stack are adjacent. Each part can have its own function.
[0053] For example, in the case of a photonic device, the first part may include components covered by an interconnect structure and the second part of the stack may be, for example, a waveguide.
[0054] The components are, for example, transistors, diodes, resistors and / or capacitors, formed in and / or on the substrate 100.
[0055] The interconnection structure comprises insulating layers traversed by lines and / or vias and / or metallic studs. The lines, vias, and studs extend deep into the insulating layers.
[0056] The lines, vias, and studs are, for example, made of copper. The insulating layers are, for example, made of silicon dioxide (SiO2). The copper elements can be formed by a process known to those skilled in the art.
[0057] More specifically, the upper interconnecting layer 200 comprises an insulating layer 210 in which an interconnecting element 220 is formed. The interconnecting element 220 is an electrically conductive element. It is preferably made of copper. It may be a pad.
[0058] In the figures, the interconnecting element 220 is shown recessed from the top face of the insulating layer 210 of the interconnecting structure.
[0059] The interconnecting element 220 is covered by a metal pad 230. The conductive pad is preferably made of aluminum. It is, for example, formed by physical vapor deposition (PVD for 'Plasma Vapor Deposition').
[0060] During step b), a protective layer 300 is formed ([Fig.2]). This layer is intended to protect the stud 230, particularly during the formation of the second opening 602. The conductive stud 230 will not come into contact with the resin or with the products necessary for removing the resin.
[0061] The protective layer 300 is deposited at least on the upper face of the metal stud 230. Preferably, it is deposited at least on the first zone ZI. It can be deposited on the first zone ZI and on the second zone Z2. It can be deposited across the entire plate.
[0062] The protective layer 300 can be formed by an atomic layer deposition (ALD) technique or by a chemical vapor deposition (CVD) technique, for example a plasma-enhanced chemical vapor deposition (PECVD) technique.
[0063] The protective layer 300 can be made of a material selected from nitrides, carbides, carbonitrides and oxides (or a mixture thereof). In particular, the material is selected from silicon nitrides, silicon carbides, silicon carbonitrides and aluminum oxides (also called alumina).
[0064] In an embodiment not shown, the protective layer can be integrated into a multilayer protective element (e.g., a two-layer element). The materials forming each of the sub-layers can be chosen from the aforementioned materials. The multilayer protective element is, for example, a silicon nitride / alumina bilayer.
[0065] According to a first embodiment (figures 1-10), the protective layer 300 is preferably made of silicon nitride.
[0066] The protective layer 300 has a thickness between 30 and 80 nm, preferably between 40 and 60 nm.
[0067] An additional oxide layer 310 can be disposed under the protective layer 300. In other words, the additional layer 310 is positioned between, on the one hand, the protective layer 300 and, on the other hand, the pad 230 and the upper interconnecting layer 200. The additional layer 310 can be a layer used to simplify the deposition of the protective layer 300.
[0068] The additional layer 310 is, for example, made of silicon oxide.
[0069] The additional layer 310 has, for example, a thickness between 10 and 30 nm, for example 20 nm.
[0070] Such an additional layer 310 is shown for example in Figures 1 to 10.
[0071] According to a second embodiment, as shown in Figures 11 and 12, the protective layer 300 can be in direct contact with the pad 230 and the upper interconnecting layer 200. In this second embodiment, there is no intermediate layer between these elements and the protective layer 300. The protective layer 300 can be an oxide layer, in particular an alumina layer.
[0072] The alumina layer has, for example, a thickness of between 20 and 40 nm, for example 30 nm.
[0073] The alumina layer can be formed by ALD ('Atomic Layer Deposition').
[0074] During step c), a passivation element 400 is formed ([Fig.3]).
[0075] The passivation element 400 may be a single layer or a stack of several layers (multilayer), in particular a bilayer or a trilayer. The protective layer 400 comprises at least one substantially moisture-proof layer for protecting the underlying elements from moisture. This is in particular a nitride layer. More preferably, it comprises a nitride layer 430 disposed on one or more (preferably two) oxide layers 410, 420.
[0076] The oxide layers 410, 420 are in particular selected from undoped silicate glass (USG for 'undoped silicate glass') or phosphosilicate glass (PSG for 'Phosphorus Silicate Glass').
[0077] The passivation element 400 comprises, for example, successively from the protective layer 300: - a first layer of oxide 410 (lower layer), preferably in USG, - a second layer of oxide 420 (intermediate layer), preferably in PSG, - a nitride layer 430 (top layer), preferably silicon nitride.
[0078] The thickness of the oxide layer(s) 410, 420 can be between 500 and 2000 nm, for example equal to 1500 nm, or between 500 and 1500 nm.
[0079] The first oxide layer 410 and the second oxide layer 420 form a bilayer whose thickness is between 500 nm and 2 pm.
[0080] The thickness of the nitride layer 430 can be between approximately 300 and 700 nm, for example approximately 500 nm.
[0081] The passivation element 400 is adapted to protect certain elements of the device, and in particular the interconnection structure.
[0082] The different layers of the passivation element can be formed by CVD, in particular by PECVD.
[0083] During step d), a first opening 601 is formed in the first zone Zl, above the pad 230. The opening 601 extends from an upper face of the passivation element 400 to the protective layer 300. The opening may extend to the upper surface of the protective layer 300 or stop within the thickness of the protective layer 300. In particular, the first opening 601 is formed by photolithography.
[0084] In order to perform selective etching, the material of the protective layer 300 is (chemically) different from the material of the lower layer 410 of the passivation element 400 (i.e., the layer of the passivation element 400 closest to the protective layer 300 in a vertical direction). Preferably, the lower layer 410 is in contact with the protective layer 300.
[0085] In the case of a multilayer protective element, the material of at least the protective layer 300 is (chemically) different from the material of the lower layer 410, while the other sub-layer can be made of any of the materials described above.
[0086] The first opening 601 is, for example, formed according to the following steps: - form a layer of resin 500 on the protective layer 400, the resin layer comprising at least one through hole 501 disposed opposite the stud 230 ([Fig.4]), - engrave the passivation element 400 through the pattern ([Fig.5]), - remove the resin 500 ([Fig.6]).
[0087] Fig. 6 illustrates the structure obtained after a photolithography step carried out on the upper face of the passivation element 400.
[0088] The pattern can be obtained by conventional photolithography steps, namely: - the deposition of a layer of 500 photosensitive resin; - exposing the 500 photosensitive resin layer to radiation through a mask formed of defined opaque and transparent zones to obtain a desired pattern in the resin; and - the dissolution in a specific aqueous or organic solution, called a development solution, of part of the resin layer to develop the pattern and form a through opening 501 above the stud 230.
[0089] The pattern shown is obtained, for example, using a positive photosensitive resin. The portion of the resin exposed to radiation (through the transparent areas of the mask) becomes soluble in the developing solution, and the portion of the resin not exposed (through the opaque areas of the mask) remains insoluble in the developing solution. Alternatively, the photosensitive resin can be negative. The portion of the resin exposed to radiation then becomes insoluble in the developing solution, and the portion of the resin not exposed remains soluble in the developing solution.
[0090] The engraving of the passivation element 400 is carried out through the resin pattern forming an engraving mask, so that the engraving takes place in the openings 501 of the pattern and in the areas not covered by said pattern.
[0091] The etching forms a cavity 601 (first opening) above the pad 230 in the passivation element 400. The protective layer 300 may not be etched or may be substantially not etched. The bottom of the cavity 601 is located on the upper surface of the protective layer 300 or within the thickness of the protective layer 300. In this case, the bottom of the cavity 601 is (substantially) located on the upper surface of the protective layer 300. Alternatively, the protective layer 300 may be partially etched, for example, due to partial over-etching during the etching step. In this case, the bottom of the cavity 601 is located within the thickness of the protective layer 300.
[0092] The etching can be a dry etching, for example using a fluorine-based plasma, or a wet etching, in particular using a fluorinated acid solution, for example hydrofluoric acid.
[0093] The concentration of acid in the solution and / or the etching time can be adjusted to etch to a given depth.
[0094] Next, a step of removing the resin layer 500 is carried out, for example by dry etching, in particular by implementing an oxygen-based plasma.
[0095] The first opening 601 forms a cavity. The width of the cavity 601 is defined by the width of the opening 501 in the resin pattern. The height of the cavity 601 is defined by the engraving depth.
[0096] For example, the first opening 601 has a circular cross-section. The diameter of the cross-section can be between 40 and 50 µm. The height of the cavity depends on the thickness of the passivation element 400.
[0097] At the end of step d), the protective layer 300 is still present. It acts as an etching stop layer.
[0098] During step e), a second opening 602 is formed at the level of the second zone Z2.
[0099] The second opening 602 is a deep trench. By deep, we mean a depth of at least 10 µm. The second opening has, for example, a depth of between 10 and 100 µm. The second opening 602 extends at least to the upper surface of the substrate 100 and, preferably, into the substrate 100. A portion of the substrate 100 is etched. The substrate 100 can be etched to a depth of 5 to 60 µm.
[0100] The second opening 602 has, for example, a cross-section greater than 1 mm2.
[0101] The second opening 602 is, for example, formed according to the following steps: - form a layer of resin 510 on the protective layer 400, the resin layer 510 having a through hole 511 positioned above the second zone Z2, the resin layer 510 filling the first opening 601 ([Fig.7]), - make a second opening 602 in the device, the second opening 602 being made by engraving from the top face of the passivation element 400, the second opening 602 extending into the substrate 100 ([Fig.8]), - remove the resin layer 510 ([Fig.9]).
[0102] The etching can be a dry etching, for example using a fluorine-based plasma, or a wet etching, in particular using a fluorinated acid solution, for example hydrofluoric acid.
[0103] The concentration of acid in the solution and / or the etching time can be adjusted to etch to a given depth.
[0104] The protective layer 300 forms an intermediate layer between the conductive pad 230 and the resin 510, but also between the pads 230 and the products required for resin removal. The protective layer 300 forms a diffusion barrier layer.
[0105] During step f), the protective layer 300 (and, in this case, any other underlayer of the multilayer protective element), and optionally the additional layer 310, are removed to make the stud 230 accessible.
[0106] When the protective layer 300 includes a nitride layer, the etching is, for example, a plasma etching.
[0107] When the protective layer 300 is an alumina layer, the etching is, for example, a wet etching.
[0108] At the end of the process, a device is obtained having, in the first zone, a new cavity 601' at the bottom of which the metal stud 230 is accessible, and, in the second zone, a deep trench 602 (Figures 10 to 12). The surface of the stud 230 is neither contaminated nor damaged. The volume of the cavity 601' corresponds to the total volume encompassing the volume of the cavity 601 and the volume previously occupied by the protective layer 300, and possibly by the additional oxide layer 310.
[0109] Fig. 12 represents, by way of illustration and not limitation, a photonic device obtained with such a process.
[0110] At the level of the first zone, there is at least one cavity 601. A stud 230 is disposed in the cavity 601. It can be used to connect the device to an external element.
[0111] In the second zone Z2, a deep trench 602 is formed. It extends from the upper surface of the passivation element 400 into the substrate 100. It traverses the entire thickness of the first part of the stack. The deep trench 602 can be used for a laser, for example.
[0112] The nitride layer 430 forming the top layer of the passivation element 400 can be structured to allow light to pass through.
[0113] The use of a 300 protective layer formed from an alumina monolayer is particularly advantageous since it is transparent. It can even be used for nitride-based waveguides.
[0114] The optical device can be used as an image acquisition device operating in the near-infrared (NIR for 'Near InfraRed'), that is to say for electromagnetic radiation with a wavelength between 800 nm and 2500 nm, and more particularly, in the short-wave infrared (SWIR or 'Short-Wave InfraRed'), that is to say for electromagnetic radiation with a wavelength between 800 nm and 2000 nm, preferably between 900 nm and 1700 nm, typically 1.4 pm.
[0115] The device can also be used in the implementation of 5G networks, data centers and servers.
[0116] The device is, for example, intended to be used in communication equipment, or in computers and peripherals.
[0117] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.
[0118] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.
Claims
Demands
1. A method for manufacturing a photonic or optical device comprising the following steps: a) providing a semiconductor substrate (100) having a first zone (Z1) and a second zone (Z2), the semiconductor substrate (100) being covered by a stack, an upper portion of the stack covering the first zone (Z1) being a dielectric layer (210) in which an interconnecting element (220) is formed, a metal pad (230) being formed on the interconnecting element (220), b) forming a protective layer (300) at least on the first zone (Z1) to cover at least the metal pad (230), c) forming a passivation element (400) on the first zone (Z1) and the second zone (Z2), the passivation element (400) comprising a lower layer (410) of a material different from the material of the protective layer (300), d) forming a first opening (601) in the passivation element (400) above the metal stud (230),the first opening (601) extending from an upper face of the passivation element (400) to the protective layer (300), e) form a second opening (602) at the level of the second zone (Z2), the second opening (602) extending from an upper face of the passivation element (400) to the semiconductor substrate (100), f) remove the protective layer (300) positioned in the first opening (601) to make the metal pad (230) accessible.
2. Method according to claim 1, wherein the metal stud (230) is made of aluminium.
3. A method according to any one of claims 1 and 2, wherein the protective layer (300) is an alumina layer.
4. Method according to the preceding claim, wherein the protective layer (300) is removed by wet etching.
5. A method according to any one of claims 1 and 2, wherein the protective layer (300) is a nitride layer.
6. A method according to the preceding claim, wherein an additional oxide layer (310) is formed at least on the metal pad (230) between step a) and step b).
7. A method according to any one of claims 5 and 6, wherein the protective layer (300) is removed by dry etching.
8. A method according to any one of the preceding claims, wherein the lower layer (410) is made of oxide, the passivation element further comprising another oxide layer (420) and / or a nitride layer (430).
9. A method according to any one of the preceding claims, wherein the passivation element (400) successively comprises a lower layer of undoped silicate glass (410), an intermediate layer of phosphorus-doped silicon oxide (420) and an upper layer of nitride (430).
10. A method according to any one of the preceding claims, wherein step d) is carried out by etching through a first layer of resin (500) having a through hole (501) opposite the first opening (601) to be formed and wherein step e) is carried out by etching through a second layer of resin (510) having another through hole (511) opposite the second opening to be formed (602), the second layer of resin (510) filling the first opening (601) and wherein the method comprises, before step f), a step in which the resin filling the first opening (601) is removed.
11. A photonic or optical device comprising a support substrate having a first zone (Z1) and a second zone (Z2), the semiconductor substrate (100) being covered by a stack, an upper portion of the stack covering the first zone (Z1) being a dielectric layer (210) in which an interconnecting element (220) is formed, a metallic pad (230) being formed on the interconnecting element (220), a passivation element (400) covering the stack at the level of the first zone (Z1) and the second zone (Z2), the passivation element (400) comprising a lower layer (410), a protective layer (300) being disposed between the stack and the passivation element (400), the lower layer (410) being made of a material different from the material of the protective layer (300), a first opening (601') extending from an upper face of the passivation element (400) up to an upper face of the metal stud (230),
12.
13.
14.
15. a second opening (602), extending from the upper face of the passivation element (400) to the semiconductor substrate (100), at the level of the second zone (Z2). Device according to the preceding claim, wherein the second opening (602) penetrates the semiconductor substrate (100) to a depth of at least 10 pm. Device according to any one of claims 11 and 12, wherein the protective layer (300) is made of alumina. Device according to any one of claims 11 and 12, wherein the protective layer (300) is made of nitride and wherein an additional layer (310) made of oxide is disposed under the protective layer (300). Device according to any one of claims 11 to 14, wherein a part of the stack covering the second zone (Z2) is a waveguide.