METHOD FOR MANUFACTURING AN EDGE-SHAPED OPTICAL WAVEGUIDE

Abstract

According to one aspect, a method for manufacturing an edge waveguide (WG1) of an optical integrated circuit (IC) is proposed, the method comprising: - forming an initial edge waveguide structure (STR) from a silicon (SOI) layer formed on an insulator (ISO) layer, then - forming a mask (MSK) having an aperture (OPN) opposite an edge (RDG) of said initial structure (STR), then - oxidation carried out so as to reduce the thickness of the edge (RDG) of said initial structure located opposite said aperture (OPN) of the mask (MSK), in order to obtain, from said initial structure (STR), an optical waveguide (WG1) having an edge (RDG) of a thickness less than the thickness of the edge of the initial structure (STR), then - removing the mask (MSK). Figure for the abstract: Figure 1

Description

Title of the invention: METHOD FOR MANUFACTURING AN EDGE-SHAPED OPTICAL WAVEGUIDE

[0001] Embodiments and implementation methods relate to integrated circuits configured to propagate optical waves.

[0002] Optical integrated circuits (in English "photonic integrated circuits") are circuits configured to propagate light.

[0003] Optical integrated circuits that use silicon as a base material for manufacturing optical components are known. These optical integrated circuits can be designated by the term "SiPho" (from the English "Silicon Photonics").

[0004] In particular, "SiPho" type integrated circuits exploit the compatibility of silicon with semiconductor manufacturing processes to create optical components. This allows for efficient integration with electronic circuits.

[0005] Integrated circuits of the "SiPho" type include, in particular, optical waveguides. These optical waveguides allow light to be directed and manipulated within the optical integrated circuits. These optical waveguides are essentially silicon structures that confine and channel light from one point to another.

[0006] Ridge waveguides (also known as ridge or rib waveguides) are well known optical structures particularly common in semiconductor-based technologies, such as devices based on III-V materials (materials composed of one or more elements from columns III and V of the periodic table), such as gallium arsenide (GaAs) or indium phosphide (InP). Ridge waveguides are used in a variety of applications, including semiconductor lasers, optical modulators, photodiode detectors, and other integrated optical components. They are particularly well-suited to devices requiring light confinement in a specific direction.

[0007] A ridge waveguide comprises a slab layer, a cladding layer, and a ridge or rib projecting over the slab layer, the ridge having a width less than that of the slab layer. The ridge waveguide can be made from a silicon-on-insulator layer.

[0008] The edge thickness of an edge-on waveguide is defined by the initial thickness of the silicon layer on the insulator. However, for some optical integrated circuits, the optimal edge thickness of an edge-on waveguide differs from the initial thickness of the silicon layer on the insulator. In particular, the edge thickness directly impacts the edge propagation index. For example, in a hybrid laser, coupling between a stack of III-V materials (materials composed of one or more elements from columns III and V of the periodic table) and the silicon on the insulator requires an edge thickness of 500 nanometers. In a PN junction of a modulator, capacitance is optimized using an edge thickness between 150 nanometers and 310 nanometers. In a fiber network coupler, optimal efficiency is achieved by using an edge thickness of approximately 300 nanometers.

[0009] Thus, it is important to provide solutions allowing for optical waveguide edges of different thicknesses in the same semiconductor wafer in order to integrate into the same integrated circuit devices requiring different edge thicknesses in the same semiconductor wafer to optimize their performance.

[0010] In particular, a known method for manufacturing an edge waveguide comprises, firstly, an initial etching step to define a new thickness of the silicon-on-insulator layer and waveguide edges having a thickness greater than the new silicon layer thickness. Next, the method comprises a photolithography step followed by etching to locally reduce the thickness of the ribbon layer and to define new edge waveguide edges having the thickness of the silicon-on-insulator layer obtained by the initial etching step. Finally, the manufacturing process comprises a step of depositing an insulating layer, in particular silicon dioxide, up to the surface of the edges with the greatest thickness.

[0011] Such a solution has the disadvantage of resulting in significant surface roughness of the edges, since these edges are defined by etching. Such roughness degrades the propagation of optical waves in the waveguide. Furthermore, the etching performed after photolithography has low resolution. Thus, the edges defined by this etching exhibit significant edge roughness, which also degrades the propagation of optical waves.

[0012] Furthermore, the thickness of the edges defined by the etching following photolithography corresponds to the thickness of the silicon-on-insulator layer obtained after the initial etching step. Such a manufacturing process does not allow for an edge thickness different from the thickness of the silicon-on-insulator layer obtained after the initial etching step.

[0013] According to one aspect, a method for manufacturing an edge waveguide of an optical integrated circuit is proposed, the method comprising:

[0014] - the formation of an initial edge-guided optical waveguide structure from of a silicon layer formed on an insulating layer, then

[0015] - a formation of a mask having an opening opposite an edge of said initial structure, then

[0016] - an oxidation carried out in such a way as to reduce the thickness of the edge of said structure initial structure located opposite said opening of the mask, in order to obtain, from said initial structure, an optical waveguide having an edge thickness less than the thickness of the edge of the initial structure, then

[0017] - a removal of the mask.

[0018] In such a manufacturing process, the edge height of the waveguide is defined after forming an initial waveguide structure. In particular, the edge height of the waveguide is adjusted by oxidation after forming said initial waveguide structure.

[0019] Such a manufacturing process has the advantage of maintaining a relatively low surface roughness on the edge of a waveguide. For example, the surface roughness of the edge can be less than 2.5 nanometers. Indeed, the photolithography performed has a high resolution, which makes it possible to obtain low roughness, and the edge thickness is reduced by oxidation, which does not add surface roughness.

[0020] Furthermore, such a manufacturing process makes it possible to locally reduce the edge thickness of an edge waveguide in order to maintain a greater silicon-on-insulator thickness for other components of the optical integrated circuit where this greater thickness allows for better performance. Thus, such a process makes it possible to fabricate an edge waveguide with a different thickness than the initial silicon-on-insulator thickness.

[0021] In an advantageous embodiment, the mask formation is carried out so that the mask covers at least a transition portion of the edge of the initial structure and the opening of the mask is opposite a main portion of the edge of the initial structure, said at least a transition portion extending longitudinally from the main portion.

[0022] In this way, oxidation makes it possible to reduce only the thickness of the main portion of the edge.

[0023] In such an embodiment, the adjustment of the thickness of the main portion and the formation of said at least one transition portion of an edge waveguide are carried out simultaneously.

[0024] In an advantageous embodiment, said at least one transition portion has a width decreasing towards the main portion of the edge of the edge waveguide.

[0025] Advantageously, said at least one transition portion has a pointed shape directed towards the main portion of the edge of the edge waveguide.

[0026] Preferably, the formation of the initial structure comprises a photolithography of the silicon layer onto the insulating layer so as to form: - a ribbon layer of the initial structure, and - said edge on said ribbon layer.

[0027] Advantageously, said photolithography is carried out in such a way as to define a final thickness of the layer in ribbon for said waveguide in edge.

[0028] Such an implementation method has the advantage of allowing an independent definition of the thickness of the ribbon layer and of the edge thickness.

[0029] In an advantageous embodiment, the process includes, prior to the formation of said mask, the formation of a dielectric coating on said initial structure, said dielectric coating having an opening opposite the edge of said initial structure.

[0030] Advantageously, the process includes, prior to the formation of said mask, a mechanochemical polishing adapted to reduce the thickness of the dielectric coating.

[0031] Preferably, the method further comprises removing the oxide obtained by said oxidation and then depositing a dielectric coating on the edge of the waveguide before removing the mask.

[0032] Advantageously, the ribbon layer is formed so as to have a thickness between 50 nanometers and 150 nanometers.

[0033] Preferably, the oxidation is carried out so that the edge of the waveguide has a thickness between 100 nanometers and 230 nanometers.

[0034] According to another aspect, an integrated circuit is proposed comprising an edge optical waveguide obtained by implementing a manufacturing process as described above.

[0035] Thus, an integrated circuit is proposed comprising an optical waveguide with an edge having an edge surface roughness of less than 2.5 nanometers.

[0036] Advantageously, the integrated circuit further comprises at least one optical waveguide having a different thickness compared to the edge thickness of the waveguide edge.

[0037] Other advantages and features of the invention will become apparent upon examination of the detailed description of embodiments, which are by no means limiting, and the accompanying drawings in which:

[0038] [Fig.1]

[0039] [Fig.2]

[0040] [Fig.3]

[0041] [Fig.4]

[0042] [Fig.5]

[0043] [Fig.6]

[0044] [Fig.7] illustrate embodiments and implementations of the invention.

[0045] Figure 1 illustrates a cross-sectional view of an embodiment of an integrated circuit (IC). This integrated circuit comprises a substrate layer SUB, an insulating layer ISO on the substrate layer SUB, a silicon layer SOI on the insulating layer ISO, and a dielectric coating DIEL. The silicon layer SOI is used to form optical waveguides WG1, WG2, WG3 and other electronic components (not shown).

[0046] The ISO insulating layer is formed of a dielectric material, for example silicon dioxide. The ISO insulating layer typically has a thickness between 700 nanometers and 5 micrometers.

[0047] The silicon SOI layer on the ISO insulator is a layer that can be designated by the English expression "Silicon on Insulator".

[0048] The optical waveguides WG1, WG2, WG3 are formed in the silicon SOI layer on the ISO insulator. These waveguides WG1, WG2, WG3 can be juxtaposed with other waveguides so that light can propagate between these waveguides.

[0049] Figure 2 illustrates a three-dimensional view of an embodiment of a portion of a WG1 waveguide. The WG1 optical waveguide is a ridge waveguide (also known as a rib waveguide). This WG1 optical waveguide therefore includes a slab layer (SLB). The slab layer corresponds to a planar portion of the ridge waveguide. The slab layer has a thickness E_SLB between 50 nanometers and 150 nanometers. The thickness E_SLB of the slab layer can vary between the different WG1 and WG2 optical waveguides. The slab layer has a width W_SLB sufficiently large so that the optical mode does not extend beyond its ends and is suitable for avoiding interactions with other waveguides. For example, the W_SLB width of the SLB ribbon layer is between 2pm and 5pm.

[0050] The WG1 edge waveguide also includes an RDG (ridge) overlying the SLB ribbon layer. This RDG is formed from the same SOI silicon layer as the SLB ribbon layer. This RDG extends longitudinally over the SLB ribbon layer.

[0051] The edge RDG may have a main portion RDG_P and at least one transition portion RDG_T extending to a longitudinal end of the edge. Said at least one transition portion RDG_T has a shape adapted to improve wave propagation between said at least one transition portion RDG_T and the main portion RDG_P.

[0052] Said at least one transition portion RDG_T has a pointed shape in the longitudinal direction of the edge RDG, the point being oriented towards said main portion RDG_P. The transition portion RDG_T therefore has a width that decreases along its length up to the main portion.

[0053] The main portion RDG_P of the edge RDG has a thickness E_RDG_P less than the thickness E_RDG_T of said at least one transition portion RDG_T. In particular, the main portion RDG_P has a thickness E_RDG_P between 100 nanometers and 230 nanometers.

[0054] The main portion RDG_P has a width W_RDG_P between 300 nanometers and 2 micrometers, in particular between 300 nanometers and 800 nanometers.

[0055] The transition portion RDG_T makes it possible to improve wave propagation between the main portion RDG_P and other waveguides extending this waveguide at edge WG1 and having a thickness corresponding to the thickness of said at least one transition portion RDG_T.

[0056] The transition portion RDG_T has a length L_RDG_T between 500 nanometers and 5 micrometers, for example on the order of 1 micrometer.

[0057] The RDG edge and the SLB ribbon layer of the edge waveguide exhibit low roughness, in particular less than 2.5 nanometers.

[0058] [Fig.3] illustrates an implementation method of manufacturing an integrated circuit such as that illustrated in [Fig.1].

[0059] The process includes a step 20 of forming an initial edge-guided STR structure from a WFR semiconductor wafer (which may also be referred to as a "wafer"). This WFR wafer comprises a SUB substrate, an ISO insulating layer on the SUB substrate, and a SOI silicon layer on the ISO insulating layer. The SOI silicon layer may have a thickness of 300 nanometers, for example.

[0060] The initial STR structure is used to then obtain an edge waveguide WG1 as described previously.

[0061] The initial STR waveguide structure is formed from the SOI silicon layer by performing high-resolution photolithography. This makes it possible to obtain low line edge roughness.

[0062] The initial STR structure comprises an SLB ribbon layer, an RDG edge, and a sheath layer (including, in particular, the ISO insulation layer and the coating (dielectric DIEL). The RDG edge has a thickness corresponding to the initial thickness of the silicon SOI layer on the ISO insulator. This thickness is therefore greater than the desired thickness for the RDG edge.

[0063] The formation of the initial STR structure nevertheless allows the desired thickness of the SLB ribbon layer of the edge waveguide to be defined.

[0064] The process also includes a step 21 of depositing a dielectric coating DIEL onto the wafer, in particular onto the initial STR structure of optical waveguides. This dielectric coating DIEL is formed so as to have an opening opposite the RDG edge of the initial STR structure of optical waveguides, for which a reduction in the thickness of the RDG edge is desired. This dielectric coating DIEL can, in particular, be made of silicon dioxide.

[0065] An embodiment of such an initial STR structure is illustrated in [Fig. 4].

[0066] The process also includes a mechanochemical polishing step 22 for reducing the thickness of the dielectric coating DIEL so that its upper surface extends to a height slightly greater than the height of the edge RDG of the initial STR waveguide edge structure. For example, the height of the upper surface of the dielectric coating DIEL is greater than the height of the edge RDG by a distance of between 1 nanometer and 20 nanometers. This mechanochemical polishing step 22 allows the thickness of the dielectric coating to be adjusted.

[0067] This mechanochemical polishing step 22 also makes it possible to obtain an electrical coating having a smooth upper surface in order to simplify the application of the MSK hard mask, as described below.

[0068] Once the mechanochemical polishing has been carried out, a thin layer of silicon oxide can be kept on the RDG edge in order to avoid damaging the waveguide.

[0069] The process includes a step 23 of forming an HMSK hard mask on the DIEL dielectric coating. An HMSK hard mask is a layer made from a robust and durable material, this layer having a predefined-shaped OPN aperture. The HMSK hard mask can, in particular, be made of SiN. The HMSK hard mask can be obtained by depositing a layer of SiN followed by photolithography and etching to obtain the OPN aperture.

[0070] In particular, the HMSK hard mask is formed so as to present an OPN aperture opposite a principal portion RDG_P of the edge RDG of the initial STR edge-guide structure, for which a reduction in the edge thickness is desired. The HSMSK hard mask is also formed so as to cover at least one transition portion RDG_T of the edge of the initial STR edge-guide structure.

[0071] More specifically, the MSK mask opening has a width greater than the RDG edge width in order to compensate for poor lithographic alignment and to use a low-cost, low-resolution mask.

[0072] Figures 5(a) and 5(b) illustrate an initial STR edge waveguide structure and an HMSK hard mask that can be obtained after the HMSK hard mask formation. In particular, [Fig. 5](b) is a top view of the edge waveguide and [Fig. 5](a) is a cross-sectional view along plane AA shown in [Fig. 5](b).

[0073] The process further comprises an oxidation step 24. The oxidation transforms a portion of the silicon on the surface of the RDG edge of the initial STR structure into silicon oxide. This reduces the thickness of the RDG edge of the waveguide in the portion not covered by the HMSK mask.

[0074] The duration of the oxidation allows the final thickness of the RDG edge of the waveguide to be defined.

[0075] The oxidation step makes it possible to obtain an edge waveguide WG1 having an edge RDG having a main portion RDG_P and at least one transition portion RDG_T, the main portion RDG_P having a thickness less than the thickness of said at least one transition portion RDG_T.

[0076] The silicon oxide generated by the oxidation may or may not then be removed. A layer of DIEL dielectric, in particular silicon dioxide, is also deposited to fill the opening in the coating above the edge of the waveguide that has undergone said oxidation. The process may then include a mechanochemical polishing step.

[0077] Figures 6(a) and 6(b) illustrate a WG1 edge waveguide and a HMSK hard mask that can be obtained by depositing the dielectric thickness DIEL above the edge of the edge waveguide. In particular, [Fig. 6](b) is a top view of the edge waveguide and [Fig. 6](a) is a cross-sectional view along the AA plane shown in [Fig. 6](b).

[0078] The process then includes a step 25 of removing the HMSK mask.

[0079] Figures 7(a), 7(b) and 7(c) illustrate an edge waveguide that can be obtained after the removal of the HMSK hard mask. In particular, [Fig.6] (b) is a top view of the edge waveguide, [Fig.7] (a) is a cross-sectional view along plane AA illustrated in [Fig.7] (b), and [Fig.7] (c) is a longitudinal cross-sectional view along plane BB illustrated in [Fig.7] (b).

[0080] Steps 23 to 25 can be repeated to define waveguides having edges of different thicknesses.

[0081] Such a manufacturing process can be implemented to manufacture an integrated circuit such as that illustrated in [Fig.1].

[0082] In such a manufacturing process, the height of the edges of an edge waveguide is defined after first forming an initial edge waveguide structure. In particular, the edge height of the edge waveguide is adjusted by oxidation after forming the initial edge waveguide structure.

[0083] Furthermore, in such a manufacturing process the adjustment of the thickness of the main portion and the formation of said at least one transition portion of an edge waveguide are carried out simultaneously.

[0084] Such a manufacturing process has the advantage of maintaining relatively low surface roughness on the edges of the waveguides. For example, the surface roughness of the edge can be less than 2.5 nanometers. Indeed, the photolithography performed has a high resolution, which makes it possible to obtain low roughness, and the edge thickness is reduced by oxidation, which does not add surface roughness.

[0085] Such a manufacturing process also has the advantage of allowing the thickness of the layer in the ribbon and the thickness of the edge to be defined independently.

Claims

Demands

1. Method of manufacturing an edge waveguide (WG1) of an optical integrated circuit (IC), the method comprising: - forming an initial structure (STR) of an optical edge waveguide from a silicon layer (SOI) formed on an insulator layer (ISO), then - forming a mask (HMSK) having an opening (OPN) opposite an edge (RDG) of said initial structure (STR), then - oxidation carried out so as to reduce the thickness of the edge (RDG) of said initial structure located opposite said opening (OPN) of the mask (HMSK), in order to obtain, from said initial structure (STR), an optical waveguide (WG1) having an edge (RDG) of a thickness less than the thickness of the edge of the initial structure (STR), then - removing the mask (HMSK).

2. A method according to claim 1, wherein the mask (HMSK) formation is carried out such that the mask (HMSK) covers at least one transition portion (RDG_T) of the edge (RDG) of the initial structure (STR) and that the opening (OPN) of the mask (MSK) is opposite a main portion (RDG_P) of the edge (RDG) of the initial structure (STR), said at least one transition portion (RDG_T) extending longitudinally from the main portion (RDG_P).

3. Method according to claim 2, wherein said at least one transition portion (RDG_T) has a width decreasing towards the main portion (RDG_P) of the edge (RDG) of the edge waveguide.

4. Method according to claim 3, wherein said at least one transition portion (RDG_T) has a pointed shape directed towards the main portion (RDG_P) of the edge of the edge waveguide.

5. A method according to any one of claims 1 to 4, wherein the formation of the initial structure comprises photolithography of the silicon layer (SOI) onto the insulator layer (ISO) so as to form: - a ribbon layer (SLB) of the initial structure, and - said edge on said layer in ribbon (SLB).

6. Method according to claim 5, wherein said photolithography is carried out so as to define a final thickness of the ribbon layer (SLB) for said edge waveguide (WG1).

7. A method according to any one of claims 1 to 6, comprising, prior to the formation of said mask (HMSK), the formation of a dielectric coating (DIEL) on said initial structure (STR), said dielectric coating (DIEL) having an opening opposite the edge of said initial structure (STR).

8. Method according to claim 7, comprising, prior to the formation of said mask (HMSK), a mechanochemical polishing adapted to reduce the thickness of the dielectric coating (DIEL).

9. A method according to any one of claims 1 to 6, further comprising removing the oxide obtained by said oxidation and then depositing a dielectric coating on the edge (RDG) of the waveguide at the edge before removing the mask (HMSK).

10. A method according to any one of claims 5 to 9, wherein the ribbon layer is formed so as to have a thickness (E_SLB) between 50 nanometers and 150 nanometers.

11. A method according to any one of claims 1 to 9, wherein the oxidation is carried out so that the edge of the waveguide edge has a thickness (E_RDG_P) between 100 nanometers and 230 nanometers.

12. A method according to any one of claims 1 to 11, further comprising a formation of at least one optical waveguide (WG2, WG3) having a different thickness compared to the edge thickness of the edge waveguide (WG1).

13. Integrated circuit comprising an edge optical waveguide obtained by implementing a manufacturing process according to any one of claims 1 to 12.

14. Integrated circuit according to claim 13, further comprising at least one optical waveguide (WG1, WG2) having a different thickness compared to the edge thickness of the edge waveguide (WG1).

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