Magnetoresistive memory with integrated selectors

Abstract

The invention relates to a magnetoresistive memory cell comprising: a pillar (MTJ) forming a magnetic tunnel junction (MTJ) and a write track (SOT) made of a spin Hall effect material or an orbital Hall effect material; a support layer (14) made of a material having a configurable metal-insulator transition; a first electrode (EL1) disposed on the support layer (14); the portion (143) of the support layer (14) confined between the first electrode (EL1) and the write track (SOT) forming a first selector (S1); a second electrode (EL2) disposed on the support layer (14); the portion (144) of the support layer (14) confined between the second electrode (EL2) and the write track (SOT) forming a second selector (S2). Figure for the abstract: Fig. 1a

Description

Title of the invention: Magnetoresistive memory with integrated selectors. Scope of application

[0001] The present invention relates to the field of design of non-volatile memory circuits and more particularly to magnetoresistive memory cells with spin-orbit torque or Hall Orbital effect, the implementation of dense memory matrices and their programming in read and write. Technical problem

[0002] Spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) is an advanced non-volatile memory that uses magnetic mechanisms to store data. It is based on magnetic tunnel junctions whose resistance varies according to the orientation of the magnetic layers. Unlike conventional MRAM, SOT MRAM uses spin-orbit transfer, where currents through a track formed by materials with strong spin-orbit coupling induce the switching of the magnetic state in a tunnel junction structure in contact with said track. This allows for faster switching, better endurance, and increased energy efficiency. SOT MRAM technology is ideal for applications requiring fast, non-volatile, and durable memory.This durability is achieved because writing does not require the writing current to pass through the magnetic tunnel junction pillar.

[0003] However, the memory cell of an SOT MRAM differs from standard non-volatile memories such as PCRAM, CBRAM, FeRAM, and STT MRAM, which are two-port electronic devices composed of a resistive element (IR) and a transistor (1T) with combined read and write paths (denoted 1T1R). The memory cell of an SOT MRAM is a three-port electronic device comprising a magnetoresistive element (IR), a write track (SOT), and two transistors (2T) with separate read and write paths. This configuration, denoted 2T1R, results in a lower integration density for the SOT MRAM, which is inherently less compact. This configuration of the SOT MRAM memory cell makes it incompatible with a crossbar array due to the use of two transistors.

[0004] For standard non-volatile memories such as PCRAM, CBRAM, FeRAM, crossbar memories have been developed, connecting memory points by two perpendicular metallic lines to increase the density of the structure. Writing and reading are performed using specific voltages, with currents following Kirchhoff's laws. Memory point selection uses selectors (S) instead of transistors, making 1S1R memory cells much more compact. The selectors are voltage-controlled, volatile On / Off nanoswitches. The selectors generally used for 1S1R memory cells are varistors formed by filament conductors primarily made of ZrO2 or HfO2, or by OTS (Ovionic Threshold Switches) phase-change conductors. These types of selectors are not compatible with MRAM memory cells, and more specifically MRAM-SOT, which have reduced operating voltage ranges. On the one hand, the voltage range of an MRAM memory cell is limited due to the low breakdown voltage of the tunnel barrier (1.3V to 2V); on the other hand, the aforementioned selectors have an ON / OFF switching threshold voltage of around 5V.

[0005] There is also a need to design at least one matrix implementation of the new MRAM-SOT memory cell architecture and to define at least one suitable read / write programming to implement the new memory cell according to the invention in an application framework.

[0006] The same need exists with the concept of MRAM-OTT (Orbital Transfer Torque) memory, which uses the injection of orbital moment currents instead of spin currents by replacing the tungsten SOT write track with an OTT track, for example, made of titanium. The invention is described for MRAM-SOT memory cells with a write track made of a spin-orbit torque material but remains valid also for MRAM-OTT (Orbital Transfer Torque) memories. The advantages and characteristics described for MRAM-SOT memory cells remain valid for MRAM-OTT memories.

[0007] Prior art / Prior art restrictions

[0008] The scientific publication [1] describes a solution that consists of replacing, in an MRAM-SOT memory cell, the read transistor when it is in series with the magnetic tunnel junction pillar with a diode. This is a 1S1T1R type structure. This solution has a disadvantage related to density because the diodes remain too large relative to the memory cell. In addition, the diode significantly increases the read energy due to the larger voltage drop across the diode.

[0009] US patent US11289143B2 describes an MRAM-SOT memory cell in which the write transistor connected in series with the SOT track is replaced by a selector, but retains the read transistor in series with the magnetic tunnel junction pillar. It is a 1S1T1R type structure. In the proposed memory cell, a write operation requires the passage of the write current through half of the SOT track and through the magnetic tunnel junction, which induces two major disadvantages: a decrease in the durability of the memory cell because the current passes through the magnetic tunnel junction, reducing its robustness, and a reduction in writing efficiency (due to the SOT effect) because the write current only passes through half of the SOT track. Answer to the problem and provision of a solution

[0010] To overcome the limitations of existing solutions, the invention proposes a spin-orbit couple magnetoresistive memory cell having a 2S1R structure, enabling the realization of dense memory structures. The memory cells comprise integrated selectors (also called nano-switches) based on a layer of a material having a configurable metal-insulator transition, preferably Mott oxides compatible with low voltages. An alternative is possible with integrated selectors based on 2D topologically insulating materials.

[0011] Furthermore, the invention presents asynchronous writing modes exploiting the hysteresis effect in the materials forming the selectors and allowing the minimization of the number of control voltages required to perform a write operation. This makes it possible to considerably reduce the energy consumption of the memory cells. The invention also provides several read modes compatible with the memory cell according to the invention.

[0012] Furthermore, the invention presents a plurality of memory matrix architectures based on the new memory cell and enabling the implementation of the different writing and reading modes proposed by the invention.

[0013] Summary / Claims

[0014] The invention relates to a magnetoresistive memory cell comprising: - a pillar forming a magnetic tunnel junction and having an upper end intended to receive a first control voltage and a lower end; - a writing track made of a spin Hall effect material or an orbital Hall effect material; the pillar being disposed on said writing track on the side of its lower end; - a support layer made of a material having a configurable metal-insulator transition; the support layer having a first face and a second opposite face; the writing track being disposed on said first face; - a first electrode disposed on said second face and intended to receive a second control voltage; the part of the support layer confined between the first electrode and the writing track having a conduction state configurable by the first and second control voltages so as to form a first selector having a high resistive state and a low resistive state; - a second electrode disposed on said second face and intended to receive a third control voltage; the part of the support layer confined between the second electrode and the writing track having a conduction state configurable by the first and third control voltage so as to form a second selector having a high resistive state and a low resistive state.

[0015] According to a particular aspect of the invention, the support layer is made of Mott oxide or a topological insulator.

[0016] According to a particular aspect of the invention, the writing track is made of a spin Hall effect material selected from beta-phase tungsten or bismuth antimonide or a BiSbTe alloy.

[0017] According to a particular aspect of the invention, the writing track is made of an orbital Hall effect material selected from chromium or zirconium or titanium or vanadium or copper or manganese or molybdenum or ruthenium or aluminium or niobium or tungsten in alpha phase.

[0018] According to a particular aspect of the invention, the writing track has a thickness less than or equal to 20 nm, advantageously 10 nm and more advantageously 5 nm.

[0019] According to a particular aspect of the invention, the first and / or second selector has a resistance greater than or equal to 10 times the resistance of the writing track when said selector is in a high resistive state.

[0020] According to a particular aspect of the invention, the first and / or second selector has a resistance greater than or equal to 10 times the resistance of the magnetic tunnel injunction when said selector is in a high resistive state.

[0021] According to a particular aspect of the invention, the first and / or second selector has a resistance less than or equal to the resistance of the writing track when said selector is in a low resistive state.

[0022] According to a particular aspect of the invention, the first and / or second selector has a resistance less than or equal to one tenth of the resistance of the magnetic tunnel junction when said selector is in a low resistive state.

[0023] According to a particular aspect of the invention, the magnetoresistive memory cell further comprises a control transistor; the source of said control transistor being connected to the upper end of the pillar.

[0024] According to a particular aspect of the invention, the magnetoresistive memory cell further comprises an attenuation transistor; the drain of said attenuation transistor being connected to the first electrode.

[0025] According to a particular aspect of the invention, the first and / or second selector is adapted to switch from a high resistive state to a low resistive state when the amplitude of the voltage across said selector is greater than a predetermined threshold voltage.

[0026] The invention also relates to a memory circuit comprising: - a memory matrix formed by a plurality of memory cells according to the invention; - a control circuit configured to generate the first control voltage, the second control voltage and the third control voltage.

[0027] According to a particular aspect of the invention, the control circuit is configured to perform a write operation on a memory cell of the matrix by applying to it: - a first zero control voltage, a second control voltage greater than the predetermined threshold voltage and a third zero control voltage to write a first logic state; - a first zero control voltage, a second zero control voltage and a third control voltage greater than the predetermined threshold voltage to write a second logic state complementary to the first logic state.

[0028] According to a particular aspect of the invention, the control circuit is configured to perform a write operation on a memory cell of the matrix by applying to it: - a first control voltage greater than the predetermined threshold voltage, a second control voltage equal to the first control voltage and a third zero control voltage to write a first logic state; - a first control voltage greater than the predetermined threshold voltage, a second zero control voltage and a third control voltage equal to the first control voltage to write a second logic state complementary to the first logic state.

[0029] According to a particular aspect of the invention, the control circuit is configured to perform a write operation on a memory cell of the matrix by applying to it: - a second control voltage greater than twice the predetermined threshold voltage; a first control voltage equal to half of the second control voltage and a third zero control voltage to write a first logic state; - a third control voltage greater than twice the predetermined threshold voltage; a first control voltage equal to half the third control voltage and a second zero control voltage to write a second logic state complementary to the first logic state.

[0030] According to a particular aspect of the invention, the control circuit is configured to perform a read operation on a memory cell of the memory matrix by applying to it a second and a third control voltage greater than the predetermined threshold voltage and a first zero control voltage.

[0031] According to a particular aspect of the invention: - the upper ends of the pillars of the memory cells belonging to the same column of the memory matrix are interconnected via a first conductive line intended to propagate the first associated control voltage; - the first electrodes of the memory cells belonging to the same row of the memory matrix are interconnected via a second conductive line intended to propagate the second associated control voltage; - the second electrodes of the memory cells belonging to the same row of the memory matrix are interconnected via a third conductive line intended to propagate the associated third control voltage.

[0032] According to a particular aspect of the invention: - the upper ends of the pillars of the memory cells belonging to the same column of the memory matrix are interconnected via a first conductive line intended to propagate the first associated control voltage; - the first electrodes of the memory cells belonging to the same row of the memory matrix are interconnected via a second conductive line intended to propagate the second associated control voltage; - the second electrodes of the memory cells belonging to the same column of the memory matrix are interconnected via a third conductive line intended to propagate the associated third control voltage;

[0033] According to a particular aspect of the invention: - the gates of the control transistors of the memory cells belonging to the same column of the memory matrix are interconnected via a first conductive line intended to propagate an associated selection signal; - the drains of the control transistors of the memory cells belonging to the same row of the memory matrix are interconnected via a second conductive line intended to propagate the first associated control voltage; - the first electrodes of the memory cells belonging to the same row of the memory matrix are interconnected via a third conductive line intended to propagate the second associated control voltage; - the second electrodes of the memory cells belonging to the same column of the memory matrix are interconnected via a fourth conductive line intended to propagate the associated third control voltage;

[0034] According to a particular aspect of the invention: - the upper ends of the memory cell pillars belonging to the same row of the memory matrix are interconnected via a first conductive line intended to propagate the first associated control voltage; - the sources of the attenuation transistors of the memory cells belonging to the same row of the memory matrix are interconnected via a second conductive line intended to propagate the second associated control voltage; - the second electrodes of the memory cells belonging to the same column of the memory matrix are interconnected via a third conductive line intended to propagate the associated third control voltage; - the gates of the attenuation transistors of the memory cells belonging to the same column of the memory matrix are interconnected via a fourth conductive line intended to propagate an associated selection signal;

[0035] According to a particular aspect of the invention: - the upper ends of the pillars of the memory cells belonging to the same column of the memory matrix are interconnected via a first conductive line intended to propagate the first associated control voltage; - the sources of the attenuation transistors of the memory cells belonging to the same row of the memory matrix are interconnected via a second conductive line intended to propagate the second associated control voltage; - the second electrodes of the memory cells belonging to the same row of the memory matrix are interconnected via a third conductive line intended to propagate the associated third control voltage; - the gates of the control transistors of the memory cells belonging to the same column of the memory matrix are interconnected via a fourth conductive line intended to propagate an associated selection signal. Detailed description

[0036] Other features and advantages of the present invention will become more apparent from the following description in relation to the following accompanying drawings.

[0037] Fig. 1a illustrates a cross-sectional view of a spin-orbit couple magnetoresistive memory cell, according to the invention, in a first configuration.

[0038] Fig. [lb] illustrates a cross-sectional view of a spin-orbit couple magnetoresistive memory cell, according to the invention, in a second configuration.

[0039] Fig. 1e illustrates an electrical diagram of a spin-orbit torque magnetoresistive memory cell according to the invention.

[0040] Figure [Fig. 2] illustrates a functional diagram of a memory circuit according to the invention.

[0041] Fig. 3a illustrates the steps of a first mode of writing the memory cell according to the invention.

[0042] Fig. 3b illustrates the steps of a second mode of writing the memory cell according to the invention.

[0043] Fig. 3c illustrates the steps of a third mode of writing the memory cell according to the invention.

[0044] Fig. 3d illustrates the steps of a first mode of reading the memory cell according to the invention.

[0045] Fig. 3e illustrates the steps of a second mode of reading the memory cell according to the invention.

[0046] Figure 4a illustrates an electrical diagram of a memory matrix used in the memory circuit according to a first embodiment of the invention.

[0047] Figure 4b illustrates an electrical diagram of a memory matrix used in the memory circuit according to a second embodiment of the invention.

[0048] Figure 4c illustrates an electrical diagram of a memory matrix used in the memory circuit according to a third embodiment of the invention.

[0049] Figure 4d illustrates an electrical diagram of a memory matrix used in the memory circuit according to a fourth embodiment of the invention.

[0050] Fig. 4e illustrates an electrical diagram of a memory matrix used in the memory circuit according to a fifth embodiment of the invention.

[0051] Figure 1a illustrates a cross-sectional view of a spin-orbit couple magnetoresistive memory cell 10 according to the invention. The memory cell 10 comprises a magnetic tunnel junction MTJ, a write track SOT, a support layer 14, a first electrode ELI and a second electrode EL2.

[0052] The MTJ magnetic tunnel junction is a magnetoresistive pillar comprising a stack of layers 11, 12, 13 which work together to enable the storage and retrieval of data via the manipulation of magnetic properties. The stack The stack comprises a first reference ferromagnetic layer 11 in which the direction of magnetic polarization is fixed and uniform. The stack further includes a second ferromagnetic layer 13 in which the direction of magnetic polarization is variable. The stack also includes a tunnel barrier layer 12 of oxide, such as MgO (magnesium oxide), confined between the first and second ferromagnetic layers 11, 13. This layer plays a crucial role in magnetoresistive tunneling, allowing electrons to pass through by quantum tunneling. The tunnel barrier layer 12 has a thickness less than Inm. The first ferromagnetic layer 11 serves as a reference for detecting changes in magnetization in the free ferromagnetic layer 13. For example, the first and second layers 11, 13 are composed of materials such as CoFeB.The operating principle of the magnetoresistive MTJ pillar is based on the change in electrical resistance depending on the magnetic polarization orientation of the free ferromagnetic layer 13 relative to that of the reference ferromagnetic layer 11. When the magnetizations of the free and reference layers 11 and 13 are parallel, the electrical resistance is low across the MTJ magnetic tunnel junction pillar. When the magnetizations are antiparallel, the electrical resistance is high. This change in resistance is detected to read a memory state (bit 0 or 1). This change in resistance is triggered to write a memory state (bit 0 or 1).

[0053] The MTJ magnetic tunnel junction rests on the SOT write track. The interface The magnetic field between the MTJ magnetic tunnel junction and the SOT write track is on the side of the free ferromagnetic layer 13. The direction of the stack forming the MTJ magnetic tunnel junction is orthogonal to the plane formed by the layer forming the SOT write track. The SOT write track is made of a spin Hall effect material (also called a spin-orbit couple effect material), for example, beta-phase tungsten or bismuth antimonide, or a stack of two layers, one tantalum and the other tungsten, or a BiSbTe alloy. When a write current flows through the SOT write track in a given direction, spin currents are generated and interact with the free ferromagnetic layer 13. This interaction allows control of the magnetic polarization direction in the free ferromagnetic layer 13 according to the direction of the write current in the SOT write track.Controlling the magnetic polarization direction in the free ferromagnetic layer 13 allows the electrical resistance of the magnetic tunnel junction MTJ to be modified without injecting a write current, which greatly increases the robustness of the memory cell 10.

[0054] The SOT writing track is disposed on a first face 141 of the support layer 14. The support layer 14 is made of a material having a metal-insulator transition, More specifically, a Mott oxide. This type of material exhibits the possibility of a volatile resistive transition between a high and a low resistive state. This transition is activated thermally and / or electrically and / or optically. It consists of a non-permanent (volatile) phase change between a stable, high-resistance, orthoclinic semiconducting phase and a metastable, low-resistance, conductive, rutile tetragonal phase. The low resistive state is maintained only under thermal, electrical, or optical stimulation. The invention exploits electrical stimulation by applying an electric field. The thickness of the support layer 14 is between 5 nm and 100 nm.

[0055] The first ELI electrode is disposed on a second face 142 of the support layer 14 opposite the first face 141. The first ELI electrode is positioned below a first end of the SOT write track. The second EL2 electrode is disposed on the second face 142. The second EL2 electrode is positioned below a second end of the SOT write track opposite the first end. The pillar forming the magnetic tunnel junction MTJ is located between the first end and the second end. The first ELI electrode and the second EL2 electrode are each made of an electrically conductive metal layer, for example, preferably tungsten, copper, or titanium nitride.

[0056] From an electrical point of view, a first control voltage VRBL is applied to the upper end of the pillar forming the magnetic tunnel junction MTJ. A second control voltage VBL is applied to the first electrode ELI. A third control voltage VBLB is applied to the second electrode EL2.

[0057] The stack formed by the first electrode ELI, area 143 of the support layer 14 made of a metal-insulating transition material, and the write track SOT locally forms a small SI selector. The SI selector is configurable between a high resistive state R1OFF and a low resistive state R10n by applying a voltage between the first electrode ELI and the write track SOT, i.e., the first and second voltages VRBL, VBL. Similarly, the stack formed by the second electrode EL2, area 144 of the support layer 14 made of a metal-insulating transition material, and the write track SOT locally forms a second small S2 selector. The second selector S2 is configurable between a high resistive state R20ff and a low resistive state R20N via the application of a voltage between the second electrode EL2 and the write track SOT i.e. the first and third voltage VRBL, VBLB.For each selector between SI and S2, activation (switching from R0FF to R on) is triggered when the voltage amplitude across the selector exceeds a predetermined threshold voltage Vth. For example, for a 14 oxide support layer. The threshold voltage of vanadium is equal to 0.6V, which is compatible with the voltage operating ranges of a magnetoresistive memory cell.

[0058] Alternatively, the support layer 14 comprises a low-voltage (< 1 V) topological insulator, for example, molybdenum disulfide. A topological insulator is a material that has the desirable property of behaving as an insulator internally (it does not conduct electricity through its volume), while having conductive surfaces or edges. This type of material is called "topological" because its surface conductive properties are protected by topological features of the material's electronic structure, meaning that they are robust against disturbances such as impurities or structural defects.

[0059] Selectors SI and S2 can be activated simultaneously by means of the same control voltage (same amplitude and same sign) or independently by means of two separate control voltages (same amplitude and opposite signs). Therefore, the direction of current flow through the selectors can be controlled according to the sign of the applied voltage, either upwards (from the associated electrode to the SOT write track) or downwards (from the SOT write track to the electrode). Thus, a bipolar current can flow through the entire SOT track for writing with commands of opposite signs, and a unipolar current can flow through the MTJ pillar after traversing half of the SOT track for reading with commands of the same sign.

[0060] Figure [Fig. 1a] illustrates a cross-sectional view of the magnetoresistive memory cell The spin-orbit pair 10 is shown in a first configuration in which SI and S2 are each in a high resistive (blocking) state. Figure [1b] illustrates a cross-sectional view of the magnetoresistive memory cell with a spin-orbit pair 10, in a second configuration in which SI and S2 are each in a low resistive (conducting) state.

[0061] The use of Mott oxides, preferably vanadium oxide and niobium oxide, presents several additional advantages in the context of the invention.

[0062] First, a characteristic of Mott oxides is the possibility of maintaining the metallic state once the transition has occurred, even when the control voltage falls below the threshold voltage Vth, provided that residual current flow is possible. This residual current maintains a certain temperature in the crystal necessary for the stability of the rutile phase. When this current becomes too low, in other words, when the crystal cools sufficiently, the tetragonal phase takes over and all electrical conduction ceases. This characteristic will be exploited within the framework of this invention to perform an "asynchronous" writing operation in a memory cell 10 according to the invention.

[0063] Furthermore, another advantage arises from the use of Mott oxides to produce the support layer 14, corresponding to the improvement of the spin-orbit coupling effect in the SOT write track. Indeed, obtaining the [3] phase in the write track This requires an oxygen supply within the tungsten lattice. In the absence of an oxygen source, the tungsten current phase (a) or a mixture of the two phases is obtained, which cancels or limits the spin-orbit coupling effect in the SOT writing track. This small amount of oxygen can be supplied, for example, by contact with the Mott oxide support layer 14.

[0064] This provides a double advantage thanks to Mott's oxides: - On the one hand, the oxide nature of the support layer 14 then makes it possible to maximize the [3] phase in the SOT writing track (or even eliminate the a phase completely) in order to improve the spin-orbit coupling; - on the other hand the volatile metal-insulator transient nature of Mott oxides makes it possible to make the two SI selectors, S2 playing the role of compact nanoswitches to improve the density of the memory cell.

[0065] In the embodiment of [Fig. 1a], the stacking direction is as follows, starting from the substrate along the Z-axis: electrodes E1 and EL2, then support layer 14, then write track SOT, then pillar MTJ. Alternatively, the memory cell 10 can be implemented in the reverse direction with respect to the cell illustrated in [Fig. 1a], starting from the substrate as the origin of the Z-axis. The pillar is oriented downwards. The stacking direction is as follows, starting from the substrate along the Z-axis: pillar MTJ oriented downwards, then write track SOT, then support layer 14, then electrodes EL1 and EL2 on the upper surface. The downward-oriented pillar MTJ is encapsulated in a dielectric layer.

[0066] Alternatively, the memory cell 10 according to the invention is a magnetoresistive memory cell exploiting the Orbital Hall effect. This embodiment differs from the embodiment of [Fig. 1a] in that the write track is configured to generate an orbital momenta current from a charge current and not a spin current. The advantage of a write path separate from the read path is retained. Writing is performed by converting the charge current into an orbital momenta current, which has a similar ability to spin current to exert a torque on the magnetization of a magnetic layer. This is the orbital Hall effect (OHE), which differs from the spin Hall effect. Writing by orbital Hall effect improves the characteristics of magnetic memories.The structure of an orbital Hall effect device is similar to that of a spin-orbit device, except that the writing track, also called the "OT" track for "Orbital Torque," is configured to generate an orbital momenta current from a charge current. Orbital moments cannot directly produce a torque on the magnetization of the MTJ pillar junction. One of two mechanisms may be required. The action of orbital moments on the magnetization may be due to an interlacing of the orbital moments with... The spin moments (known as "spin-orbital entanglement") and / or a portion of the orbital moment current is converted into spin current at the MTJ pillar junction, the latter applying a torque to a magnetization of the MTJ pillar junction. In the case of an orbital Hall effect memory cell, the OT write track is made of chromium, zirconium, titanium, vanadium, copper, manganese, molybdenum, ruthenium, aluminum, niobium, or alpha-phase tungsten.

[0067] Figure 1 illustrates an electrical diagram of the spin-orbit couple magnetoresistive memory cell, 10, according to the invention. The first selector SI is modeled by a switch controlled by the potential difference VS1. When the first selector SI is in a conducting state, it is modeled as a resistor R10n, and when it is in a blocking state, as a resistor R1OFF. The second selector S2 is modeled by a switch controlled by the potential difference VS2. When the second selector S2 is in a conducting state, it is modeled as a resistor R20N, and when it is in a blocking state, as a resistor R20FF. The portion of the write track SOT located between the first selector SI and the base of the MTJ pillar is modeled by a resistor RSoT / 2, where Rsoi is the equivalent electrical resistance of the write track.Symmetrically, the portion of the SOT write track located between the second selector S2 and the base of the MTJ pillar is modeled by a resistor Rsot / 2. ​​The two resistors Rsot / 2 are connected in series, and their common node NC is a central node located at the base of the MTJ pillar. The MTJ pillar is modeled by a variable resistor RMTj depending on the binary data "1" or "0" stored in the MTJ memory cell. It is assumed that RloFF—R2oFF—RoFF and that Rlo^—R2o^—Ro^.

[0068] The electrical behavior of each selector SI, S2 is defined by the following three parameters: the on-state resistance R0N, the off-state resistance R0FF, and the threshold voltage Vth. These three parameters can be modulated by modifying the composition of the support layer 14. According to a particular aspect of the invention, at least regions 143 and 144 of the support layer 14 are doped with chromium, iron, aluminum, or titanium atoms to lower the threshold voltage Vth and the on-state resistance R0Net in order to increase the off-state resistance Roff. According to another particular aspect of the invention, at least regions 143 and 144 of the support layer 14 are doped with titanium or tungsten atoms to increase the threshold voltage Vth and the on-state resistance R0Net in order to lower the off-state resistance R0FF.

[0069] During a write operation, a write current iwest is injected through the write track SOT from the first electrode ELI to the second electrode EL2 or vice versa. The write current iwne does not pass through the MTJ pillar and does not depend on The resistive state RMTJ of said pillar. The write current iw depends on the Ron / Rsot ratio. During a read operation, a read current ir is injected through the MTJ pillar from the first electrode ELI and / or the second electrode EL2. The read current ir depends on the Ron / Rmtj ratio.

[0070] The composition and dimensioning of at least parts 143, 144 of the support layer 14 are chosen so as to obtain the following inequalities: - Rqn < RsoT to have a writing current iw having a sufficient amplitude to modify the magnetic polarization in the MTJ pillar, more advantageously Rqn - 0-1 x R$ot; a sufficient amplitude for writing is generally greater than lOOpA. - Rqn < RwTj to have a reading current ir having a sufficient amplitude to determine the resistive state of the magnetoresistive junction MTJ; a sufficient amplitude for reading is generally greater than lOpA. - Rqff - 10 x R^ to be able to switch the SI, S2 selectors from a blocking state to a passing state during a write operation, more advantageously Rqff - 50 x RSOT; - Rqff - 10x RmtjPouf to be able to switch the SI, S2 selectors from a blocking state to a passing state during a read operation, more advantageously Rqff - IOOxRmtj;

[0071] Figure 2 illustrates a functional diagram of a DI memory circuit according to the invention comprising a memory matrix Mx formed by a plurality of memory cells 10 according to the invention and a control circuit CONT configured to generate at least the first control voltage VRBL, the second control voltage VBL and the third control voltage VBLB according to the choice of arrangement of the matrix Mx.

[0072] The memory cell 10 according to the invention is compatible with several writing and reading modes which will be detailed in the following section.

[0073] Figure 3a illustrates the steps of a first mode of writing the memory cell 10 according to the invention. Initially, the two selectors SI, S2 are in the blocking state. The control circuit CONT is configured to simultaneously apply: a first zero control voltage VRBL to the upper end of the MTJ pillar, a second control voltage VBL = Vprog such that Vprog > Vth, and a third zero control voltage VBLB. The zero potential propagates through the MTJ pillar to the SOT write track. The first selector thus sees a voltage +V^ across its terminals greater than the threshold voltage and switches to a conducting state, thereby connecting the SOT write track to the first ELI electrode, which provides the write voltage. +Vprog. During a transient period, a leakage current will flow through the MTJ pillar. This leakage current is, for example, less than 80 pA and therefore does not accidentally alter the resistive state of the MTJ pillar and does not exceed the breakdown current of the magnetic tunnel junction. During this transient period, the +Vprog potential also gradually establishes itself at the other end of the SOT write track located at the second selector S2, which thus sees a -Vprog voltage across its terminals with an amplitude greater than the threshold voltage Vth. The end of the transient regime corresponds to the switching of the second selector S2 under the influence of the -Vprog voltage propagated by the SOT write track, allowing the write current to flow from the first electrode ELI to the second electrode EL2.The advantage of the first writing method according to the invention is that it is possible to write to memory cell 10 by applying a single non-zero write voltage +Vprog to the first ELI electrode. Finally, the second control voltage VBL is gradually reset to zero to terminate the operation. It has thus been possible to pass a write current from the first ELI electrode to the second EL2 electrode through the SOT write track to write a first logic state "0", for example.

[0074] To write a complementary logic state "1", it suffices to apply a first zero control voltage VRBL to the upper end of the MTJ pillar, a second zero control voltage VBL, and a third control voltage VBLB = Vprog such that Vprog > Vth. Symmetrically, the same mechanism describes a writing current from the second electrode EL2 to the first electrode ELI through the SOT write track to write a second logic state "1".

[0075] By way of illustrative and non-limiting example, if the Mott oxide chosen is vanadium oxide, the threshold voltage is equal to 0.6V and the writing voltage Vprog= 0.7V to obtain a writing current greater than 100pA, advantageously greater than 500pA.

[0076] Advantageously, the two selectors SI, S2 remain in the conducting state for an additional duration thanks to a property of the Mott oxides used to make the two selectors SI, S2. Indeed, during the falling-off transition, as long as a non-zero voltage persists across the terminals of SI, S2, it ensures the passage of a residual ohmic current with minimal heating. The residual ohmic current sufficiently maintains the thermal stability of the conductive rutile phase in regions 143, 144. When the control voltage VBL is thus brought to zero, the Metal / Insulator falling-off transition is shifted well below the threshold voltage Vth. This is referred to as an "asynchronous" writing operation.

[0077] Figure 3b illustrates the steps of a second writing mode for the memory cell 10 according to the invention. The second writing mode according to the invention is also an "asynchronous" writing operation. Initially, both selectors S1 and S2 are in the blocking state. The control circuit CONT is configured to simultaneously apply: a first control voltage VRBL = Vprog such that Vprog > Vth to the upper end of the MTJ pillar, a second control voltage VBL = Vprog, and a third zero control voltage VBLB. The potential Vprog propagates through the pillar to the SOT write track. The second selector S2 thus sees a voltage VS2 = VBLB - VSot = -Vprog across its terminals that is greater than the threshold voltage and switches to a conducting state, thereby connecting the SOT write track to the second electrode EL2, which is connected to ground (GND). During a transient period, a leakage current will travel through the MTJ pillar to be discharged by the EL2 electrode.The leakage current, for example, is less than 80 pA and therefore does not accidentally alter the resistive state of the MTJ pillar and does not exceed the breakdown current of the magnetic tunnel junction. During this transient period, the zero voltage (GND) is also gradually established at the other end of the SOT write track located at the first SI selector, which thus sees a voltage +Vprog at its terminals with an amplitude greater than the threshold voltage Vth. The end of the transient regime corresponds to the switching of the first SI selector under the action of the potential difference VS1 = VBL - VSot = +Vprog - O, allowing the write current to flow from the first electrode ELI to the second electrode EL2. Finally, all the control voltages VBL and VRBL are gradually reset to zero to terminate the write operation.It was thus possible to pass a writing current from the first electrode ELI to the second electrode EL2 through the SOT writing track to write a first logic state "0" for example.

[0078] To write a complementary logic state "1", it suffices to apply a first control voltage VRBL = Vprog such that Vprog > Vth to the upper end of the MTJ pillar, a second control voltage VBL of zero, and a third control voltage VBLB = Vprog. Symmetrically, the same mechanism describes a writing current from the second electrode EL2 to the first electrode ELI through the SOT writing track to write a second logic state "1".

[0079] Figure 3c illustrates the steps of a third writing mode for the memory cell 10 according to the invention, of the "synchronous" type. This mode is compatible with a support layer 14 that does not exhibit a hysteresis effect, such as, for example, in the case where said support layer 14 is doped with an additional element (Cr, Al, Fe, W, Mo, Ta, Ru, etc.) or produced by epitaxy. This writing mode is also compatible with a support layer 14 comprising a topological insulator, such as for example in MoS2.

[0080] Initially, both selectors SI and S2 are in the blocking state. The CONT control circuit is configured to simultaneously apply: a first control voltage VRBL = Vprog / 2 such that Vprog > 2x Vth to the upper end of the MTJ pillar, a second control voltage VBL = Vprog, and a third control voltage VBLB = 0. The potential Vprog / 2 propagates through the pillar to the SOT write track. The first selector SI thus sees a voltage VS1 = VBL - Vsot = Vprog - Vprog / 2 = +Vprog / 2 across its terminals, which is greater than the threshold voltage, and switches to a conducting state, thus connecting the SOT write track to the first ELI electrode. The second selector S2 thus sees at its terminals a voltage VS2 = VBLB - VSot= 0 -Vprog / 2 = -Vprog / 2 having an amplitude greater than the threshold voltage and switches to a conducting state thus connecting the writing track SOT to the second electrode EL2 connected to ground GND.Following the simultaneous activation of both selectors SI and S2, a write current is established through the write track SOT from the first electrode ELI to the second electrode EL2 to write a first logic state "0", for example. Finally, all the control voltages VBL, VBLB, and VRBL are progressively reset to zero, and the selectors switch to a blocking state to terminate the operation.

[0081] To write a complementary logic state "1" according to the third write mode, the CONT control means are configured to apply simultaneously: a first control voltage VRBL = Vprog / 2 such that Vprog > 2x Vth to the upper end of the MTJ pillar, a second control voltage VBL = 0, and a third control voltage VBLB = Vprog. This results in a write current flowing through the SOT write track from the second electrode EL2 to the first electrode ELI.

[0082] Table 1 summarizes the different writing methods according to the invention compatible with the memory cell 10: Writing Mode Logic State Condition VRBL VBL VBLB 1st mode 0 Vprog>Vth 0 v V prog 0 1st mode 1 Vprog>Vth 0 0 vv prog 2nd mode 0 Vprog>Vth v V prog v V prog 0 2nd mode 1 Vprog>Vth V v prog 0 vv prog 3rd mode 0 Vprog>2x Vth 1 / , V / z ' prog v V prog 0 3rd mode 1 Vprog>2x Vth 1 / , V / z ' prog 0 v V prog

[0083] The first and second writing modes are asynchronous (delayed activation of selectors SI, S2), while the third mode is synchronous (simultaneous activation of selectors SI, S2). Each writing mode has particular advantages.

[0084] The "asynchronous" modes are advantageous because they minimize the write voltage by setting Vprog only 20% higher than the switching threshold voltage of selectors SI and S2. The memory cell provides sufficient write current, for example, greater than 500 pA, with very little leakage current in the MTJ pillar. Both the asynchronous and synchronous modes generate sufficient write current levels. In terms of energy consumption, the asynchronous write modes are the most advantageous because they reduce power consumption during writing by half and maintain control voltages below 1 V. On the other hand, the third synchronous write mode minimizes leakage currents through the MTJ pillar by simultaneously activating selectors SI and S2.

[0085] Figure 3d illustrates the steps of a first reading mode for the memory cell 10 according to the invention. The control circuit CONT is configured to simultaneously apply: a second control voltage VBL = Vread such that Vread > Vth, a third control voltage VBLB = Vread, and a first zero control voltage VRBL to the upper end of the MTJ pillar. The two selectors SI, S2 switch simultaneously to a conducting state, and the potential VreadSe propagates to the write track SOT on which the MTJ pillar rests. The MTJ pillar thus experiences a potential difference across its terminals almost equal to Vread. Consequently, a read current can be established with an intensity that depends on the resistive state of the MTJ pillar. The read current is the sum of two currents: a first current injected from the first electrode ELI, and a second current from the second electrode EL2.Finally, all the control voltages VBL, VBLB, and VRBL are gradually reset to zero, and the selectors switch to a blocking state to terminate the read operation. The advantage of this read mode is that during reading, two opposing currents flow along the SOT write track, eliminating the possibility of accidental writing.

[0086] Figure 3e illustrates the steps of a second reading mode for memory cell 10 according to the invention. The control circuit CONT is configured to simultaneously apply: a second control voltage VBL = Vread such that Vth < Vread < 2Vth, a third control voltage VBLB = V2 Vread, and a first zero control voltage VRBL to the upper end of the MTJ pillar. The first selector SI switches to a conducting state while the second selector remains in a blocking state. The potential Vread propagates to the write track SOT on which the MTJ pillar. The pillar thus experiences a potential difference across its terminals almost equal to Vread. Consequently, a reading current can be established with an intensity that depends on the resistive state of the MTJ pillar. The reading current is injected only from the first ELI electrode. Finally, all the control voltages VBL, VBLB, and VRBL are progressively reset to zero, and the selectors switch to a blocking state to terminate the reading operation.

[0087] Other reading modes are compatible with the memory cell 10 according to the invention. Table 2 summarizes the different reading modes according to the invention that are compatible with the memory cell 10: Write mode condition VRBL VBL VBLB 1st mode Vread>Vth 0 V d' read V d' read 2nd mode Vread>Vth 0 V d' read ^2 Vread 3rd mode Vth < Vread <2xVth 0 ^2 Vread V d' read 4th mode Vread>vth V d' read 0 0 5th mode Vread>Vth V d' read 0 ^2 Vread 6th mode Vth < Vread <2xVth V d ' read ^2 vread 0

[0088] Fig. 4a illustrates an electrical diagram of a memory matrix M1 used in the DI memory circuit according to a first embodiment of the invention.

[0089] The memory matrix Ml is formed by a plurality of memory cells 10 according to the invention arranged in rows L and columns Ck, i=0 to N and k=0 to M. By way of illustration and not limitation, the matrix Ml is formed by two rows Lo, Li and two columns Co and Cp

[0090] The ends of the magnetic tunnel junctions MTJ of the memory cells 10 belonging to the same column Ck of the memory matrix M1 are interconnected via a first conductive line L1,k intended to propagate the first control voltage VRBLk associated with said column Ck. The first electrodes ELI of the memory cells 10 belonging to the same row L1 of the memory matrix M1 are interconnected via a second conductive line L2,i intended to propagate the second control voltage VBL associated with said line. The second electrodes EL2 of the memory cells 10 belonging to the same row of the memory matrix M1 are interconnected via a third conductive line L3,i intended to propagate the third control voltage VBLB associated with said line.

[0091] This matrix architecture is compatible with the first and second writing modes previously described and with the six reading modes previously described.

[0092] Table 3 illustrates the application of the two asynchronous writing modes previously described to the architecture of the memory cell matrix M1. Selected Cell Unselected Cells Write Mode Logical State VRBL VBL VBLB VRBL VBL VBLB 1st mode 0 0 vv prog 0 l / 2 V 7 x ' prog 0 0 1st mode 1 0 0 v V prog 1 / , V 7 z ' prog 0 0 2nd mode 0 vv prog vv prog 0 l / 2 V 7 x ' prog vv prog vv prog 2nd mode 1 V v prog 0 v V prog l / 2 V 7 z ' prog V v prog V v prog

[0093] Table 4 illustrates the application of the six read modes described above to the architecture of the ML memory cell matrix Selected cell Unselected cells Reading mode VRBL VBL VBLB VRBL VBL VBLB 1st mode 0 V d' read V d' read ^2 Vread 0 0 2nd mode 0 V d' read ^2 Vread ^2 Vread 0 0 3rd mode 0 ^2 Vread V d' read ^2 Vread 0 0 4th mode V d' read 0 0 ^2 Vread V d ' read V d 5th mode V d ' read 0 ^2 Vread ^2 Vread ^2 Vread ^2 Vread 6th mode V d ' read ^2 Vread 0 ^2 Vread ^2 Vread ^2 Vread

[0094] Figure 4b illustrates an electrical diagram of a memory matrix used in the memory circuit according to a second embodiment of the invention.

[0095] The memory matrix M2 is formed by a plurality of memory cells 10 according to the invention arranged in rows L and columns Ck, i=0 to N and k=0 to M. By way of illustration and not limitation, the matrix M1 is formed by 2 rows Lo, Li and 2 columns Co and Cp

[0096] The ends of the magnetic tunnel junctions MTJ of the memory cells 10 belonging to the same column Ck of the memory matrix M1 are interconnected via a first conductive line L1,k intended to propagate the first control voltage VRBLk associated with said column Ck. The first electrodes ELI of the memory cells 10 belonging to the same row L1 of the memory matrix M1 are interconnected via a second conductive line L2,i intended to propagate the second control voltage VBLk associated with said row. The second electrodes EL2 of the memory cells 10 belonging to the same column Ck of the memory matrix M1 are interconnected via a third conductive line L3,k intended to propagate the third associated control voltage VBLBk.

[0097] This matrix architecture is compatible with the first writing mode previously described for writing a first logical state "0", with the second writing mode previously described for writing the complementary logical state "1", and with the six reading modes previously described.

[0098] Table 5 illustrates the application of the first asynchronous writing mode previously described to the architecture of the pixel matrix M2. Selected Cell Unselected Cells Write Mode Logical State VRBL VBL VBLB VRBL VBL VBLB 1st mode 0 0 vv prog 0 l / 2 V 7 x ' prog 0 0 2nd mode 1 v V prog 0 v V prog 1 / , V 7 z ' prog L2 Vprog L2 Vprog

[0099] Table 6 illustrates the application of the second and fifth reading modes previously described to the architecture of the pixel matrix M2. Selected cell Unselected cells Read mode VRBL VBL VBLB VRBL VBL VBLB 2nd mode 0 V d' read ^2 Vread ^2 Vread 0 0 5th mode V d' read 0 L2 Vread L2 Vread L2 Vread L2 Vread

[0100] Figure 4c illustrates an electrical diagram of a memory matrix used in the memory circuit according to a third embodiment of the invention. The memory matrix M3 is formed by a plurality of memory cells 10 according to the invention arranged in rows L and columns Ck, i=0 to N and k=0 to M. By way of illustration and not limitation, the matrix M1 is formed by 2 rows Lo, Li and 2 columns Co and Cp. Each memory cell further comprises a control transistor TL. The source of the control transistor T1 is connected to the upper end of the magnetic tunnel junction MT J. The gate of each transistor T1 is controlled by a selection signal VWL generated by the control circuit CONT.

[0101] The gates of the control transistors T1 of the memory cells 10 belonging to the same column Ck of the memory matrix M3 are interconnected via a conductive line LWL,k for propagating an associated selection signal VWLk. The drains of the control transistors T1 of the memory cells 10 belonging to the same row L; of the memory matrix M3 are interconnected via a conductive line L2,i for propagating the first associated control voltage VRBL,i. The first electrodes ELI of the memory cells 10 belonging to the same row L; of the memory matrix M3 are interconnected via a second conductive line L1,i for propagating the second control voltage VBL; associated with said line. The second electrodes EL2 of the memory cells 10 belonging to the same column Ck of the memory matrix M3 are interconnected via a conductive line L3,i intended to propagate the associated third control voltage VBLBk.

[0102] Integrating the selection transistors Tl into the memory cells allows the non-selected memory cells to be isolated from a read or write operation by applying a zero voltage to the gate of the selection transistor Tl. Selecting a memory cell for reading or writing is achieved by applying the supply voltage VDD to the gate of the transistor Tl associated with said memory cell. The memory matrix M3 according to the third embodiment is compatible with the three write modes (asynchronous and synchronous) and the six read modes previously described.

[0103] Figure [Fig.4d] illustrates an electrical diagram of a memory matrix used in the memory circuit according to a fourth embodiment of the invention.

[0104] The memory matrix M4 is formed by a plurality of memory cells 10 according to the invention arranged in rows L and columns Ck, i=0 to N and k=0 to M. By way of illustration and not limitation, the matrix M4 is formed by 2 rows Lo, Li and 2 columns Co and Cp. Each memory cell further comprises an attenuation transistor T2. The drain of said attenuation transistor T2 is connected to the first electrode ELI. The gate of each transistor T2 is controlled by a VWL selection signal generated by the CONT control circuit.

[0105] The gates of the attenuation transistors T2 of the memory cells 10 belonging to the same column Ck of the memory matrix M4 are interconnected via a conductive line LWL,k for propagating the associated selection signal VWLk. The sources of the attenuation transistors T2 of the memory cells 10 belonging to the same row L; of the memory matrix M4 are interconnected via a conductive line L2,i for propagating the associated second control voltage VBL,i. The upper ends of the pillars MTJ of the memory cells 10 belonging to the same row L; of the memory matrix M4 are interconnected via a conductive line L1,i for propagating the associated first control voltage VRBLi. The second electrodes EL2 of the memory cells 10 belonging to the same column Ck of the memory matrix M4 are interconnected via a conductive line L3,i for propagating the associated third control voltage VBLBk.

[0106] Integrating the attenuation transistors T2 into the memory cells allows the memory cells not selected for a read or write operation to be isolated by applying a zero voltage to the gate of the attenuation transistor T2. Selecting a memory cell for reading or writing is achieved by applying the supply voltage VDD to the gate of the transistor T2 associated with said cell. memory. Furthermore, modulating the voltage applied to the gate of the attenuation transistor T2 reduces the amplitude of the write and / or read current, thereby improving the technical robustness of the memory cell and preventing accidental writes. The M4 memory matrix, according to the fourth embodiment, is compatible with the three write modes (asynchronous and synchronous) and the six read modes previously described.

[0107] Figure 4e illustrates an electrical diagram of a memory matrix used in the memory circuit according to a fifth embodiment of the invention.

[0108] The memory matrix M5 according to the fifth embodiment retains the same characteristics and advantages of the memory matrix according to the fourth embodiment. The memory matrix M5 differs from the memory matrix M4 by an inversion between, on the one hand, the conductive line intended to propagate the first control voltage VRBL (common to cells in the same column in M5) and, on the other hand, the conductive line intended to propagate the third control voltage VBLB (common to cells in the same row in M5).

[0109] The M5 memory matrix according to the fifth embodiment is compatible with the three writing modes (asynchronous and synchronous) and the six reading modes previously described. References

[0110] [1] : Rana Alhalabi, Etienne Nowak, loan-Lucian Prejbeanu, Gregory Di Pendina. High density SOTMRAM memory array based on a single transistor. Non-Volatile Memory Technology Symposium (NVMTS), Oct 2018, Sendai, Japan.

Claims

Demands

1. Magnetoresistive memory cell (10) comprising: - a pillar (MTJ) forming a magnetic tunnel junction (MTJ) and having an upper end for receiving a first control voltage (VRBL) and a lower end; - a write track (SOT) of a spin Hall effect material or an orbital Hall effect material; the pillar (MTJ) being disposed on said write track on the side of its lower end; - a support layer (14) of a material having a configurable metal-insulator transition; the support layer (14) having a first face (141) and a second opposite face (142); the write track (SOT) being disposed on said first face (141); - a first electrode (ELI) disposed on said second face (142) and intended to receive a second control voltage (VBL);the portion (143) of the support layer (14) confined between the first electrode (ELI) and the writing track (SOT) having a conduction state configurable by the first and second control voltages (VRBL, VBL) so as to form a first selector (SI) having a high resistive state (R1Off) and a low resistive state (RIon); - a second electrode (EL2) disposed on said second face (142) and intended to receive a third control voltage (VBLB); the portion (144) of the support layer (14) confined between the second electrode (EL2) and the writing track (SOT) having a conduction state configurable by the first and third control voltages (VRBL, VBLB) so as to form a second selector (S2) having a high resistive state (R20ff) and a low resistive state (R2ON).

2. Magnetoresistive memory cell (10) according to claim 1 in which the support layer (14) is made of Mott oxide or a topological insulator.

3. Magnetoresistive memory cell (10) according to claim 2 in which at least one of the confined parts (143,144) of the support layer (14) is doped with chromium or tungsten or titanium or aluminium or iron or molybdenum or tantalum or ruthenium or zirconium.

4. Magnetoresistive memory cell (10) according to any one of claims 1 to 3 wherein the write track (SOT) is made of a spin Hall effect material selected from beta-phase tungsten or bismuth antimonide or a BiSbTe alloy.

5. Magnetoresistive memory cell (10) according to any one of claims 1 to 3 wherein the write track (OT) is made of an Orbital Hall effect material selected from chromium or zirconium or titanium or vanadium or copper or manganese or molybdenum or ruthenium or aluminium or niobium or tungsten in alpha phase.

6. Magnetoresistive memory cell (10) according to any one of claims 1 to 5 wherein the write track (SOT) has a thickness less than or equal to 20 nm.

7. Magnetoresistive memory cell (10) according to any one of claims 1 to 6 wherein the first and / or second selector (SI, S2) has a resistance greater than or equal to 10 times the resistance of the write track (SOT) when said selector (SI, S2) is in a high resistive state (R10ff ,R20FF).

8. Magnetoresistive memory cell (10) according to any one of claims 1 to 7 wherein the first and / or second selector (SI, S2) has a resistance greater than or equal to 10 times the resistance of the magnetic tunnel junction (MTJ) when said selector (SI, S2) is in a high resistive state (R10ff, R20ff)-

9. Magnetoresistive memory cell (10) according to any one of claims 1 to 8 wherein the first and / or second selector (SI, S2) has a resistance less than or equal to the resistance of the write track (SOT) when said selector (SI, S2) is in a low resistive state (R10n, R2on)-

10. Magnetoresistive memory cell (10) according to any one of claims 1 to 9 wherein the first and / or second selector (S1, S2) has a resistance less than or equal to one-tenth of the resistance of the magnetic tunnel junction (MTJ) when said selector (SI, S2) is in a low resistive state (RIon, R20ff)-

11. Magnetoresistive memory cell (10) according to any one of claims 1 to 10 further comprising a control transistor (Tl); the source of said control transistor (Tl) being connected to the upper end of the pillar (MTJ).

12. Magnetoresistive memory cell (10) according to any one of claims 1 to 11 further comprising an attenuation transistor (T2); the drain of said attenuation transistor (T2) being connected to the first electrode (ELI).

13. Magnetoresistive memory cell (10) according to any one of claims 1 to 12 wherein the first and / or second selector (SI, S2) is adapted to switch from a high resistive state (R10ff, R20ff) to a low resistive state (R10n, R20n) when the amplitude of the voltage across said selector is greater than a predetermined threshold voltage (Vth).

14. Memory circuit (Dl) comprising: - a memory matrix (Mx) formed by a plurality of memory cells (10) according to claim 13; - a control circuit (CONT) configured to generate the first control voltage (VRBL), the second control voltage (VBL) and the third control voltage (VBLB).

15. Memory circuit (Dl) according to claim 14 wherein the control circuit (CONT) is configured to perform a write operation on a memory cell (10) of the matrix (Mx) by applying to it: - a first control voltage (VRBL) of zero, a second control voltage (VBL) greater than the predetermined threshold voltage (Vth) and a third control voltage (VBLB) of zero to write a first logic state; - a first control voltage (VRBL) of zero, a second control voltage (VBL) of zero and a third control voltage (VBLB) greater than the predetermined threshold voltage (Vth) to write a second logic state complementary to the first logic state.

16.

17.

18. Memory circuit (Dl) according to claim 14 in which the control circuit (CONT) is configured to perform a write operation on a memory cell (10) of the matrix (Mx) by applying to it: - a first control voltage (VRBL) greater than the predetermined threshold voltage (Vth), a second control voltage (VBL) equal to the first control voltage (VRBL) and a third control voltage (VBLB) of zero to write a first logic state; - a first control voltage (VRBL) greater than the predetermined threshold voltage (Vth), a second control voltage (VBL) of zero and a third control voltage (VBLB) equal to the first control voltage (VRBL) to write a second logic state complementary to the first logic state. Memory circuit (Dl) according to claim 14 in which the control circuit (CONT) is configured to perform a write operation on a memory cell (10) of the matrix (Mx) by applying to it: - a second control voltage (VBL) greater than twice the predetermined threshold voltage (Vth); a first control voltage (VRBL) equal to half of the second control voltage (VBL) and a third control voltage (VBLB) of zero to write a first logic state; - a third control voltage (VBLB) greater than twice the predetermined threshold voltage (Vth); a first control voltage (VRBL) equal to half of the third control voltage (VBL) and a second control voltage (VBL) of zero to write a second logic state complementary to the first logic state. Memory circuit (Dl) according to claim 14 in which the control circuit (CONT) is configured to perform a read operation of a memory cell (10) of the memory matrix (Mx) by applying to it a second and a third control voltage (VBL, VBLB) greater than the predetermined threshold voltage (Vth) and a first control voltage (VRBL) of zero.

19. Memory circuit (Dl) according to claim 14 wherein: - the upper ends of the pillars (MTJ) of the memory cells (10) belonging to the same column of the memory matrix (Ml) are interconnected via a first conductive line (Ll,0 ; Ll,l) intended to propagate the first associated control voltage (VRBL0VRBLi); - the first electrodes (ELI) of the memory cells (10) belonging to the same row of the memory matrix (Ml) are interconnected via a second conductive line (L2,0 ; L2,l) intended to propagate the second associated control voltage (VBL0, VBLi); - the second electrodes (EL2) of the memory cells (10) belonging to the same row of the memory matrix (Ml) are interconnected via a third conductive line (L3,0 ; L3.1) intended to propagate the third associated control voltage (VBLB0, VBLBi).

20. Memory circuit (Dl) according to claim 14 wherein: - the upper ends of the pillars (MTJ) of the memory cells (10) belonging to the same column of the memory matrix (M2) are interconnected via a first conductive line (Ll,0; Ll,l) for propagating the first associated control voltage (VRBL0VRBLi); - the first electrodes (ELI) of the memory cells (10) belonging to the same row of the memory matrix (M2) are interconnected via a second conductive line (L2,0; L2,l) for propagating the second associated control voltage (VBL0, VBLi); - the second electrodes (EL2) of the memory cells (10) belonging to the same column of the memory matrix (M2) are interconnected via a third conductive line (L3,0; L3.1) for propagating the third associated control voltage (VBLB0, VBLBi);

21. Memory circuit (Dl) according to claim 14 in combination with claim 11, wherein: the gates of the control transistors (Tl) of the memory cells (10) belonging to the same column of the matrix

22. memory (M3) are interconnected via a first conductive line (LWL,0 ; LWL,1) intended to propagate an associated selection signal (VWL0, VWLi); - the drains of the control transistors (Tl) of the memory cells (10) belonging to the same row of the memory matrix (M3) are interconnected via a second conductive line (L2,0 ; L2,l) intended to propagate the first associated control voltage (VRBL0, VRBLi); - the first electrodes (ELI) of the memory cells (10) belonging to the same row of the memory matrix (M3) are interconnected via a third conductive line (Ll,0 ; Ll,l) intended to propagate the second associated control voltage (VBL0, VBLi); - the second electrodes (EL2) of the memory cells (10) belonging to the same column of the memory matrix (M3) are interconnected via a fourth conductive line (L3,0 ; L3,l) intended to propagate the associated third control voltage (VBLB0, VBLBi); Memory circuit (Dl) according to claim 14 in combination with claim 12, wherein: - the upper ends of the pillars (MTJ) of the memory cells (10) belonging to the same row of the memory matrix (M4) are interconnected via a first conductive line (Ll,0 ; Ll,l) intended to propagate the first associated control voltage (VRBL0, VRBLi); - the sources of the attenuation transistors (T2) of the memory cells (10) belonging to the same row of the memory matrix (M4) are interconnected via a second conductive line (L2,0 ; L2,l) intended to propagate the second associated control voltage (VBL0 ; VBLi); - the second electrodes (EL2) of the memory cells (10) belonging to the same column of the memory matrix (M4) are interconnected via a third conductive line (L3,0 ; L3,l) intended to propagate the associated third control voltage (VBLB0, VBLBi); - the gates of the attenuation transistors (T2) of the memory cells (10) belonging to the same column of the matrix

23. memory (M4) are interconnected via a fourth conductive line (LWLO; LWL1) intended to propagate an associated selection signal (VWL0, VWLi); Memory circuit (Dl) according to claim 14 in combination with claim 12, wherein: - the upper ends of the pillars (MTJ) of the memory cells (10) belonging to the same column of the memory matrix (M5) are interconnected via a first conductive line (Ll,0 ; Ll,l) intended to propagate the first associated control voltage (VRBL0 ; VRBLi); - the sources of the attenuation transistors (T2) of the memory cells (10) belonging to the same row of the memory matrix (M5) are interconnected via a second conductive line (L2,0 ; L2,l) intended to propagate the second associated control voltage (VBL0 ; VBLi); - the second electrodes (EL2) of the memory cells (10) belonging to the same line of the memory matrix (M3) are interconnected via a third conductive line (L3,0 ; L3,l) intended to propagate the associated third control voltage (VBLB0, VBLBi); - the gates of the control transistors (T2) of the memory cells (10) belonging to the same column of the memory matrix (M3) are interconnected via a fourth conductive line (LWLO; LWL1) intended to propagate an associated selection signal (VWL0, VWLi).

Images