Method for modifying the conductance value of a phase-change memory cell during an inference cycle

Abstract

A method (100) for modifying a conductance or resistance (Ract) value within a resistance distribution range (Pprog1, Pprog2, Pprog3, Pprog4) defined around a median resistance distribution value (Rprog1, Rprog2, Rprog3, Rprog4) of at least one phase-change memory cell (C1, C2, C3, C4), the method (100) comprising: A determination step in which a melting current (Imelt) and an amorphous phase current (Iamorph) are determined; A quenching step (ET) in which a first pulse (I1) having a steep downward ramp and a quenching effect is applied to at least one phase-change memory cell (C1, C2, C3, C4); A crystallization step (EC) in which a second pulse (I2) having a gradual downward ramp is applied to at least one phase-change memory cell (C1, C2, C3, C4). Figure 5

Description

Title of the invention: Method for modifying the conductance value of a phase-change memory cell during an inference cycle. Technical field

[0001] The invention relates to the field of neural networks and more particularly to a method of modifying a conductance value of a phase-change memory cell. Prior art

[0002] Artificial neural networks are widely used in many areas of artificial intelligence, such as image recognition, speech recognition, etc.

[0003] Bayesian neural networks are of particular interest because they allow for the quantification of uncertainty in their predictions. To this end, synaptic weights—that is, a parameter of the neural network that quantifies the strength of a connection between two neurons—are not represented by a single value but by a distribution of conductance or resistance values. This distribution is characterized, in particular, by a median value and a standard deviation, which are determined during a learning process.

[0004] The inference phase is the phase during which the neural network is used to make predictions. The inference phase takes place after a learning phase.

[0005] It is known to implement the distribution of conductance values ​​characterizing the synaptic weight of a Bayesian neural network using a plurality of resistive memory cells. This solution, requiring the use of a large number of resistive memory cells, notably results in significant power consumption of the neural network during the inference phase. Furthermore, this solution uses a large silicon area, which reduces the density of the neural network and increases manufacturing costs.

[0006] One solution consists of implementing the distribution of conductance values ​​using a single memory cell, such as an emergent resistive memory cell like filamentary memory, also called RRAM (acronym for "Resistive random-access memory"). Indeed, an electrical reprogramming pulse applied to the RRAM filamentary memory allows its conductance value to be modified randomly around the median conductance value at each inference cycle. It is thus possible to represent a distribution of conductance values ​​during inference cycles using a single cell.

[0007] However, applying the reprogramming pulse degrades the RRAM filament memory and can only be performed a limited number of times before probable RRAM filament memory failure. This severely restricts the use of this solution.

[0008] It is also possible to apply a read electrical pulse to the RRAM filament memory in order to modify its conductance value. Indeed, the read pulse is less aggressive than the reprogramming pulse, allowing for a long lifespan, and disrupts the conductance value of the RRAM filament memory.

[0009] The drawback is that the distribution range, i.e., the standard deviation, of conductance obtained with a read pulse is very small and unsuitable for an industrially scalable product. Furthermore, filamentary RRAM memories exhibit high conductance values, which significantly increases their power consumption, particularly during combined multiplier-accumulate operations, also known as MAC (acronym for "multiply-accumulate").

[0010] There is therefore a need for a single memory cell capable of representing a synaptic weight of a Bayesian network that overcomes the above drawbacks. Description of the invention

[0011] One embodiment relates to a method for modifying a conductance value, or respectively resistance, within a defined resistance distribution range around a median resistance distribution value, or respectively conductance value, of at least one phase-change memory cell, said at least one phase-change memory cell being included in a memory array comprising a plurality of memory cells, the at least one memory cell comprising a lower electrode, an upper electrode, and a phase-change material located between the lower and upper electrodes, the phase-change material being capable of assuming a crystalline, partially amorphous, or completely amorphous state at an interface with the lower electrode, the method being implemented by a neural network and comprising: - A determination step in which a melting current and an amorphous phase current are determined for at least one phase-change memory cell, the melting current corresponding to the current causing at least partial localized melting of the phase-change material at the interface with the lower electrode when it is applied to at least one phase-change memory cell, the amorphous phase current corresponds to the current causing the creation of a completely amorphous state at the interface with the lower electrode when applied to at least one phase-change memory cell; - A tempering step in which a first pulse with a modification current greater than or equal to the fusion current, and strictly less than the amorphous phase current, is applied to at least one phase-change memory cell, the first pulse exhibiting an upward ramp followed by an abrupt downward ramp having a tempering effect; - A crystallization step in which a second pulse to the modification current is applied to at least one phase-change memory cell, said at least one phase-change memory cell being identical to the at least one phase-change memory cell of the quenching step, the second pulse having an upward ramp followed by a progressive downward ramp.

[0012] The conductance value of the phase-change memory cell is directly related to a resistance value, since the conductance is equal to the inverse of the resistance of the phase-change memory cell. The method according to the invention therefore corresponds to a method for modifying the conductance value, or equivalently the resistance value, of the phase-change memory cell.

[0013] A neural network comprises a plurality of phase-change memory cells grouped in a memory matrix.

[0014] A phase change memory cell, also called PCM (acronym for "phase change memory"), is a type of non-volatile memory that relies on a reversible phase change of a material to store information. More specifically, the electrical resistivity of the phase change material, or in other words, its conductance value, varies according to a ratio of a highly resistive amorphous phase to a ratio of a low-resistive crystalline phase of said phase change material. The phase change material is located between a lower electrode and an upper electrode. The phase change material can take on: - a crystalline state in which the phase-change material in contact with the lower electrode is completely in the crystalline phase, - a partially amorphous state in which the phase-change material in contact with the lower electrode is partly in the crystalline phase and partly in the amorphous phase, - a completely amorphous state in which the phase-change material in contact with the lower electrode is completely in the amorphous phase.

[0015] To determine the state of the phase-change material at the interface with the lower electrode of a given phase-change memory cell, the resistance value of the phase-change memory cell is measured as a function of different applied voltages. The detection of a threshold voltage, that is, a voltage at which a sudden decrease in the resistance value of the phase-change memory cell is detected, indicates a completely amorphous state of the material at the interface with the lower electrode.

[0016] The resistance, respectively conductance, of the phase-change memory cell for which a threshold voltage is detected is called the threshold resistance, respectively conductance.

[0017] The phase change is achieved by applying an electrical pulse between the lower and upper electrodes, which heats the phase-change material of the phase-change memory cell by Joule heating. More precisely, the electrical pulse induces at least partial melting of the phase-change material. Then, according to a cooling temperature profile, i.e., according to the applied downward ramp, the crystalline or amorphous phase is created in the phase-change material.

[0018] The electrical pulse is defined as having an upward ramp during which the pulse current increases and goes from a minimum value, which may be equal to zero, to a maximum value, corresponding to the nominal current value, hereafter also referred to as the modification current, and a downward ramp during which the pulse current decreases and goes from the nominal current value to the minimum value.

[0019] Depending on the temperature profile applied by the electrical pulse, i.e. after at least partial melting of the phase-change material and according to the downward ramp applied, the phase-change material changes state so as to become more crystalline or more amorphous than before the application of the pulse.

[0020] More particularly, after melting, rapid cooling of the phase-change material, i.e. an abrupt downward ramp, leads to the appearance of the amorphous phase, while slow cooling, i.e. a progressive ramp, leads to the appearance of the crystalline phase, at the interface with the lower electrode.

[0021] For example, a pulse with a rectangular profile corresponds to a pulse whose rising and falling ramps are substantially instantaneous, so that the current rise and the current fall are rapid. The rectangular pulse profile causes the phase-change material to melt and then cool rapidly, resulting in a greater presence of the amorphous phase at the interface with the lower electrode than before the pulse. More precisely, the amorphous phase is generated at high temperature, i.e., during the melting of the phase-change material, and the subsequent rapid cooling allows for the preservation of this amorphous phase.

[0022] The duration of the applied pulse is a standard pulse duration in a neural network, typically on the order of a hundred nanoseconds. The nominal current value of the pulse is therefore crucial in determining the temperature and quantity of phase-change material that is heated by the pulse, and thus the amount of material at the interface with the lower electrode that can undergo a phase change.

[0023] For a phase-change memory cell, a melting current is defined as a nominal current value for a pulse at which at least a quantity of the phase-change material in contact with the lower electrode can change phase, such that the conductance value of the phase-change memory cell varies. A pulse applied to the phase-change memory cell with a nominal current lower than the melting current does not cause any phase change and therefore no change in conductance.

[0024] An amorphous phase current is also distinguished which corresponds to the nominal current value of a pulse beyond which the phase-change material becomes completely amorphous at the interface with the lower electrode.

[0025] The amorphous phase current is determined by the successive application of a pulse with a steep downward ramp, having a quenching effect on the phase-change memory cell, starting from a crystalline state. These pulses will progressively modify the conductance, or resistance, of the phase-change memory cell. When a threshold voltage appears in the phase-change memory cell, that is, when the phase-change memory cell is in a completely amorphous state at the interface with the lower electrode, the current of the last applied pulse is defined as the amorphous phase current.

[0026] In other words, from the value of the pulse current causing the appearance of a threshold voltage, and therefore the creation of a completely amorphous state at the interface with the lower electrode, we deduce the threshold resistance and the amorphous phase current which corresponds to said value of the pulse current.

[0027] During a learning phase, the phase-change memory cell is programmed so that the conductance value is equal to a median value of the conductance distribution. There are several ways to program the cell The process uses phase-change memory known to a person skilled in the art. Then, during an inference phase, the method seeks to modify the conductance value of the phase-change memory cell within a distribution range defined around the median value of the conductance distribution. This distribution range is defined between a lower and an upper conductance value determined during the learning phase around the median value of the conductance distribution.

[0028] At each inference cycle, the conductance value of the phase-change memory cell is modified within the distribution range so that the median value of the conductance distribution does not vary during the different inference cycles.

[0029] Thus, during the inference cycles, the median value of the conductance distribution can be defined as the median value of conduction and the distribution range as the standard deviation.

[0030] To achieve this modification of the conductance value, the method includes a determination step. During this step, the fusing current and the amorphous phase current are determined for the phase-change memory cell. According to a feature of the invention, during the determination step, a threshold voltage and, a threshold conductance or a threshold resistance, of at least one phase-change memory cell are determined.

[0031] Next, the process includes a quenching step. In this step, a first electrical pulse is applied to the phase-change memory cell. The first pulse has a steep downward ramp, resulting in the presence of an amorphous phase in the phase-change material, for example, a rectangular pulse profile, and a modification current greater than or equal to the melting current and strictly less than the amorphous phase current. Thus, the modification current is chosen to be sufficient to locally melt the phase-change material while allowing for lower power consumption than that associated with a programming pulse. Furthermore, the use of such a modification current, lower than the amorphous phase current, degrades the phase-change memory cell less and therefore allows for an extended lifespan.After the quenching stage, the conductance value of the phase-change memory cell is therefore reduced.

[0032] The process also includes a crystallization step. In this step, a second electrical pulse is applied to the phase-change memory cell. The second pulse has a gradual downward ramp, allowing the formation of a crystalline phase in the phase-change material at the change current. The downward ramp of the second pulse enables the local creation of a crystalline phase in the phase-change material. After the step Due to crystallization, the conductance value of the phase-change memory cell is therefore increased.

[0033] The process does not define an order of execution between the quenching step and the crystallization step. The quenching step can therefore be followed by the crystallization step or carried out after the latter.

[0034] Furthermore, the current applied during the first pulse is equal to the current applied during the second pulse. Thus, the reduction in conductance achieved during the quenching step is substantially equal to the increase in conductance achieved during the crystallization step, so that the conductance value remains within the distribution range defined around the median value of the conductance distribution.

[0035] The quenching and crystallization steps of the process maximize the maintenance of the phase-change memory cell's conductance value within the distribution range defined around the median value of the conductance distribution. Thus, the median value of the conductance distribution remains stable during inference cycles while ensuring satisfactory cycle-to-cycle variability of the phase-change memory cell's conductance value.

[0036] The object of this presentation may also have one or more of the following characteristics taken alone or in combination.

[0037] In some embodiments, during the determination step, a global maximum fusion current and a global minimum amorphous phase current are determined.

[0038] The overall maximum melting current corresponds to the maximum of the melting currents determined for each phase-change memory cell in the memory array. In other words, if a pulse at the overall maximum melting current is applied to all the phase-change memory cells in the memory array, then at least partial localized melting of the phase-change material at the interface with the lower electrode will occur in all the phase-change memory cells in the memory array. Thus, the conductance values ​​of all the phase-change memory cells in the memory array will be modulated.

[0039] The overall minimum amorphous phase current corresponds to the minimum of the amorphous phase currents determined for each phase-change memory cell in the memory array. In other words, if a pulse with the overall minimum amorphous phase current is applied to all the phase-change memory cells in the memory array, then at least one phase-change memory cell in the memory array will transition to the completely amorphous state.

[0040] To determine the overall minimum amorphous phase current, the conductance, or resistance, of all the phase-change memory cells in the memory array is modified to increasing resistance values, starting from a crystalline state. This is achieved by applying pulses with a steep downward ramp, a quenching effect, and an increasing modification current to all the memory cells. For each resistive state, the occurrence of a threshold voltage across all the phase-change memory cells in the memory array is evaluated. As long as no threshold voltage is detected, the injection of pulses with a steep downward ramp and a quenching effect at a higher modification current continues. The modification current at which a threshold voltage is detected in one or more cells of the memory array is defined as the "overall minimum amorphous phase current.".

[0041] In some embodiments, during the determination step, a global maximum fusion current and a global minimum amorphous phase current are determined.

[0042] In certain embodiments, during the quenching step, the first pulse to the modification current is applied simultaneously to all the phase-change memory cells of the memory matrix, and during the crystallization step, the second pulse is applied simultaneously to all the phase-change memory cells of the memory matrix.

[0043] All the phase-change memory cells in the memory matrix are therefore subjected to the same pulse. Thus, the conductance value of all the phase-change memory cells is modified simultaneously.

[0044] In some embodiments, the modification current is greater than or equal to the overall maximum fusion current and strictly less than the overall minimum amorphous phase current.

[0045] Thus, the modification current is identical for all phase-change memory cells. It is therefore not necessary to know, and thus not to store in memory, the fusion, amorphous phase, and modification currents for each phase-change memory cell.

[0046] In certain embodiments, the median value of conductance distribution, or respectively of resistance, as well as the range of conductance distribution, or respectively of resistance, of at least one phase-change memory cell are defined as greater than, respectively less than, a threshold conductance, respectively threshold resistance, corresponding to a conductance, respectively resistance, of at least one phase-change memory cell for which a threshold voltage is detected.

[0047] Thus, the phase-change memory cell remains in a crystalline or partially amorphous state.

[0048] In certain embodiments, the median value of conductance distribution, respectively of resistance, as well as the distribution range of at least one phase-change memory cell are maintained above, respectively below, the threshold conductance, respectively resistance, during the quenching and crystallization steps.

[0049] In some embodiments, the descent ramp of the first pulse is twice as fast as the descent ramp of the second pulse.

[0050] In some embodiments, the abrupt downward ramp of the first pulse has a duration less than or equal to 30ns.

[0051] In other words, a transition from the modification current to the minimum current is achieved with a duration less than or equal to 30ns.

[0052] In some embodiments, the progressive descending ramp of the second pulse has a duration greater than 30ns and preferably greater than or equal to 60ns.

[0053] In other words, a transition from the modification current to the minimum current is achieved with a duration greater than 30ns and preferably greater than or equal to 60ns.

[0054] In some embodiments, the modification current is between the fusion current and 1.2 times the fusion current.

[0055] Experience shows that 1.2 times the fusion current is always less than the amorphous phase current. Thus, the conductance value of at least one phase-change memory cell is realized around the median value.

[0056] In some embodiments, the method includes a read step in which a read pulse at a read voltage is applied to at least one phase-change memory cell in order to measure the resistance or conductance value.

[0057] The method further includes a read step that applies a pulse whose voltage is not high enough to change the conductance of the phase-change memory cell. The read step allows the conductance value of the phase-change memory cell to be measured and determined. More specifically, the read step can precisely measure the exact value of the conductance or determine only whether the conductance value is within the distribution range defined around the median value of the conductance distribution.

[0058] The reading step is part of the modification process in that it corresponds to a check of the conductance value obtained. This reading step is not necessarily used as a useful value during the implementation, i.e., during an inference cycle, of the neural network.

[0059] The read voltage cannot induce a phase change in the memory cell. Therefore, the read voltage is lower than the threshold voltage of the phase-change memory cell. Consequently, the read voltage does not change the conductance value of the phase-change memory cell. The read voltage only allows the conductance value to be determined. In other words, the read voltage allows the conductance value of the phase-change memory cell to be measured.

[0060] Preferably, the read voltage is less than the minimum threshold voltage detected on all devices present in the memory matrix.

[0061] The reading step is carried out after the quenching step and the crystallization step have been completed.

[0062] With an accumulation of inference cycles and an increase in the frequency of execution of the quenching and crystallization steps, the phase-change memory cell can lose the median value of the conductance distribution. It is therefore important to verify, after modifying the conductance value, that it is within the distribution range defined around the median value of the conductance distribution. The read step can be performed at a frequency lower than the frequency of the inference cycle.

[0063] According to one embodiment, the reading step is carried out only on at least one phase-change memory cell that has undergone the quenching and crystallization steps.

[0064] In some embodiments, a reprogramming step of at least one phase-change memory cell is carried out according to the resistance or conductance value measured during the reading step.

[0065] For example, the reprogramming step is carried out if the measured conductance value is no longer within the defined distribution range.

[0066] The reprogramming step consists of reprogramming the device of interest to the median value of the conductance or resistance distribution, according to a method known to the person skilled in the art.

[0067] In some embodiments, the phase change material is a chalcogenide material.

[0068] Chalcogenide materials are compounds containing at least one metal ion and at least one ion of a chalcogen element, which includes in particular oxygen, sulfur, selenium, and tellurium.

[0069] In some embodiments, the chalcogenide material is of a non-congruent nature.

[0070] A non-congruent material forms a liquid at a melting point that has a different chemical composition from the material in solid form.

[0071] An integration of a chalcogenide material of non-congruent nature makes it possible to increase the variability of the phase-change memory cell and thus to broaden the distribution range that can be obtained during the modification process.

[0072] In some embodiments, the chalcogenide material comprises antimony.

[0073] An antimony-rich chalcogenide material also makes it possible to improve the distribution range that can be obtained during the modification process.

[0074] In some embodiments, the change current depends on the value of the median conductance or resistance distribution, and the desired resistance distribution range.

[0075] In some embodiments, the memory matrix is ​​a neuromorphic circuit having an ITIRou 1S1R configuration.

[0076] The "1T1R" configuration in a neuromorphic circuit refers to a specific architecture, where "1T" signifies a transistor and "IR" corresponds to the phase-change memory cell. More specifically, the transistor can be a FEOL access transistor, an acronym for "Front-end-of-line." The transistor acts as a switch to control and limit the current flow through the phase-change memory cell. To change the conductance value of the phase-change memory cell, and thus to write a new value, the transistor is activated, allowing an electrical pulse to flow through the phase-change memory cell. More precisely, the greater the current flow, the larger the volume of phase-change material that will be melted during the pulse. This increases the range of conductance distribution that can be encoded in the memory cell.However, this leads to a greater risk of losing the median value of the conductance distribution and therefore a need for more frequent reprogramming.

[0077] The "1S1R" configuration in a neuromorphic circuit refers to a specific architecture, where "1S" signifies a selector and "IR" corresponds to the phase-change memory cell. The selector can be a BEOL selector device, an acronym for "Back-end-of-line." The selector acts as a switch that controls the flow of current through the phase-change memory cell in response to a switching voltage. When a new value needs to be written to the phase-change memory cell, a switching voltage is applied to the 1S1R device. This allows current to flow through the phase-change memory cell. Electrical pulses according to the process are then applied, changing the conductance value of the phase-change memory cell. After writing, the selector becomes insulating again. This protects the phase-change memory cell from leakage currents and interference during read operations in the memory array. One advantage of the "1S1R" configuration is its ability to significantly increase the overall density of the memory array. 1S1R devices are integrated into a crossbar structure, where it is possible to reduce the size of the memory cell to as small as 4F², where F is the smallest size achievable by lithography at a given technology node. This improves the performance of the neuromorphic circuit.

[0078] In some embodiments, the neural network is a Bayesian neural network.

[0079] A Bayesian neural network is an artificial neural network architecture that incorporates principles of probability and uncertainty into its learning mechanism. Unlike classical neural networks, where synaptic weights are fixed values, Bayesian neural networks treat synaptic weights as probability distributions. This allows for the modeling of inherent uncertainty in the data and predictions and provides confidence estimates for the model's predictions. These characteristics make Bayesian neural networks particularly useful in fields where uncertainty assessment is important, such as medicine or finance.

[0080] The invention, which allows the conductance value of the phase-change memory cell to be modified within a defined distribution range around a median value of the conductance distribution, is particularly suited to the Bayesian neural network.

[0081] One embodiment aims at a neural network implementing, during an inference cycle, the method of modifying a conductance value, or resistance, of at least one phase-change memory cell according to the invention.

[0082] A neural network inference cycle is performed to obtain a prediction. The inference cycle corresponds to a use of the neural network. In each inference cycle, the modification process, including the quenching step, the crystallization step, and optionally the reading and reprogramming step, is carried out. Brief description of the drawings

[0083] The invention will be better understood from the following description, which relates to an embodiment according to the present invention, given by way of non-limiting example and explained with reference to the accompanying schematic drawings, in which:

[0084] [Fig.1] illustrates an evolution of a resistance value of a phase-change memory cell as a function of an applied voltage for eight different starting resistive states.

[0085] [Fig.2] is a graph representing the evolution of the threshold voltage of the phase-change memory cell as a function of the resistance initially programmed on the cell.

[0086] [Fig.3] is a graph representing an evolution of the resistance value of the phase-change memory cell as a function of an applied current for four different starting resistive states.

[0087] [Fig.4] is a diagram that illustrates four distribution ranges and a variation of a median resistance distribution value during inference cycles.

[0088] [Fig.5] is a schematic representation of the process according to the invention. Description of the implementation methods

[0089] The invention relates to a neural network implementing, during an inference cycle, a method for modifying 100 a conductance or resistance value Ract of at least one phase-change memory cell Cl, C2, C3, C4 included in a memory matrix MM. The neural network comprises a plurality of phase-change memory cells Cl, C2, C3, C4 grouped in a memory matrix MM.

[0090] Optionally, the method 100 also includes an IL reading step during which the conductance or resistance value Ract is measured.

[0091] A neural network inference cycle is performed to obtain a prediction. The inference cycle corresponds to a use of the neural network.

[0092] Preferably, the neural network is a Bayesian neural network.

[0093] A Bayesian neural network is an artificial neural network architecture that incorporates principles of probability and uncertainty into its learning mechanism. Unlike classical neural networks, where synaptic weights are fixed values, Bayesian neural networks treat synaptic weights as probability distributions. This allows for the modeling of inherent uncertainty in the data and predictions and provides confidence estimates for the model's predictions. These characteristics make Bayesian neural networks particularly useful in fields where uncertainty assessment is important, such as medicine or finance.

[0094] The modification method 100, allowing modification of the conductance or resistance value Ract of the phase-change memory cell Cl, C2, C3, C4 in a defined resistance distribution range Pprogi, Pprog2, Pprog3, Pprog4 around a median value of the conductance distribution, or similarly of resistance Rprogi, Rprog2, Rprog3, Rprog4, is particularly suited to the Bayesian neural network.

[0095] In the following description, analogous reference is made to the conductance or resistance of the phase-change memory cell Cl, C2, C3, C4. Indeed, it is well known that resistance and conductance are two intrinsically linked but inverse electrical properties, describing respectively a material's ability to impede or facilitate the flow of electric current. Resistance, measured in ohms, is defined by Ohm's law as the ratio of voltage to current through a material. Conversely, conductance, expressed in Siemens, is the inverse of resistance. Thus, resistance and conductance are inversely proportional: a material with high resistance will have low conductance, and vice versa. Figures 1 through 4, in particular, show resistance values.

[0096] The phase change memory cell Cl, C2, C3, C4, called PCM (acronym for "phase change memory"), is a type of non-volatile memory that relies on a reversible phase change of a phase change material to store information. More specifically, the electrical resistivity of the phase change material, or in other words, its conductance value, varies according to a ratio of a highly resistive amorphous phase to a ratio of a low-resistive crystalline phase of said phase change material. The phase change material is located between a lower electrode and an upper electrode.

[0097] The phase-change material can take: - a crystalline state in which the phase-change material in contact with the lower electrode is completely in the crystalline phase, - a partially amorphous state in which the phase-change material in contact with the lower electrode is partly in the crystalline phase and partly in the amorphous phase, - a completely amorphous state in which the phase-change material in contact with the lower electrode is completely in the amorphous phase.

[0098] In some embodiments, the phase-change material is a chalcogenide material. Chalcogenide materials are compounds containing at least one metal ion and at least one ion of a chalcogen element, which includes, in particular, oxygen, sulfur, selenium, and tellurium.

[0099] In certain embodiments, the chalcogenide material is incongruent. An incongruent material forms a liquid at a melting point that has a different chemical composition than the material in its solid form. Incorporating an incongruent chalcogenide material increases the variability of the phase-change memory cell Cl, C2, C3, C4 and thus broadens the resistance distribution range Pprog1, Pprog2, Pprog3, Pprog4 that can be obtained during the modification process 100.

[0100] In some embodiments, the chalcogenide material comprises antimony. A chalcogenide material rich in antimony also makes it possible to improve the resistance distribution range Pprog1, Pprog2, Pprog3, Pprog4 that can be obtained during the modification process 100.

[0101] To determine the state of the phase-change material at the interface with the lower electrode of a given phase-change memory cell Cl, C2, C3, C4, the resistance of the phase-change memory cell Cl, C2, C3, C4 is measured as a function of different applied voltages Vapp. The detection of a threshold voltage Vth_i, Vth_2, Vth_3, Vth_4, i.e., a voltage at which a sharp decrease in the resistance value of the phase-change memory cell Cl, C2, C3, C4 is detected, indicates a completely amorphous state of the material at the interface with the lower electrode.

[0102] The resistance, respectively conductance, of the threshold Rth, respectively 1 / Rth, is called the resistance, respectively conductance, of the phase-change memory cell for which a threshold voltage is detected.

[0103] In the method according to the invention, the plurality of phase-change memory cells Cl, C2, C3, C4 of the MM memory matrix are initially programmed so as to present a crystalline or partially amorphous state at an interface with a lower electrode.

[0104] Figure 1 illustrates the evolution of the resistance value of a phase-change memory cell as a function of an applied voltage Vapp for eight different initial resistive states 1, 2, 3, 4, 5, 6, 7, 8. In the graph on the left, a threshold voltage Vth-1, Vth-2, Vth-3, Vth-4 is detected for the four resistive states 1, 2, 3, 4 shown on the left. This indicates that an amorphous phase completely covers the interface with the lower electrode of the memory cell. These are therefore four completely amorphous resistive states 1, 2, 3, 4. Breakdown of the amorphous phase, which completely covers the interface with the lower electrode of the memory cell, occurs at the threshold voltages Vth, Vth2, Vth3, and Vth4. This results in a sharp drop in the resistance of the phase-change memory cell. In the graph on the right, no threshold voltage Vth is detected for the four resistive states 5, 6, 7, and 8 shown.This indicates that the amorphous phase does not completely cover the interface with the lower electrode of the memory cell. Therefore, there are four resistive states 5, 6, 7, 8 which are either crystalline or partially amorphous.

[0105] The phase change is achieved by applying an electrical pulse II, 12, between the lower and upper electrodes, which heats by Joule effect said phase change material of the phase change memory cell Cl, C2, C3, C4.

[0106] The electrical pulse II, 12 is defined as having an upward ramp during which a pulse current increases and goes from a minimum value, which may be equal to zero, to a maximum value, corresponding to the nominal current value, hereafter also designated by the lapp modification current, and a downward ramp during which the pulse current decreases and goes from the nominal current value to the minimum value.

[0107] Depending on the downward ramp applied, the phase-change material changes state so as to become more crystalline or more amorphous than before the application of the pulse.

[0108] More particularly, rapid cooling of the phase-change material, i.e. an abrupt downward ramp, leads to the presence of the amorphous phase, while slow cooling, i.e. a gradual ramp, leads to the appearance of the crystalline phase, at the interface with the lower electrode.

[0109] For example, a pulse II with a rectangular profile corresponds to a pulse whose rising and falling ramps are substantially instantaneous, so that the current rise and fall are rapid. The pulse II with a rectangular profile causes rapid cooling of the phase-change material, which induces the appearance of the amorphous phase at the interface with the lower electrode.

[0110] The duration of the applied pulse II, 12 is a standard pulse duration in a neural network, typically on the order of a hundred nanoseconds. The nominal current value of the pulse lapp is therefore determining the temperature and quantity of phase-change material that is heated by the pulse, and thus the quantity of material at the interface with the lower electrode that can change phase.

[0111] In certain embodiments, a steep downward ramp can be defined as having a duration less than or equal to 30ns. In other words, a transition from the change current lapp to the minimum current is achieved with a duration less than or equal to 30ns.

[0112] In certain embodiments, it can be defined that a progressive descending ramp has a duration greater than 30 ns and preferably greater than or equal to 60 ns. In other words, a transition from the change current lapp to the minimum current is achieved with a duration greater than 30 ns and preferably greater than or equal to 60 ns.

[0113] A phase change in the material of the phase-change memory cell Cl, C2, C3, C4 results in a variation in its conductance or resistance. Thus, the more the material of the phase-change memory cell Cl, C2, C3, C4 is in a crystalline state, the lower its resistance, while the more the The more phase-change memory cell material Cl, C2, C3, C4 is in an amorphous state, the higher its resistance.

[0114] The value of the change current lapp is also very important to determine the phase change that will occur when the electrical pulse is applied.

[0115] Figure 3 illustrates the evolution of the resistance values ​​Rprog1, Rprog2, Rprog3, and Rprog4 of a phase-change memory cell as a function of an applied current Iapp across its terminals for four different initial resistive states C1, C2, C3, and C4. In C1, the phase-change memory cell was initially programmed with a resistance of 70 kΩ. In C2, the phase-change memory cell was initially programmed with a resistance of 40 kΩ. In C3, the phase-change memory cell was initially programmed with a resistance of 20 kΩ. In C4, the phase-change memory cell was initially programmed with a resistance of 8 kΩ. All states are programmed to ensure a crystalline or partially amorphous state, i.e., the interface with the lower electrode is not completely covered with amorphous phase.

[0116] Figure 2 illustrates a graph representing the evolution of the threshold voltage Vth of the phase-change memory cell of Figure 1 as a function of the initial resistive state 1, 2, 3, 4, 5, 6, 7, 8 of the resistance initially programmed on the cell. The minimum resistance for which a threshold voltage V* is detected in the phase-change memory cell of the memory array corresponds to a threshold resistance Rth. The associated threshold conductance is equal to 1 / Rth.

[0117] Thanks to this type of graph, one can determine a fusion current Imelt, an amorphous phase current lamorph, a threshold resistance Rth, and a threshold voltage V* of the phase-change memory cell.

[0118] These graphs make it possible, in particular, to determine: - The melting current Imelt corresponds to a nominal current value for a pulse at which at least some of the phase-change material in contact with the lower electrode can change phase, such that the conductance value of the phase-change memory cell Cl, C2, C3, C4 varies. A pulse applied to the phase-change memory cell Cl, C2, C3, C4 with a nominal current lower than the melting current Imelt results in no phase change and therefore no change in conductance 1 / Ract or resistance Ract - the amorphous phase current lamorph which corresponds to the nominal current value of a pulse beyond which the phase-change material becomes completely amorphous at the interface with the lower electrode; - The threshold resistance Rth for which the phase change material is completely amorphous at the interface with the lower electrode; - The minimum threshold voltage Vth, corresponding to the voltage required to induce breakdown of the amorphous phase completely covering the interface with the lower electrode of a memory cell programmed with a resistance equal to the threshold resistance Rth.

[0119] The amorphous phase current is determined by the successive application of a pulse with a steep downward ramp, having a quenching effect on the phase-change memory cell, starting from a crystalline state. These pulses will progressively modify the conductance, or resistance, of the phase-change memory cell. When a threshold voltage appears in the phase-change memory cell, that is, when the phase-change memory cell is in a completely amorphous state at the interface with the lower electrode, the current of the last applied pulse is defined as the amorphous phase current.

[0120] In other words, from the value of the pulse current causing the appearance of a threshold voltage, and therefore the creation of a completely amorphous state at the interface with the lower electrode, we deduce the threshold resistance and the amorphous phase current which corresponds to said value of the pulse current.

[0121] During a learning phase 200, the phase-change memory cell C1, C2, C3, C4 is programmed so that the conductance value 1 / Rct or resistance value 1 / Rct is equal to a median value of the conductance distribution 1 / Rprog, 1 / Rprog2, 1 / Rprog3, 1 / Rprog4 or resistance values ​​Rprog, Rprog2, Rprog3, Rprog4. The median values ​​of the resistance distributions Rprog, Rprog2, Rprog3, Rprog4 are always programmed so as to always be less than the threshold resistance Rth. The median values ​​of the conductance distributions 1 / Rprog, 1 / Rprog2, 1 / Rprog3, 1 / Rprog4 are always programmed so as to always be greater than the threshold conductance 1 / R*. There are several ways to program the phase change memory cell Cl, C2, C3, C4 known to a person skilled in the art.

[0122] Then, during an inference phase, the method 100 seeks to modify the conductance or resistance value Ract of the phase-change memory cell Cl, C2, C3, C4 within the resistance distribution range Pprog1, Pprog2, Pprog3, Pprog4 defined around this median value of the conductance distribution 1 / Rprog1, 1 / Rprog2, 1 / Rprog3, 1 / Rprog4, respectively resistance Rprog1, Rprog2, Rprog3, Rprog4, so that to always remain above, respectively below, the threshold conductance 1 / Rth, respectively threshold resistance Rth. The resistance distribution range Pprogi, PProg2, Pprog3, Pprog4 is defined between a lower and an upper resistance value, determined during the learning phase 200. The resistance distribution Rprogi, Rprog2, Rprog3, Rprog4 of the phase-change memory cell must always remain below the threshold resistance Rth.

[0123] The objective of modification process 100 is illustrated in [Fig.5]. In each inference cycle, the conductance or resistance value of the cell is modified while maintaining the conductance value 1 / Ract or the resistance Ract, Ract corresponding to the resistance value Rprogi, Rprog2, Rprog3, Rprog4 on [Fig. 4], within the distribution range corresponding to the resistance distribution ranges Pprogi, Pprog2, Pprog3, Pprog4. These resistance distribution ranges Pprogi, Pprog2, Pprog3, Pprog4 are defined around the median resistance distribution value Rprogi, Rprog2, Rprog3, Rprog4. [Fig. 4] illustrates a variation in the median resistance distribution value Rprogi, Rprog2, Rprog3, Rprog4 during inference cycles by implementing the modification process 100. It can be seen that this median resistance distribution value Rprogi, Rprog2, Rprog3, Rprog4 is essentially constant.Since the median value of the resistance distribution Rprogi, Rprog2, Rprog3, Rprog4 is a representation of the resistance value, the modification process 100 allows the median value of the resistance distribution to be maintained over time.

[0124] The modification method 100 is illustrated more particularly in [Fig.5]. As already explained, the purpose of the method 100 is to modify the conductance value 1 / Ract or resistance Ract of the phase-change memory cell Cl, C2, C3, C4, during the inference cycles, so that the conductance value 1 / Ract or resistance Ract remains within the resistance distribution range Pprogi, Pprog2, Pprog3, Pprog4 defined around the median value of the resistance distribution Rprogi, Rprog2, Rprog3, Rprog4.

[0125] For this purpose, the method 100 includes a determination step. During this step, the melting current Imelt, the amorphous phase current lamorph, and optionally the minimum threshold voltage Vth and the threshold resistance Rth are determined for the phase-change memory cell Cl, C2, C3, C4.

[0126] Next, the process 100 includes a quenching step ET. In this step, a first electrical pulse II is applied to the phase-change memory cell Cl, C2, C3, C4. The first pulse II has a steep downward ramp, resulting in the appearance of an amorphous phase in the phase-change material, for example, a rectangular pulse profile, and a modification current lapp greater than or equal to the melting current Imelt and strictly less than the amorphous phase current lamorph. Thus, the modification current lapp is A sufficient current was chosen to locally melt the phase-change material while allowing for lower power consumption than that associated with a programming pulse. Furthermore, the use of such a phase-change current, lapp, which is lower than the amorphous phase current lamorph, degrades the phase-change memory cell Cl, C2, C3, C4 less and thus allows for an extended lifespan. After the ET quenching step, the resistance value Ract of the phase-change memory cell Cl, C2, C3, C4 is therefore increased.

[0127] The process also includes a crystallization step EC. In this step, a second electrical pulse 12 is applied to the phase-change memory cell Cl, C2, C3, C4. The second pulse 12 has a gradual downward ramp, allowing the formation of a crystalline phase in the phase-change material at the change current lapp. The downward ramp of the second pulse 12 enables the local creation of a crystalline phase in the phase-change material. After the crystallization step, the resistance value Ract of the phase-change memory cell Cl, C2, C3, C4 is therefore reduced.

[0128] Process 100 does not define an order of execution between the quenching step ET and the crystallization step EC. The quenching step ET can therefore be followed by the crystallization step EC or carried out after the latter.

[0129] Furthermore, the lapp modification current applied during the first pulse II is equal to the lapp modification current applied during the second pulse 12.

[0130] Thus, the increase in resistance achieved during the quenching step ET is substantially equal to the reduction in resistance achieved during the crystallization step EC, so that the resistance value Ract remains within the range of the resistance distribution Pprogi, Pprog2, Pprog3, Pprog4 defined around the median value of the resistance distribution Rprogi, Rprog2, Rprog3, Rprog4-

[0131] Performing the two steps ET, EC of process 100 maximizes the maintenance of the resistance value Ract of the phase-change memory cell Cl, C2, C3, C4 within the resistance distribution range Pprogi, Pprog2, Pprog3, Pprog4 defined around the median value of the resistance distribution Rprogi, Rprog2, Rprog3, Rprog4. Thus, the median value of the resistance distribution Rprogi, Rprog2, Rprog3, Rprog4 remains stable during inference cycles while ensuring satisfactory cycle-to-cycle variability of the resistance value Ract of the phase-change memory cell Cl, C2, C3, C4.

[0132] In certain embodiments, during the determination step, a global maximum fusion current and a global minimum amorphous phase current are determined. The global maximum fusion current corresponds to the maximum of the The melting currents are determined for each phase-change memory cell Cl, C2, C3, C4 of the MM memory array. In other words, if a pulse at the overall maximum melting current is applied to all phase-change memory cells Cl, C2, C3, C4 of the MM memory array, then at least partial localized melting of the phase-change material at the interface with the lower electrode will occur on all phase-change memory cells Cl, C2, C3, C4 of the MM memory array. Thus, the resistance values ​​Ract of all phase-change memory cells Cl, C2, C3, C4 of the MM memory array will be modulated.

[0133] The global minimum amorphous phase current corresponds to the minimum of the amorphous phase currents determined for each phase-change memory cell Cl, C2, C3, C4 of the MM memory matrix. In other words, if a pulse at the global minimum amorphous phase current is applied to all the phase-change memory cells Cl, C2, C3, C4 of the MM memory matrix, then at least one phase-change memory cell Cl, C2, C3, C4 of the MM memory matrix will pass into the completely amorphous state.

[0134] To determine the overall minimum amorphous phase current, the conductance, or resistance, of all phase-change memory cells C1, C2, C3, C4 of the MM memory array is modified to increasing resistance values, starting from a crystalline state. This is achieved by applying pulses with a steep downward ramp, a quenching effect, and an increasing modification current to all memory cells. For each resistive state, the occurrence of a minimum threshold voltage MIN V* across all phase-change memory cells of the memory array is evaluated. As long as no minimum threshold voltage MIN Vth is detected, the injection of pulses with a steep downward ramp and a quenching effect at a higher modification current continues.The modification current for which a minimum threshold voltage MIN V* is detected on one or more cells Cl, C2, C3, C4 of the MM memory matrix is ​​defined as the "global minimum amorphous phase current".

[0135] In certain embodiments, during the quenching step ET, the first pulse II at the modification current lapp is applied simultaneously to all phase-change memory cells Cl, C2, C3, C4 of the memory matrix MM, and during the crystallization step EC, the second pulse 12 is applied simultaneously to all phase-change memory cells Cl, C2, C3, C4 of the memory matrix MM. All phase-change memory cells Cl, C2, C3, C4 of the memory matrix MM are therefore subjected at the same pulse. Thus, the resistance value Ract of all the phase-change memory cells Cl, C2, C3, C4 is modified at the same time.

[0136] In certain embodiments, the lapp modification current is greater than or equal to the overall maximum fusion current and strictly less than the overall minimum amorphous phase current. Thus, the lapp modification current is identical for all phase-change memory cells Cl, C2, C3, C4. It is therefore not necessary to know, and thus not to store in memory, the Imelt fusion current, the lamorph amorphous phase current, and the lapp modification current for each phase-change memory cell Cl, C2, C3, C4.

[0137] In some embodiments, the descent ramp of the first pulse II is twice as fast as the descent ramp of the second pulse 12.

[0138] In some embodiments, the phase change current lapp is between the melting current Imelt and 1.2 times the melting current Imelt. Experience shows that 1.2 times the melting current Imelt is always less than the amorphous phase current lamorph. Thus, the resistance value Ract of at least one phase change memory cell Cl, C2, C3, C4 is realized around the median value.

[0139] In certain embodiments, the change current lapp depends on the median value of the conductance distribution 1 / Rprog1, 1 / Rprog2, 1 / Rprog3, 1 / Rprog4, or of the resistance distribution Rprog1, Rprog2, Rprog3, Rprog4, and on the desired resistance distribution range Pprog1, Pprog2, Pprog3, Pprog4*

[0140] In some embodiments, the method 100 includes a read step EL in which a read pulse IL at a read voltage is applied to at least one phase-change memory cell Cl, C2, C3, C4 in order to measure the value of the resistance Ract. The read voltage is not high enough to change the resistance Ract of the phase-change memory cell Cl, C2, C3, C4; that is, the read voltage cannot change the phase of the phase-change material. The read voltage is therefore lower than the threshold voltage Vth. Preferably, the read voltage is lower than the minimum threshold voltage MIN V* of the memory array MM. The read step EL allows the value of the resistance Ract of the phase-change memory cell Cl, C2, C3, C4 to be measured and determined.More specifically, the EL reading stage can accurately measure the exact value of resistance Ract, determining only if the resistance value Ract is within the resistance distribution range Pprogi, Pprog2, Pprog3, Pprog4 defined around the median value of the conductance or resistance distribution Rprogi, Rprog2, Rprog3, Rprog4.

[0141] The EL reading step is part of the modification process 100 in that it corresponds to checking the resistance value obtained Ract.

[0142] The EL reading step is carried out after the ET quenching step and the EC crystallization step have been carried out.

[0143] With an accumulation of inference cycles and an increase in the execution frequency of the quenching ET and crystallization EC steps, the phase-change memory cell Cl, C2, C3, C4 may lose the median value of the conductance distribution 1 / Rprog1, 1 / Rprog2, 1 / Rprog3, 1 / Rprog4, or of the resistance Rprog1, Rprog2, Rprog3, Rprog4. It is therefore important to verify, after performing the modification of the resistance value Ract, that it is within the range of the resistance distribution Pprog1, Pprog2, Pprog3, Pprog4 defined around the median value of the resistance distribution Rprog1 Rprog2, Rprog3, Rprog4. The reading step EL may be performed at a frequency lower than the inference cycle frequency.

[0144] According to one embodiment, the EL reading step is carried out only on at least one phase change memory cell Cl, C2, C3, C4 which has undergone the quenching ET and crystallization EC steps.

[0145] Next, depending on the measured resistance value Ract during the EL reading step, an ERP reprogramming step is performed. The ERP reprogramming step consists of reprogramming the median value of the conductance distribution, or of resistance Rprog1, Rprog2, Rprog3, Rprog4 according to a method known to the person skilled in the art, if the measured resistance value Ract is no longer within the defined range of resistance distributions Pprog1, Pprog2, Pprog3, Pprog4.

[0146] The ERP reprogramming step is similar to the programming steps taking place during the learning phase 200.

[0147] In some embodiments, the phase-change memory cell Cl, C2, C3, C4 is integrated into a neuromorphic circuit having a 1T1R or 1S1R configuration.

[0148] The "1T1R" configuration in a neuromorphic circuit refers to a specific architecture, where "1T" signifies a transistor and "IR" corresponds to the phase-change memory cell Cl, C2, C3, C4. More specifically, the transistor can be a front-end-of-line (FEOL) access transistor. The transistor acts as a switch to control and limit the current flow through the phase-change memory cell Cl, C2, C3, C4. To change the resistance value Ract of the phase-change memory cell Cl, C2, C3, C4, and thus to write a new value, the transistor is activated, allowing an electrical pulse to flow through the phase-change memory cell Cl, C2, C3, C4. More precisely, the greater the current flow, the greater the volume of phase-change material that will be melted during the pulse.This allows for an increase in the conductance distribution range that can be encoded. in the memory cell. However, this leads to a greater risk of losing the median value of the conductance distribution, or resistance Rprogi, Rprog2, Rprog3, Rprog4, and therefore a need for more frequent reprogramming.

[0149] The "1S1R" configuration in a neuromorphic circuit refers to a specific architecture, where "1S" signifies a selector and "IR" corresponds to the phase-change memory cell Cl, C2, C3, C4. The selector can be a BEOL (Back-End-of-Line) selector device. The selector acts as a switch that controls the flow of current through the phase-change memory cell Cl, C2, C3, C4 in response to a switching voltage. When a new value is to be written to the phase-change memory cell Cl, C2, C3, C4, a switching voltage is applied to the 1S1R device. This allows current to flow through the phase-change memory cell Cl, C2, C3, C4. Electrical pulses according to the process are then applied, changing the conductance value of the phase-change memory cell Cl, C2, C3, C4.After writing, the selector becomes insulating again, thus protecting the phase-change memory cell from leakage currents and interference during read operations in the MM memory array. One advantage of the "1S1R" configuration is its ability to significantly increase the overall density of the MM memory array. 1S1R devices are integrated into a crossbar structure, where it is possible to reduce the size of the memory cell to as small as 4F², where F is the smallest size achievable by lithography at a given technology node. This improves the performance of the neuromorphic circuit.

[0150] Although the present invention has been described with reference to specific embodiments, it is evident that modifications and changes can be made to these examples without departing from the general scope of the invention as defined by the claims. In particular, individual features of the various embodiments illustrated / mentioned can be combined in additional embodiments. Therefore, the description and drawings should be considered in an illustrative rather than a restrictive sense.

[0151] It is also evident that all the characteristics described with reference to a process are transposable, alone or in combination, to a device, and conversely, all the characteristics described with reference to a device are transposable, alone or in combination, to a process.

Claims

1. Demands A method for modifying (100) a conductance value (1 / Ract), or respectively a resistance value (Ract), within a range of resistance distributions (Pprog1, Pprog2, Pprog3, Pprog4) defined around a median resistance distribution value (Rprog1, Rprog2, Rprog3, Rprog4), or respectively a conductance value, of at least one phase-change memory cell (Cl, C2, C3, C4), said at least one phase-change memory cell (Cl, C2, C3, C4) being included in a memory array (MA) comprising a plurality of memory cells (Cl, C2, C3, C4), the at least one memory cell (Cl, C2, C3, C4) comprising a lower electrode, an upper electrode, and a phase-change material situated between the lower and upper electrodes, the phase-change material being capable of assuming a crystalline, partially amorphous, or completely amorphous state at an interface with the lower electrode,the process (100) being implemented by a neural network and comprising:, - A determination step in which a melting current (Imelt) and an amorphous phase current (lamorph) are determined for at least one phase-change memory cell (Cl, C2, C3, C4), the melting current (Imelt) corresponding to the current causing at least partial localized melting of the phase-change material at the interface with the lower electrode when applied to at least one phase-change memory cell (Cl, C2, C3, C4), the amorphous phase current (lamorph) corresponding to the current causing the creation of a completely amorphous state at the interface with the lower electrode when applied to at least one phase-change memory cell (Cl, C2, C3, C4); - A tempering step (ET) in which a first pulse (II) at a modification current (lapp) greater than or equal to the melting current (Imelt) and strictly less than the amorphous phase current (lamorph) is applied to at least one phase-change memory cell (C1, C2, C3, C4), the first pulse (II) presenting an upward ramp followed by an abrupt downward ramp having a quenching effect; - A crystallization step (EC) in which a second pulse (12) at the modification current (lapp) is applied to at least one phase change memory cell (Cl, C2, C3, C4), said at least one phase change memory cell (Cl, C2, C3, C4) being identical to the at least one phase change memory cell (Cl, C2, C3, C4) of the quenching step, the second pulse (12) having an upward ramp followed by a gradual downward ramp.

2. Method (100) according to claim 1, wherein the median value of conductance distribution, or respectively resistance (Rprogi, RProg2, Rprog3, Rprog4), as well as the range of conductance distribution, or respectively resistance (Pprogi, Pprog2, Pprog3, PProg4), of at least one phase-change memory cell (Cl, C2, C3, C4) are defined as greater than, respectively less than, a threshold conductance 1 / Rth, respectively threshold resistance (R*), corresponding to a conductance, respectively resistance, of at least one phase-change memory cell (Cl, C2, C3, C4) for which a threshold voltage (V*) is detected.

3. A method according to any one of the preceding claims, wherein the abrupt downward ramp of the first pulse (II) has a duration less than or equal to 30ns.

4. A method (100) according to any one of the preceding claims, wherein the progressive downward ramp of the second pulse (12) has a duration greater than 30ns and preferably greater than or equal to 60ns.

5. Method (100) according to any one of the preceding claims, wherein the modification current (lapp) is between the melting current (Imelt) and 1.2 times the melting current (Imelt).

6. Method (100) according to any one of the preceding claims, further comprising a read step (EL) in which a read pulse (IL) at a read voltage is applied to at least one phase-change memory cell (Cl, C2, C3, C4) in order to measure the value of resistance (Ract) or conductance.

7. Method (100) according to claim 6, wherein a reprogramming step (EPR) of at least one phase-change memory cell (Cl, C2, C3, C4) is performed as a function of the resistance (Ract) or conductance value measured during the reading (EL) step.

8. A method (100) according to any one of the preceding claims, wherein the phase-change material is a chalcogenide material.

9. Method (100) according to any one of the preceding claims, wherein the change current (lapp) depends on the value of the median of conductance distribution, or resistance (Rprogi, Rprog2, Rprog3, Rprog4), and the range of resistance distribution (Pprogi, Pprog2, Pprog3, Pprog4) SOuhaitCC.

10. Method (100) according to any one of the preceding claims, wherein the memory matrix (MM) is a neuromorphic circuit having a 1T1R or 1S1R configuration.

11. Method (100) according to any one of the preceding claims, wherein the neural network is a Bayesian neural network.

12. Neural network implementing, during an inference cycle, the method of modifying (100) a conductance or resistance value (Ract), of at least one phase-change memory cell (Cl, C2, C3, C4) according to any one of the preceding claims.

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