Memory device with memory cell array

Abstract

Memory cell array device. Memory device (100) comprising an array of memory cells (102.1-102.4), each containing M memory elements (106), and a switch (104), the memory cells being addressed by word lines (108), source lines (112), and bit lines (110), wherein: - a first conduction electrode of each switch is coupled to a first electrode of each of the memory elements in one of the memory cells; - each word line is coupled to a control electrode of each switch in one and the same column of memory cells; - each source line is coupled to a second conduction electrode of each switch in one and the same row of memory cells; - each bit line is coupled to a second electrode of one of the memory elements in each memory cell in one and the same column of memory cells. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Memory device with memory cell matrix technical field

[0001] The present description relates generally to the field of electronic devices with memory cell arrays, including in particular resistive memory elements (called RRAM or ReRAM for "Resistive Random-Access Memory" in English) for example based on oxide (of the OxRAM type for "Oxide-based Random-Access Memory" in English) or of metallic electrolyte (of the CBRAM type or "Conductive-Bridging Random-Access Memory" in English), or with magnetoresistive memory elements (called MRAM for "Magnetoresistive Random-Access Memory" in English), or including a phase-change material (called PCM for "Phase-Change Material" in English). Previous technique

[0002] The main block of a memory, or memory device, is generally formed of an array of memory cells, or "bitcells". Each memory cell may include a selection switch, for example at least one selection transistor, allowing the selection and electrical access to the memory cell, and at least one memory element, or memory point, in which information, for example a bit, is stored for the memory cell.

[0003] In an RRAM-type memory cell, each memory element may include a portion of metallic oxide or electrolyte arranged between two electrodes. The document P. Polakowski et al., "Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory applications", 2014 IEEE 6th International Memory Workshop (IMW), Taipei, Taiwan, 2014, pp. 1-4, describes such a configuration of an OxRAM-type memory cell.

[0004] Programming a memory cell can be achieved using a single selection transistor coupled to one of the two electrodes of the memory element or of each memory element of the memory cell. Such a memory cell is called an ITnR, where n corresponds to the number of memory elements in the cell.

[0005] Memory cells are addressed by word lines, bit lines, and source lines. Word lines are coupled to memory cells perpendicular to bit lines so that the desired memory cells can be selected and addressed using word and bit lines.

[0006] The dimensions of a memory element are very small compared to those of a transistor. The storage density achievable by such a memory cell matrix is ​​therefore limited by the transistor dimensions. It is possible to improve the achievable storage density by implementing several distinct memory elements within each memory cell. However, as the number of memory elements per memory cell increases, various design constraints arise, such as those related to the floating nature of nodes (the connection between the memory elements and the selection transistor in each memory cell) other than the one selected during a write operation, the reduced number of memory cells accessible in parallel, or parasitic currents that are proportional to the number of parallel accesses to the memory cells.

[0007] Different memory cell array architectures, called "crossbar" architectures, have been proposed. In these architectures, the selection of one of the memory cells is not performed by a transistor, and the achievable storage density is greater. However, the selection of memory cells for implementing the various read, write, and erase operations is problematic because it involves complex nonlinear components. Summary of the invention

[0008] There is therefore a need to propose a memory device comprising a matrix of memory cells enabling high storage density without the disadvantages of known architectures and without a so-called "crossbar" architecture.

[0009] One embodiment proposes a solution to all or part of the drawbacks of known solutions and proposes a memory device comprising a matrix of memory cells, each memory cell having M memory elements, with M being an integer greater than or equal to 1, and a switch configured to allow or block a current between two conduction electrodes of the switch, the memory cells being addressed by word lines, source lines and bit lines, wherein:

[0010] - a first of the conduction electrodes of each switch is coupled to a first electrode of each of the memory elements of only one of the memory cells;

[0011] - each word line is coupled to a control electrode of each switch of a single column of memory cells;

[0012] - each source line is coupled to a second of the conduction electrodes of each switch of a single row of memory cells;

[0013] - each bit line is coupled to a second electrode of one of the elements memories of each memory cell in a single column of memory cells.

[0014] According to a particular embodiment, each of the memory elements comprises a resistive portion and said memory element is of the OxRAM type, or comprises a solid electrolyte and said memory element is of the CB RAM type, or comprises a magnetoresistive stack and said memory element is of the MRAM type, or comprises a phase change material and said memory element is of the PCM type.

[0015] According to a particular embodiment, the switch of each memory cell comprises at least one MOS transistor, and the control electrode of the switch corresponds to the gate of the MOS transistor and the conduction electrodes of the switch correspond to the source and drain electrodes of the MOS transistor.

[0016] According to a particular embodiment, M bit lines are associated with each of the memory cell columns, the bit lines being different from one column to another.

[0017] According to a particular embodiment, M is between 1 and 16.

[0018] According to a particular embodiment, the memory device further comprises a control circuit configured to apply voltages to each of the bit lines, word lines and source lines.

[0019] According to a particular embodiment, the control circuit is configured to apply, during a write operation in at least one memory element of at least one of the memory cells of one of the memory cell columns:

[0020] - a voltage V Set_sbl on the bit line coupled to said memory element;

[0021] - a voltage V Set_ssl on the source line coupled to the switch of said cell memory ;

[0022] - a voltage V Set_ubl on the bit lines other than that coupled to said element memory ;

[0023] - a voltage V Set_usl on source lines other than that coupled to the switch of said memory cell;

[0024] with V SET_SBL > V set_usl > V set_ubl V set_ssl-

[0025] According to a particular embodiment, in a first configuration:

[0026] - the voltage V Set_sbl is equal to (3-a).VL;

[0027] - the voltage V Set_ssl is equal to 0;

[0028] - the voltage V Set_ubl is equal to VL;

[0029] - the voltage V Set_usl equal to approximately 2. VL;

[0030] or, in a second configuration:

[0031] - the voltage V Set_sbl is equal to approximately (2-a).VL;

[0032] - the voltage V Set_ssl is equal to 0;

[0033] - the voltage V Set_ubl is equal to approximately 0;

[0034] - the voltage V Set_usl is equal to approximately VL;

[0035] with VL corresponding to a value of a limit voltage of no write in said memory element, and a corresponding to a coefficient of uncertainty due to the finite conductance of the switch of said memory cell and to the uncertainty of the conductance state of the M memory elements of said memory cell.

[0036] According to a particular embodiment, during the writing operation, the control circuit is configured to apply, on the word line coupled to the switch of said memory cell, a switching voltage of the switch of said memory cell, and on the word lines other than that coupled to the switch of said memory cell, a blocking voltage of the switches coupled to these word lines.

[0037] According to a particular embodiment, the control circuit is configured to apply, during an erasure operation in at least one memory element of at least one of the memory cells:

[0038] - a voltage V REset_sbl on the bit line coupled to said memory element;

[0039] - a voltage V REset_ssl on the source line coupled to the switch of said memory cell;

[0040] - a voltage V REset_ubl on the bit lines other than that coupled to said element memory ;

[0041] - a voltage V REset_usl on source lines other than that coupled to the switch of said memory cell;

[0042] with V RESET_SSL > V RESET_UBL V RESET_USL > V RESET_SBL-

[0043] According to a particular embodiment, in a first configuration:

[0044] - the voltage V REset_sbl is equal to 0;

[0045] - the voltage V REset_ssl is equal to (3-«).VL ;

[0046] - the voltage V REset_ubl is equal to (2-a).VL;

[0047] - the voltage V REset_usl is equal to (1-a). VL;

[0048] or, in a second configuration:

[0049] - the voltage V REset_sbl is equal to 0;

[0050] - the voltage VREset_ssl is equal to 2.VL;

[0051] - the voltage V RESet_ubl is equal to VL;

[0052] - the voltage V REset_usl is approximately equal to V L.

[0053] According to a particular embodiment, during the erasure operation, the control circuit is configured to apply, on the word line coupled to the switch of said memory cell, a switching voltage of the switch of said memory cell, and on word lines other than that coupled to the switch of said memory cell, a blocking voltage of the switches coupled to these word lines.

[0054] According to a particular embodiment, the control circuit is configured to successively apply, during an operation of reading several memory elements from each memory cell of one of the columns of the matrix, a non-zero voltage VR on each of the bit lines coupled to said memory elements, a zero voltage being applied on the bit line(s) coupled to the other memory elements;

[0055] and the memory device further includes a current reading circuit for currents flowing in the source lines, configured to read these currents at each application of the voltage VR on the bit lines coupled to said memory elements.

[0056] According to a particular embodiment, the control circuit is configured to apply, during a read operation of a memory element of each memory cell of one of the columns of the matrix, a non-zero voltage VR on the bit line coupled to said memory element, a zero voltage being applied on the bit line(s) coupled to the other memory elements;

[0057] and the memory device further includes a circuit for reading currents flowing in the source lines.

[0058] According to a particular embodiment, the memory device further comprises a calculation circuit configured to determine information stored in each of the memory elements read from a conductance value of one of the switches, the value of the voltage VR and the values ​​of the currents flowing in the source lines. Brief description of the drawings

[0059] These features and advantages, as well as others, will be described in detail in the following description of specific examples and embodiments, given by way of non-limiting agreement, in connection with the accompanying figures, among which:

[0060] - [Fig. 1] represents an electrical diagram of part of a cell matrix memories of a memory device according to a particular embodiment;

[0061] - [Fig.2] schematically represents an example of a configuration during a operation writing to memory cells of a memory device according to a particular embodiment;

[0062] - [Fig.3] schematically represents an example of a configuration during a erasure operation in memory cells of a memory device according to a particular embodiment;

[0063] - [Fig.4] schematically represents an example of a configuration during a operation of reading memory cells of a memory device according to a particular embodiment. Description of the implementation methods

[0064] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0065] For the sake of clarity, only the steps and elements necessary for understanding the described embodiments have been shown and are detailed. In particular, various elements (read circuit, row decoder, column decoder, control circuit, etc.) of the memory device are not detailed. A detailed implementation of these elements is within the capabilities of a person skilled in the art using the functional description given below.

[0066] In the various figures, the visible elements are not represented at the same scale relative to each other to facilitate understanding of these figures.

[0067] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without any intervening elements other than conductors, and when referring to two elements connected or coupled, this means that these two elements can be connected or linked via one or more other elements. Furthermore, the term "coupled" is used to denote electrical coupling between elements.

[0068] In the following description, when reference is made to absolute positional qualifiers, such as "front," "back," "top," "bottom," "left," "right," etc., or relative positional qualifiers, such as "above," "below," "superior," "inferior," etc., or to orientational qualifiers, such as "horizontal," "vertical," etc., unless otherwise specified, reference is made to the orientation of the figures in a normal operating position of the device. However, these terms do not imply the actual position and orientation of the device during its use.

[0069] Throughout this document, the terms "row" and "column" are used with reference to the configurations shown in the figures, a row referring to a horizontal orientation and a column referring to a vertical orientation. Alternatively, these terms may be reversed depending on the actual orientation of the memory device, with rows then corresponding to columns, and columns then corresponding to rows.

[0070] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0071] An electrical diagram of an example of a memory device 100 according to a particular embodiment is described below in relation to [Fig.1].

[0072] The memory device 100 comprises several memory cells arranged side by side, for example in the same plane, in the form of a matrix. In [Fig. 1], four memory cells 102.1, 102.2, 102.3, and 102.4 are shown. Memory cells 102.1 and 102.2 are in the same row of the matrix, and memory cells 102.3 and 102.4 are in the same row of the matrix, different from the one containing memory cells 102.1 and 102.2. Memory cells 102.1 and 102.3 are in the same column of the matrix, and memory cells 102.2 and 102.4 are in the same column of the matrix, different from the one containing memory cells 102.1 and 102.3. The total number of rows and columns in the matrix depends in particular on the desired storage capacity for the memory device 100.

[0073] The memory cells of the device 100 are of type 1T-MR, with M an integer greater than or equal to 1, and for example between 2 and 16 or advantageously between 2 and 8.

[0074] Each memory cell of the device 100 includes a switch 104, or selector, corresponding, for example, to an N-type or P-type MOS selector transistor, or a transmission gate formed by an NMOS transistor and a PMOS transistor. Alternatively, other types of switches 104 are possible, allowing the selection of one or more memory cells during a write, erase, or read operation.Each switch 104 is configured to open or close a conduction path formed between the first and second conduction electrodes of the switch 104 (corresponding to the source and drain electrodes when the switch 104 corresponds to a MOS transistor, the conduction path being formed from the drain electrode to the source electrode in the case of an NMOS transistor, or formed from the source electrode to the drain electrode in the case of a PMOS transistor), that is, to allow or prevent the flow of current between its conduction electrodes. This current flow is controlled by applying a sufficient voltage to a control electrode of the switch 104 (corresponding to the gate when the switch 104 corresponds to a MOS transistor).When switch 104 corresponds to an NMOS transistor, the voltage applied to its gate is high enough to turn the NMOS transistor on, and when switch 104 corresponds to a PMOS transistor, the voltage applied to its gate is low enough to turn the PMOS transistor on. When switch 104 corresponds to a transmission gate, the control voltages applied to its inputs are... commands must be sufficiently different from each other and such that the transmission gate becomes passable.

[0075] Each memory cell of the device 100 comprises M memory elements 106, for example resistive RRAM-type elements, in which information is intended to be stored. For example, each memory element 106 may be of the OxRAM type and comprise a resistive portion including HfO2 or any other suitable oxide for storing information by forming a conductive filament within it. This resistive portion may be arranged between two electrodes, each comprising, for example, a first portion of Ti, TiN, or TaN, positioned against the resistive portion, and at least a second portion comprising, for example, tungsten, TiN, copper, or cobalt, serving for the electrical interconnection of the memory element 106.According to one embodiment, the memory element 106 may optionally include a portion of getter material based on titanium, tantalum, hafnium, or any other material having an electrochemical affinity for oxygen when the memory element 106 is of the OxRAM type. Such a portion of getter material can contribute to the creation of one or more electrically conductive filaments in the resistive portion.

[0076] Alternatively, each memory element 106 may be of another type, for example CBRAM, by replacing the constituent parts of these OxRAM memory elements with their equivalents in CBRAM memory elements, namely, in particular, the lower and upper electrodes with a chemically inert electrode and a chemically active electrode, respectively, and the resistive layer with a solid electrolyte. According to another example, each memory element 106 may be of the MRAM type, by replacing the resistive layer with a magnetoresistive stack comprising a tunnel oxide layer, for example based on MgO, arranged between two magnetic layers, for example based on cobalt. According to yet another example, each memory element 106 may be of the PCM type, by replacing the resistive layer with a phase-change material layer.

[0077] In the example shown in [Fig.1], each memory cell 102.1-102.4 has several memory elements 106, four of these memory elements 106 being shown for each of the memory cells.

[0078] In each memory cell of the device 100, a first electrode of each memory element 106 is coupled to a first conduction electrode of the cell's switch 104. For example, when the switch 104 corresponds to a MOS transistor, the first conduction electrode of the switch 104 corresponds to the source or drain electrode of the transistor (for example, the drain electrode in the case of an NMOS transistor). In each memory cell, the first electrode of each memory element 106 of the memory cell and the first The conduction electrodes of switch 104 of the memory cell are coupled to a central node 107 of the memory cell. The central nodes 107 of the memory cells are not electrically connected to each other, either by row or by column. In other words, the first conduction electrode of each switch 104 is coupled to the first electrode of each of the memory elements 106 of only one of the memory cells.

[0079] The memory cells of the device 100 are addressed by word lines 108, bit lines 110, and source lines 112. Each word line 108 is coupled to the control electrode of the switches 104 (the gate in the case of switches 104 corresponding to MOSFET transistors) that are part of a single column of memory cells. When the switches 104 correspond to transmission gates, two word lines 108 are associated with each column of memory cells, and complementary control signals are sent to these lines for reception at the control inputs of the transmission gates. Furthermore, each source line 112 is coupled to the second conduction electrode of the switches 104 (for example, the source in the case of switches 104 corresponding to NMOS transistors) that are part of a single row of memory cells.Finally, each of the bit lines 110 is coupled to a second electrode of the memory element 106 or of a single one of the memory elements 106 of each memory cell in a single column of memory cells.

[0080] The number of bit lines 110 associated with each column of memory cells depends on the number of memory elements 106 present in each memory cell. For example, when each memory cell has a single memory element 106, a single bit line 110 can be associated with each column of memory cells and coupled to a second electrode of the memory element 106 in each of the memory cells in that column. More generally, when each memory cell has M memory elements 106, M bit lines 110 can be associated with each column of memory cells, and each of these can be coupled to a second electrode of one of the M memory elements 106 in each of the memory cells in that column. In the example shown in [Fig. 1], four memory elements 106 are shown for each of the memory cells 102.1-102.4, and four bit lines 110 are represented for each of the memory cell columns, such that each of these bit lines 110 is coupled to the second electrode of one of the memory elements 106 of each memory cell and distinct from those to which the other bit lines 110 associated with that memory cell column are coupled.

[0081] The device 100 also includes a control circuit (not shown in the figures) for voltages applied to each of the bit lines 110, word lines 108 and source lines 112. This circuit is capable of applying the appropriate voltages to these lines for the implementation of write (“set”), erase (“reset”) and read (“read”) operations in the memory elements 106 of the memory cells.

[0082] Figure 2 schematically represents an example of the configuration of the device 100 during a write operation in memory cells of the memory device 100. In this example, each of the memory cells, referenced 102.1 to 102.6 in Figure 2, comprises two memory elements 106 designated by the letters "A" to "L". Memory cells 102.1 and 102.2 are part of the first row of the matrix, memory cells 102.3 and 102.4 are part of the second row of the matrix, and memory cells 102.5 and 102.6 are part of the third row of the matrix. In addition, memory cells 102.1, 102.3 and 102.5 are part of a first column of the matrix, and memory cells 102.2, 102.4 and 102.6 are part of a second column of the matrix.

[0083] In the example of [Fig.2], the switches 104 correspond to NMOS transistors whose gates are coupled to the word lines 108, whose sources are coupled to the source lines 112, and whose drains are coupled to the memory elements 106, forming the central connection nodes 107 of the memory cells.

[0084] In the example of [Fig.2], the writing is intended to be carried out in only one of the memory elements 106 of each of the two memory cells 102.3 and 102.5 belonging to the same column and to two different rows of the matrix, these memory elements 106 being those designated by the letters "E" and "F".

[0085] To perform a write operation, a voltage V set_sbl can be applied to the bit line(s) 110 coupled to the memory element(s) 106 in which the write operation is intended to be performed. In the example in [Fig. 2], the voltage V set_sbl is applied to the bit line 110 coupled to the memory elements 106 designated by the letters "D", "E", and "F". Furthermore, a voltage V set_ubl can be applied to any other bit line(s) 110 coupled to the other memory elements 106 in the same column but in which the write operation is not intended to be performed. In the example in [Fig. 2], the voltage V set_ubl is applied to the bit line 110 coupled to the memory elements 106 designated by the letters "A", "B", and "C". Finally, the same voltage, for example zero, can be applied to the bit lines 110 associated with each of the columns not involved in the write operation.In the example of [Fig.2], a tension. null is applied to the bit lines 110 coupled to the memory elements 106 designated by the letters "G", "H", "I", "J", "K" and "L".

[0086] Furthermore, for this write operation, a voltage capable of turning on a switch 104 can be applied to the word line 108 connected to the switches 104 of the column to which the memory cell(s) in which the write operation is to be performed belong. In the example of [Fig. 2], such a voltage V is applied to the word line 108 connected to the switches 104 of the first column, to which memory cells 102.1, 102.3, and 102.5 belong. A voltage that turns off the switches 104 can be applied to the other word lines 108 connected to the switches 104 of the memory cells in the columns not involved in the write operation. In the example of [Fig.2], a zero voltage is applied to word line 108 coupled to memory cells 102.2, 102.4 and 102.6 of the second column.

[0087] Finally, for this write operation, a voltage VSEt_ssl can be applied to the source line(s) 112 connected to the switch(s) 104 of the memory cell(s) in which the write operation is to be performed. In the example of [Fig. 2], the voltage VSet_ssl is applied to the source lines 112 connected to the switches 104 of the lines to which memory cells 102.3, 102.4, 102.5, and 102.6 belong. In addition, a voltage VSet_usl can be applied to the source lines 112 connected to the switches 104 of the memory cells 102 of the lines not involved in the write operation. In the example of [Fig.2], the voltage VSet_usl is applied to the source line 112 coupled to the switches 104 of the memory cells 102.1 and 102.2 of the first line.

[0088] For the implementation of the desired write operation, the voltages V Set_sbl -, V set_ssl, v setjubl and V set_usl can be such that V set_sbl > U set_usl > V setjubl > V set_ssl- The choice of the values ​​of these voltages can be made such that a sufficiently large voltage is applied to the memory element(s) 106 in which the write operation is intended to be carried out, while limiting the absolute voltage seen by the other memory elements 106 and which is less than a value VL corresponding to a value of a limit voltage of no write in a memory element 106, that is to say the value below which a write does not occur with sufficient certainty to ensure the operation of the memory.

[0089] In a first configuration allowing the maximum write voltage seen by the memory element(s) 106 in which the write operation is intended to be performed, the voltage values ​​applied to the word lines 108 and the bit lines 110 belonging to the column(s) containing the memory elements to be written and the source lines 112 can be, as a first approximation, such as:

[0090] - the voltage V Set_sbl is equal to (3-a).VL;

[0091] - the voltage V Set_ssl is equal to 0;

[0092] - the voltage V Set_ubl is equal to VL;

[0093] - the voltage V Set_usl is equal to approximately IN L.

[0094] a corresponds to a coefficient of uncertainty due to the uncertainty on the voltage of the nodes 107 due to the finite conductance of the switch 104 and to the conductance state, a priori unknown, of the memory elements 106 connected to this node 107.

[0095] The values ​​of the above voltages and of the coefficient a may vary and may be determined by the simulation implementation.

[0096] For example, considering switches 104 formed by NMOS transistors in 22 nm technology, with a supply voltage of the memory cell matrix equal to 1.8 V, these voltages can be for example: V Set_sbl = 1.7 V; V SET_SSL = 0 V; V SETJJBL = 0.7 V; V SET_USL = 1.35 V.

[0097] In a second configuration allowing for the minimization of parasitic currents in the memory element(s) 106 in which the write operation is not intended to be performed and belonging to a memory cell 102 comprising a memory element intended to be written, in order to be able to measure more precisely the write current used, the values ​​of the voltages applied to the word lines 108, and the bit lines 110 belonging to the column(s) containing the memory elements to be written and the source lines 112 may be such as:

[0098] - the voltage V Set_sbl is equal to (2-a).VL;

[0099] - the voltage V SEt_ssl is equal to 0;

[0100] - the voltage V Set_ubl is equal to approximately 0;

[0101] - the voltage V Set_usl is equal to approximately V L.

[0102] For example, considering switches 104 formed by NMOS transistors in 22 nm technology, with a supply voltage of the memory cell array equal to 1.8 V, these voltages can be for example: V set_sbl = 1.1 V ; V SET_SSL = 0 V ; V SET_UBL = 0 V ! V SET_USL = 0.7 V.

[0103] In [Fig. 2], which represents the implementation of a write operation in the memory elements 106 designated by the letters "E" and "F", the solid arrows correspond to the write currents flowing between the bit line 110 coupled to the memory elements "E" and "F" and the source lines 112 coupled to the memory cells 102.3 and 102.5, passing through the memory elements "E" and "F" and thus writing the memory state of these elements to a high state. The dashed arrows correspond to the parasitic currents flowing in certain switches 104 and memory elements 106 that are not intended to change memory state. These parasitic currents are due in particular to the different voltages applied to the bit lines 110 associated with the memory cell column 102 to which the memory elements 106 belong, in which the write operation is intended to be implemented.

[0104] [Fig.3] schematically represents an example of the configuration of device 100 during an erasure operation in memory cells of memory device 100. As in the example of [Fig.2], only two memory elements 106 are shown for each of the memory cells referenced 102.1 to 102.6, and the switches 104 correspond to NMOS transistors.

[0105] In the example of [Fig.3], the erasure is intended to be carried out in only one of the memory elements 106 of each of two memory cells 102.3 and 102.5 belonging to the same column and to two different rows of the matrix, these memory elements 106 being those designated by the letters "E" and "F".

[0106] To perform this erasure operation, a voltage VRES Et_sbl can be applied to the bit line(s) 110 coupled to the memory element(s) 106 in which the erasure operation is to be performed. In the example of [Fig. 3], the voltage VRES Et_sbl is applied to the bit line 110 coupled to the memory elements 106 designated by the letters "D", "E", and "F". In addition, a voltage VREset_ubl can be applied to any other bit lines 110 coupled to the other memory elements 106 of the memory cells 102 in which the erasure operation is to be performed. In the example of [Fig.3], the voltage V RES et_ubl is applied to the bit line 110 coupled to the memory elements 106 designated by the letters "A", "B" and "C".Finally, the same voltage, for example zero, can be applied to the bit lines coupled to the memory elements 106 of the memory cells 102 in each of the columns not involved in the erasure operation. In the example of [Fig. 3], a zero voltage is applied to the bit lines 110 coupled to the memory elements 106 designated by the letters "G", "H", "I", "J", "K" and "L".

[0107] Furthermore, for this erasure operation, a voltage capable of turning on a switch 104 can be applied to the word line 108 connected to the switches 104 of the column to which the memory cell(s) 102 belong in which the erasure operation is to be performed. In the example of [Fig. 3], such a voltage V is applied to the word line 108 connected to the switches 104 of the first column to which memory cells 102.1, 102.3, and 102.5 belong. A switching voltage for the switches 104 can be applied to the other word lines 108 connected to the switches 104 of the memory cells 102 in the columns not involved in the erasure operation. On In the example of [Fig.3], a zero voltage is applied to word line 108 coupled to memory cells 102.2, 102.4 and 102.6 of the second column.

[0108] Finally, for this erasure operation, a voltage VRES Et_ssl can be applied to the source line(s) 112 connected to the switch(s) 104 of the memory cell(s) in which the erasure operation is to be performed. In the example of [Fig. 3], the voltage VRES Et_ssl is applied to the source lines 112 connected to the switches 104 of the lines to which memory cells 102.3, 102.4, 102.5, and 102.6 belong. In addition, a voltage VRES et_usl can be applied to the source lines 112 connected to the switches 104 of the memory cells 102 of the lines not involved in the erasure operation. In the example of [Fig.3], the voltage V RES et_usl is applied to the source line 112 coupled to the switches 104 of the memory cells 102.1 and 102.2 of the first line.

[0109] In [Fig. 3], the solid arrows represent the erase currents flowing between the source lines 112 coupled to memory cells 102.3 and 102.5 and the bit line 110 coupled to memory elements "E" and "F", passing through memory elements "E" and "F" in the opposite direction to the write currents described previously, thus changing the memory state of these elements, switching them to a low state. The dashed arrows represent the parasitic currents flowing, in particular, in the switch 104 and the memory elements 106 of memory cell 102.1, which is not involved in the erase operation. These parasitic currents are due in particular to the different voltages applied on the bit lines 110 associated with the column of memory cells 102 to which belong the memory elements 106 in which the erasure operation is intended to be implemented.Furthermore, in the example described, the parasitic currents flowing through memory elements B and C also contribute to the erasure of cells E and F.

[0110] For the implementation of the desired erasure operation, the voltages VRES et_sbl , V RES ET-SSL, V RES et_ubl and V RES et_usl can be such that V RES ET_S SE > V RES ET_U B l> V res et_u sl>V res et_s b l- The choice of the values ​​of these voltages can be made such that a sufficiently large voltage is applied to the memory element(s) 106 in which the erasure operation is intended to be carried out, while limiting the absolute voltage seen by the other memory elements 106 and which is less than a value VL corresponding to a value of a limit voltage of no write in a memory element 106, that is to say the value below which a write or an erasure does not occur with sufficient certainty to ensure the operation of the memory.

[0111] In a first configuration allowing the erasure voltage seen by the memory element(s) 106 in which the erasure operation is intended to be performed to be maximized, the voltage values ​​applied to the word lines 108, and the bit lines 110 belonging to the column(s) containing the memory elements to be erased and the source lines 112 may be such that:

[0112] - the voltage V RES et_sbl is equal to 0;

[0113] - the voltage V RES ET_SSE is equal to (3-a). VL ;

[0114] - the voltage V RES et_ubl is equal to (2-a). VL ;

[0115] - the voltage V RES et_usl is equal to approximately (1-a). V L.

[0116] a corresponds to a coefficient of uncertainty due to the uncertainty on the voltage of the nodes 107 due to the finite conductance of the switch 104 and to the conductance state, a priori unknown, of the memory elements 106 connected to this node 107.

[0117] For example, considering switches 104 formed by NMOS transistors in 22 nm technology, with a supply voltage of the memory cell matrix equal to 1.8 V, these voltages can be for example: V RES et_sbl = 0 V ; V RES ET_SSL = 1.8 V ; V REs ET_UBL = 1.2 V ; V RE$ ET_USL = 0.5 V.

[0118] In a second configuration allowing for minimization of leakage currents in the memory element(s) 106 not involved in the erasure operation, the bit lines 110 and the source lines 112 may be such that:

[0119] - the voltage V REset_sbl is equal to 0;

[0120] - the voltage V REset_ssl is equal to 2.VL;

[0121] - the voltage V RESet_ubl is equal to VL;

[0122] - the voltage V REset_usl is approximately equal to V L.

[0123] For example, considering switches 104 formed by NMOS transistors in 22 nm technology, with a supply voltage of the memory cell matrix equal to 1.8 V, these voltages can be for example: V RES et_sbl = 0 V ; V RES ET_SSL = 1.4 V ; V RE$ ET_UBL = 0.7 V ; V RE$ ET_USL = 0.7 V.

[0124] Fig. 4 schematically represents an example of the configuration of device 100 during a memory cell read operation of memory device 100. As in the example of Figures 2 and 3, only two memory elements 106 are shown for each of the memory cells referenced 102.1 to 102.6, and the switches 104 correspond to NMOS transistors.

[0125] In the example of [Fig.4], the reading is intended to be carried out in only one of the memory elements 106 of each of the memory cells 102.1, 102.3 and 102.5 belonging to the same column of the matrix, these memory elements 106 being those designated by the letters "D", "E" and "F" on [Fig.4].

[0126] To perform this read operation, a non-zero voltage VR is applied to the bit line 110 coupled to the memory elements 106 to be read, and a zero voltage is applied to the bit line(s) coupled to the other memory elements 106. The value of the voltage VR is chosen to be sufficiently low so as not to trigger writing to the memory elements 106. For example, the value of the voltage VR can be equal to 0.2 V.

[0127] Furthermore, to perform this read operation, a voltage capable of turning on a switch 104 is applied to the word line 108 connected to the switches 104 of the column to which the memory cell(s) 102 belong for which the read operation is to be performed. In the example of [Fig. 4], such a voltage V is applied to the word line 108 connected to the switches 104 of the first column, to which memory cells 102.1, 102.3, and 102.5 belong. A switching voltage, for example zero, is applied to the other word lines 108 connected to the switches 104 of the memory cells 102 in the columns not involved in the erase operation. In the example of [Fig.4], a zero voltage is applied to word line 108 coupled to memory cells 102.2, 102.4 and 102.6 of the second column.

[0128] Finally, for this reading operation, a zero voltage is applied to the source lines 112, and the current passing through the source lines 112 is measured.

[0129] In [Fig. 4], the solid arrows represent the read currents flowing between the bit line 110 coupled to the read memory elements 106 and each of the source lines 112. The current levels obtained on the different source lines 112 represent the information stored in the read memory elements 106. To perform the reading of these currents, the memory device 100 may include a read circuit, not shown in [Fig. 4]. In addition, the dashed arrows represent the leakage currents flowing through the other memory elements 106 in the column (memory elements "A", "B", and "C" in [Fig. 4]).

[0130] Thus, the readings carried out in the different memory cells of the column read can be carried out in parallel with each other.

[0131] A first way of performing this reading operation can consist of implementing, for all the memory cells in the same column of the matrix, a grouped read of several memory elements 106 from each of the memory cells. Knowing the value of the conductance yr of each of the switches 104 (this conductance yT being considered identical for all the switches 104), and from the currents 11 measured in the lines of Source 112, by successively applying the voltage VR to each of the bit lines coupled to the memory elements intended to be read (and leaving a zero voltage on the other bit lines), it is possible to calculate the memory states of the memory elements 106 by calculating the conductances _ yTxt of each memory element yi ~ 106 with % _ , with i and j between 1 and M the number of memory elements 106 per memory cell 102. Such a reading allows to determine precisely, in a grouped manner, the conductance of all the M memory elements 106 of each memory cell of the same column of the matrix.

[0132] A second way of performing this reading operation can consist of implementing, for all the memory cells in the same column of the matrix, an individual approximate read of a memory element 106 from each of the memory cells. Knowing the value of the conductance yr of each of the switches 104 (this conductance yT being considered identical for all the switches 104), and from the currents 1T measured in the source lines 112 by applying the voltage VR to the bit line coupled to the memory elements intended to be read (and leaving a zero voltage on the other bit lines), it is possible to calculate the memory states of the memory elements 106 by calculating the conductances ,, _ II of each memory element 106. This reading is all the more vR more precise than the sum of the conductances of the memory elements 106 of a memory cell is small compared to the conductance yT Such a reading allows to read approximately one memory element 106 of each memory cell of the same column simultaneously.

[0133] The voltage values ​​given in the examples above may differ from those indicated. Other voltage levels may be used, for example, to adjust the resulting parasitic current levels. Furthermore, the finite conductance of the transistor and the uncertainty in the resistive state of the devices may be taken into account to optimize the applied voltage values. In addition, it is possible to exploit the resulting parasitic conductance, for example, to avoid current saturation in the transistor (nonlinear effect) and to prevent a collapse of the conductance, dynamic or overall, when a large current flows through the transistor. Finally, in the read operation example described above, the read currents are obtained on the source lines 112. Other read variants are possible.

[0134] In these different operations, a column of memory cells 102 is active.

[0135] Thanks to the architecture of the memory cell matrix 102 of the device 100, all the central nodes 107 formed, in each memory cell 102 belonging to the active column, at the connection point of the first conduction electrode of the switch 104 with the first electrode of each of the M memory elements 106 of the memory cell are controllable via the electrical potentials applied on the source lines 112.

[0136] Furthermore, considering a memory cell matrix comprising N rows of memory cells 102, and therefore iV source rows 112, N memory cells are thus accessible simultaneously in parallel, for writing, erasing and reading.

[0137] Furthermore, the values ​​of the parasitic currents flowing in the memory cells 102 during write, erase or read operations are independent of the number of memory cells being subjected to these operations.

[0138] Furthermore, considering a memory cell array 102, each comprising M memory elements 106 coupled to a switch 104, it can be advantageous to minimize the value of M while ensuring sufficient conductance and saturation current of the switch 104 for writing to the memory elements 106, and a desired storage density. Indeed, the larger M is, the greater the potential leakage currents, which can reduce the energy efficiency of the cell and constrain the peripheral electronics of the array. The value of M can therefore be chosen to ensure that the implemented write operations do not disturb the other memory elements 106 coupled to the switch 104. In addition, a large value of M can reduce the wasted area between the switches 104.

[0139] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0140] Finally, the practical implementation of the described examples of realization and variants is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Memory device (100) comprising a memory cell array (102.1-102.6), each memory cell (102.1-102.6) having M memory elements (106), with M being an integer greater than or equal to 1, and a switch (104) configured to allow or block current between two conduction electrodes of the switch (104), the memory cells (102.1-102.6) being addressed by word lines (108), source lines (112) and bit lines (110), wherein: - a first of the conduction electrodes of each switch (104) is coupled to a first electrode of each of the memory elements (106) of only one of the memory cells (102.1-102.6); - each word line (108) is coupled to a control electrode of each switch (104) of a single column of memory cells (102.1-102.6); - each source line (112) is coupled to a second of the conduction electrodes of each switch (104) of a single row of memory cells (102.1-102.6); - each bit line (110) is coupled to a second electrode of one of the memory elements (106) of each memory cell (102.1-102.6) of a single column of memory cells (102.1-102.6).

2. Memory device (100) according to claim 1, wherein each of the memory elements (106) comprises a resistive portion and said memory element (106) is of the OxRAM type, or comprises a solid electrolyte and said memory element (106) is of the CBRAM type, or comprises a magnetoresistive stack and said memory element (106) is of the MRAM type, or comprises a phase change material and said memory element (106) is of the PCM type.

3. A memory device (100) according to claim 1 or 2, wherein the switch (104) of each memory cell (102.1-102.6) comprises at least one MOS transistor, and wherein the control electrode of the switch (104) corresponds to the gate of the MOS transistor and the conduction electrodes of the switch (104) correspond to the source and drain electrodes of the MOS transistor.

4. Memory device (100) according to any one of the preceding claims, wherein M bit lines (110) are associated with each of the memory cell columns (102.1-102.6), the bit lines (110) being different from one column to another.

5. Memory device (100) according to any one of the preceding claims, wherein M is between 1 and 16.

6. Memory device (100) according to any one of the preceding claims, further comprising a control circuit configured to apply voltages to each of the bit lines (110), word lines (108) and source lines (112).

7. Memory device (100) according to claim 6, wherein the control circuit is configured to apply, during a write operation in at least one memory element (106) of at least one of the memory cells (102.3, 102.5) of one of the memory cell columns (102.1-102.6): - a voltage V Set_sbl on the bit line (110) coupled to said memory element (106); - a voltage V Set_ssl on the source line (112) coupled to the switch of said memory cell (102.3, 102.5); - a voltage V setjubl on the bit lines (110) other than that coupled to said memory element (106); - a voltage V Set_usl on the source lines (112) other than that coupled to the switch (104) of said memory cell (102.3, 102.5); with V SET_SBL > V SET_USL > V SETJUBL V SET_SSL-

8. Memory device (100) according to claim 7, wherein, in a first configuration: - the voltage V Set_sbl is equal to (3-a).VL; - the voltage V Set_ssl is equal to 0; - the voltage V setjubl is equal to VL; - the voltage V Set_usl is equal to approximately 2.VL; or wherein, in a second configuration: - the voltage V Set_sbl is equal to approximately (2-a).VL; - the voltage V Set_ssl is equal to 0; - the voltage V Set_ubl is equal to approximately 0; - the voltage V Set_usl is equal to approximately VL; with VL corresponding to a value of a limit voltage of no writing in said memory element (106), and a corresponding to a coefficient of uncertainty due to the finite conductance of the switch (104) of said memory cell (102.3, 102.5) and to the uncertainty of the conductance state of the M memory elements (106) of said memory cell (102.3, 102.5).

9. Memory device (100) according to claim 7 or 8, wherein, during the write operation, the control circuit is configured to apply, on the word line (108) coupled to the switch (104) of said memory cell (102.3, 102.5), a switching voltage of the switch (104) of said memory cell (102.3, 102.5), and on the word lines (108) other than that coupled to the switch (104) of said memory cell (102.3, 102.5), a switching voltage of the switches (104) coupled to these word lines (108).

10. Memory device (100) according to any one of claims 6 to 9, wherein the control circuit is configured to apply, during an erase operation in at least one memory element (106) of at least one of the memory cells (102.3, 102.5): - a voltage V RE Set_sbl on the bit line (110) coupled to said memory element (106); - a voltage V RES et_ssl on the source line (112) coupled to the switch (104) of said memory cell (102.3, 102.5); - a voltage V RES et_ubl on the bit lines (110) other than that coupled to said memory element (102.3, 102.5); - a voltage V RES et_usl on the source lines (112) other than that coupled to the switch (104) of said memory cell (102.3, 102.5); with V REs Et_s sl > V res et_u b V RE$ EE_E sl > V RE$ Et_s b l-

11. Memory device (100) according to claim 10, wherein, in a first configuration: the voltage V RESet_sbl is equal to 0; the voltage V beset_ssl is equal to (3-a). VL ; the voltage V besetjjbl is equal to (2-a).VL ; the voltage Vbesetjjsl is equal to (la).VL ; or in which, in a second configuration: - the voltage V beset_sbl is equal to 0 ; the voltage V besetjjsl is equal to 2. VL ; the voltage V besetjjbl is equal to VL ; - the voltage V besetjjsl is approximately equal to V L.

12. Memory device (100) according to claim 10 or 11, wherein, during the erasure operation, the control circuit is configured to apply, on the word line (108) coupled to the switch (104) of said memory cell (102.3, 102.5), a switching voltage of the switch (104) of said memory cell (102.3, 102.5), and on the word lines (108) other than that coupled to the switch (104) of said memory cell (102.3, 102.5), a switching voltage of the switches (104) coupled to these word lines (108).

13. A memory device (100) according to any one of claims 6 to 12, wherein the control circuit is configured to successively apply, during a read operation of several memory elements (106) of each memory cell (102.1, 102.3, 102.5) of one of the columns of the matrix, a non-zero voltage Vr on each of the bit lines (110) coupled to said memory elements (106), a zero voltage being applied on the bit line(s) (110) coupled to the other memory elements (106); and further comprising a current reading circuit for currents flowing in the source lines (112), configured to read these currents at each application of the voltage VR to the bit lines (110) coupled to said memory elements (106).

14. Memory device (100) according to any one of claims 6 to 12, wherein the control circuit is configured to apply, during a read operation of a memory element (106) of each memory cell (102.1, 102.3, 102.5) of one of the columns of the matrix, a non-zero voltage VR on the bit line (110) coupled to said memory element (106), a zero voltage being applied to the bit line(s) (110) coupled to the other memory elements (106); and further comprising a circuit for reading currents flowing in the source lines (112).

15. Memory device (100) according to claim 13 or 14, further comprising a calculation circuit configured to determine information stored in each of the memory elements (106) read from a conductance value of one of the switches (104), the value of the voltage VR and the values ​​of the currents flowing in the source lines (112).

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