Electronic circuit for implementing a Bayesian neural network

Abstract

Electronic circuit for implementing a Bayesian neural network The invention relates to an electronic circuit (10) for implementing a Bayesian neural network, comprising bit, source and word lines;and - at least one primary branch (15), each comprising a primary cell (30) connected between source and bit lines and including a primary memory component (32) and a primary switch (34) connected in series, - at least one secondary branch (20), each comprising a secondary cell (50) connected between source and bit lines and including a secondary memory component (52) and a secondary switch (54) connected together, - an accumulation device (25) configured to accumulate a total quantity being the sum of a primary quantity of charges from a primary cell and a secondary quantity of charges from a secondary cell, the primary and secondary quantities being accumulated independently of each other. Figure for the abstract: Figure 1;

Description

Title of the invention: Electronic circuit for implementing a Bayesian neural network

[0001] The present invention relates to an electronic circuit for the implementation of a Bayesian neural network.

[0002] The invention then relates to the field of electronic circuits adapted for the implementation, in particular the inference, of neural networks, in particular Bayesian neural networks.

[0003] Bayesian networks are particularly well-suited for security applications, such as healthcare or autonomous driving. One of the strengths of these networks is their ability to quantify the uncertainty of the results based on the input data. In the example of a classifier, once training is complete, the dispersion of the results allows us to identify two types of uncertainty: either the classification is unclear (noisy data or the inputs correspond to the characteristics of several classes simultaneously), or the classification is unknown.

[0004] Neural networks are generally classified into two families: deterministic neural networks, which provide a deterministic output for a given input; and Bayesian neural networks, also called probabilistic neural networks, which are based on Bayesian deep learning models and encode synaptic parameters, including synaptic weights, using probability distributions.

[0005] In deterministic neural networks, the weights are real numbers, and the output of each neuron is the weighted sum of its inputs, to which an activation function is then applied.

[0006] Instead of choosing fixed weights for training, Bayesian neurons sample their weights from distributions. Rather than using any distribution, Gaussian (or normal) distributions have the advantage of simplifying the formulation and evaluation of a Bayesian model by using the properties of Gaussian random variables.

[0007] To generate a Gaussian distribution, a first approach is to generate this distribution from a multitude of memory components, such as oxide-based resistive random access memory (OxRAM). Each sample of the Gaussian is then obtained by programming a respective memory component. This first approach is described, for example, in the article "In situ learning using intrinsic memristor variability". via Markov chain Monte Carlo sampling” by Dalgaty et al., published in Nature electronics in 2021, as well as in the article “Bringing uncertainty quantification to the extreme-edge with memristor-based Bayesian neural networks” by Bonnet et al., published in Nature communications in 2023.

[0008] However, according to this first approach, the hardware implementation of the Bayesian neural network generates a large surface area electronic circuit since a memory is required for each sample of the Gaussian distribution.

[0009] A second approach to generating the Gaussian distribution is to store the main properties of the Gaussian distribution, namely its mean value and standard deviation, in memory components, and then to perform read operations with these components to generate random values ​​representative of this Gaussian distribution.

[0010] According to this second approach, document EP4 174724B1 describes a synapse circuit for a Bayesian neural network, the circuit comprising a first resistive memory device coupling a first voltage rail to a first terminal of a capacitor, the first terminal of the capacitor being coupled to a second voltage rail via a variable conductance; and a second resistive memory device coupling a third voltage rail to a first output line of the synapse circuit, a second terminal of the capacitor being coupled to a terminal of the second resistive memory device.

[0011] For the generation of a random value of the Gaussian distribution, in the form of a current signal on an output line of the synapse circuit, this document describes programming the first resistive memory device to have a first level of conductance; programming the second resistive memory device to have a second level of conductance; and applying a voltage to the first voltage rail in order to generate a current signal on the output line.

[0012] However, with such a synapse circuit, the capacitor between the first and second resistive memory devices induces a certain correlation between the two devices, and thereby a problematic dependence between the mean value and the standard deviation of the generated distribution. Furthermore, document EP 4 174 724 B1 proposes exploiting the thermal noise of the first resistive memory device as the main source of variability, but does not provide a solution for the case where this same memory device is subject to random telegraph noise.

[0013] The aim of the invention is to propose an electronic circuit enabling the generation of a Gaussian distribution with better control for the implementation of a Bayesian neural network, while keeping dimensions small.

[0014] To this end, the invention relates to an electronic circuit for implementing a Bayesian neural network, comprising:

[0015] - bit lines;

[0016] - source lines;

[0017] - at least one line of words;

[0018] - at least one primary branch, the or each primary branch comprising at less a primary cell connected between a respective source line and bit line, the or each primary cell including a primary memory component and a primary switch connected in series, the primary switch having a control electrode connected to a respective word line,

[0019] - at least one secondary branch, the secondary branch or branches comprising at least one secondary cell connected between a respective source line and bit line, the secondary cell or cells including a secondary memory component and a secondary switch connected together,

[0020] the source and bit lines associated with the secondary branch(es) being distinct from the source and bit lines associated with the primary branch(es),

[0021] - an accumulation device connected to the primary and secondary branches and configured to accumulate a total amount of electrical charges from a respective pair of cells, the pair being formed of a respective primary cell and a respective secondary cell, the total amount being the sum of a primary amount of charges from said primary cell and a secondary amount of charges from said secondary cell, the primary and secondary amounts being accumulated independently of each other.

[0022] With the electronic circuit according to the invention, each standard deviation of the Gaussian distribution is stored in a respective primary cell and each mean value of the Gaussian distribution is stored in a respective secondary cell. Accumulating the primary and secondary quantities independently of each other reduces the correlation between the mean value and the standard deviation of the generated distribution, each random value of the generated Gaussian distribution being obtained from a respective value of the total accumulated quantity. Independent charge accumulation between the primary and secondary branches allows for different integration times to be defined for each branch. This constitutes an additional design parameter for controlling the correlation between the branches.

[0023] For this purpose also, each primary cell is included in a corresponding primary branch, and each secondary cell is included in a corresponding secondary branch, the or each secondary branch being distinct from the or each primary branch and arranged in parallel with it.

[0024] During a sampling operation to obtain several samples of the Gaussian distribution, each sample results for example from a value of an output voltage of the accumulation device, this output voltage depending on the total quantity accumulated.

[0025] Preferably, each primary, secondary memory component includes an oxide-based resistive memory, or OxRAM, which then makes it possible to take advantage of the read-to-read variability of the OxRAM for the sampling operation.

[0026] According to other advantageous aspects of the invention, the electronic circuit comprises one or more of the following features, taken individually or in all technically possible combinations:

[0027] - the primary quantity is accumulated during two successive phases: a charging phase with a first voltage value applied to the corresponding source line, and a discharging phase with a second voltage value applied to said source line, the second value being distinct from the first value;

[0028] - each primary branch further comprises a voltage-to-current converter of the primary cell, the voltage-current converter being connected between an additional potential and the accumulation device, the voltage-current converter having a control electrode connected to the primary cell via the corresponding bit line;

[0029] - the additional potential has a value greater than a reference potential in input of the accumulation device during the charging phase, and a value lower than the reference potential at the input of the accumulation device during the discharging phase;

[0030] - the primary branch or branches further comprise a variable conductance, connected between a reference potential and the control electrode of the voltage-current converter;

[0031] - the or each primary branch further comprises a capacitor having a terminal connected to the control electrode of the voltage-to-current converter and the other terminal to a reference potential;

[0032] the or each primary branch preferably comprising an auxiliary switch connected between the terminal of the capacitor which is connected to said control electrode and a pre-charge potential of the capacitor;

[0033] - the electronic circuit further comprises a cascode, called the primary cascode, connected between the primary branch or branches and the accumulation device;

[0034] - the primary memory component or components is a noise-sensitive memory random telegraphic;

[0035] the primary memory component(s) preferably being a memory selected from the group consisting of: an oxide-based resistive memory; a memory conductive bridging RAM; phase-change RAM; magnetic RAM; and ferroelectric stacking memory, such as tunnel junction ferroelectric memory;

[0036] - the secondary memory component or components is a memory selected from the group consisting of: oxide-based resistive RAM; conductive bridging RAM; phase-change RAM; magnetic RAM; and ferroelectric stacking memory such as ferroelectric capacitor or tunnel junction ferroelectric memory;

[0037] - the secondary memory component and the secondary switch are connected in series between the respective source line and bit line, the secondary switch having a control electrode connected to a respective word line;

[0038] - the secondary memory component or components is a component selected from the group consisting of: a ferroelectric memory field-effect transistor; and a ferroelectric field-effect transistor;

[0039] - the secondary memory component is connected between the source line and the line of respective bits, and the secondary switch is connected between a word line and a control electrode of the secondary memory component;

[0040] - the electronic circuit further comprises a cascode, called a secondary cascode, connected between the secondary branch(es) and the accumulation device;

[0041] - the accumulation device includes at least one transimpedance amplifier;

[0042] - the electronic circuit comprises N primary branches and N branches secondary arranged in N pairs of primary and secondary branches, and the accumulation device comprises N transimpedance amplifiers, each connected to a respective pair of primary and secondary branches, N being an integer greater than or equal to 2;

[0043] - the electronic circuit comprises N secondary branches, N being an integer greater than or equal to 2;

[0044] - the electronic circuit comprises a single primary branch;

[0045] - the electronic circuit comprises N primary branches; and

[0046] - the accumulation device comprises a single transimpedance amplifier capacitive.

[0047] These features and advantages of the invention will become clearer upon reading the following description, given solely by way of non-limiting example, and made with reference to the accompanying drawings, in which:

[0048] [Fig-1] [Fig.1] is a schematic representation of an electronic circuit, according to the invention, comprising bit lines; source lines; at least one word line; at least one primary branch, each comprising at least one primary cell including a primary memory component and a primary switch; at less a secondary branch, each comprising at least one secondary cell including a secondary memory component and a secondary switch; and an accumulation device connected to the primary and secondary branches to accumulate a total quantity of electrical charges from a respective pair of cells; [Fig.1] being according to a first embodiment of the circuit without the addition of cascode, according to a first example of an embodiment of the primary branch with in addition a voltage-current converter of the primary cell, according to a first type - called capacitive - of primary cell, and according to a first type of secondary cell;

[0049] [Fig.2] [Fig.2] is a partial schematic representation of the electronic circuit where the secondary branch and the accumulation device are not shown, according to a second embodiment of the circuit with an additional cascode, called the primary cascode, connected between a respective primary branch and the accumulation device;

[0050] [Fig.3] [Fig.3] is a set of schematic curves of different magnitudes illustrating the operation of the electronic circuit according to the second embodiment and following a first implementation where a square wave signal, i.e. in the shape of a square, is applied to the primary memory component in order to bias the primary cell;

[0051] [Fig.4] [Fig.4] is a view analogous to that of [Fig.3], following a second implementation where a triangular-shaped signal is applied to a capacitor of the primary branch in order to bias the primary cell;

[0052] [Fig.5] [Fig.5] is a schematic representation of the primary branch, according to a second type - called resistive - of primary cell, and according to a first example without addition of variable conductance;

[0053] [Fig.6] [Fig.6] is a set of schematic curves of different magnitudes illustrating the operation of the primary branch of [Fig.5];

[0054] [Fig.7] [Fig.7] is a schematic representation of the primary branch and the secondary branch connected in parallel, the primary branch being according to the second type - called resistive - of primary cell, and according to a second example with addition of variable conductance;

[0055] [Fig.8] [Fig.8] is a view analogous to that of [Fig.6], for the primary cell of [Fig.7];

[0056] [Fig.9] [Fig.9] is a partial schematic representation of the electronic circuit where the primary branch and the accumulation device are not shown, according to a third embodiment of the circuit with an additional cascode, called secondary cascode, connected between a respective secondary branch and the accumulation device;

[0057] [Fig. 10] the [Fig. 10] is a schematic representation of the secondary branch, according to a second type of secondary cell where the secondary memory component is a FeFET or a FeMFET;

[0058] [Fig. 11] [Fig. 11] is a schematic representation of the parallel arrangement of several primary and secondary branches of the circuit, each branch typically comprising several cells, according to a first arrangement with N primary branches, N secondary branches, N > 2, and the accumulation device comprising a single transimpedance amplifier connected to said N primary and secondary branches;

[0059] [Fig. 12] [Fig. 12] is a schematic view of an example implementation with representation of line control logic units in the case of a primary branch and a secondary branch connected in parallel at the input of a transimpedance amplifier, according to a fourth embodiment of the circuit with both the primary cascode connected between the primary branch and the accumulation device and the secondary cascode connected between the secondary branch and the accumulation device;

[0060] [Fig.13] [Fig.13] is a view analogous to that of [Fig.12], in the case of two primary branches connected in parallel at the input of the transimpedance amplifier; and

[0061] [Fig. 14] The [Fig. 14] illustrates two schematic representations of the parallel arrangement of the primary and secondary branches of the circuit; one being according to a second arrangement with N pairs of primary and secondary branches, N > 2, and the accumulation device comprising N transimpedance amplifiers, each being connected to a respective pair of primary and secondary branches; the other being according to a third arrangement with a single primary branch, N secondary branches, N > 2, and the accumulation device comprising a single transimpedance amplifier connected to said primary and secondary branches.

[0062] An electronic circuit 10 for implementing a Bayesian neural network includes bit lines BLj, with j an integer index greater than or equal to 1, such as the first BL1 and second BL2 bit lines, visible in Figures 12 and 13; source lines SLj, such as the first SL1 and second SL2 source lines, also visible in Figures 12 and 13; and at least one word line WLi, with i an integer index greater than or equal to 1, such as the first WLI and second WL2 word lines, shown in Figures 12 and 13.

[0063] The electronic circuit 10 also includes at least one primary branch 15, at least one secondary branch 20, and an accumulation device 25 connected to the primary branch(es) 15 and secondary branch(es) 20.

[0064] In the example of [Fig.1], the electronic circuit 10 shown comprises a single primary branch 15 and a single secondary branch 20.

[0065] In figures 11 and 14 representing different examples of parallel arrangement of primary branch(es) 15 and secondary branch(es) 20, the electronic circuit 10 comprises several secondary branches 20 and one or more primary branches 15 depending on the examples.

[0066] As an optional complement, such as in the examples of Figures 2 and 11 to 13, the electronic circuit 10 further includes a cascode, called primary cascode 26, connected between a respective primary branch 15 and the accumulation device 25.

[0067] As an optional addition, such as in the examples of figures 9, 11 and 12, the electronic circuit 10 further comprises another cascode, called secondary cascode 28, connected between a respective secondary branch 20 and the accumulation device 25.

[0068] Each primary branch 15 comprises at least one primary cell 30 connected between a respective source line SLj and bit line BLj, each primary cell 30 including a primary memory component 32 and a primary switch 34 connected in series.

[0069] In the examples in Figures 11 to 13, each primary branch 15 comprises several primary cells 30 connected in parallel to each other between the respective source line SLj and bit line BLj, each primary cell 30 having one end connected to said source line SLj and the other end connected to said bit line BLj.

[0070] In addition, according to a first embodiment of the primary branch 15, as shown in Figures 1, 2, 7 and 11 to 13, the primary branch 15 further comprises a voltage-current converter 36 of the primary memory cell 30, the voltage-current converter 36 being connected between an additional potential VD and the accumulation device 25.

[0071] Alternatively, according to a second embodiment of the primary branch 15, as shown in [Fig.5], the primary branch 15 does not include a voltage-current converter.

[0072] According to a first type – called capacitive – of the primary branch 15, as shown in Figures 1 to 4 and 11 to 13, the primary branch 15 further comprises a capacitor 38 having one terminal connected to the voltage-current converter 36 and the other terminal to a reference potential VCap-

[0073] According to this first type, the primary branch 15 advantageously comprises a first auxiliary switch 40 connected between the terminal of the capacitor 38, which is connected to the voltage-current converter 36, and a pre-charge offset potential VC of the capacitor 38. The first auxiliary switch 40 then serves to pre-charge the capacitor 38. The first auxiliary switch 40 also serves to provide access for programming the corresponding primary cell(s) 30.

[0074] Alternatively, the primary branch 15 is of a second type, called resistive, as shown in Figures 5 and 7.

[0075] In the example of [Fig.5], the primary branch 15 comprises only the primary cell 30, that is to say only the primary memory component 32 and the primary switch 34.

[0076] In the example of [Fig.7], according to an optional complement for the second type - called resistive - of the primary branch 15, the primary branch 15 further comprises a variable conductance 42, connected between a reference potential VCv and the voltage-current converter 36. The variable conductance 42 is for example a variable resistance 44 whose resistance value Rref is controlled by the parameter CTRL.

[0077] Each primary branch 15 is also called the first branch. Furthermore, with the electronic circuit 10 according to the invention, each standard deviation of the Gaussian distribution is stored in a respective primary cell 30. Since the standard deviation is generally represented by the Greek letter sigma, each primary branch 15 is also called the sigma branch.

[0078] Each secondary branch 20 comprises at least one secondary cell 50 connected between a respective SLk source line and a BLk bit line, each secondary cell 50 including a secondary memory component 52 and a secondary switch 54 connected together. The SLk source and BLk bit lines associated with each secondary branch 20 are distinct from the SLj source and BLj bit lines associated with each primary branch 15.

[0079] In the examples in Figures 11 and 12, each secondary branch 20 comprises several secondary cells 50 connected in parallel with each other between the respective source line SLj and bit line BLj, each secondary cell 50 having one end connected to said source line SLj and the other end connected to said bit line BLj.

[0080] As an optional addition, the secondary branch 20 includes a second auxiliary switch 56 connected between the secondary cascode 28 and the pre-charge potential Voffset, as shown in Figures 11 and 12. The second auxiliary switch 56 serves to provide access for programming the corresponding secondary cell(s) 50.

[0081] Each secondary branch 20 is also called the second branch. Furthermore, with the electronic circuit 10 according to the invention, each average value of the Gaussian distribution is stored in a respective secondary cell 50. The value Since the average is generally represented by the Greek letter mu, each secondary branch 20 is also called a mu branch.

[0082] The accumulation device 25 is configured to accumulate the total quantity Qtot of electrical charges from a respective pair of cells 30, 50, the pair being formed of a respective primary cell 30 and a respective secondary cell 50, the total quantity Qtot being the sum of a primary quantity Qo of charges from said primary cell 30 and a secondary quantity QLI of charges from said secondary cell 50, the primary quantity Qo and the secondary quantity QLI being accumulated independently of each other.

[0083] Advantageously, the accumulation device 25 is configured to accumulate the primary quantity Qo during two successive phases, namely a charging phase with a first voltage value VT0P+ applied to the corresponding source line SLj, and a discharging phase with a second voltage value VTop applied to said source line SLj, the second value VT0P+ being distinct from the first value VTop+-

[0084] When the primary branch 15 is supplemented, it also includes the voltage-current converter 36 connected between the additional potential VD and the storage device 25. The additional potential VD preferentially has a value VD+ greater than a reference potential VE at the input of the storage device 25 during the charging phase, and a value VD. less than the reference potential VE at the input of the storage device 25 during the discharging phase.

[0085] In the examples in Figures 1 and 11 to 14, the storage device 25 includes at least one transimpedance amplifier 60. The transimpedance amplifier 60 is known per se, and is also denoted TIA (Transimpedance Amplifier). The transimpedance amplifier 60 is configured to convert an input current into a proportional output voltage VOut. Advantageously, the transimpedance amplifier 60 is a capacitive transimpedance amplifier, also denoted CTIA (Capacitive Transimpedance Amplifier), by including one or more capacitive elements to improve certain performance characteristics, such as frequency response and noise reduction.

[0086] In the examples of Figures 1 and 11 to 14, the transimpedance amplifier 60 is a CTIA, and comprises an operational amplifier 62 receiving at its input terminals, on the one hand, the reference potential VE, described previously, and on the other hand, an input voltage V1N at the connection point of the respective pair of primary 30 and secondary 50 cells, and delivering at its output terminal the output voltage Vout- The transimpedance amplifier 60 further comprises a feedback capacitor 64 of capacitance CCTia and a control switch 66, the capacitor of feedback 64 and the control switch 66 being connected in parallel with each other between the output terminal of the operational amplifier 62 and the input terminal receiving the input voltage V1N.

[0087] In the examples in Figures 1 and 11 to 13, as well as in the lower part of [Fig. 14], the storage device 25 comprises a single transimpedance amplifier 60. Alternatively, as in the upper part of [Fig. 14], the storage device 25 comprises several transimpedance amplifiers 60, typically with one transimpedance amplifier 60 for each pair of primary 15 and secondary 20 branches.

[0088] Each primary memory component 32 is advantageously a memory sensitive to random telegraphy noise, also called RTN (from the English Random Telegraphy Noise).

[0089] Each primary memory component 32 is advantageously a non-volatile random access memory.

[0090] Each primary memory component 32 is, for example, a memory selected from the group consisting of: an oxide-based resistive random access memory, also called OxRAM; a conductive bridging random access memory, also called CBRAM; a phase-change memory, also called PCM; a magnetoresistive random access memory, also called MRAM; and a ferroelectric tunnel junction memory, also called FTJ.

[0091] In the examples in Figures 1 to 8 and 11 to 13, the primary memory component 32 is a resistive random access memory, with resistance denoted Rsigma-

[0092] Each of the switches among the primary switch 34, the first auxiliary switch 40, the secondary switch 54, the second auxiliary switch 56, and the pilot switch 66 has two conduction electrodes and one control electrode to control the switching of the corresponding switch between a conducting state in which a current flows between the conduction electrodes and a blocking state in which no current flows between the conduction electrodes. Those skilled in the art will observe that when the switch in question is a transistor, such as a metal-oxide-semiconductor field-effect transistor, or MOSFET, then the conduction electrodes are the drain and source electrodes, and the control electrode is the gate electrode.

[0093] The primary switch 34 has its control electrode connected to a respective WLi word line. The primary switch 34 is used for programming the primary memory component 32 to which it is connected. In other words, the primary switch 34 is used to store the desired value in the primary memory component 32.

[0094] In the examples in Figures I to I and I to I, the primary switch 34 is a MOSFET transistor, denoted MA, whose gate electrode is driven by a voltage VWL associated with the respective word line WLi.

[0095] The voltage-to-current converter 36 has its control electrode connected to the primary memory cell via the corresponding bit line BLj. The voltage-to-current converter 36 is used to amplify variations in a voltage VG from the primary memory component 32 via the corresponding bit line BLj.

[0096] In the examples in Figures 1 to 4, 7, 8 and 11 to 13, the voltage-current converter 36 is a MOSFET transistor, denoted MB, whose gate electrode is driven by the voltage VG.

[0097] The capacitor 38 has one terminal connected to the control electrode of the voltage-current converter 36 and the other terminal to a reference potential VCAp, and has a capacitance CBl-

[0098] The first auxiliary switch 40 is connected between the pre-charge Voffset potential of the capacitor 38 and the terminal of the capacitor 38 which is connected to the control electrode of the voltage-current converter 36.

[0099] The variable conductance 42 is connected between the reference potential VCv and the control electrode of the voltage-current converter 36. In the example of [Fig.7], the variable conductance 42 is achieved via the variable resistance 44 controlled by the parameter CTRL.

[0100] Each secondary memory component 52 is advantageously a non-volatile random access memory.

[0101] In the examples of Figures 1, 9, 11 and 12, according to a first type of the secondary cell 50, each secondary memory component 52 is a memory selected from the group consisting of: an oxide-based resistive RAM, also called OxRAM; a conductive bridge RAM, also called CB RAM; a phase-change RAM, also called PCM; a magnetic RAM, also called MRAM; and a tunnel junction ferroelectric memory, also called FTJ; and a ferroelectric memory also called FeRAM.

[0102] In these examples in Figures 1, 9, 11 and 12, the secondary memory component 52 and the secondary switch 54 are connected in series between the respective source line SLk and bit line BLk, the secondary switch 54 having a control electrode connected to a respective word line WLj.

[0103] In these examples in Figures 1, 9, 11 and 12, the secondary memory component 52 is a resistive random access memory, with resistance denoted RMU.

[0104] Alternatively, according to a second type of the secondary cell 50, each secondary memory component 52 comprises a field-effect transistor using a ferroelectric material.

[0105] According to this embodiment, each secondary memory component 52 is, for example, a ferroelectric-Metal Field-Effect Transistor (FeMFET), as shown in [Fig. 10]; or a ferroelectric Field-Effect Transistor (FeFET). The FeMFET is a type of field-effect transistor whose gate is connected to a ferroelectric capacitance formed by a metal-ferroelectric-metal dielectric junction. The biasing of the ferroelectric layer modifies the electrical properties of the FeMFET, allowing its use in non-volatile memory.The FeFET is a field-effect transistor that uses a ferroelectric material as its gate dielectric. The bias of this ferroelectric dielectric controls the conduction channel, thus providing non-volatile memory with characteristics similar to those of MOSFETs. In both cases, FeMFETs and FeFETs are subject to a shift in their threshold voltages when the ferroelectric bias changes.

[0106] According to this embodiment, the secondary memory component 52 is connected between the respective source line SLk and bit line BLk, and the secondary switch 54 is connected between a word line WLj and a control electrode of the secondary memory component 52. According to this embodiment, the secondary switch 54 is then configured to select the secondary memory component 52 with which it is associated, this selection being carried out by applying the voltage VSel to the control electrode of the secondary switch 54, and when the secondary switch 54 is in its conducting state, it then allows the application of the voltage VWL to the control electrode of the secondary memory component 52, this voltage VWl being received via the word line WLi connected to the secondary switch 54.

[0107] The operation of the electrical circuit 10 according to the invention will now be explained, in particular with regard to figures 3, 4, 6 and 8, these figures representing sets of schematic curves of different quantities involved in the operation of the electrical circuit 10 according to the invention, in particular of different voltages applied to elements of the electrical circuit 10.

[0108] A person skilled in the art will observe in particular that the voltages shown in each of these figures 3, 4, 6 and 8 correspond to those shown in the electrical circuit 10 of each of the preceding figures, the voltages shown in figures 3 and 4 being then visible on [Fig.2], and partially on [Fig.1], likewise the tensions represented in [Fig.6] being visible in [Fig.5], and those represented in [Fig.8] being visible in [Fig.7].

[0109] Thus, in Figures 3 and 4, the tensions are respectively as follows, from top to bottom:

[0110] - the VWL voltage applied to the control electrode of the primary switch 34 via the WLi word line, this voltage VWL varies between a low potential formed by the GND potential of an electrical mass and a high potential noted VDD;

[0111] - a Vcascode voltage applied to the primary cascode control electrode 26, represented by dotted lines;

[0112] - the VT0P voltage applied to the primary memory component 32 via the source line SLj, taking in particular the first voltage value VT0P+ in the charging phase and the second voltage value VTop in the discharging phase;

[0113] - a voltage V0PPset applied to one end of the first auxiliary switch 40 and used to pre-charge capacitor 38;

[0114] - a voltage VD applied at one end of the voltage-current converter 36, taking a value VD+ in the charging phase, a value VD . in the discharging phase and a value VRu otherwise, the value VRu being a reference value of the input voltage Vin corresponding to a balance of charges, i.e. to an absence of charge accumulation by the accumulation device 25, the value VREp also being called the pre-charge voltage of the accumulation device 25;

[0115] - a voltage VCap applied to the lower terminal of capacitor 38; a source of constant voltage (connected to ground in the example of [Fig.3]) or dynamic ([Fig.4])

[0116] - a threshold voltage VTH of the voltage-current converter 36;

[0117] - the VG voltage, also called the VG grid voltage, applied to the electrode of control of the voltage-current converter 36; and the person skilled in the art will observe that the value of this voltage VG depends on the value of the primary memory component 32, such as the value of the resistance Rsigma, the voltage VG then being variable as a function of the value of the resistance Rsigma, with representation in figures 3 and 4 of both a curve denoted VG(Rmin) for a minimum value Rmin of this resistance Rsigma, and of a curve denoted VG(Rmax) for a maximum value Rmax of this resistance Rsigma;

[0118] - the reference potential VE received at the input of the transimpedance amplifier 60, also noted VE _Ctia;

[0119] - the output voltage VOut at the output of the storage device 25; and the man Those in the know will note that the value of this output voltage VOut also depends on the value of the primary memory component 32, such that the value of the resistance Rsigma—the output voltage VOut—is then variable depending on the value of the resistance Rsigma, with representation in Figures 3 and 4 of both a curve denoted Vout(CRmin) for the minimum value Rmin of this resistance Rsigma, and a curve denoted VOut(Rmax) for the maximum value Rmax of this resistance Rsigma; and

[0120] - the GND potential of the electrical mass.

[0121] The tensions represented in figures 6 and 8 are each among those defined above.

[0122] The electrical circuit 10 according to the invention forms a transient Gaussian generator with RTN noise and uses the read variability of the primary memory components 32 and secondary memory components 52 to construct a transient Gaussian generator, such a generator being particularly useful for the hardware implementation of Bayesian neural networks. The properties of each Gaussian distribution are then controlled by a pair of mean and standard deviation values, each being stored in a respective memory component 32, 52, each standard deviation value being stored in a respective primary memory component 32 and each mean value in a respective secondary memory component 52.

[0123] For reading these values, the principle is to carry out an accumulation of charges via the accumulation device 25, the total quantity Qtot then being the sum of the primary quantity Qo of charges from said primary cell 30 and the secondary quantity QLI of charges from said secondary cell 50, and this total quantity Qtot being related to the output voltage VOut at the output of the accumulation device 25 via the following equation:

[0124] [1]

[0125] Q = Q + Q = C CTIA (VV j

[0126] where Qtot represents the total quantity,

[0127] Qo represents the primary quantity,

[0128] Qp represents the secondary quantity,

[0129] Cctia represents the capacitance of the feedback capacitor 64 of a respective capacitive transimpedance amplifier of the accumulation device 25,

[0130] VE represents the reference potential received at the input of the transimpedance amplifier, this reference potential VE being, for example, equal to the value VREE, i.e., the pre-charge voltage of the storage device 25 and

[0131] Vout represents the output voltage of said respective capacitive transimpedance amplifier.

[0132] As shown in particular in [Fig.1], the primary quantity Qo of charges from said primary cell 30 corresponds to the change in charges resulting on the one hand from a current io+ flowing from the respective primary cell 30 to the accumulation device 25 and on the other hand from a current io- flowing in the opposite direction from the accumulation device 25 to the respective primary cell 30.

[0133] More precisely, the primary quantity Qo satisfies the following equation:

[0134] [2]

[0135]

[0136] where Qo represents the primary quantity,

[0137] io+ represents the current flowing from the respective primary cell 30 to the storage device 25 during the charging phase with the first voltage value VTop+ applied to the corresponding source line SLj, for a first duration ti; and advantageously in the presence of the voltage-current converter 36 amplifying the voltage variations, with the higher value VD+ of the additional potential VD;

[0138] io- represents the reverse current flowing from the storage device 25 to the respective primary cell 30 during the discharge phase with the second voltage value VT0P . applied to said source line SLj, for a second duration t2; and advantageously in the presence of the voltage-current converter 36 amplifying the voltage variations, with the lower value VD . of the additional potential VD.

[0139] The secondary quantity QLI of charges from said secondary cell 50 results from a current ip flowing from the respective secondary cell 50 to the accumulation device 25.

[0140] More specifically, the secondary quantity QLI satisfies the following equation:

[0141] [3]

[0142]

[0143] where Qp represents the secondary quantity,

[0144] ip represents the current flowing from the respective secondary cell 50 to the accumulation device 25 during the charging phase, for a third duration t3, distinct and independent of the first and second durations tb t2.

[0145] To avoid a correlation between the mean and standard deviation values, each current io on the one hand and ip on the other hand is sampled independently, but not necessarily sequentially by the accumulation device 25.

[0146] For the respective primary cell 30, due to the io+, io- currents flowing in opposite directions successively during the charging and discharging phases, the primary quantity Qo exhibits a distribution whose average value is independent of the value of the primary memory component 32, such that the value of the resistance Rsigma, and whose variance results from the noise RTN of the primary memory component 32. The primary quantity Q then satisfies the following equations:

[0147] [4]

[0148] E( Q^ = constant ~ 0

[0149] [5] 101501 V(Q a}=F(R slaMA )

[0151] where Qo represents the primary quantity,

[0152] E represents the expectation

[0153] V represents the variance,

[0154] F represents a first mathematical function, and

[0155] Rsigma represents the resistance of the primary memory component 32.

[0156] For the respective secondary cell 50, the secondary memory component 52 is in the form of any non-volatile memory as long as the variance-to-mean ratio remains acceptable. A range of acceptable values ​​for this variance-to-mean ratio is typically predefined, for example, according to the application concerned, and / or following measurements and / or simulations performed. For example, the range of acceptable values ​​for this variance-to-mean ratio is [0; 0.1], that is, a variance of at most 10% of the mean.

[0157] The secondary quantity QLI then satisfies the following equations:

[0158] [6] 101591 E (g„)=G(« Ml )

[0160] [7]

[0161] V(Q^) ^constant ~ 0

[0162] where QLI represents the secondary quantity,

[0163] E represents the expectation

[0164] V represents the variance,

[0165] G represents a second mathematical function, and

[0166] Rmu represents the resistance of the secondary memory component 52.

[0167] In addition, in the presence of the voltage-to-current converter 36, this allows for the amplification of variations in the gate voltage VG between its gate electrode and the primary memory component 32. Advantageously, a strong dependence between the value, such as the resistance Rsigma, of the primary memory component 32 and the gate voltage VG allows for better measurement of these fluctuations. Two levers are then possible: the first is a process parameter, ensuring that the noise level, such as the RTN noise, is maximized in the highly resistive state; called HRS (High Resistive State), of the primary memory component 32 and decreases with the conductance in the low resistive state, also called LRS (Low Resistive State), of said primary memory component 32. A second lever is a design parameter by positioning a cutoff frequency fc of the RC filter, formed by the primary memory component 32 and the capacitor 38, in accordance with a clock frequency fciock of the electronic circuit 10, as will be explained in more detail later with regard to the examples in figures 3 and 4.

[0168] According to this supplement, the voltage-to-current converter 36, when it is a MOSFET, operates advantageously in inversion mode, that is, with its gate-source voltage VGS greater than the threshold voltage VTH, to avoid a lognormal distribution. Indeed, when VGS is less than VTh, the MOSFET operates below the threshold and the current is an exponential function of the gate-source voltage VGS. If the gate-source voltage VGS followed a normal law with respect to time, the measured current would, by definition, follow a lognormal law.

[0169] The RTN noise changes the value, such as the RSiGma resistance, of the primary memory component 32 around its nominal values. In the ideal case, illustrated in the upper part of [Fig. 6], the voltage values ​​VTop+, VTOp are chosen so that, in the absence of variation in RSiGma resistance, the initial value of the output voltage VOut is the same as the final value of the output voltage VOut: the continuous, or DC, portion is then eliminated.

[0170] Nevertheless, during charging or discharging phases, certain RTN events may occur, the RSiGma resistance also being subject to thermal noise.

[0171] The accumulated charge Qtot being limited by the capacitance CCTia of the feedback capacitor 64 according to the relation nvj from equation [1] V to t~^CTiA\ v E- V OUT ] The second type – called resistive – of the primary cell 30, as described in the first example without the addition of variable conductance and without the voltage-to-current converter 36, is advantageous if a short pulse of the voltage VTOp applied to the primary memory component 32 can be precisely controlled via the corresponding source line SLj. Otherwise, the capacitance Cctia will be saturated.

[0172] To avoid saturation and allow RTN events to still occur, the resistance value is sampled using short pulses of said voltage VT0P applied to the primary memory component 32, these pulses being repeated and spaced with an arbitrary spacing time, as shown in the lower part of [Fig. 6]. Ideally, the spacing should be greater than the transmit and capture times in order to accumulate different values ​​in the charge / discharge phases.

[0173] To accumulate more useful data without saturating the CCTia capacitance of the feedback capacitor 64, one solution is to use a different architecture, such as, for example, the second type—the resistive type—of the primary cell 30, as shown in the second example with the addition of the variable conductance 42 and with the voltage-current converter 36, visible in [Fig. 7]. When the voltage-current converter 36 is conducting, the primary cell 30 simplifies into a resistive divider between the resistances Rsigma of the primary memory component 32 and Rref of the variable conductance 42. For a fixed value of the voltage VT0P applied to the primary memory component 32, any variation in the resistance Rsigma of the primary memory component 32 will then be reflected in the gate voltage VG according to the following equation of a transfer function H:

[0174] [8]

[0175] „ _ v«Vcv _ Rref VTOp-^CV Rref+RsiGMA

[0176] where VG is the grid voltage applied to the control electrode of the voltage-current converter 36,

[0177] VTOp is the voltage applied to the primary memory component 32 via the corresponding SLj source line,

[0178] Vcv is the voltage applied to the second terminal of the variable resistor 44,

[0179] Rref is the value of the variable resistor 44, and

[0180] Rsigma is the resistance of the primary memory component 32.

[0181] As in the previous example in Figures 5 and 6, a pulse strategy is possible to improve the energy consumption of the primary cell 30, as shown in [Fig. 8]. The voltage across the voltage-current converter 36, i.e., the potential difference VD-V1N, can be chosen to be as small as possible to operate in the linear regime of the MOSFET transistor MB.

[0182] For the first type - called capacitive - of the primary cell 30, corresponding to the examples in Figures 1 to 4, the implementation of the electronic circuit 10 according to the invention includes an initial PC pre-charge phase at the voltage Voffset of the capacitor 38 and of the connection node of the primary switch 34 to the capacitor 38, called floating node, this initial PC phase preceding a reading RD with a charging phase of duration t1 and a discharging phase of duration t2 in Figures 3 and 4.

[0183] For RD reading with charge and discharge phases, the transient signal for the voltage VT0P or for the voltage VCap is, for example, square or triangular in shape, and the voltage VG depends on the value of the primary memory component 32, such as the value of the resistance Rsigma. The accumulation of the current flowing through the voltage-current converter 36 then results in an increase in charge, i.e., a charge phase, when the potential difference VD-V1N is positive. i.e., when the potential difference VD-VREF is positive; and respectively, a decrease in charge, i.e., a discharge phase, when the potential difference VD-ViN is negative, i.e., when the potential difference VD-VREF is negative. These charging and discharging phases are typically iterated several times over several successive cycles.

[0184] A person skilled in the art will also observe that when the primary memory component 32 is an oxide-based resistive random access memory, or OxRAM, the potential difference VTOp-VG must be less than the threshold voltage of the OxRAM to avoid erasure of the OxRAM.

[0185] In the example in [Fig. 3], the transient signal for the voltage VTOp is square wave and the signal for the voltage VCap is continuous, or DC, with the voltage VG then being triangular wave. In this example in [Fig. 3], the primary memory component 32 and the capacitor 38 together form a low-pass filter acting as an integrator, and the transfer function H then satisfies the following equation:

[0186] [9]

[0187] "Vg-Vcap 1 ^TOP'^CAP LX

[0188] where VG is the voltage applied to the control electrode of the voltage-current converter 36,

[0189] VTOp is the voltage applied to the primary memory component 32,

[0190] with x satisfying the equation:

[0191]

[10]

[0192] "_Z X ïc

[0193] where f is a frequency of the circuit,

[0194] fc is the cutoff frequency of the filter, and satisfies the following equation:

[0195]

[11]

[0196] f = A......

[0197] with RSiGma the resistance of the primary memory component 32, and

[0198] Cbl the capacitance of capacitor 38, also noted C in figures 3 and 4.

[0199] On [Fig.3], the transfer function H is schematically represented for the minimum values ​​Rmin and maximum Rmax of the resistance Rsicma of the primary memory component 32, with illustration of the respective cutoff frequencies 1 / (2jrRmin.C) and 1 / (2irRmax.C), where C then denotes the capacitance of the capacitor 38.

[0200] A person skilled in the art will then notice that in this example the clock frequency fciock is advantageously chosen to be greater than or equal to the cutoff frequency fc of the low-pass filter in order to take advantage of the variability resulting from the resistance Rsicma of the primary memory component 32. It should be noted that if the clock frequency fciock is equal At l / (2irRmin.C), the variation of the transfer function H is maximum. When the clock frequency fciock is much higher than the cutoff frequency fc, we are in the filter's attenuation zone and the relationship between the transfer function H and the resistance Rsigma is no longer measurable.

[0201] In the example in [Fig. 4], the signal for the voltage VT0P is continuous, or DC, and the transient signal for the voltage VCap is triangular in shape, while the voltage VG is square in shape. In this example in [Fig. 4], the primary memory component 32 and the capacitor 38 together form a high-pass filter acting as a differentiator, and the transfer function H then satisfies the following equation:

[0202]

[12]

[0203] „ _ Wcap _ a- ^TOP^CAP

[0204] where VG is the potential applied to the control electrode of the voltage-current converter 36 also connected to the first terminal of the capacitor 38,

[0205] VTOp is the voltage applied to the primary memory component 32,

[0206] Vcap is the voltage applied to the second terminal of capacitor 38

[0207] with x satisfying the previous equation

[10] .

[0208] On [Fig.4], the transfer function H is also schematically represented for the minimum values ​​Rmin and maximum Rmax of the resistance Rsigma of the primary memory component 32, with illustration of the respective cutoff frequencies l / (2irRmin.C) and l / (2irRmax.C), where C then denotes the capacitance of the capacitor 38.

[0209] Those skilled in the art will also note that in this example the clock frequency fciock is advantageously chosen to be less than or equal to the cutoff frequency fc of the high-pass filter in order to utilize the variability resulting from the resistance Rsigma of the primary memory component 32. It should be noted that since the clock frequency fciock is equal to 1 / (2irRmax.C), the variation of the transfer function H is at its maximum. When the clock frequency fciock is significantly lower than the cutoff frequency fc, the filter is in its attenuation region and the relationship between the transfer function H and the resistance Rsigma is no longer measurable.

[0210] In these examples in Figures 2 to 4, the primary cascode 26 makes it possible to limit, or even to starve, the discharge of the transimpedance amplifier 60, and also to amplify the fluctuations of the drain current ID of the voltage-current converter 36, when it is of the MOSFET type, by modulating the efficiency of a transconductance gm / ID.

[0211] The person skilled in the art will observe that the curves in Figures 3 and 4 correspond to the electronic circuit of [Fig.2], and that those corresponding to the electronic circuit of [Fig.1] are similar except that the VCascode voltage is then suppressed, since the electronic circuit of [Fig.1] does not include the primary cascode 26.

[0212] For the reading associated with a respective secondary cell 50, i.e. for the accumulation of charges from said secondary cell 50 via the accumulation device 25, typically according to the preceding equation [3], it is advantageous to have a low current ip when the secondary cell 50 is of the first type, in particular when the secondary memory component 52 is a resistive oxide-based random access memory, or OxRAM.

[0213] This advantageous aspect is obtained for example either by having a low value, typically on the order of mV in the LRS state, for the respective VT0P voltage applied to the secondary memory component 52 via the corresponding SLk source line; or by using the OxRAM selector designed to form / program the series resistance; or by adding an additional series resistance via the addition of the secondary cascode 28 as in the example of [Fig.9].

[0214] Advantageously, the secondary cell 50 is of the second type, the secondary memory component 52 then comprising a field-effect transistor using a ferroelectric material, the secondary memory component 52 being typically a FeMFET or a FeFET. This has the advantage of lower sensitivity to RTN noise, compared for example to the RTN noise of an OxRAM, and thus limits the risk of biasing the variability observed on the current from the primary cell 30, for which the primary memory component 32 is advantageously sensitive to RTN noise.

[0215] In addition, as with an oxide-based resistive random access memory, or OxRAM, the capacity of the FeMFET or FeFET is programmable over several levels, which makes it possible to obtain several levels of value for the secondary quantity Qp, and therefore several levels of average value of Gaussian distribution.

[0216] A person skilled in the art will observe that the primary memory component 32 is also programmable on several levels, in particular when the primary memory component 32 is of the OxRAM, CB RAM, PCM, MRAM or FTJ type, which also allows several levels of value to be obtained for the primary quantity Qo, and therefore several levels of standard deviation value of Gaussian distribution.

[0217] The matrix arrangement of the primary 30 and secondary 50 cells within the electronic circuit 10 according to the invention will now be described with reference to figures 11 to 14.

[0218] In the examples in Figures 11 to 14, the primary branch(es) 15 are arranged in one or more parallel columns, each primary branch 15 typically comprising several primary cells 30 connected in parallel, the primary cells 30 then corresponding to different parallel rows. Similarly, the secondary branch(es) 20 are arranged in one or more parallel columns, each secondary branch 20 typically comprising several secondary cells 50 connected in parallel, the secondary cells 50 then corresponding to different parallel rows.

[0219] In the examples in Figures 11 to 14, the voltage notations used are those previously described for Figures 1 to 10, with the clarification that the voltage VC Sigma corresponds to the voltage Vc ascoded for the sigma branch, i.e. for the primary branch 15; and respectively that the voltage Vc_ mu corresponds to the voltage Vc ascoded for the mu branch, i.e. for the secondary branch 20.

[0220] The person skilled in the art will further observe that in these examples in Figures 11 to 14, the primary branch or branches 15 are arranged in parallel with the secondary branch or branches 50, each of these branches 30, 50 corresponding to a respective column of the matrix arrangement.

[0221] According to a first arrangement, the electronic circuit 10 comprises N primary branches 15 and N secondary branches 20 arranged in parallel with each other, N being an integer greater than or equal to 2, and the accumulation device 25 comprises a single transimpedance amplifier 60 connected to the primary branches 15 and secondary branches 20, as shown in [Fig. 11]. In the example of [Fig. 11], the primary branches 15 and secondary branches 20 are arranged alternately, with a secondary branch 20 in parallel and following a primary branch 15, then another primary branch 15 in parallel and following said secondary branch 20, and so on.The person skilled in the art will nevertheless understand that according to this first arrangement, the order in which the primary branches 15 and secondary branches 20 are arranged in parallel is of no importance, and has no influence on the operation of the electronic circuit 10, and in particular on the accumulation of charges via the accumulation device 25.

[0222] Figure 12 represents a more detailed implementation of the parallel arrangement of a respective primary branch 15 and secondary branch 20, with the first bit lines BL1 and source SL1 associated with the primary branch 15, and the second bit lines BL2 and source SL2 associated with the secondary branch 20, and with a primary cell 30 followed by a secondary cell 50 for each respective row, each row being connected to a respective word line WLi. The selection of the source lines SLj, SLk, such as the source lines SL1, SL2, and respectively of the word lines WLi, such as the source lines WLI, WL2, is carried out by means of respective selectors 70, also called control logic units.

[0223] Fig. 13 is similar to Fig. 12, and represents a more detailed implementation of the parallel arrangement of two primary branches 15, with the first bit lines BL1 and source SL1 associated with a first primary branch 15, and the second bit lines BL2 and source SL2 associated with a second primary branch 15, and with two successive primary cells 30 for each respective row, each row being linked to a respective word line WLi. The selection Source lines SL1, SL2 and word lines WL1, WL2 is also performed using respective selectors 70.

[0224] According to a second arrangement, the electronic circuit 10 comprises N primary branches 15 and N secondary branches 20 arranged in N pairs of primary 15 and secondary 20 branches, N being an integer greater than or equal to 2, and the accumulation device 25 comprises N transimpedance amplifiers 60, each being connected to a respective pair of primary 15 and secondary 20 branches, as shown in the upper part of [Fig. 14].

[0225] This second arrangement has the advantage of being able to carry out parallel accumulations of charges for each pair of primary 15 and secondary 20 branches, and therefore of being able to generate in parallel pairs of standard deviation value and mean value of Gaussian distribution.

[0226] According to a third arrangement, the electronic circuit 10 comprises a single primary branch 15 and N secondary branches 20 arranged in parallel, N being an integer greater than or equal to 2, and the accumulation device 25 comprises a single transimpedance amplifier 60 connected to the primary 15 and secondary 20 branches, as shown in the lower part of [Fig. 14].

[0227] This third arrangement has the advantage of being able to generate several distinct Gaussian distributions, with several distinct mean values ​​and the same standard deviation value, while requiring a limited number of electronic components, in particular branches 15, 20.

Claims

Demands

1. Electronic circuit (10) for implementing a Bayesian neural network, comprising: - bit lines (BLj); - source lines (SLj); - at least one word line (WLi); - at least one primary branch (15), the primary branch or branches (15) comprising at least one primary cell (30) connected between a respective source line (SLj) and bit line (BLj), the primary cell or cells (30) including a primary memory component (32) and a primary switch (34) connected in series, the primary switch (34) having a control electrode connected to a respective word line (WLi), - at least one secondary branch (20), the secondary branch or branches (20) comprising at least one secondary cell (50) connected between a respective source line (SLk) and bit line (BLk), the secondary cell or cells (50) including a secondary memory component (52) and a secondary switch (54) connected together,the source lines (SLk) and bit lines (BLk) associated with the secondary branch(es) (20) being distinct from the source lines (SLj) and bit lines (BLj) associated with the primary branch(es) (15) and secondary branch(es) (20) and configured to accumulate a total quantity (Qtot) of electrical charges from a respective pair of cells (30, 50), the pair being formed of a respective primary cell (30) and a respective secondary cell (50), the total quantity (Qtot) being the sum of a primary quantity (Qo) of charges from said primary cell (30) and a secondary quantity (QLI) of charges from said secondary cell (50), the primary quantity (Qo) and the secondary quantity (QLI) being accumulated independently of each other.

2. Electronic circuit (10) according to claim 1, wherein the primary quantity (Qo) is accumulated during two successive phases: a charging phase with a first voltage value (VT0P+) applied to the corresponding source line (SLj), and a discharging phase with a second voltage value (VT0P. ) applied to said source line (SLj), the second value (VTOp _) being distinct from the first value (VTop+)-

3. Electronic circuit (10) according to claim 1 or 2, wherein the primary branch or branches (15) further comprise a voltage-current converter (36) of the primary cell (30), the voltage-current converter (36) being connected between an additional potential (VD) and the accumulation device (25), the voltage-current converter (36) having a control electrode connected to the primary cell (30) via the corresponding bit line (BLj).

4. Electronic circuit (10) according to claims 2 and 3, wherein the additional potential (VD) has a value (VD+) greater than a reference potential (VE) at the input of the storage device (25) during the charging phase, and a value (VD.) less than the reference potential (VE) at the input of the storage device (25) during the discharging phase.

5. Electronic circuit (10) according to claim 3 or 4, wherein the primary branch or branches (15) further comprise a variable conductance (42), connected between a reference potential (VCv) and the control electrode of the voltage-current converter (36).

6. Electronic circuit (10) according to claim 3 or 4, wherein the primary branch or branches (15) further comprise a capacitor (38) having one terminal connected to the control electrode of the voltage-current converter (36) and the other terminal to a reference potential (VCap); the primary branch or branches (15) preferably comprising an auxiliary switch (40) connected between the terminal of the capacitor (38) which is connected to said control electrode and a pre-charge potential (Voppset) of the capacitor (38).

7. Electronic circuit (10) according to any one of the preceding claims, wherein the electronic circuit (10) further comprises a cascode, referred to as the primary cascode (26), connected between the primary branch or branches (15) and the accumulation device (25).

8. Electronic circuit (10) according to any one of the preceding claims, wherein the or each primary memory component (32) is a random telegraph noise (RTN) sensitive memory; the or each primary memory component (32) preferably being a memory selected from the group consisting of: an oxide-based resistive memory (OxRAM); a conductive bridged memory (CBRAM); a phase-change memory (PCM); a magnetic memory (MRAM); and a ferroelectric stacking memory, such as a tunnel junction ferroelectric memory (FTJ).

9. Electronic circuit (10) according to any one of claims 1 to 8, wherein the or each secondary memory component (52) is a memory selected from the group consisting of: an oxide-based resistive memory (OxRAM); a conductive bridged memory (CBRAM); a phase-change memory (PCM); a magnetic memory (MRAM); and a ferroelectric stacking memory such as a ferroelectric capacitor (FeRAM) or a ferroelectric tunnel junction memory (FTJ).

10. Electronic circuit (10) according to claim 9, wherein the secondary memory component (52) and the secondary switch (54) are connected in series between the respective source line (SLk) and bit line (BLk), the secondary switch (54) having a control electrode connected to a respective word line (WLj).

11. Electronic circuit (10) according to any one of claims 1 to 8, wherein the or each secondary memory component (52) is a component selected from the group consisting of: a ferroelectric memory field-effect transistor (FeMFET); and a ferroelectric field-effect transistor (FeFET).

12. Electronic circuit (10) according to claim 11 wherein the secondary memory component (52) is connected between the respective source line (SLk) and bit line (BLk), and the secondary switch (54) is connected between a word line (WLj) and a control electrode of the secondary memory component (52).

13. Electronic circuit (10) according to any one of the preceding claims, wherein the electronic circuit (10) further comprises a cascode, called secondary cascode (28), connected between the or each secondary branch (20) and the accumulation device (25).

14. Electronic circuit (10) according to any one of the preceding claims, wherein the accumulation device (25) comprises at least one transimpedance amplifier (60).

15. Electronic circuit (10) according to claim 14, wherein the electronic circuit (10) comprises N primary branches (15) and N secondary branches (20) arranged in N pairs of primary (15) and secondary (20) branches, and the accumulation device (25) comprises N transimpedance amplifiers (60), each being connected to a respective pair of primary (15) and secondary (20) branches, N being an integer greater than or equal to 2.

Images