Photonic plate with test device

Abstract

The invention relates to a photonic plate (PP) comprising at least one motif (MOT), a motif comprising at least one so-called functional photonic chip (PPf) and a test device (DT), the test device (DT) comprising: a first test assembly (E1t) comprising: a first coupler by the test slice (EDC1t), called the first test coupler, a first test light / waveguide coupling device (DC1t), a second coupler by the test slice (EDC2t), called the second test coupler, a second test light / waveguide coupling device (DC2t), the first and second test couplers being arranged symmetrically with respect to a point O, a so-called reference assembly (Er) comprising a reference waveguide (WGr) and a first (DC1r) and a second (DC2r) reference light / waveguide coupling device,The first (DC1t) and second (DC2t) test light / guide coupling devices and the first (DC1r) and second (DC2r) reference light / guide coupling devices are all identical. Figure 4,

Description

Title of the invention: Photonic plate with test device FIELD OF INVENTION

[0001] The field of the invention is silicon photonics, for example used in telecommunications. The invention relates to photonic wafers comprising an array of photonic chips in which photonic circuits are integrated, and their characterization. More particularly, the invention relates to the characterization of couplers by the wafer that allows light to be injected into the circuit and / or recovered at the circuit output. STATE OF THE ART

[0002] With regard to data centers, high-performance computing, or 5G, silicon photonics is essential for having very high-speed data streams, and the demand for throughput is only increasing.

[0003] Every photonic solution requires integration with other optical and / or electronic components. Optically, a photonic wafer or chip comprises a substrate Sub defining an XY plane on which a cladding layer CL is arranged. Waveguides configured to guide light are integrated within this CL layer. The waveguides extend in the XY plane.

[0004] An example of an optical interface is the fiber-chip interface. These fiber-chip interfaces optically connect photonic chips (typically waveguides) with optical fibers in order to send and receive signals in communication networks. Various types of couplers are used to implement the fiber-chip interface.

[0005] A first type of coupler is the grating coupler (“Grating coupler” GC in English) which achieves a so-called vertical coupling via the surface of the chip.

[0006] A second type of coupler is the edge coupler, also known in English as an EDC or Spot Size Converter (SSC). The use of EDCs helps to limit optical losses at the interface. In optical telecommunications, reducing optical losses allows, among other things, for increased communication distances and / or bandwidth, or for reduced energy consumption in optical systems. All three offer a commercial advantage. Quantum photonics applications, in particular, depend heavily on the absence of losses, and many Applications are possible only with very low losses in the optical system as a whole.

[0007] Many types of EDCs and fibers exist, often optimized to improve certain performance levels. The publication by Riccardo Marchetti, et al., "Coupling strategies for Silicon photonics integrated chips [Invited]", Photon. Res. 7, 201-239 (2019) provides a good overview and explains strategies for assembling them in its last chapter, "6. PACKAGING TECHNIQUES".

[0008] Typically, an EDC consists of a waveguide portion WG0 and an end EXT0 configured to match the optical mode propagating in the waveguide to the mode of the optical fiber to which it is coupled. For example, the cross-section of a waveguide is typically less than 1 pm (200-900 nm), while the core of an optical fiber has a diameter of at least 5 pm. A commonly used example of EDCs is the "taper," which has an end whose cross-section gradually decreases, allowing the mode to be spread out to match the fiber. However, many other types of EDCs exist, with various shapes and structures (see, for example, the aforementioned Marchetti publication).

[0009] Edge coupling between an EDC and a fiber is achieved by cutting a TR trench in the photonic plate, as illustrated [Fig. 1]. The plate can then optionally be cut at the TR trench to make the FC facet more accessible. A thin sheath layer is maintained between the end of the EDC EXT0 and the FC facet created by the TR trench, enabling coupling with the fiber.

[0010] In practice, it is difficult to obtain low-loss EDC-fiber coupling. The system is very sensitive to the slightest misalignment, whether translational or angular. The conditions for perfect coupling are difficult to achieve. For perfect coupling, the light beams guided by the fiber and by the EDC must be identical and ideally perfectly superimposed (i.e., their respective modes overlap), meaning that their shape, mode size, propagation axis, and the wavefront that locally describes the phase of the light must be identical and perfectly superimposed (overlap of the respective modes).

[0011] The losses measured during an EDC-fiber coupling consist of losses related to imperfect coupling, losses intrinsically related to the EDC, and other losses. Thus, the losses measured during an EDC-fiber coupling are the sum of losses due to: (i) partial overlap between the modes of the fiber and the EDC (poor design and / or misalignment between the fiber and the EDC), (ii) propagation losses in the EDC (intrinsic losses), and (iii) the interfaces between the fiber and the chip (reflections).

[0012] To test the performance of an EDC-fiber coupling, a widely used approach in the community is the use of a characterization bench illustrated in [Fig. 2]. This bench comprises two EDCs connected via the waveguide portion, each end EXT1, EXT2 being coupled respectively to an associated fiber FOI, FO2. Nano-positioners are used to align the fibers with the EDCs, and a microscope is used to visualize the alignment. Losses are typically measured by calculating the ratio of the current Iout at the output of one of the fibers (FO2) to the current Iin injected into the other fiber (FOI). These losses, often expressed on a logarithmic scale, correspond to those of the complete fiber-EDC system plus waveguide plus EDC-fiber.

[0013] Document WO 2020 / 132968 describes a test method with EDCs, and how to connect a fiber ribbon (110, 150) to the EDCs (111, 151) of a photonic structure 140 of a photonic chip, as illustrated [Fig. 3]. This method has the advantage of being able to test the optical components of the photonic chip on the scale of an entire wafer, including the EDCs. Using this method allows testing of an assembly composed of EDCs, fibers, and photonic structures, but does not provide information on the EDC alone.

[0014] Indeed, in most test systems, such as the one in [Fig. 1], the result is influenced by numerous factors that degrade measurement accuracy. There may be angular and / or translational misalignment, which can be amplified by vibrations, often originating from external sources. Alignment is delicate and highly sensitive. The optical fiber itself contributes to losses. Uncertainties related to its manufacture (mode size can vary, fiber surface condition, etc.) impact the measurement. In a commercial circuit, the fibers would be glued to the chip, which also introduces uncertainties during testing (adhesive condition, etc.) and makes it destructive because the gluing process is necessary for measurement. In the case of optical fibers without an integrated lens, the nominal working distance is zero. Under this condition, the fiber and EDC should be in contact. Practically speaking, this is not feasible due to the risk of damaging the EDC or the fiber.The environment between the fiber and the chip has just as much of an impact on EDC performance.

[0015] Thus these different methods have the disadvantage of measuring only global losses, whereas it would be interesting to characterize the different elements separately, and more particularly to independently measure the intrinsic losses of the EDC.

[0016] An object of the present invention is to remedy the aforementioned drawbacks by proposing a photonic plate integrating a test circuit allowing a measurement of the intrinsic losses of the EDC of the plate. DESCRIPTION OF THE INVENTION

[0017] The present invention relates to a photonic plate comprising at least one motif, a motif comprising at least one so-called functional photonic chip and a test device, a functional photonic chip comprising photonic circuits comprising at least one coupler per functional edge and functional waveguides,

[0018] the photonic plate comprising a substrate along an XY plane, a sheathing layer and waveguides integrated into said sheathing layer,

[0019] the test device comprising: • an initial set of tests including: • a first coupler per test slice, called the first test coupler, comprising a first test waveguide and a first end, • a first test light / guide coupling device, • a second coupler per test slice, called the second test coupler, comprising a second test waveguide and a second end, • a second test light / guide coupling device, • the first and second test couplers being identical, • the first and second test couplers being arranged symmetrically with respect to a point O, the first and second ends facing each other and separated by a first non-zero separation distance, • a so-called reference assembly comprising a reference waveguide and a first and second light / reference waveguide coupling device, • the first and second test light / guide coupling devices and the first and second reference light / guide coupling devices being all identical.

[0020] According to one embodiment, the functional chip extends over a so-called functional area and the test device is disposed outside of said functional area.

[0021] According to one embodiment the first separation distance is equal to twice a nominal distance between an end of a coupler by the functional slice and an optical fiber to which said coupler by the functional slice is associated.

[0022] According to one variant, a trench has been engraved in a separation zone between the first end and the second end.

[0023] According to one embodiment, the trench is filled with an element chosen from a solid material, a liquid, a gas or a vacuum.

[0024] According to one embodiment the substrate is made of silicon, the sheathing layer is made of silicon oxide and the waveguides are made of silicon or silicon nitride.

[0025] According to the test device further includes at least a second test set having a second separation distance different from the first separation distance.

[0026] According to one embodiment, the photonic plate comprises a plurality of second test sets, each having a separation distance different from the other second sets.

[0027] According to one embodiment the test device further comprises at least a third test set, and the third test set is arranged so that the ends of said first and second test coupler of said third test set are offset along the Y axis by an associated lateral distance.

[0028] According to one embodiment, the photonic plate comprises a plurality of third test sets, each having a different associated lateral distance from the other third sets.

[0029] According to one embodiment the test device further comprises at least a fourth test set, and the fourth test set is arranged so that the waveguides and the ends of the first and second test coupler of the fourth set make respectively an angle al and -al with the X axis.

[0030] According to one embodiment, the photonic plate comprises a plurality of fourth test sets, each having an angle value a different from the other fourth sets.

[0031] According to one embodiment, the first set, and where applicable the second, third and fourth sets, comprises a plurality of first and second test couplers arranged in series, the second test light / guide coupling device being connected to the last second test coupler.

[0032] According to another aspect, the invention relates to a method for testing a photonic plate with a test device, the photonic plate comprising at least one pattern, a pattern comprising at least one so-called functional photonic chip and said test device, a functional photonic chip comprising photonic circuits comprising a plurality of functional per-edge couplers and functional waveguides, the photonic plate comprising a substrate in an XY plane, a sheathing layer and waveguides integrated in said sheathing layer, the method comprising the steps of: • To measure so-called reference insertion losses of a reference assembly comprising a reference waveguide and a first and second light / reference waveguide coupling device, • B. Measure the so-called global insertion losses of a first set, called the test set, comprising: • a first coupler per test slice, called the first test coupler, comprising a first test waveguide and a first end, • a first test light / guide coupling device, • a second coupler per test slice, called the second test coupler, comprising a second test waveguide and a second end, • a second test light / guide coupling device, • the first and second test couplers being identical, • the first and second test couplers being arranged symmetrically with respect to a point O, the first and second ends facing each other and separated by a first non-zero separation distance, • the first and second test light / guide coupling devices and the first and second reference light / guide coupling devices being all identical. • C determine intrinsic insertion losses of the first and / or second test coupler from the overall insertion losses and the reference insertion losses.

[0033] According to one embodiment, said intrinsic insertion losses are determined in step C by the formula, on a logarithmic scale:

[0034] ILEDC = (ILtot - ILref) / 2

[0035] with ILEDC intrinsic insertion losses, ILtot global insertion losses, ILref reference insertion losses.

[0036] According to one embodiment, the first assembly comprises a plurality of 2N first and second test couplers arranged in series, the second test light / guide coupling device being connected to the last second test coupler, and said intrinsic insertion losses are determined in step C by the formula, on a logarithmic scale:

[0037] ILEDC = (IUt-ILref) / 2N

[0038] with ILEDC intrinsic insertion losses, ILtot global insertion losses, ILref reference insertion losses.

[0039] According to another, the invention relates to a method for manufacturing at least one functional photonic chip comprising: • a manufacturing step of a photonic plate according to one aspect of the invention, where at least one functional chip extends over a so-called functional area, and the test device is disposed outside said functional area, • a step consisting of implementing the test method for said photonic plate according to another aspect of the invention, • a cutting step of said at least one functional chip along a cutting line not passing through the test device.

[0040] According to an embodiment wherein the photonic plate manufacturing step comprises a substep of etching trenches in a separation zone between the first end and the second end of the first assembly of the test device, and a substep of etching trenches in said at least one functional chip for coupling with the couplers by the functional wafer, the two etching substeps being carried out with the same etching technology.

[0041] The following description presents several embodiments of the device of the invention: these examples are not limiting to the scope of the invention. These embodiments present both the essential features of the invention and additional features related to the embodiments considered.

[0042] The invention will be better understood and other features, objectives and advantages thereof will become apparent from the following detailed description and with reference to the accompanying drawings given by way of non-limiting examples and in which:

[0043] The [Fig. 1] already cited illustrates a photonic plate having a trench allowing light / waveguide coupling by the edge.

[0044] The [Fig.2] already cited illustrates a characterization bench for an EDC-fiber system according to the state of the art.

[0045] The [Fig.3] already cited illustrates a test method for an assembly composed of EDC and fibers allowing characterization on the scale of an entire plate according to the state of the art.

[0046] Figure 4 illustrates a photonic plate incorporating a test device according to the invention.

[0047] Figure 5 illustrates a variant of the invention in which the test device includes trenches.

[0048] Figure 6 illustrates a trenchless embodiment of the test device according to the invention allowing the evaluation of a distancing / bringing together effect of the two ends along the X axis.

[0049] Fig. 7 illustrates an embodiment of the test device according to the invention with a trench allowing the evaluation of a distancing / bringing together effect of the two ends along the X axis.

[0050] Figure 8 illustrates a trenchless embodiment of the test device according to the invention, allowing the effect of misalignment perpendicular to the X axis to be quantified.

[0051] Fig. 9 illustrates an embodiment of the test device according to the invention with a trench allowing the effect of a misalignment perpendicular to the X axis to be quantified.

[0052] Fig. 10 illustrates a trenchless embodiment of the test device according to the invention, allowing the effect of angular misalignment with respect to the X axis to be quantified.

[0053] Fig. 11 illustrates an embodiment of the test device according to the invention with a trench allowing the effect of an angular misalignment with respect to the X axis to be quantified.

[0054] Fig. 12 illustrates an example of combining the embodiments shown in Figures 7, 9 and 11.

[0055] Figure 13 illustrates an embodiment of the test device according to the invention in which a plurality of test coupler pairs are arranged in series. DETAILED DESCRIPTION OF THE INVENTION

[0056] Figure 4 describes a PP photonic wafer according to the invention. The photonic wafer is the equivalent of an electronic wafer for circuit fabrication. It comprises at least one MOT pattern, a pattern comprising at least one PPf functional photonic chip, and a DT test device. The fabrication of the complete wafer (also called the "photonic wafer") is typically carried out by duplicating the pattern. The PPf functional photonic chips comprise a set of photonic circuits, a photonic circuit comprising at least one EDCf functional wafer coupler, and functional waveguides (WGf). A functional photonic chip may also include other photonic structures. "Functional" refers to elements intended for use in the intended application of the chip or circuit. The test device is conventionally integrated into a test chip in which all the test systems are concentrated.

[0057] Classically the photonic plate comprises a substrate SUB along an XY plane, a sheathing layer CL and waveguides integrated into the sheathing layer.

[0058] The EDCf couplers shown in [Fig.4] as an example are "taper" couplers, but the test device (and the functional photonic chips) can include any type of EDC.

[0059] In addition to the functional elements, a pattern of the plate includes a test device DT comprising a first test set Elt and a so-called reference set Er.

[0060] The first test assembly includes a first coupler by the test slice EDClt, referred to as the first test coupler, comprising a first test waveguide WGlt and a first end EXlt and a second coupler by the test slice EDC2t, referred to as the second test coupler, comprising a second test waveguide WG2t and a second end EX2t.

[0061] The ET1 assembly also includes a first light / waveguide coupling device DClt and a second light / waveguide coupling device DC2t, associated with WGlt and WG2t respectively. A light / waveguide coupling device is defined as a coupler for injecting or recovering light into the associated waveguide. These light / waveguide coupling devices can be of any type, vertically coupled (grating) or edge-coupled.

[0062] According to one embodiment, the first test assembly also includes a first intermediate waveguide between the first light / waveguide coupling device DClt and the first test waveguide WGlt, and the second test assembly also includes a second intermediate waveguide between the second light / waveguide coupling device DC2t and the second test waveguide WG2t. Preferably, this is an extension of the waveguides WGlt / WG2t, which may have non-straight sections for design convenience, as illustrated in Figures 4 and 5.

[0063] The first and second test coupler EDClt and EDC2t are identical, that is to say they have an identical shape and are made of the same material.

[0064] Preferably, to ensure that the characterization performed with the DT device is as representative as possible, the EDClt and EDC2t test couplers are identical to a coupler via the EDCf functional slice. Thus, the test results performed using EDClt and EDC2t correspond to the performance of couplers present on the PPf functional chips.

[0065] The first and second test couplers EDC1t and EDC2t are arranged symmetrically with respect to a point O, with the first end EX1t and the second end EX2t facing each other and separated by a first non-zero separation distance DSI, as illustrated in [Fig. 4]. The bottom of [Fig. 4] corresponds to a zoom in on the area around the two ends. The EDC1t and EDC2t couplers extend along an X-axis, and the waveguides to which they are connected then extend in the XY plane. The separation distance DSI is chosen to be representative of twice the nominal operating distance of a functional coupler, i.e., twice the distance between an optical fiber and a functional coupler.

[0066] The light injected, for example, by DClt, propagates in the first intermediate waveguide when it exists; in EDClt, first in the waveguide portion WGlt and then in the end EXlt, which is configured, as explained above, to adapt The mode of light propagation in the waveguide typically widens it. The light propagates in the intermediate zone between the two ends, then couples to the EDC2t coupler via the EX2t end, propagates through WG2t (and then through the second intermediate waveguide if present), and is then extracted from the waveguide via DC2t. Thus, DClt is used as the light input and DC2t as the output for the first test set, Elt. No fiber is involved in the light path between DClt and DC2t.

[0067] The test device DT also includes a so-called reference assembly Er comprising a reference waveguide WGr and a first light / reference waveguide coupling device DClr and a second light / reference waveguide coupling device DC2r. DClr is used as the light input and DC2t as the output in the reference assembly Er.

[0068] The light injected for example by DClr propagates in WGr and is then recovered in DC2r.

[0069] For the implementation of the EDC1t / EDC2t coupler test, the reference insertion losses ILref of the reference assembly are measured, and the global insertion losses ILtot of the first test assembly Elt are measured. The intrinsic insertion losses IL|I)C of the first or second test coupler (these two couplers are identical, and preferably chosen to be identical to the functional couplers of the functional chip) are then determined from the global insertion losses and the reference insertion losses.

[0070] The measurement is carried out with a light having a wavelength used in the functional chip, for example X = 915 nm, 1310 nm, or 1550 nm.

[0071] In order to compare ILref and ILtot, the first and second test light / guide coupling devices DClt, DC2t, and the first and second reference light / guide coupling devices DClr, DC2r, are all identical (same type, parameters, technology, etc.). For example, these four couplers are network couplers.

[0072] The reference waveguide WGr typically has the same cross-section and material as the waveguides WGlt / WG2t. Furthermore, if the test assembly Elt contains a first and second intermediate waveguide, the reference waveguide of the reference assembly also incorporates the structural characteristics of these intermediate waveguides. The idea is that the reference waveguide WGr has a structure, in terms of cross-section and material, that is close to, and if possible equivalent to, that of the waveguides in the test assembly. Preferably, the shape of WGr corresponds to that which the two waveguides of the test assembly would have if placed end to end, without the ends of EDClt and EDC2t.

[0073] Thus, typically, the two assemblies Elt and Er are made up of identical components, with the sole difference being the presence of the two ends of the test EDCs EDClt and EDC2t separated by the distance DSI for Elt. Since it is the same EDC twice, the intrinsic losses of a single test EDC can be calculated from the formula (on a logarithmic scale):

[0074] 2 x ILEDC = ILtot-Ibref

[0075] That is:

[0076] ILEDC = (IUt- ILref) / 2

[0077] By integrating the test device on the PP plate incorporating the PPf functional chips, the plate according to the invention is freed from undesirable contributions to the measurement of losses of the test system of [Fig.2].

[0078] An EDC / fiber system is expected to exhibit lower losses than a fiber coupled with a network coupler. However, in reality, many different factors contribute to the overall losses of a system such as the one illustrated in [Fig. 2]: fiber alignment, the medium between the fiber and the EDC, propagation within the EDC, linear and angular misalignment, manufacturing errors, etc. Ideally, losses of between 0 and 0.5 dB are sought for the EDC / fiber system, but in practice, losses of up to 1.5 to 3 dB are measured, which is much higher than expected. In order to optimize the system, it is important to know the source of the losses, and an overall measurement on a system such as the one in [Fig. 2] does not provide this information.

[0079] In the DT device according to the invention, instead of placing each EDC opposite a fiber, the two (identical) test EDCs are placed opposite each other, maintaining central symmetry, with the same EDC on both sides of the fixed point O. The solid connection between the two EDCs allows for perfect and static positioning. The positioning is no longer affected by slight vibrations of the test bench.

[0080] The DT test device integrated into the PP plate according to the invention thus allows a measurement of the intrinsic losses of a coupler by the edge, isolated from the contributions of the other elements of the system, unlike the measurements carried out with known test devices illustrated [Fig.2] or 3. This measurement of IL| I)C allowed by the DT device according to the invention relates only to the EDC, and it is precise and reliable.

[0081] Furthermore, each supplier of integrated optical chips that uses EDCs as an interface has an interest in specifying their performance. The DT device integrated into a wafer or pattern allows for precise characterization of the EDCs. It integrates into the set of test systems implemented on the wafer and allows verification of the proper functioning of the functional chips on the wafer.

[0082] According to one embodiment, the reference waveguide length Lref is equal to the sum of the waveguide length between DC1t and EX1t and the waveguide length between DC2t and EX2t. The comparison between IL1t and ILref then represents improved accuracy.

[0083] According to an embodiment also illustrated [Fig. 4], at least one PPf functional chip of the MOT pattern extends over a so-called functional area, and the DT test device is disposed outside the functional area. This is made possible by the structure of the test device, which can be completely isolated from the chip circuits. Thus, the manufacturer receiving the PP board can, if necessary, perform tests with the DT circuit and then separate the chip(s) by cutting, for example, along a LD cutting line illustrated [Fig. 4].

[0084] According to one embodiment, the first separation distance DSI is equal to twice the nominal distance dn between the end of a coupler via the functional slice EDCf and an optical fiber to which the coupler via the functional slice is connected. The reproduction, by the test device according to the invention, of the actual coupling situation in a functional chip is thus improved.

[0085] According to an illustrated variant [Fig. 5], a TR trench has been etched in the separation zone between the first end EX1 and the second end EX2t. The TR trench is devoid of a cladding layer CL and can also be partially or completely etched into the substrate SUB. The trench can extend over the entire space between the two ends, or a small thickness of cladding can be retained in contact with each end. The latter case corresponds to the technological reality. Preferably, the etching technology used to create the trench in the test device is identical to that used to create the trenches in the functional chips.

[0086] These deep trenches (100 pm is a typical value) are very commonly used to define the face of the EDC (see [Fig. 1]). By integrating a trench between the two EDCt, a surface state close to the actual situation of a functional EDCf fiber / coupler coupling is created.

[0087] According to one embodiment, the trench TR is filled with an element El selected from a solid material, a liquid, a gas, or a vacuum. Preferably, the element El is identical to that used for the functional trenches enabling the coupling of a coupler by the functional slice EDCf of a functional chip PPf of the PP wafer with an associated optical fiber.

[0088] Integrating a trench between the two test EDCs thus makes it possible to extract the intrinsic performance of an EDC under real operating conditions, and preferably of a functional EDC under real operating conditions, for the case where the test EDCs have been chosen to be identical to the functional EDCs.

[0089] According to one embodiment the trench material is an index liquid or an adhesive.

[0090] For example, the PP plate substrate is made of silicon, the CL sheathing layer is made of silicon oxide SiO2 and the waveguides are made of silicon Si or silicon nitride SixNy.

[0091] According to one embodiment of the invention, applicable to the test device without or with trench, the test device DT comprises at least a second test set E2tl having a second separation distance DS2 different from the first separation distance, as illustrated [Fig.6] for the test device without trench and [Fig.7] for the variant of the test device with trench.

[0092] The separation distance DS2 can be zero (applicable to the trenchless variant), which allows the performance of the coupler to be measured in a configuration where the two ends touch.

[0093] According to one embodiment, the DT device comprises a plurality of second test sets E2ti indexed i varying from 1 to n, each presenting a separation distance DSi different from the other second sets.

[0094] By way of example, for the embodiment of [Fig.6], sets (Elt and E2ti) are made with separation distances of 0.5, 2.5, 5, 7.5 and 10 pm.

[0095] The measurement of the associated intrinsic losses ILEDC(i) makes it possible to quantify the effect of a distancing / rearing of the two ends along the X axis, relative to the "reference" DSI distance of the first set.

[0096] According to one embodiment of the invention, applicable to the test device with or without a trench, the test device DT comprises at least one third test set E3ti, the third test set being arranged such that the ends of the first and second test couplers of the third test set are offset along the Y-axis by an associated lateral distance dyi. This embodiment is illustrated [Fig. 8] for the test device without a trench and [Fig. 9] for the variant of the test device with a trench.

[0097] For the embodiment of [Fig.9], according to one option the different assemblies share the same trench as illustrated [Fig.9].

[0098] According to one embodiment, as illustrated in Figures 8 and 9, the DT device comprises a plurality of third test sets E3tj indexed j varying from 1 to m, each presenting an associated lateral distance dy, different from the other third sets.

[0099] The measurement of the associated intrinsic losses ILEDC(j) makes it possible to quantify the effect of a misalignment perpendicular to the X axis, with respect to the configuration aligned along X of the first set Elt.

[0100] The test setup illustrated in [Fig. 8] or 9, and the associated measurements ILEDC(j) as a function of dyj, also allows the mode diameter, known as MFD for "Mode Field Diameter," to be quantified. This parameter is very useful for selecting a fiber with a suitable core, i.e., with a similar MFD, in order to reduce EDC / fiber coupling losses.

[0101] By way of example, for the embodiment of [Fig.8], sets (Elt and E3tj) are made with lateral offsets of 0, 0.5, 1, 2, 3 and 5 pm.

[0102] According to one embodiment of the invention, applicable to the test device without or with a trench, the test device DT comprises at least a fourth test set E4tb, the fourth test set being arranged so that the waveguides and the ends of the first and second test couplers of the fourth set make angles al and -al respectively with the X-axis. The first and second test couplers of the fourth set are then no longer arranged symmetrically at point O, and no longer both extend along the X-axis.

[0103] This embodiment is illustrated [Fig. 10] for the trenchless test device and [Fig. 11] for the variant of the test device with trench.

[0104] For the embodiment of [Fig. 11], according to one option the different assemblies share the same trench as illustrated [Fig. 11].

[0105] According to one embodiment, as illustrated in figures 10 and 11, the DT device comprises a plurality of fourth test sets E4tk indexed k varying from 1 to 1, each presenting an angle value ak different from the other fourth sets.

[0106] The measurement of the associated intrinsic losses ILEDC(k) makes it possible to quantify the effect of an angular misalignment with respect to the X axis, with respect to the X-aligned configuration of the first set Elt.

[0107] The various embodiments illustrated in Figures 6 to 11 can, of course, be combined with each other. By way of example, [Fig. 12] illustrates the combination of the embodiments of Figures 7, 9, and 11, with the option of a plurality of first sets Elt. According to another option, the DT device comprises only one first set Elt, associated with several second, and / or third, and / or fourth sets, with and / or without trenches.

[0108] For the embodiments illustrated in figures 6 to 12, the reference set Er has not been shown.

[0109] According to an embodiment illustrated [Fig. 13], the first assembly Elt comprises a plurality of first and second test couplers arranged in series, the second test light / guide coupling device DC2t being connected to the last second test coupler. This results in a total of N pairs (EDClt, EDC2t). [Fig. 13] illustrates N=3 pairs (EDClt, EDC2t), identified as pair Cm (EDClt(m), EDC2t(m)). with m being the number of the pair ranging from 1 to 3. This embodiment is of course also applicable to the second, third and fourth sets.

[0110] Let Lt be the length of the waveguide between the light / guide coupling device and the associated end of each of the identical test couplers, and Lr ef the length of the reference waveguide.

[0111] Preferably we have:

[0112] Lref = 2N.Lt

[0113] According to another aspect the invention relates to a method for testing 100 of a PP photonic plate with a DT test device as described above.

[0114] In a first step A, the reference insertion losses ILref of the reference set Er are measured. In a second step B, the total insertion losses ILtot of the first test set Elt are measured. Steps A and B can, of course, be reversed in time. The insertion loss measurements are typically taken from input and output current measurements. Typically, it is sufficient to measure only the output currents. Using the same measurement system, the same losses are added to ILref and ILtot and consequently do not change the difference ILtot - ILref.

[0115] Finally, in a step C, the intrinsic insertion losses ILedc of the first and / or second test coupler (they are identical) are determined from the global insertion losses and the reference insertion losses.

[0116] Preferably the intrinsic insertion losses ILEDC of an EDCt are determined by the formula, on a logarithmic scale (for a pair (EDClt, EDC2t)):

[0117] ILEDC = (IUt-ILref) / 2

[0118] For the embodiment with N pairs of test couplers in series, the formula becomes:

[0119] ILedc = (ILtot - ILref) / (2xN)

[0120] Test method 100 is a systematic test of EDCs post-wafer fabrication.

[0121] For photonic wafer manufacturers, it is attractive to display intrinsic performance and to use ILEDC measurements performed according to method 100 to quantify the ILEDC of their EDCs. Indeed, intrinsic performance is generally higher than system performance. Intrinsic ILEDC performance is, for example, part of specifications provided by the wafer manufacturer or a chip vendor.

[0122] According to yet another aspect the invention relates to a method for manufacturing at least one functional PPf photonic chip.

[0123] In a (first) step, a PP photonic plate as described above is manufactured, incorporating the DT test device. The methods for manufacturing such a plate are known to those skilled in the art. The plate is arranged so that at least one PPF functional chip extends over a so-called functional area, and the DT test device is disposed outside the functional area. This arrangement is permitted because the test device is independent of the circuits of the functional chip.

[0124] Then in a step the test procedure 100 is implemented.

[0125] In another step, at least one functional PPF chip is cut according to a The LD cutting line (see Figures 4 and 5) does not pass through the test device. This is permitted because the test device is located outside the functional area. The cutting step can be performed before or after the test process implementation step.

[0126] According to one embodiment, the manufacturing step of the PP photonic wafer comprises a substep of etching trenches in the separation zone between the first end and the second end of the first assembly of the DT test device, and a substep of etching trenches in at least one functional chip for coupling with the couplers via the EDCf functional wafer. Both etching substeps, for releasing the EDCt and EDCf, are performed using the same etching technology.

[0127] The DT test device, and the associated test method 100, are thus representative of the actual coupling conditions in the functional chip.

[0128] Preferably the two sub-steps of engraving form only one, the engraving being carried out in parallel, simultaneously on the whole motif or even on the whole plate.

Claims

Demands

1. Photonic plate (PP) comprising at least one motif (MOT), a motif comprising at least one so-called functional photonic chip (PPf) and a test device (DT), a functional photonic chip comprising photonic circuits comprising at least one functional edge coupler (EDCf) and functional waveguides (WGf), the photonic plate comprising a substrate (SUB) along an XY plane, a sheathing layer (CL) and waveguides integrated in said sheathing layer, the test device (DT) comprising: a first set of tests (Elt) comprising: • a first coupler by the test slice (EDClt), called the first test coupler, comprising a first test waveguide (WGlt) and a first end (EXlt), • a first light / guide test coupling device (DClt), • a second coupler per test slice (EDC2t), referred to as the second test coupler, comprising a second test waveguide (WG2t) and a second end (EX2t), • a second light / guide test coupling device (DC2t), • the first and second test couplers being identical, • the first and second test couplers being arranged symmetrically with respect to a point O, the first and second ends facing each other and being separated by a first non-zero separation distance (DSI), a so-called reference assembly (Er) comprising a reference waveguide (WGr) and a first (DClr) and a second (DC2r) light / reference waveguide coupling device, the first (DClt) and second (DC2t) test light / guide coupling devices and the first (DClr) and second (DC2r) light / reference guide coupling devices being all identical.

2. Photonic plate according to the preceding claim wherein the functional chip extends over a so-called functional area and the test device (TD) is disposed outside said functional area.

3. Photonic plate according to any one of the preceding claims wherein the first separation distance (DSI) is equal to twice a nominal distance (dn) between one end of a coupler by the functional slice (EDCf) and an optical fiber to which said coupler by the functional slice is associated.

4. Photonic plate according to any one of the preceding claims in which a trench (TR) has been etched in a separation zone between the first end and the second end.

5. Photonic plate according to the preceding claim in which the trench is filled with an element (El) selected from a solid material, a liquid, a gas or a vacuum.

6. Photonic plate according to any one of the preceding claims wherein the substrate is made of silicon, the cladding layer is made of silicon oxide (SiO2) and the waveguides are made of silicon (Si) or silicon nitride (SixNy).

7. Photonic plate according to any one of the preceding claims wherein the test device further comprises at least one second test set (E2ti) having a second separation distance (DS2) different from the first separation distance.

8. Photonic plate according to the preceding claim, comprising a plurality of second test sets (E2t;) each having a separation distance (DSi) different from the other second sets.

9. Photonic plate according to any one of the preceding claims wherein the test device further comprises at least one third test set (E3ti) and wherein the third test set is arranged such that the ends of said first and second test coupler of said third test set are offset along the Y axis by an associated lateral distance (dyO).

10. A photonic plate according to the preceding claim, comprising a plurality of third test sets (E3tj) each having an associated lateral distance (dyj) different from the other third sets.

11. Photonic plate according to any one of the preceding claims wherein the test device further comprises at least one fourth test set (E4ti), and wherein the fourth test set is arranged such that the waveguides and the ends of the first and second test coupler of the fourth set make an angle al and -al respectively with the X axis.

12. A photonic plate according to the preceding claim, comprising a plurality of fourth test sets (E4tk), each having an angle value α(ak) different from the other fourth sets

13. Photonic plate according to any one of the preceding claims wherein the first set, and where applicable the second, third and fourth sets, comprises a plurality of first and second test couplers arranged in series, the second test light / guide coupling device (DC2t) being connected to the last second test coupler.

14. A test method (100) for a photonic plate (PP) with a test device (TD), the photonic plate comprising at least one motif (MOT), a motif comprising at least one so-called functional photonic chip (PPf) and said test device (TD), a functional photonic chip comprising photonic circuits comprising a plurality of functional slice couplers (EDCf) and functional waveguides (WGf), the photonic plate comprising a substrate (SUB) along an XY plane, a sheathing layer (CL) and waveguides (WG) integrated into said sheathing layer, the method comprising the steps of: • Measuring so-called reference insertion losses (ILref) of a reference assembly comprising a reference waveguide (WGr) and a first (DClr) and a second (DC2r) light / reference waveguide coupling device,• B measure total insertion losses (ILtot) of a first set called a test set (Elt) comprising:, • a first coupler by the test slice (EDClt), called the first test coupler, comprising a first test waveguide (WGlt) and a first end (EXlt), • a first test light / waveguide coupling device (DClt), • a second test coupler by the test slice (EDC2t), called the second test coupler, comprising a second test waveguide (WG2t) and a second end (EX2t), • a second test light / waveguide coupling device (DC2t), • the first and second test couplers being identical, • the first and second test couplers being arranged symmetrically with respect to a point 0, the first and second end facing each other and being separated by a first non-zero separation distance (DSI), • the first (DClt) and second (DC2t) test light / waveguide coupling devices and the first (DClr) and second (DC2r) reference light / waveguide coupling devices being all identical.• C determine intrinsic insertion losses (ILEDC) of the first and / or second test coupler from the overall insertion losses and the reference insertion losses.

15. A method according to the preceding claim, wherein said intrinsic insertion losses are determined in step C by the formula, on a logarithmic scale: ILedc = (ILtot — ILref) / 2 with ILedc intrinsic insertion losses, ILtot global insertion losses, ILref reference insertion losses.

16. A method according to any one of claims 14 or 15, wherein the first assembly comprises a plurality of 2N first and second test couplers arranged in series, the second test light / guide coupling device (DC2t) being connected to the last second test coupler, and in which said intrinsic insertion losses are determined at step C by the formula, on a logarithmic scale: ILEDC = (ILtot - ILref) / 2N with ILEDC intrinsic insertion losses, ILtot global insertion losses, ILref reference insertion losses.

17. A method for manufacturing at least one functional photonic chip (FPC) comprising: • a step of manufacturing a photonic wafer according to any one of claims 1 to 13, the at least one functional chip extending over a so-called functional area, and the test device (TD) being disposed outside said functional area, • a step consisting of carrying out the test method for said photonic wafer according to any one of claims 14 to 16, • a step of cutting said at least one functional chip along a cutting line (CL) not passing through the test device.

18. A method according to the preceding claim wherein the photonic plate manufacturing step comprises a substep of trenching in a separation zone between the first end and the second end of the first assembly of the test device, and a substep of trenching in said at least one functional chip for coupling with the functional wafer couplers, the two etching substeps being carried out with the same etching technology.

Images