Memory device with series-connected ferroelectric transistor and capacitor, associated electronic circuit, programming method and reading method
The integration of a ferroelectric field-effect transistor and capacitor in a memory device addresses the von Neumann bottleneck by enabling logical operations with reduced current consumption, facilitating efficient AND, OR, and NAND functions.
FR3170692A1Pending Publication Date: 2026-06-26COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Applications
- Current Assignee / Owner
- COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Filing Date
- 2024-12-24
- Publication Date
- 2026-06-26
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Abstract
Memory device with series-connected ferroelectric transistor and capacitor, associated electronic circuit, programming method and reading method. The present invention relates to a memory device (14) comprising: - a ferroelectric field-effect transistor (20) having a gate electrode (21) and first (22) and second (23) conduction electrodes; - a ferroelectric capacitor (25) having first (27) and second (28) charge electrodes; the transistor (20) and the ferroelectric capacitor (25) being connected according to a first connection configuration (C1) in which the first conduction electrode (22) is connected to a reference potential (GND) and the second conduction electrode (23) is connected to the first charge electrode (27);or according to a second connection configuration in which the first conduction electrode (22) is connected to the first charging electrode (27) and the second conduction electrode (23) is connected to the second charging electrode (28). Figure for the abbreviation: Figure 2;
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